coreboot April 2010

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[FILO] r122 - trunk/filo
by repository service 02 Apr '10

02 Apr '10

Author: stepan Date: Fri Apr 2 18:18:59 2010 New Revision: 122 URL: http://tracker.coreboot.org/trac/filo/changeset/122 Log: As suggested by Wang Qing Pei: Fix FILO compilation without extra parameters on AMD64 Signed-off-by: Wang Qing Pei <wangqingpei(a)gmail.com> Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/filo/Makefile Modified: trunk/filo/Makefile ============================================================================== --- trunk/filo/Makefile Fri Mar 26 15:32:47 2010 (r121) +++ trunk/filo/Makefile Fri Apr 2 18:18:59 2010 (r122) @@ -41,15 +41,17 @@ Q := @ endif -CC = gcc +CROSS_PREFIX = +CC = $(CROSS_PREFIX)gcc -m32 +AS = $(CROSS_PREFIX)as --32 +LD = $(CROSS_PREFIX)ld -belf32-i386 +STRIP = $(CROSS_PREFIX)strip +NM = $(CROSS_PREFIX)nm HOSTCC = gcc HOSTCXX = g++ HOSTCFLAGS := -I$(srck) -I$(objk) -pipe HOSTCXXFLAGS := -I$(srck) -I$(objk) -pipe -STRIP ?= strip -NM ?= nm - ifeq ($(strip $(HAVE_DOTCONFIG)),) all: config

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[commit] r5344 - in trunk/src: arch/i386/include/arch arch/i386/init arch/i386/lib arch/i386/llshell console cpu/amd/model_lx cpu/intel/model_106cx cpu/intel/model_6ex cpu/intel/model_6fx cpu/x86/3...
by repository service 01 Apr '10

01 Apr '10

Author: stepan Date: Thu Apr 1 11:50:32 2010 New Revision: 5344 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5344 Log: -Â get rid of ASM_CONSOLE_LOGLEVEL except in two assembler files. - start naming all versions of post code output "post_code()" Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/arch/i386/include/arch/intel.h trunk/src/arch/i386/init/bootblock_prologue.c trunk/src/arch/i386/init/car.S trunk/src/arch/i386/init/crt0.S.lb trunk/src/arch/i386/lib/c_start.S trunk/src/arch/i386/lib/printk_init.c trunk/src/arch/i386/llshell/console.inc trunk/src/arch/i386/llshell/ramtest.inc trunk/src/arch/i386/llshell/readme.coreboot trunk/src/console/console.c trunk/src/cpu/amd/model_lx/cache_as_ram.inc trunk/src/cpu/intel/model_106cx/cache_as_ram.inc trunk/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/src/cpu/intel/model_6fx/cache_as_ram.inc trunk/src/cpu/x86/32bit/entry32.inc trunk/src/include/console/console.h trunk/src/include/console/loglevel.h trunk/src/mainboard/amd/db800/romstage.c trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/norwich/romstage.c trunk/src/mainboard/amd/pistachio/romstage.c trunk/src/mainboard/artecgroup/dbe61/romstage.c trunk/src/mainboard/broadcom/blast/romstage.c trunk/src/mainboard/digitallogic/adl855pc/romstage.c trunk/src/mainboard/digitallogic/msm586seg/romstage.c trunk/src/mainboard/digitallogic/msm800sev/romstage.c trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/lippert/roadrunner-lx/romstage.c trunk/src/mainboard/lippert/spacerunner-lx/romstage.c trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/newisys/khepri/romstage.c trunk/src/mainboard/pcengines/alix1c/romstage.c trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/romstage.c trunk/src/mainboard/technologic/ts5300/romstage.c trunk/src/mainboard/tyan/s2850/romstage.c trunk/src/mainboard/tyan/s2881/romstage.c trunk/src/mainboard/tyan/s2885/romstage.c trunk/src/mainboard/winent/pl6064/romstage.c trunk/src/northbridge/amd/gx2/pll_reset.c trunk/src/northbridge/amd/lx/pll_reset.c trunk/src/northbridge/amd/lx/raminit.c Modified: trunk/src/arch/i386/include/arch/intel.h ============================================================================== --- trunk/src/arch/i386/include/arch/intel.h Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/arch/i386/include/arch/intel.h Thu Apr 1 11:50:32 2010 (r5344) @@ -45,10 +45,8 @@ jmp *%esp -/* originally this macro was from STPC BIOS */ -#define intel_chip_post_macro(value) \ - movb $value, %al ; \ +#define post_code(value) \ + movb $value, %al; \ outb %al, $0x80 - #endif /* ROM_INTEL_H */ Modified: trunk/src/arch/i386/init/bootblock_prologue.c ============================================================================== --- trunk/src/arch/i386/init/bootblock_prologue.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/arch/i386/init/bootblock_prologue.c Thu Apr 1 11:50:32 2010 (r5344) @@ -33,5 +33,5 @@ .section ".rom.data", "a", @progbits .section ".rom.text", "ax", @progbits - intel_chip_post_macro(0x01) /* delay for chipsets */ + post_code(0x01) /* delay for chipsets */ Modified: trunk/src/arch/i386/init/car.S ============================================================================== --- trunk/src/arch/i386/init/car.S Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/arch/i386/init/car.S Thu Apr 1 11:50:32 2010 (r5344) @@ -54,7 +54,7 @@ /* Save the BIST result. */ movl %eax, %ebp - intel_chip_post_macro(0x01) + post_code(0x01) movw $ROM_DATA_SEG, %ax movw %ax, %ds Modified: trunk/src/arch/i386/init/crt0.S.lb ============================================================================== --- trunk/src/arch/i386/init/crt0.S.lb Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/arch/i386/init/crt0.S.lb Thu Apr 1 11:50:32 2010 (r5344) @@ -25,6 +25,10 @@ #include <arch/intel.h> #include <console/loglevel.h> +#ifndef ASM_CONSOLE_LOGLEVEL +#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +#endif + /* * This is the entry code the code in .reset section * jumps to this address. @@ -33,7 +37,7 @@ .section ".rom.data", "a", @progbits .section ".rom.text", "ax", @progbits - intel_chip_post_macro(0x01) /* delay for chipsets */ + post_code(0x01) /* delay for chipsets */ #include "crt0_includes.h" @@ -61,7 +65,7 @@ * isn\'t really that big we just copy/clear using bytes, not * double words. */ - intel_chip_post_macro(0x11) /* post 11 */ + post_code(0x11) /* post 11 */ cld /* clear direction flag */ @@ -78,7 +82,7 @@ call cbfs_and_run_core .Lhlt: - intel_chip_post_macro(0xee) /* post fe */ + post_code(0xee) /* post fe */ hlt jmp .Lhlt Modified: trunk/src/arch/i386/lib/c_start.S ============================================================================== --- trunk/src/arch/i386/lib/c_start.S Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/arch/i386/lib/c_start.S Thu Apr 1 11:50:32 2010 (r5344) @@ -15,7 +15,7 @@ movl %eax, %fs movl %eax, %gs - intel_chip_post_macro(0x13) /* post 13 */ + post_code(0x13) /* post 13 */ /** clear stack */ cld @@ -74,7 +74,7 @@ * bss is cleared. Now we call the main routine and * let it do the rest. */ - intel_chip_post_macro(0xfe) /* post fe */ + post_code(0xfe) /* post fe */ /* Restore the stack location */ movl %ebp, %esp @@ -83,7 +83,7 @@ call hardwaremain /*NOTREACHED*/ .Lhlt: - intel_chip_post_macro(0xee) /* post ee */ + post_code(0xee) /* post ee */ hlt jmp .Lhlt Modified: trunk/src/arch/i386/lib/printk_init.c ============================================================================== --- trunk/src/arch/i386/lib/printk_init.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/arch/i386/lib/printk_init.c Thu Apr 1 11:50:32 2010 (r5344) @@ -19,19 +19,8 @@ #include <console/console.h> #include <console/vtxprintf.h> -#include <console/loglevel.h> #include <uart8250.h> -/* Using a global varible can cause problems when we reset the stack - * from cache as ram to ram. If we make this a define USE_SHARED_STACK - * we could use the same code on all architectures. - */ -#if 0 -int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; -#else -#define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL -#endif - static void console_tx_byte(unsigned char byte) { if (byte == '\n') Modified: trunk/src/arch/i386/llshell/console.inc ============================================================================== --- trunk/src/arch/i386/llshell/console.inc Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/arch/i386/llshell/console.inc Thu Apr 1 11:50:32 2010 (r5344) @@ -234,180 +234,6 @@ #define CONSOLE_SPEW_TX_STRING(string) __CONSOLE_TX_STRING(string) #define CONSOLE_SPEW_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string) -#if 0 -#if ASM_CONSOLE_LOGLEVEL <= BIOS_EMERG -#undef CONSOLE_EMERG_TX_CHAR -#undef CONSOLE_EMERG_INLINE_TX_CHAR -#undef CONSOLE_EMERG_TX_HEX8 -#undef CONSOLE_EMERG_INLINE_TX_HEX8 -#undef CONSOLE_EMERG_TX_HEX32 -#undef CONSOLE_EMERG_INLINE_TX_HEX32 -#undef CONSOLE_EMERG_TX_STRING -#undef CONSOLE_EMERG_INLINE_TX_STRING -#define CONSOLE_EMERG_TX_CHAR(byte) -#define CONSOLE_EMERG_INLINE_TX_CHAR(byte) -#define CONSOLE_EMERG_TX_HEX8(byte) -#define CONSOLE_EMERG_INLINE_TX_HEX8(byte) -#define CONSOLE_EMERG_TX_HEX32(lword) -#define CONSOLE_EMERG_INLINE_TX_HEX32(lword) -#define CONSOLE_EMERG_TX_STRING(string) -#define CONSOLE_EMERG_INLINE_TX_STRING(string) -#endif - - -#if ASM_CONSOLE_LOGLEVEL <= BIOS_ALERT -#undef CONSOLE_ALERT_TX_CHAR -#undef CONSOLE_ALERT_INLINE_TX_CHAR -#undef CONSOLE_ALERT_TX_HEX8 -#undef CONSOLE_ALERT_INLINE_TX_HEX8 -#undef CONSOLE_ALERT_TX_HEX32 -#undef CONSOLE_ALERT_INLINE_TX_HEX32 -#undef CONSOLE_ALERT_TX_STRING -#undef CONSOLE_ALERT_INLINE_TX_STRING -#define CONSOLE_ALERT_TX_CHAR(byte) -#define CONSOLE_ALERT_INLINE_TX_CHAR(byte) -#define CONSOLE_ALERT_TX_HEX8(byte) -#define CONSOLE_ALERT_INLINE_TX_HEX8(byte) -#define CONSOLE_ALERT_TX_HEX32(lword) -#define CONSOLE_ALERT_INLINE_TX_HEX32(lword) -#define CONSOLE_ALERT_TX_STRING(string) -#define CONSOLE_ALERT_INLINE_TX_STRING(string) -#endif - -#if ASM_CONSOLE_LOGLEVEL <= BIOS_CRIT -#undef CONSOLE_CRIT_TX_CHAR -#undef CONSOLE_CRIT_INLINE_TX_CHAR -#undef CONSOLE_CRIT_TX_HEX8 -#undef CONSOLE_CRIT_INLINE_TX_HEX8 -#undef CONSOLE_CRIT_TX_HEX32 -#undef CONSOLE_CRIT_INLINE_TX_HEX32 -#undef CONSOLE_CRIT_TX_STRING -#undef CONSOLE_CRIT_INLINE_TX_STRING -#define CONSOLE_CRIT_TX_CHAR(byte) -#define CONSOLE_CRIT_INLINE_TX_CHAR(byte) -#define CONSOLE_CRIT_TX_HEX8(byte) -#define CONSOLE_CRIT_INLINE_TX_HEX8(byte) -#define CONSOLE_CRIT_TX_HEX32(lword) -#define CONSOLE_CRIT_INLINE_TX_HEX32(lword) -#define CONSOLE_CRIT_TX_STRING(string) -#define CONSOLE_CRIT_INLINE_TX_STRING(string) -#endif - -#if ASM_CONSOLE_LOGLEVEL <= BIOS_ERR -#undef CONSOLE_ERR_TX_CHAR -#undef CONSOLE_ERR_INLINE_TX_CHAR -#undef CONSOLE_ERR_TX_HEX8 -#undef CONSOLE_ERR_INLINE_TX_HEX8 -#undef CONSOLE_ERR_TX_HEX32 -#undef CONSOLE_ERR_INLINE_TX_HEX32 -#undef CONSOLE_ERR_TX_STRING -#undef CONSOLE_ERR_INLINE_TX_STRING -#define CONSOLE_ERR_TX_CHAR(byte) -#define CONSOLE_ERR_INLINE_TX_CHAR(byte) -#define CONSOLE_ERR_TX_HEX8(byte) -#define CONSOLE_ERR_INLINE_TX_HEX8(byte) -#define CONSOLE_ERR_TX_HEX32(lword) -#define CONSOLE_ERR_INLINE_TX_HEX32(lword) -#define CONSOLE_ERR_TX_STRING(string) -#define CONSOLE_ERR_INLINE_TX_STRING(string) -#endif - -#if ASM_CONSOLE_LOGLEVEL <= BIOS_WARNING -#undef CONSOLE_WARNING_TX_CHAR -#undef CONSOLE_WARNING_INLINE_TX_CHAR -#undef CONSOLE_WARNING_TX_HEX8 -#undef CONSOLE_WARNING_INLINE_TX_HEX8 -#undef CONSOLE_WARNING_TX_HEX32 -#undef CONSOLE_WARNING_INLINE_TX_HEX32 -#undef CONSOLE_WARNING_TX_STRING -#undef CONSOLE_WARNING_INLINE_TX_STRING -#define CONSOLE_WARNING_TX_CHAR(byte) -#define CONSOLE_WARNING_INLINE_TX_CHAR(byte) -#define CONSOLE_WARNING_TX_HEX8(byte) -#define CONSOLE_WARNING_INLINE_TX_HEX8(byte) -#define CONSOLE_WARNING_TX_HEX32(lword) -#define CONSOLE_WARNING_INLINE_TX_HEX32(lword) -#define CONSOLE_WARNING_TX_STRING(string) -#define CONSOLE_WARNING_INLINE_TX_STRING(string) -#endif - -#if ASM_CONSOLE_LOGLEVEL <= BIOS_NOTICE -#undef CONSOLE_NOTICE_TX_CHAR -#undef CONSOLE_NOTICE_INLINE_TX_CHAR -#undef CONSOLE_NOTICE_TX_HEX8 -#undef CONSOLE_NOTICE_INLINE_TX_HEX8 -#undef CONSOLE_NOTICE_TX_HEX32 -#undef CONSOLE_NOTICE_INLINE_TX_HEX32 -#undef CONSOLE_NOTICE_TX_STRING -#undef CONSOLE_NOTICE_INLINE_TX_STRING -#define CONSOLE_NOTICE_TX_CHAR(byte) -#define CONSOLE_NOTICE_INLINE_TX_CHAR(byte) -#define CONSOLE_NOTICE_TX_HEX8(byte) -#define CONSOLE_NOTICE_INLINE_TX_HEX8(byte) -#define CONSOLE_NOTICE_TX_HEX32(lword) -#define CONSOLE_NOTICE_INLINE_TX_HEX32(lword) -#define CONSOLE_NOTICE_TX_STRING(string) -#define CONSOLE_NOTICE_INLINE_TX_STRING(string) -#endif - -#if ASM_CONSOLE_LOGLEVEL <= BIOS_INFO -#undef CONSOLE_INFO_TX_CHAR -#undef CONSOLE_INFO_INLINE_TX_CHAR -#undef CONSOLE_INFO_TX_HEX8 -#undef CONSOLE_INFO_INLINE_TX_HEX8 -#undef CONSOLE_INFO_TX_HEX32 -#undef CONSOLE_INFO_INLINE_TX_HEX32 -#undef CONSOLE_INFO_TX_STRING -#undef CONSOLE_INFO_INLINE_TX_STRING -#define CONSOLE_INFO_TX_CHAR(byte) -#define CONSOLE_INFO_INLINE_TX_CHAR(byte) -#define CONSOLE_INFO_TX_HEX8(byte) -#define CONSOLE_INFO_INLINE_TX_HEX8(byte) -#define CONSOLE_INFO_TX_HEX32(lword) -#define CONSOLE_INFO_INLINE_TX_HEX32(lword) -#define CONSOLE_INFO_TX_STRING(string) -#define CONSOLE_INFO_INLINE_TX_STRING(string) -#endif - -#if ASM_CONSOLE_LOGLEVEL <= BIOS_DEBUG -#undef CONSOLE_DEBUG_TX_CHAR -#undef CONSOLE_DEBUG_INLINE_TX_CHAR -#undef CONSOLE_DEBUG_TX_HEX8 -#undef CONSOLE_DEBUG_INLINE_TX_HEX8 -#undef CONSOLE_DEBUG_TX_HEX32 -#undef CONSOLE_DEBUG_INLINE_TX_HEX32 -#undef CONSOLE_DEBUG_TX_STRING -#undef CONSOLE_DEBUG_INLINE_TX_STRING -#define CONSOLE_DEBUG_TX_CHAR(byte) -#define CONSOLE_DEBUG_INLINE_TX_CHAR(byte) -#define CONSOLE_DEBUG_TX_HEX8(byte) -#define CONSOLE_DEBUG_INLINE_TX_HEX8(byte) -#define CONSOLE_DEBUG_TX_HEX32(lword) -#define CONSOLE_DEBUG_INLINE_TX_HEX32(lword) -#define CONSOLE_DEBUG_TX_STRING(string) -#define CONSOLE_DEBUG_INLINE_TX_STRING(string) -#endif - -#if ASM_CONSOLE_LOGLEVEL <= BIOS_SPEW -#undef CONSOLE_SPEW_TX_CHAR -#undef CONSOLE_SPEW_INLINE_TX_CHAR -#undef CONSOLE_SPEW_TX_HEX8 -#undef CONSOLE_SPEW_INLINE_TX_HEX8 -#undef CONSOLE_SPEW_TX_HEX32 -#undef CONSOLE_SPEW_INLINE_TX_HEX32 -#undef CONSOLE_SPEW_TX_STRING -#undef CONSOLE_SPEW_INLINE_TX_STRING -#define CONSOLE_SPEW_TX_CHAR(byte) -#define CONSOLE_SPEW_INLINE_TX_CHAR(byte) -#define CONSOLE_SPEW_TX_HEX8(byte) -#define CONSOLE_SPEW_INLINE_TX_HEX8(byte) -#define CONSOLE_SPEW_TX_HEX32(lword) -#define CONSOLE_SPEW_INLINE_TX_HEX32(lword) -#define CONSOLE_SPEW_TX_STRING(string) -#define CONSOLE_SPEW_INLINE_TX_STRING(string) -#endif -#endif - /* uses: esp, ax, dx */ console_tx_al: __CONSOLE_INLINE_TX_AL Modified: trunk/src/arch/i386/llshell/ramtest.inc ============================================================================== --- trunk/src/arch/i386/llshell/ramtest.inc Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/arch/i386/llshell/ramtest.inc Thu Apr 1 11:50:32 2010 (r5344) @@ -112,7 +112,7 @@ jmp 3b 5: CONSOLE_INFO_TX_STRING($rt_toomany) - intel_chip_post_macro(0xf1) + post_code(0xf1) jmp .Lhlt 6: Modified: trunk/src/arch/i386/llshell/readme.coreboot ============================================================================== --- trunk/src/arch/i386/llshell/readme.coreboot Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/arch/i386/llshell/readme.coreboot Thu Apr 1 11:50:32 2010 (r5344) @@ -16,7 +16,7 @@ 3) Optionally, comment out two lines in ramtest.inc: 5: CONSOLE_INFO_TX_STRING($rt_toomany) - // intel_chip_post_macro(0xf1) + // post_code(0xf1) // jmp .Lhlt otherwise, a ramtest failure will hang Modified: trunk/src/console/console.c ============================================================================== --- trunk/src/console/console.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/console/console.c Thu Apr 1 11:50:32 2010 (r5344) @@ -76,7 +76,7 @@ /* * Write POST information */ -void post_code(uint8_t value) +void post_code(u8 value) { #if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0 #if CONFIG_SERIAL_POST==1 Modified: trunk/src/cpu/amd/model_lx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/model_lx/cache_as_ram.inc Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/cpu/amd/model_lx/cache_as_ram.inc Thu Apr 1 11:50:32 2010 (r5344) @@ -17,6 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef ASM_CONSOLE_LOGLEVEL +#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL +#endif + #define LX_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */ #define LX_STACK_END LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1) @@ -206,7 +210,7 @@ * isn\'t really that big we just copy/clear using bytes, not * double words. */ - intel_chip_post_macro(0x11) /* post 11 */ + post_code(0x11) /* post 11 */ cld /* clear direction flag */ @@ -220,7 +224,7 @@ call cbfs_and_run_core .Lhlt: - intel_chip_post_macro(0xee) /* post fail ee */ + post_code(0xee) /* post fail ee */ hlt jmp .Lhlt Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Thu Apr 1 11:50:32 2010 (r5344) @@ -20,7 +20,6 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE -#define post_code(x) intel_chip_post_macro(x) #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Thu Apr 1 11:50:32 2010 (r5344) @@ -20,7 +20,6 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE -#define post_code(x) intel_chip_post_macro(x) #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Thu Apr 1 11:50:32 2010 (r5344) @@ -20,7 +20,6 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE -#define post_code(x) intel_chip_post_macro(x) #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> Modified: trunk/src/cpu/x86/32bit/entry32.inc ============================================================================== --- trunk/src/cpu/x86/32bit/entry32.inc Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/cpu/x86/32bit/entry32.inc Thu Apr 1 11:50:32 2010 (r5344) @@ -50,7 +50,7 @@ /* Save the BIST value */ movl %eax, %ebp - intel_chip_post_macro(0x10) /* post 10 */ + post_code(0x10) /* post 10 */ movw $ROM_DATA_SEG, %ax movw %ax, %ds Modified: trunk/src/include/console/console.h ============================================================================== --- trunk/src/include/console/console.h Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/include/console/console.h Thu Apr 1 11:50:32 2010 (r5344) @@ -10,7 +10,7 @@ void console_tx_flush(void); unsigned char console_rx_byte(void); int console_tst_byte(void); -void post_code(uint8_t value); +void post_code(u8 value); void __attribute__ ((noreturn)) die(const char *msg); #if CONFIG_CONSOLE_VGA == 1 void vga_console_init(void); @@ -31,7 +31,14 @@ extern struct console_driver econsole_drivers[]; extern int console_loglevel; -#endif /* !__PRE_RAM__ */ +#else +/* __PRE_RAM__ */ +/* Using a global varible can cause problems when we reset the stack + * from cache as ram to ram. If we make this a define USE_SHARED_STACK + * we could use the same code on all architectures. + */ +#define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL +#endif #ifndef __ROMCC__ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); @@ -121,6 +128,8 @@ #define print_debug_hex32(HEX) printk(BIOS_DEBUG, "%08x", (HEX)) #define print_spew_hex32(HEX) printk(BIOS_SPEW, "%08x", (HEX)) #else + + /* __ROMCC__ */ static void __console_tx_byte(unsigned char byte) { @@ -139,14 +148,14 @@ static void __console_tx_char(int loglevel, unsigned char byte) { - if (ASM_CONSOLE_LOGLEVEL >= loglevel) { + if (console_loglevel >= loglevel) { uart_tx_byte(byte); } } static void __console_tx_hex8(int loglevel, unsigned char value) { - if (ASM_CONSOLE_LOGLEVEL >= loglevel) { + if (console_loglevel >= loglevel) { __console_tx_nibble((value >> 4U) & 0x0fU); __console_tx_nibble(value & 0x0fU); } @@ -154,7 +163,7 @@ static void __console_tx_hex16(int loglevel, unsigned short value) { - if (ASM_CONSOLE_LOGLEVEL >= loglevel) { + if (console_loglevel >= loglevel) { __console_tx_nibble((value >> 12U) & 0x0fU); __console_tx_nibble((value >> 8U) & 0x0fU); __console_tx_nibble((value >> 4U) & 0x0fU); @@ -164,7 +173,7 @@ static void __console_tx_hex32(int loglevel, unsigned int value) { - if (ASM_CONSOLE_LOGLEVEL >= loglevel) { + if (console_loglevel >= loglevel) { __console_tx_nibble((value >> 28U) & 0x0fU); __console_tx_nibble((value >> 24U) & 0x0fU); __console_tx_nibble((value >> 20U) & 0x0fU); @@ -178,7 +187,7 @@ static void __console_tx_string(int loglevel, const char *str) { - if (ASM_CONSOLE_LOGLEVEL >= loglevel) { + if (console_loglevel >= loglevel) { unsigned char ch; while((ch = *str++) != '\0') { if (ch == '\n') Modified: trunk/src/include/console/loglevel.h ============================================================================== --- trunk/src/include/console/loglevel.h Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/include/console/loglevel.h Thu Apr 1 11:50:32 2010 (r5344) @@ -2,11 +2,6 @@ #define LOGLEVEL_H /* Safe for inclusion in assembly */ - -#ifndef ASM_CONSOLE_LOGLEVEL -#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -#endif - #define BIOS_EMERG 0 /* system is unusable */ #define BIOS_ALERT 1 /* action must be taken immediately */ #define BIOS_CRIT 2 /* critical conditions */ Modified: trunk/src/mainboard/amd/db800/romstage.c ============================================================================== --- trunk/src/mainboard/amd/db800/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/amd/db800/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -33,7 +33,6 @@ #include "southbridge/amd/cs5536/cs5536.h" #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) -#define POST_CODE(x) outb(x, 0x80) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #include "southbridge/amd/cs5536/cs5536_early_smbus.c" @@ -98,7 +97,7 @@ void cache_as_ram_main(void) { - POST_CODE(0x01); + post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -45,8 +45,6 @@ #include "pc80/serial.c" #include "console/console.c" -#define post_code(x) outb(x, 0x80) - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/amd/mahogany/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -45,8 +45,6 @@ #include "pc80/serial.c" #include "console/console.c" -#define post_code(x) outb(x, 0x80) - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" Modified: trunk/src/mainboard/amd/norwich/romstage.c ============================================================================== --- trunk/src/mainboard/amd/norwich/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/amd/norwich/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -32,8 +32,6 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" -#define POST_CODE(x) outb(x, 0x80) - #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" @@ -95,7 +93,7 @@ void cache_as_ram_main(void) { - POST_CODE(0x01); + post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} Modified: trunk/src/mainboard/amd/pistachio/romstage.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/amd/pistachio/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -39,8 +39,6 @@ #include "pc80/serial.c" #include "console/console.c" -#define post_code(x) outb(x, 0x80) - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" Modified: trunk/src/mainboard/artecgroup/dbe61/romstage.c ============================================================================== --- trunk/src/mainboard/artecgroup/dbe61/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/artecgroup/dbe61/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -35,8 +35,6 @@ #include "southbridge/amd/cs5536/cs5536.h" #include "spd_table.h" -#define POST_CODE(x) outb(x, 0x80) - #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" @@ -112,7 +110,7 @@ void cache_as_ram_main(void) { - POST_CODE(0x01); + post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} Modified: trunk/src/mainboard/broadcom/blast/romstage.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/broadcom/blast/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -17,17 +17,6 @@ #include "console/console.c" #include "lib/ramtest.c" -#if 0 -static void post_code(uint8_t value) { -#if 0 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -1,4 +1,3 @@ -#define ASM_CONSOLE_LOGLEVEL 8 #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> Modified: trunk/src/mainboard/digitallogic/msm586seg/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/digitallogic/msm586seg/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -1,4 +1,3 @@ -#define ASM_CONSOLE_LOGLEVEL 8 #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm800sev/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -13,7 +13,6 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" -#define POST_CODE(x) outb(x, 0x80) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #include "southbridge/amd/cs5536/cs5536_early_smbus.c" @@ -63,7 +62,7 @@ void cache_as_ram_main(void) { extern void RestartCAR(); - POST_CODE(0x01); + post_code(0x01); static const struct mem_controller memctrl [] = { {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} @@ -105,7 +104,7 @@ We use method 1 on Norwich. */ - POST_CODE(0x02); + post_code(0x02); print_err("POST 02\n"); __asm__("wbinvd\n"); print_err("Past wbinvd\n"); Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -32,7 +32,6 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" -#define POST_CODE(x) outb(x, 0x80) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #include "southbridge/amd/cs5536/cs5536_early_smbus.c" @@ -102,7 +101,7 @@ void cache_as_ram_main(void) { - POST_CODE(0x01); + post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/kontron/kt690/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -46,8 +46,6 @@ #include "pc80/serial.c" #include "console/console.c" -#define post_code(x) outb(x, 0x80) - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" Modified: trunk/src/mainboard/lippert/roadrunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -36,8 +36,6 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" -#define POST_CODE(x) outb(x, 0x80) - #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" #include "superio/ite/it8712f/it8712f_early_serial.c" @@ -132,7 +130,7 @@ void cache_as_ram_main(void) { - POST_CODE(0x01); + post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -37,8 +37,6 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" -#define POST_CODE(x) outb(x, 0x80) - #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" #include "superio/ite/it8712f/it8712f_early_serial.c" @@ -194,7 +192,7 @@ void cache_as_ram_main(void) { int err; - POST_CODE(0x01); + post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/msi/ms9185/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -52,17 +52,6 @@ #include "pc80/serial.c" #include "console/console.c" -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - #include <cpu/amd/model_fxx_rev.h> #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/newisys/khepri/romstage.c ============================================================================== --- trunk/src/mainboard/newisys/khepri/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/newisys/khepri/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -18,17 +18,6 @@ #include "console/console.c" #include "lib/ramtest.c" -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/pcengines/alix1c/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -33,7 +33,6 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" -#define POST_CODE(x) outb(x, 0x80) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) /* The ALIX1.C has no SMBus; the setup is hard-wired. */ @@ -148,7 +147,7 @@ extern void RestartCAR(); - POST_CODE(0x01); + post_code(0x01); SystemPreInit(); msr_init(); @@ -195,7 +194,7 @@ * * We use method 1 on Norwich and on this board too. */ - POST_CODE(0x02); + post_code(0x02); print_err("POST 02\n"); __asm__("wbinvd\n"); print_err("Past wbinvd\n"); Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -45,8 +45,6 @@ #include "pc80/serial.c" #include "console/console.c" -#define post_code(x) outb(x, 0x80) - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -45,8 +45,6 @@ #include "pc80/serial.c" #include "console/console.c" -#define post_code(x) outb(x, 0x80) - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" Modified: trunk/src/mainboard/technologic/ts5300/romstage.c ============================================================================== --- trunk/src/mainboard/technologic/ts5300/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/technologic/ts5300/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -4,7 +4,6 @@ * (c) 2006 coresystems GmbH */ -#define ASM_CONSOLE_LOGLEVEL 6 #include <stdint.h> #include <device/pci_def.h> #include <arch/io.h> Modified: trunk/src/mainboard/tyan/s2850/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2850/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/tyan/s2850/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -13,17 +13,6 @@ #include "console/console.c" #include "lib/ramtest.c" -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/amd/amd8111/amd8111_early_smbus.c" Modified: trunk/src/mainboard/tyan/s2881/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2881/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/tyan/s2881/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -17,17 +17,6 @@ #include "console/console.c" #include "lib/ramtest.c" -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" Modified: trunk/src/mainboard/tyan/s2885/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2885/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/tyan/s2885/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -12,17 +12,6 @@ #include "console/console.c" #include "lib/ramtest.c" -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif - #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" Modified: trunk/src/mainboard/winent/pl6064/romstage.c ============================================================================== --- trunk/src/mainboard/winent/pl6064/romstage.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/mainboard/winent/pl6064/romstage.c Thu Apr 1 11:50:32 2010 (r5344) @@ -34,7 +34,6 @@ #include "southbridge/amd/cs5536/cs5536.h" #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) -#define POST_CODE(x) outb(x, 0x80) #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #include "southbridge/amd/cs5536/cs5536_early_smbus.c" @@ -99,7 +98,7 @@ void cache_as_ram_main(void) { - POST_CODE(0x01); + post_code(0x01); static const struct mem_controller memctrl[] = { {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} Modified: trunk/src/northbridge/amd/gx2/pll_reset.c ============================================================================== --- trunk/src/northbridge/amd/gx2/pll_reset.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/northbridge/amd/gx2/pll_reset.c Thu Apr 1 11:50:32 2010 (r5344) @@ -115,7 +115,6 @@ #if USE_GOODRICH_VERSION /////////////////////////////////////////////////////////////////////////////// // Goodrich Version of pll_reset -#define POST_CODE(x) outb(x, 0x80) // PLLCHECK_COMPLETED is the "we've already done this" flag #define PLLCHECK_COMPLETED (1 << RSTPLL_LOWER_SWFLAGS_SHIFT) @@ -149,7 +148,7 @@ // Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the // correct Strap Table. - POST_CODE(POST_PLL_INIT); + post_code(POST_PLL_INIT); // configure for DDR msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT); @@ -157,7 +156,7 @@ // Use Manual settings // UseManual: - POST_CODE(POST_PLL_MANUAL); + post_code(POST_PLL_MANUAL); // DIV settings manually entered. // ax = VDIV, upper eax = MDIV, upper ecx = FbDIV @@ -237,7 +236,7 @@ wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll); // You should never get here..... The chip has reset. - POST_CODE(POST_PLL_RESET_FAIL); + post_code(POST_PLL_RESET_FAIL); while (1); } // we haven't configured the PLL; do it now Modified: trunk/src/northbridge/amd/lx/pll_reset.c ============================================================================== --- trunk/src/northbridge/amd/lx/pll_reset.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/northbridge/amd/lx/pll_reset.c Thu Apr 1 11:50:32 2010 (r5344) @@ -31,12 +31,12 @@ print_debug(":"); print_debug_hex32(msrGlcpSysRstpll.lo); print_debug("\n"); - POST_CODE(POST_PLL_INIT); + post_code(POST_PLL_INIT); if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) { print_debug("Configuring PLL\n"); if (manualconf) { - POST_CODE(POST_PLL_MANUAL); + post_code(POST_PLL_MANUAL); /* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */ msrGlcpSysRstpll.hi = PLLMSRhi; @@ -44,7 +44,7 @@ msrGlcpSysRstpll.lo = PLLMSRlo; } else { /*automatic configuration (straps) */ - POST_CODE(POST_PLL_STRAP); + post_code(POST_PLL_STRAP); msrGlcpSysRstpll.lo &= ~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT); msrGlcpSysRstpll.lo |= @@ -64,7 +64,7 @@ /* You should never get here..... The chip has reset. */ print_debug("CONFIGURING PLL FAILURE\n"); - POST_CODE(POST_PLL_RESET_FAIL); + post_code(POST_PLL_RESET_FAIL); __asm__ __volatile__("hlt\n"); } Modified: trunk/src/northbridge/amd/lx/raminit.c ============================================================================== --- trunk/src/northbridge/amd/lx/raminit.c Wed Mar 31 16:57:55 2010 (r5343) +++ trunk/src/northbridge/amd/lx/raminit.c Thu Apr 1 11:50:32 2010 (r5344) @@ -67,7 +67,7 @@ spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS); if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) { print_emerg("Number of module banks not compatible\n"); - POST_CODE(ERROR_BANK_SET); + post_code(ERROR_BANK_SET); hcf(); } dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT; @@ -78,7 +78,7 @@ spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM); if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) { print_emerg("Number of device banks not compatible\n"); - POST_CODE(ERROR_BANK_SET); + post_code(ERROR_BANK_SET); hcf(); } dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT; @@ -94,7 +94,7 @@ if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0) || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) { print_emerg("Assymetirc DIMM not compatible\n"); - POST_CODE(ERROR_UNSUPPORTED_DIMM); + post_code(ERROR_UNSUPPORTED_DIMM); hcf(); } banner("SPDBANKDENSITY"); @@ -111,7 +111,7 @@ banner("TEST DIMM SIZE>8"); if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */ print_emerg("Only support up to 1 GB per DIMM\n"); - POST_CODE(ERROR_DENSITY_DIMM); + post_code(ERROR_DENSITY_DIMM); hcf(); } dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT; @@ -144,7 +144,7 @@ banner("MAXCOLADDR"); if (spd_byte > MAX_COL_ADDR) { print_emerg("DIMM page size not compatible\n"); - POST_CODE(ERROR_SET_PAGE); + post_code(ERROR_SET_PAGE); hcf(); } banner(">12address test"); @@ -186,7 +186,7 @@ /* I don't think you need this check. if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0){ print_emerg("DIMM overclocked. Check GeodeLink Speed\n"); - POST_CODE(POST_PLL_MEM_FAIL); + post_code(POST_PLL_MEM_FAIL); hcf(); } */ @@ -201,7 +201,7 @@ /* current speed > max speed? */ if (GeodeLinkSpeed() > speed) { print_emerg("DIMM overclocked. Check GeodeLink Speed\n"); - POST_CODE(POST_PLL_MEM_FAIL); + post_code(POST_PLL_MEM_FAIL); hcf(); } } @@ -341,7 +341,7 @@ spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)]; } else { print_emerg("DIMM CAS Latencies not compatible\n"); - POST_CODE(ERROR_DIFF_DIMMS); + post_code(ERROR_DIFF_DIMMS); hcf(); } @@ -570,41 +570,41 @@ uint8_t spd_byte; banner("sdram_set_spd_register\n"); - POST_CODE(POST_MEM_SETUP); // post_70h + post_code(POST_MEM_SETUP); // post_70h spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES); banner("Check DIMM 0"); /* Check DIMM is not Register and not Buffered DIMMs. */ if ((spd_byte != 0xFF) && (spd_byte & 3)) { print_emerg("DIMM0 NOT COMPATIBLE\n"); - POST_CODE(ERROR_UNSUPPORTED_DIMM); + post_code(ERROR_UNSUPPORTED_DIMM); hcf(); } banner("Check DIMM 1"); spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES); if ((spd_byte != 0xFF) && (spd_byte & 3)) { print_emerg("DIMM1 NOT COMPATIBLE\n"); - POST_CODE(ERROR_UNSUPPORTED_DIMM); + post_code(ERROR_UNSUPPORTED_DIMM); hcf(); } - POST_CODE(POST_MEM_SETUP2); // post_72h + post_code(POST_MEM_SETUP2); // post_72h banner("Check DDR MAX"); /* Check that the memory is not overclocked. */ checkDDRMax(); /* Size the DIMMS */ - POST_CODE(POST_MEM_SETUP3); // post_73h + post_code(POST_MEM_SETUP3); // post_73h banner("AUTOSIZE DIMM 0"); auto_size_dimm(DIMM0); - POST_CODE(POST_MEM_SETUP4); // post_74h + post_code(POST_MEM_SETUP4); // post_74h banner("AUTOSIZE DIMM 1"); auto_size_dimm(DIMM1); /* Set CAS latency */ banner("set cas latency"); - POST_CODE(POST_MEM_SETUP5); // post_75h + post_code(POST_MEM_SETUP5); // post_75h setCAS(); /* Set all the other latencies here (tRAS, tRP....) */ @@ -640,7 +640,7 @@ ;* 9) MRS w/ memory config & reset DLL clear ;* 8) DDR SDRAM ready for normal operation ;********************************************************************/ - POST_CODE(POST_MEM_ENABLE); // post_76h + post_code(POST_MEM_ENABLE); // post_76h /* Only enable MTest for TLA memory debug */ /*EnableMTest(); */ @@ -650,7 +650,7 @@ if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) == ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) { print_emerg("No memory in the system\n"); - POST_CODE(ERROR_NO_DIMMS); + post_code(ERROR_NO_DIMMS); hcf(); } @@ -760,7 +760,7 @@ wrmsr(msrnum, msr); print_emerg("DRAM controller init done.\n"); - POST_CODE(POST_MEM_SETUP_GOOD); //0x7E + post_code(POST_MEM_SETUP_GOOD); //0x7E /* make sure there is nothing stale in the cache */ /* CAR stack is in the cache __asm__ __volatile__("wbinvd\n"); */

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coreboot April 2010