coreboot April 2010

coreboot@coreboot.org

64 participants
402 discussions

[commit] r5351 - trunk/util/romcc
by repository service 03 Apr '10

03 Apr '10

Author: stepan Date: Sat Apr 3 02:03:07 2010 New Revision: 5351 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5351 Log: Add noreturn attribute to die() in romcc. This makes life a lot easier for static analyzers such as scan-build. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/romcc/romcc.c Modified: trunk/util/romcc/romcc.c ============================================================================== --- trunk/util/romcc/romcc.c Sat Apr 3 00:31:35 2010 (r5350) +++ trunk/util/romcc/romcc.c Sat Apr 3 02:03:07 2010 (r5351) @@ -135,7 +135,7 @@ struct filelist *include_filelist = NULL; -static void die(char *fmt, ...) +static void __attribute__((noreturn)) die(char *fmt, ...) { va_list args;

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[PATCH] continue cleaning up log levels
by Myles Watson 03 Apr '10

03 Apr '10

x86_emu_debug.diff: Change DEBUG for the emulator to DEBUG_EMU to avoid conflicts with DEBUG for log levels. loglevel.diff: Remove BIOS_EMERG, BIOS_ALERT, BIOS_CRIT, BIOS_NOTICE, BIOS_NEVER I didn't change their numerical values. They were rarely used. BIOS_EMERG, BIOS_ALERT, BIOS_CRIT -> BIOS_ERR BIOS_NOTICE -> BIOS_INFO BIOS_NEVER -> BIOS_SPEW+1 loglevel2.diff: BIOS_ERR -> ERROR BIOS_WARNING -> WARNING BIOS_INFO -> INFO BIOS_DEBUG -> DEBUG BIOS_SPEW -> SPEW For 80 character line aficionados, this puts most of the lines back, since printk_debug(...) is about the same length as printk(DEBUG, ...) I didn't change llshell in any of these patches. It would be easy to add. Abuild tested. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Thanks, Myles

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[commit] r5350 - in trunk/src: cpu/amd/model_gx2 northbridge/amd/amdht northbridge/amd/gx2 southbridge/amd/rs780
by repository service 03 Apr '10

03 Apr '10

Author: stepan Date: Sat Apr 3 00:31:35 2010 New Revision: 5350 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5350 Log: remove more warnings. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/amd/model_gx2/cpubug.c trunk/src/northbridge/amd/amdht/h3finit.h trunk/src/northbridge/amd/amdht/h3ncmn.c trunk/src/northbridge/amd/gx2/northbridgeinit.c trunk/src/southbridge/amd/rs780/rs780_early_setup.c Modified: trunk/src/cpu/amd/model_gx2/cpubug.c ============================================================================== --- trunk/src/cpu/amd/model_gx2/cpubug.c Sat Apr 3 00:13:27 2010 (r5349) +++ trunk/src/cpu/amd/model_gx2/cpubug.c Sat Apr 3 00:31:35 2010 (r5350) @@ -92,7 +92,7 @@ * ****************************************************************************/ -void bug784(void) +static void bug784(void) { msr_t msr; //static char *name = "Geode by NSC"; @@ -133,7 +133,7 @@ * Modified: * **************************************************************************/ -void eng1398(void) +static void eng1398(void) { msr_t msr; @@ -164,7 +164,7 @@ * Modified: * **************************************************************************/ -void +static void eng2900(void) { msr_t msr; @@ -248,7 +248,7 @@ } } -void bug118253(void) +static void bug118253(void) { /* GLPCI PIO Post Control shouldn't be enabled */ msr_t msr; @@ -258,7 +258,7 @@ wrmsr(GLPCI_SPARE, msr); } -void bug118339(void) +static void bug118339(void) { /* per AMD, do this always */ msr_t msr = {0,0}; @@ -337,7 +337,7 @@ /** Modified:*/ /***/ /****************************************************************************/ -void disablememoryreadorder(void) +static void disablememoryreadorder(void) { msr_t msr; msr = rdmsr(MC_CF8F_DATA); Modified: trunk/src/northbridge/amd/amdht/h3finit.h ============================================================================== --- trunk/src/northbridge/amd/amdht/h3finit.h Sat Apr 3 00:13:27 2010 (r5349) +++ trunk/src/northbridge/amd/amdht/h3finit.h Sat Apr 3 00:31:35 2010 (r5350) @@ -353,7 +353,7 @@ * * --------------------------------------------------------------------------------------- */ - BOOL (*AMD_CB_CustomizeTrafficDistribution)(); + BOOL (*AMD_CB_CustomizeTrafficDistribution)( void ); /**---------------------------------------------------------------------------------------- Modified: trunk/src/northbridge/amd/amdht/h3ncmn.c ============================================================================== --- trunk/src/northbridge/amd/amdht/h3ncmn.c Sat Apr 3 00:13:27 2010 (r5349) +++ trunk/src/northbridge/amd/amdht/h3ncmn.c Sat Apr 3 00:31:35 2010 (r5350) @@ -1041,7 +1041,7 @@ /**---------------------------------------------------------------------------------------- * - * void + * static void * ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb) * * Description: @@ -1058,7 +1058,7 @@ * * --------------------------------------------------------------------------------------- */ -void ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb) +static void ht1SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb) { u8 curNode; SBDFO linkBase; Modified: trunk/src/northbridge/amd/gx2/northbridgeinit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridgeinit.c Sat Apr 3 00:13:27 2010 (r5349) +++ trunk/src/northbridge/amd/gx2/northbridgeinit.c Sat Apr 3 00:31:35 2010 (r5350) @@ -704,7 +704,6 @@ int i; msr_t msr; uint8_t SysMemCacheProp; - uint8_t RegionProp; /* Locate SYSMEM entry in GLIU0table */ for(i = 0; gliu0table[i].desc_name != GL_END; i++) { Modified: trunk/src/southbridge/amd/rs780/rs780_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_early_setup.c Sat Apr 3 00:13:27 2010 (r5349) +++ trunk/src/southbridge/amd/rs780/rs780_early_setup.c Sat Apr 3 00:31:35 2010 (r5350) @@ -17,6 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef CONFIG_NORTHBRIDGE_AMD_AMDFAM10 +#define CONFIG_NORTHBRIDGE_AMD_AMDFAM10 0 +#endif + #include "rs780_rev.h" #define NBHTIU_INDEX 0x94 /* Note: It is different with RS690, whose HTIU index is 0xA8 */ @@ -142,7 +146,7 @@ } } -static void get_cpu_rev() +static void get_cpu_rev(void) { u32 eax; @@ -168,17 +172,17 @@ printk(BIOS_INFO, "CPU Rev is K8_10.\n"); } -static u8 is_famly10() +static u8 is_famly10(void) { return (cpuid_eax(1) & 0xff00000) != 0; } -static u8 l3_cache() +static u8 l3_cache(void) { return (cpuid_edx(0x80000006) & (0x3FFF << 18)) != 0; } -static u8 cpu_core_number() +static u8 cpu_core_number(void) { return (cpuid_ecx(0x80000008) & 0xFF) + 1; } @@ -226,7 +230,7 @@ [0xe] = 0xC6, /* 2.6Ghz HyperTransport 3 only */ }; -static void rs780_htinit() +static void rs780_htinit(void) { /* * About HT, it has been done in enumerate_ht_chain(). @@ -325,7 +329,7 @@ * Function2: DRAM and HT technology Trace mode configuration * Function3: Miscellaneous configuration *******************************************************/ -static void k8_optimization() +static void k8_optimization(void) { device_t k8_f0, k8_f2, k8_f3; msr_t msr; @@ -367,7 +371,7 @@ #endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */ #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */ -void fam10_optimization() +void fam10_optimization(void) { device_t cpu_f0, cpu_f2, cpu_f3; msr_t msr;

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[commit] r5348 - in trunk/src: cpu/amd/model_gx2 include/console mainboard/advantech/pcm-5820 mainboard/amd/db800 northbridge/amd/lx southbridge/amd/cs5536
by repository service 03 Apr '10

03 Apr '10

Author: stepan Date: Sat Apr 3 00:11:20 2010 New Revision: 5348 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5348 Log: remove some more warnings Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/amd/model_gx2/vsmsetup.c trunk/src/include/console/console.h trunk/src/mainboard/advantech/pcm-5820/irq_tables.c trunk/src/mainboard/amd/db800/romstage.c trunk/src/northbridge/amd/lx/pll_reset.c trunk/src/northbridge/amd/lx/raminit.c trunk/src/southbridge/amd/cs5536/cs5536.c trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c Modified: trunk/src/cpu/amd/model_gx2/vsmsetup.c ============================================================================== --- trunk/src/cpu/amd/model_gx2/vsmsetup.c Fri Apr 2 23:39:12 2010 (r5347) +++ trunk/src/cpu/amd/model_gx2/vsmsetup.c Sat Apr 3 00:11:20 2010 (r5348) @@ -35,7 +35,6 @@ #include <arch/io.h> #include <cbfs.h> -u32 VSA_vrRead(u16 classIndex); void do_vsmbios(void); #define VSA2_BUFFER 0x60000 @@ -150,7 +149,7 @@ /* andrei: Some VSA virtual register helpers: raw read and MSR read. */ -u32 VSA_vrRead(u16 classIndex) +static u32 VSA_vrRead(u16 classIndex) { unsigned eax, ebx, ecx, edx; asm volatile ( @@ -166,7 +165,7 @@ return eax; } -u32 VSA_msrRead(u32 msrAddr) +static u32 VSA_msrRead(u32 msrAddr) { unsigned eax, ebx, ecx, edx; asm volatile ( Modified: trunk/src/include/console/console.h ============================================================================== --- trunk/src/include/console/console.h Fri Apr 2 23:39:12 2010 (r5347) +++ trunk/src/include/console/console.h Sat Apr 3 00:11:20 2010 (r5348) @@ -44,6 +44,9 @@ #endif #ifndef __ROMCC__ +void console_init(void); +void post_code(u8 value); +void __attribute__ ((noreturn)) die(const char *msg); int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); #undef WE_CLEANED_UP_ALL_SIDE_EFFECTS Modified: trunk/src/mainboard/advantech/pcm-5820/irq_tables.c ============================================================================== --- trunk/src/mainboard/advantech/pcm-5820/irq_tables.c Fri Apr 2 23:39:12 2010 (r5347) +++ trunk/src/mainboard/advantech/pcm-5820/irq_tables.c Sat Apr 3 00:11:20 2010 (r5348) @@ -30,7 +30,7 @@ 0x1078, /* Vendor */ 0x2, /* Device */ 0, /* Crap (miniport) */ - // { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ 0xde, /* Checksum */ { /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ Modified: trunk/src/mainboard/amd/db800/romstage.c ============================================================================== --- trunk/src/mainboard/amd/db800/romstage.c Fri Apr 2 23:39:12 2010 (r5347) +++ trunk/src/mainboard/amd/db800/romstage.c Sat Apr 3 00:11:20 2010 (r5348) @@ -24,6 +24,7 @@ #include <device/pnp_def.h> #include <arch/hlt.h> #include "pc80/serial.c" +#include <console/console.h> #include "console/console.c" #include "lib/ramtest.c" #include "cpu/x86/bist.h" Modified: trunk/src/northbridge/amd/lx/pll_reset.c ============================================================================== --- trunk/src/northbridge/amd/lx/pll_reset.c Fri Apr 2 23:39:12 2010 (r5347) +++ trunk/src/northbridge/amd/lx/pll_reset.c Sat Apr 3 00:11:20 2010 (r5348) @@ -72,6 +72,7 @@ return; } +#if 0 // Unused static unsigned int CPUSpeed(void) { unsigned int speed; @@ -84,6 +85,8 @@ } return (speed); } +#endif + static unsigned int GeodeLinkSpeed(void) { unsigned int speed; @@ -96,6 +99,8 @@ } return (speed); } + +#if 0 // Unused static unsigned int PCISpeed(void) { msr_t msr; @@ -107,3 +112,4 @@ return (33); } } +#endif Modified: trunk/src/northbridge/amd/lx/raminit.c ============================================================================== --- trunk/src/northbridge/amd/lx/raminit.c Fri Apr 2 23:39:12 2010 (r5347) +++ trunk/src/northbridge/amd/lx/raminit.c Sat Apr 3 00:11:20 2010 (r5348) @@ -514,6 +514,8 @@ wrmsr(MC_CF07_DATA, msr); } +#undef TLA_MEMORY_DEBUG +#ifdef TLA_MEMORY_DEBUG static void EnableMTest(void) { msr_t msr; @@ -534,6 +536,7 @@ print_info("Enabled MTest for TLA debug\n"); } +#endif static void sdram_set_registers(const struct mem_controller *ctrl) { @@ -642,8 +645,10 @@ ;********************************************************************/ post_code(POST_MEM_ENABLE); // post_76h +#ifdef TLA_MEMORY_DEBUG /* Only enable MTest for TLA memory debug */ - /*EnableMTest(); */ + EnableMTest(); +#endif /* If both Page Size = "Not Installed" we have a problems and should halt. */ msr = rdmsr(MC_CF07_DATA); Modified: trunk/src/southbridge/amd/cs5536/cs5536.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536.c Fri Apr 2 23:39:12 2010 (r5347) +++ trunk/src/southbridge/amd/cs5536/cs5536.c Sat Apr 3 00:11:20 2010 (r5348) @@ -77,7 +77,7 @@ {PMS_IO_BASE + PM_SIDD, 0x000008C02}, {PMS_IO_BASE + PM_WKD, 0x0000000A0}, {PMS_IO_BASE + PM_WKXD, 0x0000000A0}, - {0, 0, 0} + {0, 0} }; struct FLASH_DEVICE { @@ -197,7 +197,7 @@ /* Run after VSA init to enable the flash PCI device header */ /* **/ /* ***************************************************************************/ -static void enable_ide_nand_flash_header() +static void enable_ide_nand_flash_header(void) { /* Tell VSA to use FLASH PCI header. Not IDE header. */ outl(0x80007A40, 0xCF8); Modified: trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c Fri Apr 2 23:39:12 2010 (r5347) +++ trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c Sat Apr 3 00:11:20 2010 (r5348) @@ -156,7 +156,7 @@ * * See page 412 of the AMD Geode CS5536 Companion Device data book. */ -void cs5536_setup_onchipuart1(void) +static void cs5536_setup_onchipuart1(void) { msr_t msr; @@ -196,7 +196,7 @@ wrmsr(MDD_UART1_CONF, msr); } -void cs5536_setup_onchipuart2(void) +static void cs5536_setup_onchipuart2(void) { msr_t msr;

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[commit] r5349 - trunk/src/include/console
by repository service 03 Apr '10

03 Apr '10

Author: stepan Date: Sat Apr 3 00:13:27 2010 New Revision: 5349 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5349 Log: oops, sorry, overlapping work Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/include/console/console.h Modified: trunk/src/include/console/console.h ============================================================================== --- trunk/src/include/console/console.h Sat Apr 3 00:11:20 2010 (r5348) +++ trunk/src/include/console/console.h Sat Apr 3 00:13:27 2010 (r5349) @@ -4,12 +4,6 @@ #include <stdint.h> #include <console/loglevel.h> -#ifndef __ROMCC__ -void console_init(void); -void post_code(u8 value); -void __attribute__ ((noreturn)) die(const char *msg); -#endif - #ifndef __PRE_RAM__ void console_tx_byte(unsigned char byte); void console_tx_flush(void);

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[commit] r5347 - in trunk/src/include: . console
by repository service 02 Apr '10

02 Apr '10

Author: myles Date: Fri Apr 2 23:39:12 2010 New Revision: 5347 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5347 Log: Fix console prototypes for non-romcc boards. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/include/console/console.h trunk/src/include/lib.h Modified: trunk/src/include/console/console.h ============================================================================== --- trunk/src/include/console/console.h Fri Apr 2 22:14:21 2010 (r5346) +++ trunk/src/include/console/console.h Fri Apr 2 23:39:12 2010 (r5347) @@ -4,14 +4,17 @@ #include <stdint.h> #include <console/loglevel.h> -#ifndef __PRE_RAM__ +#ifndef __ROMCC__ void console_init(void); +void post_code(u8 value); +void __attribute__ ((noreturn)) die(const char *msg); +#endif + +#ifndef __PRE_RAM__ void console_tx_byte(unsigned char byte); void console_tx_flush(void); unsigned char console_rx_byte(void); int console_tst_byte(void); -void post_code(u8 value); -void __attribute__ ((noreturn)) die(const char *msg); #if CONFIG_CONSOLE_VGA == 1 void vga_console_init(void); #endif Modified: trunk/src/include/lib.h ============================================================================== --- trunk/src/include/lib.h Fri Apr 2 22:14:21 2010 (r5346) +++ trunk/src/include/lib.h Fri Apr 2 23:39:12 2010 (r5347) @@ -37,6 +37,7 @@ /* Defined in src/lib/ramtest.c */ void ram_check(unsigned long start, unsigned long stop); +void quick_ram_check(void); /* Defined in src/pc80/serial.c */ void uart_init(void);

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[commit] r5346 - trunk/src/northbridge/amd/amdk8
by repository service 02 Apr '10

02 Apr '10

Author: myles Date: Fri Apr 2 22:14:21 2010 New Revision: 5346 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5346 Log: Fix includes for showallroutes. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/northbridge/amd/amdk8/amdk8.h trunk/src/northbridge/amd/amdk8/util.c Modified: trunk/src/northbridge/amd/amdk8/amdk8.h ============================================================================== --- trunk/src/northbridge/amd/amdk8/amdk8.h Fri Apr 2 18:30:25 2010 (r5345) +++ trunk/src/northbridge/amd/amdk8/amdk8.h Fri Apr 2 22:14:21 2010 (r5346) @@ -8,7 +8,7 @@ #include "amdk8_pre_f.h" #endif -#ifndef __PRE_RAM__ +#ifndef __ROMCC__ void showallroutes(int level, device_t dev); #endif Modified: trunk/src/northbridge/amd/amdk8/util.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/util.c Fri Apr 2 18:30:25 2010 (r5345) +++ trunk/src/northbridge/amd/amdk8/util.c Fri Apr 2 22:14:21 2010 (r5346) @@ -27,12 +27,10 @@ */ #ifndef __PRE_RAM__ #include <console/console.h> -#include <string.h> #include <device/pci.h> -#include <cpu/amd/amdk8_sysconf.h> #include <device/pci_ops.h> -#include "amdk8.h" #endif +#include "amdk8.h" /* Function 1 */ /* the DRAM, MMIO,and PCIIO routing are 64-bit registers, hence the ending at

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[commit] r5345 - trunk/src/devices
by repository service 02 Apr '10

02 Apr '10

Author: stepan Date: Fri Apr 2 18:30:25 2010 New Revision: 5345 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5345 Log: The error message is misleading, even for a SPEW, because the slot is empty, it's NOT a bad ID (and the message is more confusing than helpful even in SPEW) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/devices/pci_device.c Modified: trunk/src/devices/pci_device.c ============================================================================== --- trunk/src/devices/pci_device.c Thu Apr 1 11:50:32 2010 (r5344) +++ trunk/src/devices/pci_device.c Fri Apr 2 18:30:25 2010 (r5345) @@ -910,10 +910,14 @@ dummy.path.pci.devfn = devfn; id = pci_read_config32(&dummy, PCI_VENDOR_ID); /* Have we found something? - * Some broken boards return 0 if a slot is empty. + * Some broken boards return 0 if a slot is empty, but + * the expected answer is 0xffffffff */ - if ((id == 0xffffffff) || (id == 0x00000000) || - (id == 0x0000ffff) || (id == 0xffff0000)) { + if (id == 0xffffffff) { + return NULL; + } + if ((id == 0x00000000) || (id == 0x0000ffff) || + (id == 0xffff0000)) { printk(BIOS_SPEW, "%s, bad id 0x%x\n", dev_path(&dummy), id); return NULL; }

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[PATCH] remove annoying noisy message
by Stefan Reinauer 02 Apr '10

02 Apr '10

See patch

3 4

patch for avoding amd64 compiling error
by Qing Pei Wang 02 Apr '10

02 Apr '10

the patch make filo can compiling well without any parameters of make Signed-off-by: Wang Qing Pei <wangqingpei(a)gmal.com> -- Wang Qing Pei MSN:wangqingpei@hotmail.com <MSN%3Awangqingpei(a)hotmail.com> Gmail:wangqingpei@gmail.com <Gmail%3Awangqingpei(a)gmail.com> Phone:86+13426369984

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coreboot April 2010