coreboot April 2010

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build service results for r5363
by coreboot information 07 Apr '10

07 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5363 to the coreboot repository. This caused the following changes: Change Log: "no warnings day" last round for today. still warnings - help appreciated. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of via:epia-m700 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5363&device=epia-m700&vend… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5365 - trunk/src/mainboard/asrock/939a785gmh
by repository service 07 Apr '10

07 Apr '10

Author: stepan Date: Wed Apr 7 04:09:54 2010 New Revision: 5365 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5365 Log: no duplicate names in cmos.layout. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/asrock/939a785gmh/cmos.layout Modified: trunk/src/mainboard/asrock/939a785gmh/cmos.layout ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/cmos.layout Wed Apr 7 04:06:53 2010 (r5364) +++ trunk/src/mainboard/asrock/939a785gmh/cmos.layout Wed Apr 7 04:09:54 2010 (r5365) @@ -67,7 +67,7 @@ 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 reserved_memory +1000 24 r 0 amd_reserved

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[commit] r5364 - in trunk/src: drivers/generic/debug mainboard/msi/ms7135 mainboard/tyan/s2735 mainboard/via/epia mainboard/via/epia-m mainboard/via/epia-m700 mainboard/via/epia-n southbridge/intel...
by repository service 07 Apr '10

07 Apr '10

Author: stepan Date: Wed Apr 7 04:06:53 2010 New Revision: 5364 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5364 Log: switch some ROMCC boards back to ROMCC. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/drivers/generic/debug/debug_dev.c trunk/src/mainboard/msi/ms7135/mptable.c trunk/src/mainboard/tyan/s2735/Kconfig trunk/src/mainboard/via/epia-m/Kconfig trunk/src/mainboard/via/epia-m700/Kconfig trunk/src/mainboard/via/epia-n/Kconfig trunk/src/mainboard/via/epia/Kconfig trunk/src/southbridge/intel/esb6300/esb6300_bridge1c.c trunk/src/southbridge/intel/esb6300/esb6300_ide.c trunk/src/southbridge/intel/esb6300/esb6300_lpc.c trunk/src/southbridge/intel/esb6300/esb6300_sata.c trunk/src/southbridge/via/vt8235/vt8235_early_serial.c trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c trunk/src/superio/smsc/lpc47m10x/superio.c Modified: trunk/src/drivers/generic/debug/debug_dev.c ============================================================================== --- trunk/src/drivers/generic/debug/debug_dev.c Wed Apr 7 03:44:04 2010 (r5363) +++ trunk/src/drivers/generic/debug/debug_dev.c Wed Apr 7 04:06:53 2010 (r5364) @@ -59,7 +59,7 @@ } } -static void print_cpuid() +static void print_cpuid(void) { msr_t msr; unsigned index; Modified: trunk/src/mainboard/msi/ms7135/mptable.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/mptable.c Wed Apr 7 03:44:04 2010 (r5363) +++ trunk/src/mainboard/msi/ms7135/mptable.c Wed Apr 7 04:06:53 2010 (r5364) @@ -47,7 +47,6 @@ unsigned sbdn; int bus_num; - int i; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); Modified: trunk/src/mainboard/tyan/s2735/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2735/Kconfig Wed Apr 7 03:44:04 2010 (r5363) +++ trunk/src/mainboard/tyan/s2735/Kconfig Wed Apr 7 04:06:53 2010 (r5364) @@ -15,6 +15,7 @@ select USE_DCACHE_RAM select USE_WATCHDOG_ON_BOOT select BOARD_ROMSIZE_KB_512 + select USE_PRINTK_IN_CAR config MAINBOARD_DIR string Modified: trunk/src/mainboard/via/epia-m/Kconfig ============================================================================== --- trunk/src/mainboard/via/epia-m/Kconfig Wed Apr 7 03:44:04 2010 (r5363) +++ trunk/src/mainboard/via/epia-m/Kconfig Wed Apr 7 04:06:53 2010 (r5364) @@ -10,22 +10,13 @@ select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_256 + select ROMCC config MAINBOARD_DIR string default via/epia-m depends on BOARD_VIA_EPIA_M -#config DCACHE_RAM_BASE -# hex -# default 0xffef0000 -# depends on BOARD_VIA_EPIA_M - -#config DCACHE_RAM_SIZE -# hex -# default 0x8000 -# depends on BOARD_VIA_EPIA_M - config MAINBOARD_PART_NUMBER string default "EPIA-M" Modified: trunk/src/mainboard/via/epia-m700/Kconfig ============================================================================== --- trunk/src/mainboard/via/epia-m700/Kconfig Wed Apr 7 03:44:04 2010 (r5363) +++ trunk/src/mainboard/via/epia-m700/Kconfig Wed Apr 7 04:06:53 2010 (r5364) @@ -7,6 +7,7 @@ select BOARD_HAS_FADT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 + select USE_PRINTK_IN_CAR config MAINBOARD_DIR string Modified: trunk/src/mainboard/via/epia-n/Kconfig ============================================================================== --- trunk/src/mainboard/via/epia-n/Kconfig Wed Apr 7 03:44:04 2010 (r5363) +++ trunk/src/mainboard/via/epia-n/Kconfig Wed Apr 7 04:06:53 2010 (r5364) @@ -18,16 +18,6 @@ default via/epia-n depends on BOARD_VIA_EPIA_N -#config DCACHE_RAM_BASE -# hex -# default 0xffef0000 -# depends on BOARD_VIA_EPIA_N -# -#config DCACHE_RAM_SIZE -# hex -# default 0x8000 -# depends on BOARD_VIA_EPIA_N - config MAINBOARD_PART_NUMBER string default "EPIA-N" Modified: trunk/src/mainboard/via/epia/Kconfig ============================================================================== --- trunk/src/mainboard/via/epia/Kconfig Wed Apr 7 03:44:04 2010 (r5363) +++ trunk/src/mainboard/via/epia/Kconfig Wed Apr 7 04:06:53 2010 (r5364) @@ -7,22 +7,13 @@ select SUPERIO_WINBOND_W83627HF select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 + select ROMCC config MAINBOARD_DIR string default via/epia depends on BOARD_VIA_EPIA -#config DCACHE_RAM_BASE -# hex -# default 0xffef0000 -# depends on BOARD_VIA_EPIA -# -#config DCACHE_RAM_SIZE -# hex -# default 0x8000 -# depends on BOARD_VIA_EPIA - config MAINBOARD_PART_NUMBER string default "EPIA" Modified: trunk/src/southbridge/intel/esb6300/esb6300_bridge1c.c ============================================================================== --- trunk/src/southbridge/intel/esb6300/esb6300_bridge1c.c Wed Apr 7 03:44:04 2010 (r5363) +++ trunk/src/southbridge/intel/esb6300/esb6300_bridge1c.c Wed Apr 7 04:06:53 2010 (r5364) @@ -7,9 +7,6 @@ static void bridge1c_init(struct device *dev) { - - uint16_t word; - /* configuration */ pci_write_config8(dev, 0x1b, 0x30); // pci_write_config8(dev, 0x3e, 0x07); @@ -31,7 +28,6 @@ /* multi transaction timer */ pci_write_config8(dev, 0x42, 0x08); - } static struct device_operations pci_ops = { Modified: trunk/src/southbridge/intel/esb6300/esb6300_ide.c ============================================================================== --- trunk/src/southbridge/intel/esb6300/esb6300_ide.c Wed Apr 7 03:44:04 2010 (r5363) +++ trunk/src/southbridge/intel/esb6300/esb6300_ide.c Wed Apr 7 04:06:53 2010 (r5364) @@ -9,7 +9,6 @@ { /* Enable ide devices so the linux ide driver will work */ - uint16_t word; /* Enable IDE devices */ pci_write_config16(dev, 0x40, 0x0a307); @@ -19,6 +18,7 @@ pci_write_config16(dev, 0x54, 0x5055); #if 0 + uint16_t word; word = pci_read_config16(dev, 0x40); word |= (1 << 15); pci_write_config16(dev, 0x40, word); Modified: trunk/src/southbridge/intel/esb6300/esb6300_lpc.c ============================================================================== --- trunk/src/southbridge/intel/esb6300/esb6300_lpc.c Wed Apr 7 03:44:04 2010 (r5363) +++ trunk/src/southbridge/intel/esb6300/esb6300_lpc.c Wed Apr 7 04:06:53 2010 (r5364) @@ -51,13 +51,13 @@ device_t dev, struct resource *res, config_t *config) { uint32_t gpio_use_sel, gpio_use_sel2; - int i; // gpio_use_sel = 0x1B003100; // gpio_use_sel2 = 0x03000000; gpio_use_sel = 0x1BBC31C0; gpio_use_sel2 = 0x03000FE1; #if 0 + int i; for(i = 0; i < 64; i++) { int val; switch(config->gpio[i] & ESB6300_GPIO_USE_MASK) { @@ -84,13 +84,13 @@ device_t dev, struct resource *res, config_t *config) { uint32_t gpio_io_sel, gpio_io_sel2; - int i; // gpio_io_sel = 0x0000ffff; // gpio_io_sel2 = 0x00000000; gpio_io_sel = 0x1900ffff; gpio_io_sel2 = 0x00000fe1; #if 0 + int i; for(i = 0; i < 64; i++) { int val; switch(config->gpio[i] & ESB6300_GPIO_SEL_MASK) { @@ -118,7 +118,6 @@ { uint32_t gpio_lvl, gpio_lvl2; uint32_t gpio_blink; - int i; // gpio_lvl = 0x1b3f0000; // gpio_blink = 0x00040000; @@ -127,6 +126,7 @@ gpio_blink = 0x00000000; gpio_lvl2 = 0x00000fff; #if 0 + int i; for(i = 0; i < 64; i++) { int val, blink; switch(config->gpio[i] & ESB6300_GPIO_LVL_MASK) { @@ -157,10 +157,10 @@ device_t dev, struct resource *res, config_t *config) { uint32_t gpio_inv; - int i; gpio_inv = 0x00003100; #if 0 + int i; for(i = 0; i < 32; i++) { int val; switch(config->gpio[i] & ESB6300_GPIO_INV_MASK) { Modified: trunk/src/southbridge/intel/esb6300/esb6300_sata.c ============================================================================== --- trunk/src/southbridge/intel/esb6300/esb6300_sata.c Wed Apr 7 03:44:04 2010 (r5363) +++ trunk/src/southbridge/intel/esb6300/esb6300_sata.c Wed Apr 7 04:06:53 2010 (r5364) @@ -7,9 +7,7 @@ static void sata_init(struct device *dev) { - /* Enable sata devices so the linux sata driver will work */ - uint16_t word; /* Enable SATA devices */ Modified: trunk/src/southbridge/via/vt8235/vt8235_early_serial.c ============================================================================== --- trunk/src/southbridge/via/vt8235/vt8235_early_serial.c Wed Apr 7 03:44:04 2010 (r5363) +++ trunk/src/southbridge/via/vt8235/vt8235_early_serial.c Wed Apr 7 04:06:53 2010 (r5364) @@ -38,9 +38,6 @@ static void enable_vt8235_serial(void) { - unsigned long x; - uint8_t c; - device_t dev; // turn on pnp vt8235_writepnpaddr(0x87); vt8235_writepnpaddr(0x87); Modified: trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c ============================================================================== --- trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c Wed Apr 7 03:44:04 2010 (r5363) +++ trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c Wed Apr 7 04:06:53 2010 (r5364) @@ -85,7 +85,6 @@ unsigned long loops; loops = SMBUS_TIMEOUT; do { - unsigned char val; smbus_delay(); c = inb(SMBUS_IO_BASE + SMBHSTSTAT); while((c & 1) == 1) { @@ -121,7 +120,6 @@ unsigned char byte; loops = SMBUS_TIMEOUT; do { - unsigned char val; smbus_delay(); byte = inb(SMBUS_IO_BASE + SMBHSTSTAT); Modified: trunk/src/superio/smsc/lpc47m10x/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47m10x/superio.c Wed Apr 7 03:44:04 2010 (r5363) +++ trunk/src/superio/smsc/lpc47m10x/superio.c Wed Apr 7 04:06:53 2010 (r5364) @@ -44,7 +44,7 @@ static void pnp_enter_conf_state(device_t dev); static void pnp_exit_conf_state(device_t dev); -static void dump_pnp_device(device_t dev); +//static void dump_pnp_device(device_t dev); struct chip_operations superio_smsc_lpc47m10x_ops = { CHIP_NAME("SMSC LPC47M10x Super I/O")

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[commit] r5363 - in trunk/src: mainboard/msi/ms9185 mainboard/via/epia-m mainboard/via/epia-n northbridge/amd/amdfam10 northbridge/amd/amdk8 northbridge/via/cn400 northbridge/via/vt8623 northbridge...
by repository service 07 Apr '10

07 Apr '10

Author: stepan Date: Wed Apr 7 03:44:04 2010 New Revision: 5363 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5363 Log: "no warnings day" last round for today. still warnings - help appreciated. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/msi/ms9185/mptable.c trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/via/epia-m/fadt.c trunk/src/mainboard/via/epia-m/mainboard.c trunk/src/mainboard/via/epia-n/acpi_tables.c trunk/src/mainboard/via/epia-n/fadt.c trunk/src/northbridge/amd/amdfam10/setup_resource_map.c trunk/src/northbridge/amd/amdk8/incoherent_ht.c trunk/src/northbridge/amd/amdk8/raminit_f.c trunk/src/northbridge/amd/amdk8/setup_resource_map.c trunk/src/northbridge/via/cn400/cn400.h trunk/src/northbridge/via/cn400/northbridge.c trunk/src/northbridge/via/vt8623/northbridge.c trunk/src/northbridge/via/vt8623/raminit.c trunk/src/northbridge/via/vx800/vx800.h trunk/src/northbridge/via/vx800/vx800_ide.c trunk/src/southbridge/broadcom/bcm5785/bcm5785.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_ide.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_reset.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c trunk/src/southbridge/ricoh/rl5c476/rl5c476.c trunk/src/southbridge/via/vt8235/vt8235.c trunk/src/southbridge/via/vt8235/vt8235_lpc.c trunk/src/southbridge/via/vt8235/vt8235_usb.c trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c Modified: trunk/src/mainboard/msi/ms9185/mptable.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/mptable.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/mainboard/msi/ms9185/mptable.c Wed Apr 7 03:44:04 2010 (r5363) @@ -43,8 +43,8 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[3] = "MSI"; - static const char productid[6] = "MS9185 "; + static const char oem[8] = "MSI "; + static const char productid[12] = "MS9185 "; struct mp_config_table *mc; unsigned char bus_num; @@ -82,8 +82,7 @@ /*I/O APICs: APIC ID Version State Address*/ { - device_t dev = 0; - int i; + device_t dev = 0; struct resource *res; for(i=0; i<3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/mainboard/msi/ms9185/romstage.c Wed Apr 7 03:44:04 2010 (r5363) @@ -57,6 +57,7 @@ #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" +#include <reset.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" @@ -151,7 +152,8 @@ }; - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; unsigned bsp_apicid = 0; Modified: trunk/src/mainboard/via/epia-m/fadt.c ============================================================================== --- trunk/src/mainboard/via/epia-m/fadt.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/mainboard/via/epia-m/fadt.c Wed Apr 7 03:44:04 2010 (r5363) @@ -37,8 +37,8 @@ memcpy(header->asl_compiler_id,ASLC,4); header->asl_compiler_revision=0; - fadt->firmware_ctrl=facs; - fadt->dsdt= dsdt; + fadt->firmware_ctrl=(u32)facs; + fadt->dsdt=(u32)dsdt; fadt->preferred_pm_profile=0; fadt->sci_int=5; fadt->smi_cmd = 0; @@ -84,9 +84,9 @@ fadt->reset_reg.addrh = 0x0; fadt->reset_value = 0; - fadt->x_firmware_ctl_l = facs; + fadt->x_firmware_ctl_l = (u32)facs; fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = dsdt; + fadt->x_dsdt_l = (u32)dsdt; fadt->x_dsdt_h = 0; fadt->x_pm1a_evt_blk.space_id = 1; Modified: trunk/src/mainboard/via/epia-m/mainboard.c ============================================================================== --- trunk/src/mainboard/via/epia-m/mainboard.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/mainboard/via/epia-m/mainboard.c Wed Apr 7 03:44:04 2010 (r5363) @@ -7,9 +7,6 @@ #include "chip.h" #include "vgachip.h" -void vga_enable_console(); - - static void vga_fixup(void) { // we do this right here because: // - all the hardware is working, and some VGA bioses seem to need @@ -22,8 +19,6 @@ do_vgabios(); post_code(0x93); vga_enable_console(); - - } void write_protect_vgabios(void) Modified: trunk/src/mainboard/via/epia-n/acpi_tables.c ============================================================================== --- trunk/src/mainboard/via/epia-n/acpi_tables.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/mainboard/via/epia-n/acpi_tables.c Wed Apr 7 03:44:04 2010 (r5363) @@ -126,7 +126,6 @@ unsigned long current; acpi_rsdp_t *rsdp; acpi_rsdt_t *rsdt; - acpi_xsdt_t *xsdt; acpi_madt_t *madt; acpi_fadt_t *fadt; acpi_facs_t *facs; @@ -163,8 +162,10 @@ dsdt = (acpi_header_t *)current; current += AmlCode.length; memcpy((void *)dsdt, &AmlCode, AmlCode.length); +#if 0 dsdt->checksum = 0; // don't trust intel iasl compiler to get this right dsdt->checksum = acpi_checksum(dsdt,dsdt->length); +#endif printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n",dsdt,dsdt->length); printk(BIOS_DEBUG, "ACPI: * FADT\n"); Modified: trunk/src/mainboard/via/epia-n/fadt.c ============================================================================== --- trunk/src/mainboard/via/epia-n/fadt.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/mainboard/via/epia-n/fadt.c Wed Apr 7 03:44:04 2010 (r5363) @@ -39,8 +39,8 @@ memcpy(header->asl_compiler_id,ASLC,4); header->asl_compiler_revision=0; - fadt->firmware_ctrl=facs; - fadt->dsdt= dsdt; + fadt->firmware_ctrl=(u32)facs; + fadt->dsdt= (u32)dsdt; fadt->preferred_pm_profile=0; fadt->sci_int=VT8237R_ACPI_IRQ; fadt->smi_cmd = 0; @@ -86,9 +86,9 @@ fadt->reset_reg.addrh = 0x0; fadt->reset_value = 0; - fadt->x_firmware_ctl_l = facs; + fadt->x_firmware_ctl_l = (u32)facs; fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = dsdt; + fadt->x_dsdt_l = (u32)dsdt; fadt->x_dsdt_h = 0; fadt->x_pm1a_evt_blk.space_id = 1; Modified: trunk/src/northbridge/amd/amdfam10/setup_resource_map.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/setup_resource_map.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/northbridge/amd/amdfam10/setup_resource_map.c Wed Apr 7 03:44:04 2010 (r5363) @@ -195,6 +195,7 @@ #endif } +#if 0 static void setup_iob_resource_map(const u32 *register_values, u32 max) { u32 i; @@ -227,5 +228,5 @@ outl(reg, where); } } - +#endif Modified: trunk/src/northbridge/amd/amdk8/incoherent_ht.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/incoherent_ht.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/northbridge/amd/amdk8/incoherent_ht.c Wed Apr 7 03:44:04 2010 (r5363) @@ -444,7 +444,6 @@ #if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 if(offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used ) { uint16_t flags; - int i; flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS); flags &= ~0x1f; flags |= CONFIG_HT_CHAIN_END_UNITID_BASE & 0x1f; @@ -452,6 +451,7 @@ #if RAMINIT_SYSINFO == 1 // Here need to change the dev in the array + int i; for(i=0;i<sysinfo->link_pair_num;i++) { struct link_pair_st *link_pair = &sysinfo->link_pair[i]; Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/northbridge/amd/amdk8/raminit_f.c Wed Apr 7 03:44:04 2010 (r5363) @@ -33,7 +33,7 @@ #define QRANK_DIMM_SUPPORT 0 #endif -#if DEBUG_RAM_SETUP +#if CONFIG_DEBUG_RAM_SETUP #define printk_raminit(fmt, arg...) printk(BIOS_DEBUG, fmt, arg) #else #define printk_raminit(fmt, arg...) Modified: trunk/src/northbridge/amd/amdk8/setup_resource_map.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/setup_resource_map.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/northbridge/amd/amdk8/setup_resource_map.c Wed Apr 7 03:44:04 2010 (r5363) @@ -192,6 +192,7 @@ #endif } +#if 0 static void setup_iob_resource_map(const unsigned int *register_values, int max) { int i; @@ -267,7 +268,6 @@ } } -#if 0 static void setup_mem_resource_map(const unsigned int *register_values, int max) { int i; Modified: trunk/src/northbridge/via/cn400/cn400.h ============================================================================== --- trunk/src/northbridge/via/cn400/cn400.h Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/northbridge/via/cn400/cn400.h Wed Apr 7 03:44:04 2010 (r5363) @@ -19,7 +19,8 @@ */ #ifndef __PRE_RAM__ -static void cn400_noop(void) +// HACK +static inline void cn400_noop(device_t dev) { } #endif Modified: trunk/src/northbridge/via/cn400/northbridge.c ============================================================================== --- trunk/src/northbridge/via/cn400/northbridge.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/northbridge/via/cn400/northbridge.c Wed Apr 7 03:44:04 2010 (r5363) @@ -238,7 +238,7 @@ if (mc_dev) { unsigned long tomk, tolmk; unsigned char rambits; - int i, idx; + int idx; rambits = pci_read_config8(mc_dev, 0x47); tomk = rambits * 32 * 1024; Modified: trunk/src/northbridge/via/vt8623/northbridge.c ============================================================================== --- trunk/src/northbridge/via/vt8623/northbridge.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/northbridge/via/vt8623/northbridge.c Wed Apr 7 03:44:04 2010 (r5363) @@ -105,7 +105,7 @@ static void vga_init(device_t dev) { // unsigned long fb; - msr_t clocks1,clocks2,instructions,setup; + //msr_t clocks1,clocks2,instructions,setup; printk(BIOS_DEBUG, "VGA random fixup ...\n"); pci_write_config8(dev, 0x04, 0x07); Modified: trunk/src/northbridge/via/vt8623/raminit.c ============================================================================== --- trunk/src/northbridge/via/vt8623/raminit.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/northbridge/via/vt8623/raminit.c Wed Apr 7 03:44:04 2010 (r5363) @@ -69,7 +69,7 @@ { device_t north = (device_t) 0; uint8_t b, c, bank; - uint16_t i,j; + uint16_t i; unsigned long bank_address; print_debug("vt8623 init starting\n"); Modified: trunk/src/northbridge/via/vx800/vx800.h ============================================================================== --- trunk/src/northbridge/via/vx800/vx800.h Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/northbridge/via/vx800/vx800.h Wed Apr 7 03:44:04 2010 (r5363) @@ -21,7 +21,7 @@ #define VX800_H 1 #ifndef __PRE_RAM__ -static void vx800_noop() +static inline void vx800_noop(device_t dev) { } #endif Modified: trunk/src/northbridge/via/vx800/vx800_ide.c ============================================================================== --- trunk/src/northbridge/via/vx800/vx800_ide.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/northbridge/via/vx800/vx800_ide.c Wed Apr 7 03:44:04 2010 (r5363) @@ -166,13 +166,10 @@ static void ide_init(struct device *dev) { - uint8_t enables, Rx89, RxC0; u8 i, data; - struct ATA_REG_INIT_TABLE *pEntry; printk(BIOS_INFO, "ide_init\n"); -#if 1 - /*these 3 lines help to keep interl back door for DID VID SUBID untouched */ + /* these 3 lines help to keep interl back door for DID VID SUBID untouched */ u16 data16_1, data16_2; data16_1 = pci_read_config16(dev, 0xba); data16_2 = pci_read_config16(dev, 0xbe); @@ -189,7 +186,7 @@ //these 2 lines help to keep interl back door for DID VID SUBID untouched pci_write_config16(dev, 0xba, data16_1); pci_write_config16(dev, 0xbe, data16_2); -#endif + /* Force interrupts to use compat mode. */ pci_write_config8(dev, PCI_INTERRUPT_PIN, 0x0); pci_write_config8(dev, PCI_INTERRUPT_LINE, 0xff); Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785.c Wed Apr 7 03:44:04 2010 (r5363) @@ -12,8 +12,7 @@ { device_t sb_pci_main_dev; device_t bus_dev; - unsigned index; - unsigned reg_old, reg; + // unsigned index; /* See if we are on the behind the pcix bridge */ bus_dev = dev->bus->dev; @@ -23,18 +22,17 @@ unsigned devfn; devfn = bus_dev->path.pci.devfn + (1 << 3); sb_pci_main_dev = dev_find_slot(bus_dev->bus->secondary, devfn); -// index = ((dev->path.pci.devfn & ~7) >> 3) + 8; + // index = ((dev->path.pci.devfn & ~7) >> 3) + 8; } else if ((bus_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && (bus_dev->device == 0x0104)) // device under PCI Bridge( under PCI-X ) { unsigned devfn; devfn = bus_dev->bus->dev->path.pci.devfn + (1 << 3); sb_pci_main_dev = dev_find_slot(bus_dev->bus->dev->bus->secondary, devfn); -// index = ((dev->path.pci.devfn & ~7) >> 3) + 8; + // index = ((dev->path.pci.devfn & ~7) >> 3) + 8; } else { // same bus unsigned devfn; - uint32_t id; devfn = (dev->path.pci.devfn) & ~7; if( dev->vendor == PCI_VENDOR_ID_SERVERWORKS ) { if(dev->device == 0x0036) //PCI-X Bridge @@ -43,7 +41,7 @@ { devfn -= (1<<3); } } sb_pci_main_dev = dev_find_slot(dev->bus->secondary, devfn); -// index = dev->path.pci.devfn & 7; + // index = dev->path.pci.devfn & 7; } if (!sb_pci_main_dev) { return; @@ -51,6 +49,7 @@ // get index now #if 0 + unsigned reg_old, reg; if (index < 16) { reg = reg_old = pci_read_config16(sb_pci_main_dev, 0x48); reg &= ~(1 << index); Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c Wed Apr 7 03:44:04 2010 (r5363) @@ -6,8 +6,6 @@ static void bcm5785_enable_rom(void) { unsigned char byte; - uint32_t dword; - uint16_t word; device_t addr; /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */ @@ -109,7 +107,7 @@ } -static void hard_reset(void) +void hard_reset(void) { bcm5785_enable_wdt_port_cf9(); @@ -120,7 +118,7 @@ outb(0x0e, 0x0cf9); } -static void soft_reset(void) +void soft_reset(void) { bcm5785_enable_wdt_port_cf9(); @@ -164,7 +162,6 @@ static void bcm5785_early_setup(void) { uint8_t byte; - uint16_t word; uint32_t dword; device_t dev; @@ -181,13 +178,12 @@ byte |= (1<<0); // SATA enable pci_write_config8(dev, 0x84, byte); -// wdt and cf9 for later in coreboot_ram to call hard_reset +// WDT and cf9 for later in coreboot_ram to call hard_reset bcm5785_enable_wdt_port_cf9(); bcm5785_enable_msg(); -#if 1 // IDE related //F0 byte = pci_read_config8(dev, 0x4e); @@ -207,9 +203,8 @@ byte = pci_read_config8(dev, 0x49); byte |= 1; // enable second channel pci_write_config8(dev, 0x49, byte); -#endif -//F2 + //F2 dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); byte = pci_read_config8(dev, 0x40); @@ -218,7 +213,6 @@ pci_write_config32(dev, 0x60, 0x0000ffff); // LPC Memory hole start and end -#if 1 // USB related pci_write_config8(dev, 0x90, 0x40); pci_write_config8(dev, 0x92, 0x06); @@ -227,5 +221,4 @@ pci_write_config8(dev, 0xa5, 0x02); //mask reg - low/full speed func pci_write_config8(dev, 0xa6, 0x00); //mask reg - high speed func pci_write_config8(dev, 0xb4, 0x40); -#endif } Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_ide.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_ide.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_ide.c Wed Apr 7 03:44:04 2010 (r5363) @@ -12,9 +12,6 @@ static void bcm5785_ide_read_resources(device_t dev) { - struct resource *res; - unsigned long index; - /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); @@ -26,9 +23,6 @@ static void ide_init(struct device *dev) { - uint16_t word; - - } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) @@ -36,6 +30,7 @@ pci_write_config32(dev, 0x40, ((device & 0xffff) << 16) | (vendor & 0xffff)); } + static struct pci_operations lops_pci = { .set_subsystem = lpci_set_subsystem, }; Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_lpc.c Wed Apr 7 03:44:04 2010 (r5363) @@ -70,7 +70,6 @@ unsigned link; uint32_t reg; int i; - int var_num = 0; reg = pci_read_config8(dev, 0x44); Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_reset.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_reset.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_reset.c Wed Apr 7 03:44:04 2010 (r5363) @@ -4,6 +4,7 @@ */ #include <arch/io.h> +#include <reset.h> #define PCI_DEV(BUS, DEV, FN) ( \ (((BUS) & 0xFFF) << 20) | \ Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_sata.c Wed Apr 7 03:44:04 2010 (r5363) @@ -12,17 +12,13 @@ #include <arch/io.h> #include "bcm5785.h" - static void sata_init(struct device *dev) { - uint8_t byte; - uint8_t *base; - uint8_t *mmio; + u32 mmio; struct resource *res; - unsigned int mmio_base; - volatile unsigned int *mmio_reg; + u32 mmio_base; int i; if(!(dev->path.pci.devfn & 7)) { // only set it in Func0 @@ -31,27 +27,24 @@ pci_write_config8(dev, 0x78, byte); res = find_resource(dev, 0x24); - base = res->base; - - mmio_base = base; + mmio_base = res->base; mmio_base &= 0xfffffffc; - mmio_reg = (unsigned int *)( mmio_base + 0x10f0 ); - * mmio_reg = 0x40000001; - mmio_reg = ( unsigned int *)( mmio_base + 0x8c ); - * mmio_reg = 0x00ff2007; + + write32(mmio_base + 0x10f0, 0x40000001); + write32(mmio_base + 0x8c, 0x00ff2007); mdelay( 10 ); - * mmio_reg = 0x78592009; + write32(mmio_base + 0x8c, 0x78592009); mdelay( 10 ); - * mmio_reg = 0x00082004; + write32(mmio_base + 0x8c, 0x00082004); mdelay( 10 ); - * mmio_reg = 0x00002004; + write32(mmio_base + 0x8c, 0x00002004); mdelay( 10 ); //init PHY printk(BIOS_DEBUG, "init PHY...\n"); for(i=0; i<4; i++) { - mmio = base + 0x100 * i; + mmio = res->base + 0x100 * i; byte = read8(mmio + 0x40); printk(BIOS_DEBUG, "port %d PHY status = %02x\n", i, byte); if(byte & 0x4) {// bit 2 is set @@ -62,10 +55,7 @@ printk(BIOS_DEBUG, "after reset port %d PHY status = %02x\n", i, byte); } } - } - - } static void lpci_set_subsystem(device_t dev, unsigned vendor, unsigned device) Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c Wed Apr 7 03:44:04 2010 (r5363) @@ -25,8 +25,6 @@ uint8_t byte_old; int nmi_option; - uint32_t dword; - /* Set up NMI on errors */ byte = inb(0x70); // RTC70 byte_old = byte; @@ -47,7 +45,6 @@ static void bcm5785_sb_read_resources(device_t dev) { struct resource *res; - unsigned long index; /* Get the normal pci resources of this device */ pci_dev_read_resources(dev); @@ -64,6 +61,7 @@ res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED; } + static int lsmbus_recv_byte(device_t dev) { unsigned device; Modified: trunk/src/southbridge/ricoh/rl5c476/rl5c476.c ============================================================================== --- trunk/src/southbridge/ricoh/rl5c476/rl5c476.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/southbridge/ricoh/rl5c476/rl5c476.c Wed Apr 7 03:44:04 2010 (r5363) @@ -162,7 +162,7 @@ *cptr = 0x41; } -void rl5c476_read_resources(device_t dev) +static void rl5c476_read_resources(device_t dev) { struct resource *resource; @@ -181,7 +181,7 @@ cardbus_read_resources(dev); } -void rl5c476_set_resources(device_t dev) +static void rl5c476_set_resources(device_t dev) { struct resource *resource; printk(BIOS_DEBUG, "%s In set resources \n",dev_path(dev)); @@ -212,12 +212,10 @@ .device = PCI_DEVICE_ID_RICOH_RL5C476, }; -void southbridge_init(device_t dev) +static void southbridge_init(device_t dev) { - struct southbridge_ricoh_rl5c476_config *conf = dev->chip_info; enable_cf_boot = conf->enable_cf; - } struct chip_operations southbridge_ricoh_rl5c476_ops = { Modified: trunk/src/southbridge/via/vt8235/vt8235.c ============================================================================== --- trunk/src/southbridge/via/vt8235/vt8235.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/southbridge/via/vt8235/vt8235.c Wed Apr 7 03:44:04 2010 (r5363) @@ -10,7 +10,6 @@ /* * Base VT8235. */ -static int enabled = 0; void hard_reset(void) { @@ -53,11 +52,9 @@ static void vt8235_enable(struct device *dev) { - struct southbridge_via_vt8235_config *conf = dev->chip_info; unsigned char regval; unsigned short vendor,model; - vendor = pci_read_config16(dev,0); model = pci_read_config16(dev,0x2); @@ -72,7 +69,6 @@ printk(BIOS_DEBUG, "Initialising Devices\n"); - setup_i8259(); // make sure interupt controller is configured before keyboard init /* enable RTC and ethernet */ @@ -87,8 +83,6 @@ regval = pci_read_config8(dev, 0x50); regval &= ~(0x36); pci_write_config8(dev, 0x50, regval); - - } struct chip_operations southbridge_via_vt8235_ops = { Modified: trunk/src/southbridge/via/vt8235/vt8235_lpc.c ============================================================================== --- trunk/src/southbridge/via/vt8235/vt8235_lpc.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/southbridge/via/vt8235/vt8235_lpc.c Wed Apr 7 03:44:04 2010 (r5363) @@ -105,9 +105,8 @@ * can't figure out how to do !!!! */ -void setup_pm(device_t dev) +static void setup_pm(device_t dev) { - // Set gen config 0 pci_write_config8(dev, 0x80, 0x20); @@ -216,7 +215,7 @@ /* total kludge to get lxb to call our childrens set/enable functions - these are not called unless this device has a resource to set - so set a dummy one */ -void vt8235_read_resources(device_t dev) +static void vt8235_read_resources(device_t dev) { struct resource *res; @@ -234,21 +233,20 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -void vt8235_set_resources(device_t dev) +static void vt8235_set_resources(device_t dev) { - struct resource *resource; + //struct resource *resource; //resource = find_resource(dev,1); //resource->flags |= IORESOURCE_STORED; pci_dev_set_resources(dev); } -void vt8235_enable_resources(device_t dev) +static void vt8235_enable_resources(device_t dev) { /* vt8235 is not a pci bridge and has no resources of its own (other than standard PC i/o addresses) however it does control the isa bus and so we need to manually call enable childrens resources on that bus */ pci_dev_enable_resources(dev); enable_childrens_resources(dev); - } static void southbridge_init(struct device *dev) Modified: trunk/src/southbridge/via/vt8235/vt8235_usb.c ============================================================================== --- trunk/src/southbridge/via/vt8235/vt8235_usb.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/southbridge/via/vt8235/vt8235_usb.c Wed Apr 7 03:44:04 2010 (r5363) @@ -27,7 +27,6 @@ */ } -/* static struct device_operations usb_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -42,4 +41,4 @@ .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_82C586_2, }; -*/ + Modified: trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c Wed Apr 7 03:41:01 2010 (r5362) +++ trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c Wed Apr 7 03:44:04 2010 (r5363) @@ -65,7 +65,6 @@ { #if CONFIG_EPIA_VT8237R_INIT device_t pdev; - u8 reg; #endif /* PCI PNP Interrupt Routing INTE/F - disable */

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[commit] r5362 - trunk/src/mainboard/via/epia-n
by repository service 07 Apr '10

07 Apr '10

Author: stepan Date: Wed Apr 7 03:41:01 2010 New Revision: 5362 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5362 Log: oops... this is a critical issue. Some boards in the tree don't compile with romcc even though they don't have CAR either. We need to check all boards and fix those that are broken like this. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/via/epia-n/Kconfig Modified: trunk/src/mainboard/via/epia-n/Kconfig ============================================================================== --- trunk/src/mainboard/via/epia-n/Kconfig Wed Apr 7 02:38:09 2010 (r5361) +++ trunk/src/mainboard/via/epia-n/Kconfig Wed Apr 7 03:41:01 2010 (r5362) @@ -11,6 +11,7 @@ select EPIA_VT8237R_INIT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 + select ROMCC config MAINBOARD_DIR string

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[commit] r5361 - in trunk/src: mainboard/asus/a8n_e mainboard/asus/a8v-e_se mainboard/asus/m2v-mx_se mainboard/hp/dl145_g3 mainboard/msi/ms7135 mainboard/msi/ms9282 mainboard/msi/ms9652_fam10 mainb...
by repository service 07 Apr '10

07 Apr '10

Author: stepan Date: Wed Apr 7 02:38:09 2010 New Revision: 5361 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5361 Log: - unify use of SB_HT_CHAIN_UNITID_OFFSET_ONLY - cleanup reset - some minor warning fixes. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/asus/a8n_e/Kconfig trunk/src/mainboard/asus/a8v-e_se/Kconfig trunk/src/mainboard/asus/m2v-mx_se/Kconfig trunk/src/mainboard/hp/dl145_g3/Kconfig trunk/src/mainboard/msi/ms7135/Kconfig trunk/src/mainboard/msi/ms9282/get_bus_conf.c trunk/src/mainboard/msi/ms9282/mptable.c trunk/src/mainboard/msi/ms9652_fam10/Kconfig trunk/src/mainboard/sunw/ultra40/Kconfig trunk/src/mainboard/supermicro/h8dme/Kconfig trunk/src/mainboard/supermicro/h8dmr/Kconfig trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig trunk/src/mainboard/tyan/s2850/Kconfig trunk/src/mainboard/tyan/s2875/Kconfig trunk/src/mainboard/tyan/s2892/Kconfig trunk/src/mainboard/tyan/s2895/Kconfig trunk/src/northbridge/amd/amdfam10/Kconfig trunk/src/northbridge/amd/amdk8/Kconfig trunk/src/northbridge/amd/amdk8/reset_test.c trunk/src/southbridge/nvidia/mcp55/mcp55_reset.c trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.c trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.h Modified: trunk/src/mainboard/asus/a8n_e/Kconfig ============================================================================== --- trunk/src/mainboard/asus/a8n_e/Kconfig Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/mainboard/asus/a8n_e/Kconfig Wed Apr 7 02:38:09 2010 (r5361) @@ -44,11 +44,6 @@ default 2 depends on BOARD_ASUS_A8N_E -config SB_HT_CHAIN_UNITID_OFFSET_ONLY - bool - default n - depends on BOARD_ASUS_A8N_E - config MAINBOARD_PART_NUMBER string default "A8N-E" Modified: trunk/src/mainboard/asus/a8v-e_se/Kconfig ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/Kconfig Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/mainboard/asus/a8v-e_se/Kconfig Wed Apr 7 02:38:09 2010 (r5361) @@ -44,11 +44,6 @@ default 1 depends on BOARD_ASUS_A8V_E_SE -config SB_HT_CHAIN_UNITID_OFFSET_ONLY - bool - default n - depends on BOARD_ASUS_A8V_E_SE - config MAINBOARD_PART_NUMBER string default "A8V-E SE" Modified: trunk/src/mainboard/asus/m2v-mx_se/Kconfig ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/Kconfig Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/mainboard/asus/m2v-mx_se/Kconfig Wed Apr 7 02:38:09 2010 (r5361) @@ -86,11 +86,6 @@ default 0x0 depends on BOARD_ASUS_M2V_MX_SE -config SB_HT_CHAIN_UNITID_OFFSET_ONLY - bool - default n - depends on BOARD_ASUS_M2V_MX_SE - config SB_HT_CHAIN_ON_BUS0 int default 1 Modified: trunk/src/mainboard/hp/dl145_g3/Kconfig ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/Kconfig Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/mainboard/hp/dl145_g3/Kconfig Wed Apr 7 02:38:09 2010 (r5361) @@ -47,11 +47,6 @@ default 2 depends on BOARD_HP_DL145_G3 -config SB_HT_CHAIN_UNITID_OFFSET_ONLY - bool - default n - depends on BOARD_HP_DL145_G3 - config MAINBOARD_PART_NUMBER string default "ProLiant DL145 G3" Modified: trunk/src/mainboard/msi/ms7135/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms7135/Kconfig Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/mainboard/msi/ms7135/Kconfig Wed Apr 7 02:38:09 2010 (r5361) @@ -79,11 +79,6 @@ default 2 depends on BOARD_MSI_MS7135 -config SB_HT_CHAIN_UNITID_OFFSET_ONLY - bool - default n - depends on BOARD_MSI_MS7135 - config IRQ_SLOT_COUNT int default 13 Modified: trunk/src/mainboard/msi/ms9282/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/get_bus_conf.c Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/mainboard/msi/ms9282/get_bus_conf.c Wed Apr 7 02:38:09 2010 (r5361) @@ -68,31 +68,6 @@ static unsigned get_bus_conf_done = 0; -static unsigned get_hcid(unsigned i) -{ - unsigned id = 0; - - unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; - - unsigned devn = sysconf.hcdn[i] & 0xff; - - device_t dev; - - dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); - - switch (dev->device) { - case 0x0369: //IO55 - id = 4; - break; - } - - // we may need more way to find out hcid: subsystem id? GPIO read ? - - // we need use id for 1. bus num, 2. mptable, 3. acpi table - - return id; -} - void get_bus_conf(void) { Modified: trunk/src/mainboard/msi/ms9282/mptable.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/mptable.c Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/mainboard/msi/ms9282/mptable.c Wed Apr 7 02:38:09 2010 (r5361) @@ -38,12 +38,12 @@ { static const char sig[4] = "PCMP"; static const char oem[8] = "MSI "; - static const char productid[12] = "MS9282 "; + static const char productid[12] = "MS9282 "; struct mp_config_table *mc; - struct mb_sysconf_t *m; - unsigned sbdn; + struct mb_sysconf_t *m; + unsigned sbdn; - int i,j; + int i,j; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/Kconfig Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/mainboard/msi/ms9652_fam10/Kconfig Wed Apr 7 02:38:09 2010 (r5361) @@ -16,6 +16,7 @@ select ENABLE_APIC_EXT_ID select AMDMCT select TINY_BOOTBLOCK + select SB_HT_CHAIN_UNITID_OFFSET_ONLY config MAINBOARD_DIR string @@ -189,11 +190,6 @@ default 1 depends on BOARD_MSI_MS9652_FAM10 -config SB_HT_CHAIN_UNITID_OFFSET_ONLY - bool - default y - depends on BOARD_MSI_MS9652_FAM10 - config VAR_MTRR_HOLE bool default n Modified: trunk/src/mainboard/sunw/ultra40/Kconfig ============================================================================== --- trunk/src/mainboard/sunw/ultra40/Kconfig Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/mainboard/sunw/ultra40/Kconfig Wed Apr 7 02:38:09 2010 (r5361) @@ -44,11 +44,6 @@ default 2 depends on BOARD_SUNW_ULTRA40 -config SB_HT_CHAIN_UNITID_OFFSET_ONLY - bool - default n - depends on BOARD_SUNW_ULTRA40 - config MAINBOARD_PART_NUMBER string default "Ultra 40" Modified: trunk/src/mainboard/supermicro/h8dme/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/Kconfig Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/mainboard/supermicro/h8dme/Kconfig Wed Apr 7 02:38:09 2010 (r5361) @@ -51,11 +51,6 @@ default 2 depends on BOARD_SUPERMICRO_H8DME -config SB_HT_CHAIN_UNITID_OFFSET_ONLY - bool - default n - depends on BOARD_SUPERMICRO_H8DME - config MAINBOARD_PART_NUMBER string default "H8DME-2" Modified: trunk/src/mainboard/supermicro/h8dmr/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/Kconfig Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/mainboard/supermicro/h8dmr/Kconfig Wed Apr 7 02:38:09 2010 (r5361) @@ -50,11 +50,6 @@ default 2 depends on BOARD_SUPERMICRO_H8DMR -config SB_HT_CHAIN_UNITID_OFFSET_ONLY - bool - default n - depends on BOARD_SUPERMICRO_H8DMR - config MAINBOARD_PART_NUMBER string default "H8DMR-i2" Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig Wed Apr 7 02:38:09 2010 (r5361) @@ -68,11 +68,6 @@ default 2 depends on BOARD_SUPERMICRO_H8DMR_FAM10 -config SB_HT_CHAIN_UNITID_OFFSET_ONLY - bool - default n - depends on BOARD_SUPERMICRO_H8DMR_FAM10 - config MAINBOARD_PART_NUMBER string default "H8DMR-i2 (Fam10)" Modified: trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig Wed Apr 7 02:38:09 2010 (r5361) @@ -69,11 +69,6 @@ default 2 depends on BOARD_SUPERMICRO_H8QME_FAM10 -config SB_HT_CHAIN_UNITID_OFFSET_ONLY - bool - default n - depends on BOARD_SUPERMICRO_H8QME_FAM10 - config MAINBOARD_PART_NUMBER string default "H8QME-2+ (Fam10)" Modified: trunk/src/mainboard/tyan/s2850/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2850/Kconfig Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/mainboard/tyan/s2850/Kconfig Wed Apr 7 02:38:09 2010 (r5361) @@ -10,6 +10,7 @@ select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 + select SB_HT_CHAIN_UNITID_OFFSET_ONLY config MAINBOARD_DIR string @@ -56,11 +57,6 @@ default 0x20 depends on BOARD_TYAN_S2850 -config SB_HT_CHAIN_UNITID_OFFSET_ONLY - bool - default y - depends on BOARD_TYAN_S2850 - config SB_HT_CHAIN_ON_BUS0 int default 0 Modified: trunk/src/mainboard/tyan/s2875/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2875/Kconfig Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/mainboard/tyan/s2875/Kconfig Wed Apr 7 02:38:09 2010 (r5361) @@ -11,6 +11,7 @@ select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 + select SB_HT_CHAIN_UNITID_OFFSET_ONLY config MAINBOARD_DIR string @@ -62,11 +63,6 @@ default 0x20 depends on BOARD_TYAN_S2875 -config SB_HT_CHAIN_UNITID_OFFSET_ONLY - bool - default y - depends on BOARD_TYAN_S2875 - config SB_HT_CHAIN_ON_BUS0 int default 0 Modified: trunk/src/mainboard/tyan/s2892/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2892/Kconfig Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/mainboard/tyan/s2892/Kconfig Wed Apr 7 02:38:09 2010 (r5361) @@ -75,11 +75,6 @@ default 2 depends on BOARD_TYAN_S2892 -config SB_HT_CHAIN_UNITID_OFFSET_ONLY - bool - default n - depends on BOARD_TYAN_S2892 - config IRQ_SLOT_COUNT int default 11 Modified: trunk/src/mainboard/tyan/s2895/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2895/Kconfig Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/mainboard/tyan/s2895/Kconfig Wed Apr 7 02:38:09 2010 (r5361) @@ -75,11 +75,6 @@ default 2 depends on BOARD_TYAN_S2895 -config SB_HT_CHAIN_UNITID_OFFSET_ONLY - bool - default n - depends on BOARD_TYAN_S2895 - config IRQ_SLOT_COUNT int default 11 Modified: trunk/src/northbridge/amd/amdfam10/Kconfig ============================================================================== --- trunk/src/northbridge/amd/amdfam10/Kconfig Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/northbridge/amd/amdfam10/Kconfig Wed Apr 7 02:38:09 2010 (r5361) @@ -57,4 +57,9 @@ default "northbridge/amd/amdfam10/bootblock.c" depends on NORTHBRIDGE_AMD_AMDFAM10 +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on NORTHBRIDGE_AMD_AMDFAM10 + source src/northbridge/amd/amdfam10/root_complex/Kconfig Modified: trunk/src/northbridge/amd/amdk8/Kconfig ============================================================================== --- trunk/src/northbridge/amd/amdk8/Kconfig Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/northbridge/amd/amdk8/Kconfig Wed Apr 7 02:38:09 2010 (r5361) @@ -47,4 +47,9 @@ default n depends on NORTHBRIDGE_AMD_AMDK8 +config SB_HT_CHAIN_UNITID_OFFSET_ONLY + bool + default n + depends on NORTHBRIDGE_AMD_AMDK8 + source src/northbridge/amd/amdk8/root_complex/Kconfig Modified: trunk/src/northbridge/amd/amdk8/reset_test.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/reset_test.c Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/northbridge/amd/amdk8/reset_test.c Wed Apr 7 02:38:09 2010 (r5361) @@ -7,9 +7,9 @@ #define HTIC_BIOSR_Detect (1<<5) #define HTIC_INIT_Detect (1<<6) -static int cpu_init_detected(unsigned nodeid) +static inline int cpu_init_detected(unsigned nodeid) { - unsigned long htic; + u32 htic; device_t dev; dev = PCI_DEV(0, 0x18 + nodeid, 0); @@ -18,25 +18,25 @@ return !!(htic & HTIC_INIT_Detect); } -static int bios_reset_detected(void) +static inline int bios_reset_detected(void) { - unsigned long htic; + u32 htic; htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); return (htic & HTIC_ColdR_Detect) && !(htic & HTIC_BIOSR_Detect); } -static int cold_reset_detected(void) +static inline int cold_reset_detected(void) { - unsigned long htic; + u32 htic; htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); return !(htic & HTIC_ColdR_Detect); } -static void distinguish_cpu_resets(unsigned nodeid) +static inline void distinguish_cpu_resets(unsigned nodeid) { - uint32_t htic; + u32 htic; device_t device; device = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); @@ -46,7 +46,7 @@ static void set_bios_reset(void) { - unsigned long htic; + u32 htic; htic = pci_read_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL); htic &= ~HTIC_BIOSR_Detect; pci_write_config32(PCI_DEV(0, 0x18, 0), HT_INIT_CONTROL, htic); @@ -54,10 +54,10 @@ static unsigned node_link_to_bus(unsigned node, unsigned link) { - unsigned reg; + u8 reg; for(reg = 0xE0; reg < 0xF0; reg += 0x04) { - unsigned config_map; + u32 config_map; config_map = pci_read_config32(PCI_DEV(0, 0x18, 1), reg); if ((config_map & 3) != 3) { continue; @@ -71,17 +71,16 @@ return 0; } -static unsigned get_sblk(void) +static inline unsigned get_sblk(void) { - uint32_t reg; + u32 reg; /* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */ reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64); return ((reg>>8) & 3) ; } -static unsigned get_sbbusn(unsigned sblk) +static inline unsigned get_sbbusn(unsigned sblk) { return node_link_to_bus(0, sblk); } - Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_reset.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_reset.c Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_reset.c Wed Apr 7 02:38:09 2010 (r5361) @@ -22,6 +22,7 @@ */ #include <arch/io.h> +#include <reset.h> #define PCI_DEV(BUS, DEV, FN) ( \ (((BUS) & 0xFFF) << 20) | \ Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.c Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.c Wed Apr 7 02:38:09 2010 (r5361) @@ -100,7 +100,6 @@ static void mcp55_sm_read_resources(device_t dev) { - struct resource *res; unsigned long index; /* Get the normal pci resources of this device */ @@ -110,7 +109,6 @@ pci_get_resource(dev, index); } compact_resources(dev); - } static void mcp55_sm_init(device_t dev) Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.h ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.h Wed Apr 7 01:55:17 2010 (r5360) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_smbus.h Wed Apr 7 02:38:09 2010 (r5361) @@ -40,23 +40,6 @@ outb(0x80, 0x80); } -static int smbus_wait_until_ready(unsigned smbus_io_base) -{ - unsigned long loops; - loops = SMBUS_TIMEOUT; - do { - unsigned char val; - smbus_delay(); - val = inb(smbus_io_base + SMBHSTSTAT); - val &= 0x1f; - if (val == 0) { - return 0; - } - outb(val,smbus_io_base + SMBHSTSTAT); - } while(--loops); - return -2; -} - static int smbus_wait_until_done(unsigned smbus_io_base) { unsigned long loops;

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build service results for r5360
by coreboot information 07 Apr '10

07 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5360 to the coreboot repository. This caused the following changes: Change Log: fix CK804 boards. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of asus:a8n_e has been fixed Compilation of msi:ms7135 has been fixed Compilation of sunw:ultra40 has been fixed Compilation of tyan:s2891 has been fixed Compilation of tyan:s2892 has been fixed Compilation of tyan:s2895 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5360 - trunk/src/southbridge/nvidia/ck804
by repository service 07 Apr '10

07 Apr '10

Author: stepan Date: Wed Apr 7 01:55:17 2010 New Revision: 5360 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5360 Log: fix CK804 boards. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c Tue Apr 6 23:50:21 2010 (r5359) +++ trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c Wed Apr 7 01:55:17 2010 (r5360) @@ -314,7 +314,7 @@ return set_ht_link_ck804(4); } -static void hard_reset(void) +void hard_reset(void) { set_bios_reset(); @@ -323,7 +323,7 @@ outb(0x0e, 0x0cf9); } -static void soft_reset(void) +void soft_reset(void) { set_bios_reset(); Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Tue Apr 6 23:50:21 2010 (r5359) +++ trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Wed Apr 7 01:55:17 2010 (r5360) @@ -339,7 +339,7 @@ return set_ht_link_ck804(4); } -static void hard_reset(void) +void hard_reset(void) { set_bios_reset(); @@ -348,7 +348,7 @@ outb(0x0e, 0x0cf9); } -static void soft_reset(void) +void soft_reset(void) { set_bios_reset();

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Re: [coreboot] [commit] r5359 - in trunk/src: . cpu/amd/model_10xxxcpu/amd/model_fxx cpu/amd/model_lx cpu/x86/mtrrinclude/cpu/x86 mainboard/amd/mahogany_fam10mainboard/amd/serengeti_cheetah mainboard/asus/a8n_...
by Stefan Reinauer 07 Apr '10

07 Apr '10

wasn't meant to be private only. On 4/7/10 12:24 AM, Stefan Reinauer wrote: > On 4/7/10 12:06 AM, Myles Watson wrote: > >> >> >>> -----Original Message----- >>> From: coreboot-bounces(a)coreboot.org [mailto:coreboot-bounces@coreboot.org] >>> On Behalf Of repository service >>> Sent: Tuesday, April 06, 2010 3:50 PM >>> To: coreboot(a)coreboot.org >>> Subject: [coreboot] [commit] r5359 - in trunk/src: . >>> cpu/amd/model_10xxxcpu/amd/model_fxx cpu/amd/model_lx >>> cpu/x86/mtrrinclude/cpu/x86 >>> mainboard/amd/mahogany_fam10mainboard/amd/serengeti_cheetah >>> mainboard/asus/a8n_... >>> >>> Author: stepan >>> Date: Tue Apr 6 21:50:21 2010 >>> New Revision: 5359 >>> URL: https://tracker.coreboot.org/trac/coreboot/changeset/5359 >>> >>> Log: >>> No warnings day, next round. >>> >>> >> Thanks. >> >> >> >>> trunk/src/cpu/x86/mtrr/earlymtrr.c >>> >>> >> >> >>> trunk/src/include/cpu/x86/mtrr.h >>> >>> >> >> >>> Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c >>> ========================================================================== >>> ==== >>> --- trunk/src/cpu/x86/mtrr/earlymtrr.c Tue Apr 6 21:49:31 2010 >>> (r5358) >>> +++ trunk/src/cpu/x86/mtrr/earlymtrr.c Tue Apr 6 21:50:21 2010 >>> (r5359) >>> @@ -4,37 +4,7 @@ >>> #include <cpu/x86/mtrr.h> >>> #include <cpu/x86/msr.h> >>> >>> -/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */ >>> -#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE) >>> -# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE" >>> >>> >> ... >> I'm surprised you wanted to move this. It made sense to me to check it when >> compiling CAR. >> >> > The idea was to be able to have the check, no matter if only > cpu/x86/earlymtrr.c or only cpu/amd/amd_earlymtrr.c is included. > > It seems that in the long term most of the earlymtrr code can completely > go away though, so I was not sure where to put it. > > >>> Modified: trunk/src/include/cpu/x86/mtrr.h >>> ========================================================================== >>> ==== >>> --- trunk/src/include/cpu/x86/mtrr.h Tue Apr 6 21:49:31 2010 >>> (r5358) >>> +++ trunk/src/include/cpu/x86/mtrr.h Tue Apr 6 21:50:21 2010 >>> (r5359) >>> >>> >> ... >> >> >>> +#if !defined(CONFIG_RAMTOP) >>> +# error "CONFIG_RAMTOP not defined" >>> +#endif >>> >>> >> Now that we have Kconfig, I think this check can disappear. Is there a way >> to un-define CONFIG_RAMTOP? >> > In theory, yes. If you say this in Kconfig: > > config FOO > bool > depends on SOME_FEATURE > > config BAR > bool > depends on FOO > > You might end up with BAR not being there even though we modified > Kconfig to always set 0 bools to 0 instead of omitting them. > That's because Kconfig completely skips BAR if FOO is not set. > > With RAMTOP being > > config RAMTOP > hex > default 0x200000 > > it can't happen. > > But I didn't want to change the rough logical flow with self-acked code, > so I thought I better leave an error check too many in there ;-) > > If you feel it should go, you have my Acked-by: Stefan Reinauer > <stepan(a)coresystems.de> > > -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

2 1

build service results for r5359
by coreboot information 07 Apr '10

07 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5359 to the coreboot repository. This caused the following changes: Change Log: No warnings day, next round. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of asus:a8n_e has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5359&device=a8n_e&vendor=a… Compilation of msi:ms7135 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5359&device=ms7135&vendor=… Compilation of sunw:ultra40 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5359&device=ultra40&vendor… Compilation of tyan:s2891 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5359&device=s2891&vendor=t… Compilation of tyan:s2892 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5359&device=s2892&vendor=t… Compilation of tyan:s2895 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5359&device=s2895&vendor=t… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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2005

2004

2003

2002

coreboot April 2010