coreboot April 2010

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[commit] r5359 - in trunk/src: . cpu/amd/model_10xxx cpu/amd/model_fxx cpu/amd/model_lx cpu/x86/mtrr include/cpu/x86 mainboard/amd/mahogany_fam10 mainboard/amd/serengeti_cheetah mainboard/asus/a8n_...
by repository service 07 Apr '10

07 Apr '10

Author: stepan Date: Tue Apr 6 21:50:21 2010 New Revision: 5359 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5359 Log: No warnings day, next round. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/Kconfig trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/model_fxx/model_fxx_init.c trunk/src/cpu/amd/model_lx/cpureginit.c trunk/src/cpu/x86/mtrr/earlymtrr.c trunk/src/include/cpu/x86/cache.h trunk/src/include/cpu/x86/mtrr.h trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/serengeti_cheetah/romstage.c trunk/src/mainboard/asus/a8n_e/mptable.c trunk/src/mainboard/asus/a8n_e/romstage.c trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/intel/d945gclf/Makefile.inc trunk/src/mainboard/kontron/986lcd-m/Makefile.inc trunk/src/mainboard/roda/rk886ex/Makefile.inc trunk/src/mainboard/tyan/s4880/romstage.c trunk/src/northbridge/amd/amdk8/amdk8_f.h trunk/src/northbridge/amd/amdk8/misc_control.c trunk/src/northbridge/amd/amdk8/raminit.c trunk/src/northbridge/amd/amdk8/raminit_f.c trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c trunk/src/northbridge/amd/lx/raminit.c trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c trunk/src/southbridge/amd/cs5536/cs5536_ide.c trunk/src/southbridge/amd/rs780/rs780_early_setup.c trunk/src/southbridge/amd/sb700/sb700_smbus.c trunk/src/southbridge/amd/sb700/sb700_smbus.h trunk/src/southbridge/via/vt8237r/vt8237_fadt.c Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/Kconfig Tue Apr 6 21:50:21 2010 (r5359) @@ -621,7 +621,8 @@ depends on (SOUTHBRIDGE_VIA_VT8237R \ || NORTHBRIDGE_VIA_VX800 \ || NORTHBRIDGE_VIA_CX700 \ - || NORTHBRIDGE_AMD_AMDK8) + || NORTHBRIDGE_AMD_AMDK8 \ + || NORTHBRIDGE_AMD_AMDFAM10) help This option enables additional SMBus (and SPD) debug messages. Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Tue Apr 6 21:50:21 2010 (r5359) @@ -91,7 +91,7 @@ wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg //mtrr for that range? -// set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE); + // set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE); set_wrap32dis(); @@ -293,7 +293,7 @@ } -static void STOP_CAR_AND_CPU() +static void STOP_CAR_AND_CPU(void) { msr_t msr; @@ -529,7 +529,7 @@ } #endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */ -void AMD_Errata281(u8 node, u32 revision, u32 platform) +static void AMD_Errata281(u8 node, u32 revision, u32 platform) { /* Workaround for Transaction Scheduling Conflict in * Northbridge Cross Bar. Implement XCS Token adjustment @@ -591,7 +591,7 @@ } -void AMD_Errata298(void) +static void AMD_Errata298(void) { /* Workaround for L2 Eviction May Occur during operation to * set Accessed or dirty bit. Modified: trunk/src/cpu/amd/model_fxx/model_fxx_init.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/model_fxx_init.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/cpu/amd/model_fxx/model_fxx_init.c Tue Apr 6 21:50:21 2010 (r5359) @@ -244,7 +244,6 @@ static void init_ecc_memory(unsigned node_id) { unsigned long startk, begink, endk; - unsigned long hole_startk = 0; unsigned long basek; struct mtrr_state mtrr_state; @@ -291,6 +290,8 @@ endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 + unsigned long hole_startk = 0; + #if CONFIG_K8_REV_F_SUPPORT == 0 if (!is_cpu_pre_e0()) { Modified: trunk/src/cpu/amd/model_lx/cpureginit.c ============================================================================== --- trunk/src/cpu/amd/model_lx/cpureginit.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/cpu/amd/model_lx/cpureginit.c Tue Apr 6 21:50:21 2010 (r5359) @@ -25,7 +25,7 @@ ;* SetDelayControl ;* ;*************************************************************************/ -void SetDelayControl(void) +static void SetDelayControl(void) { unsigned int msrnum, glspeed; unsigned char spdbyte0, spdbyte1; Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c ============================================================================== --- trunk/src/cpu/x86/mtrr/earlymtrr.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/cpu/x86/mtrr/earlymtrr.c Tue Apr 6 21:50:21 2010 (r5359) @@ -4,37 +4,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> -/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */ -#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE) -# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE" -#endif -#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE) -# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE" -#endif -#if !defined(CONFIG_RAMTOP) -# error "CONFIG_RAMTOP not defined" -#endif - -#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0) -# error "CONFIG_XIP_ROM_SIZE is not a power of 2" -#endif -#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0) -# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE" -#endif - -#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0 -# error "CONFIG_RAMTOP must be a power of 2" -#endif - -#if defined(CONFIG_XIP_ROM_SIZE) -# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK - extern unsigned long AUTO_XIP_ROM_BASE; -# define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE -# else -# define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE -# endif -#endif - +#if 0 static void disable_var_mtrr(unsigned reg) { /* The invalid bit is kept in the mask so we simply @@ -45,6 +15,7 @@ zero.lo = zero.hi = 0; wrmsr(MTRRphysMask_MSR(reg), zero); } +#endif static void set_var_mtrr( unsigned reg, unsigned base, unsigned size, unsigned type) @@ -61,6 +32,7 @@ wrmsr(MTRRphysMask_MSR(reg), maskm); } +#if 0 static void set_var_mtrr_x( unsigned reg, uint32_t base_lo, uint32_t base_hi, uint32_t size_lo, uint32_t size_hi, unsigned type) @@ -79,6 +51,7 @@ } wrmsr(MTRRphysMask_MSR(reg), maskm); } +#endif static void cache_lbmem(int type) { Modified: trunk/src/include/cpu/x86/cache.h ============================================================================== --- trunk/src/include/cpu/x86/cache.h Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/include/cpu/x86/cache.h Tue Apr 6 21:50:21 2010 (r5359) @@ -1,3 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Eric W. Biederman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #ifndef CPU_X86_CACHE #define CPU_X86_CACHE @@ -17,6 +36,7 @@ { asm volatile("invd" ::: "memory"); } + static inline void wbinvd(void) { asm volatile ("wbinvd"); Modified: trunk/src/include/cpu/x86/mtrr.h ============================================================================== --- trunk/src/include/cpu/x86/mtrr.h Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/include/cpu/x86/mtrr.h Tue Apr 6 21:50:21 2010 (r5359) @@ -31,7 +31,6 @@ #define MTRRfix4K_F0000_MSR 0x26e #define MTRRfix4K_F8000_MSR 0x26f - #if !defined (ASSEMBLY) && !defined(__PRE_RAM__) #include <device/device.h> void enable_fixed_mtrr(void); @@ -42,5 +41,39 @@ void x86_setup_fixed_mtrrs(void); #endif +/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */ +#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE) +# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE" +#endif +#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE) +# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE" +#endif +#if !defined(CONFIG_RAMTOP) +# error "CONFIG_RAMTOP not defined" +#endif + +#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0) +# error "CONFIG_XIP_ROM_SIZE is not a power of 2" +#endif +#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0) +# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE" +#endif + +#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0 +# error "CONFIG_RAMTOP must be a power of 2" +#endif + + +#if !defined (ASSEMBLY) +#if defined(CONFIG_XIP_ROM_SIZE) +# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK + extern unsigned long AUTO_XIP_ROM_BASE; +# define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE +# else +# define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE +# endif +#endif + +#endif #endif /* CPU_X86_MTRR_H */ Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Tue Apr 6 21:50:21 2010 (r5359) @@ -58,18 +58,13 @@ #include "northbridge/amd/amdfam10/reset_test.c" #include <console/loglevel.h> -#if 0 -void die(const char *msg); -int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3))); -#define printk(BIOS_EMERG, fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg) -#endif -#define printk(BIOS_INFO, fmt, arg...) do_printk(BIOS_INFO ,fmt, ##arg) #include "cpu/x86/bist.h" static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8718f/it8718f_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include <cpu/amd/mtrr.h> #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/rs780/rs780_early_setup.c" Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Tue Apr 6 21:50:21 2010 (r5359) @@ -29,20 +29,11 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -#if 0 -static void post_code(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x80000;i++) { - outb(value, 0x80); - } -#endif -} -#endif #include "pc80/serial.c" #include "console/console.c" #include <cpu/amd/model_fxx_rev.h> #include "southbridge/amd/amd8111/amd8111_early_smbus.c" +#include <reset.h> #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" @@ -54,7 +45,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include <cpu/amd/mtrr.h> #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/asus/a8n_e/mptable.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/mptable.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/mainboard/asus/a8n_e/mptable.c Tue Apr 6 21:50:21 2010 (r5359) @@ -41,7 +41,7 @@ static const char productid[12] = "A8N-E "; struct mp_config_table *mc; unsigned sbdn; - int i, bus_num; + int bus_num; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); Modified: trunk/src/mainboard/asus/a8n_e/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/romstage.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/mainboard/asus/a8n_e/romstage.c Tue Apr 6 21:50:21 2010 (r5359) @@ -96,7 +96,6 @@ static void sio_setup(void) { - unsigned value; uint32_t dword; uint8_t byte; Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Tue Apr 6 21:50:21 2010 (r5359) @@ -187,7 +187,6 @@ int needs_reset = 0; struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - char *p; sio_init(); w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); Modified: trunk/src/mainboard/intel/d945gclf/Makefile.inc ============================================================================== --- trunk/src/mainboard/intel/d945gclf/Makefile.inc Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/mainboard/intel/d945gclf/Makefile.inc Tue Apr 6 21:50:21 2010 (r5359) @@ -17,11 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. -## - obj-y += rtl8168.o - smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o Modified: trunk/src/mainboard/kontron/986lcd-m/Makefile.inc ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/Makefile.inc Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/mainboard/kontron/986lcd-m/Makefile.inc Tue Apr 6 21:50:21 2010 (r5359) @@ -17,11 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. -## - obj-y += rtl8168.o - smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o Modified: trunk/src/mainboard/roda/rk886ex/Makefile.inc ============================================================================== --- trunk/src/mainboard/roda/rk886ex/Makefile.inc Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/mainboard/roda/rk886ex/Makefile.inc Tue Apr 6 21:50:21 2010 (r5359) @@ -17,13 +17,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -## -## This mainboard requires DCACHE_AS_RAM enabled. It won't work without. -## - obj-y += m3885.o obj-y += ec.o obj-y += rtl8168.o - smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o Modified: trunk/src/mainboard/tyan/s4880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/romstage.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/mainboard/tyan/s4880/romstage.c Tue Apr 6 21:50:21 2010 (r5359) @@ -56,7 +56,6 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 - int ret; unsigned device=(ctrl->channel0[0])>>8; smbus_write_byte(SMBUS_HUB, 0x01, device); smbus_write_byte(SMBUS_HUB, 0x03, 0); Modified: trunk/src/northbridge/amd/amdk8/amdk8_f.h ============================================================================== --- trunk/src/northbridge/amd/amdk8/amdk8_f.h Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/northbridge/amd/amdk8/amdk8_f.h Tue Apr 6 21:50:21 2010 (r5359) @@ -520,6 +520,8 @@ #include <reset.h> +#if ((CONFIG_MEM_TRAIN_SEQ != 1) && defined(__PRE_RAM__)) || \ + ((CONFIG_MEM_TRAIN_SEQ == 1) && !defined(__PRE_RAM__)) static void wait_all_core0_mem_trained(struct sys_info *sysinfo) { @@ -585,5 +587,6 @@ } } +#endif #endif /* AMDK8_F_H */ Modified: trunk/src/northbridge/amd/amdk8/misc_control.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/misc_control.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/northbridge/amd/amdk8/misc_control.c Tue Apr 6 21:50:21 2010 (r5359) @@ -110,7 +110,7 @@ { uint32_t cmd, cmd_ref; int needs_reset; - struct device *f0_dev, *f2_dev; + struct device *f0_dev; printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. "); needs_reset = 0; @@ -161,6 +161,7 @@ } } else if(is_cpu_pre_d0()) { + struct device *f2_dev; uint32_t dcl; f2_dev = dev_find_slot(0, dev->path.pci.devfn - 3 + 2); /* Errata 98 Modified: trunk/src/northbridge/amd/amdk8/raminit.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/northbridge/amd/amdk8/raminit.c Tue Apr 6 21:50:21 2010 (r5359) @@ -18,10 +18,6 @@ #define QRANK_DIMM_SUPPORT 0 #endif -#if defined (__GNUC__) -static void hard_reset(void); -#endif - static void setup_resource_map(const unsigned int *register_values, int max) { int i; Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/northbridge/amd/amdk8/raminit_f.c Tue Apr 6 21:50:21 2010 (r5359) @@ -707,12 +707,14 @@ printk(BIOS_SPEW, "done.\n"); } +#if 0 static int is_dual_channel(const struct mem_controller *ctrl) { uint32_t dcl; dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); return dcl & DCL_Width128; } +#endif static int is_opteron(const struct mem_controller *ctrl) { @@ -727,6 +729,7 @@ return !!(nbcap & NBCAP_128Bit); } +#if 0 static int is_registered(const struct mem_controller *ctrl) { /* Test to see if we are dealing with registered SDRAM. @@ -737,7 +740,7 @@ dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW); return !(dcl & DCL_UnBuffDimm); } - +#endif static void spd_get_dimm_size(unsigned device, struct dimm_size *sz) { @@ -2481,6 +2484,7 @@ pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); } +#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */ static void set_SlowAccessMode(const struct mem_controller *ctrl) { uint32_t dch; @@ -2491,6 +2495,7 @@ pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch); } +#endif /* DRAM_OUTPUT_DRV_COMP_CTRL 0, 0x20 Modified: trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Tue Apr 6 21:50:21 2010 (r5359) @@ -1872,6 +1872,7 @@ return pos; } +#if CONFIG_MEM_TRAIN_SEQ == 0 static int dqs_save_MC_NVRAM_ch(unsigned int dev, int ch, int pos) { /* 30 bytes per channel */ @@ -1902,6 +1903,7 @@ reg = pci_read_config32(dev, DRAM_CONFIG_HIGH); pos = s3_save_nvram_early(reg, 4, pos); } +#endif static void dqs_restore_MC_NVRAM(unsigned int dev) { Modified: trunk/src/northbridge/amd/lx/raminit.c ============================================================================== --- trunk/src/northbridge/amd/lx/raminit.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/northbridge/amd/lx/raminit.c Tue Apr 6 21:50:21 2010 (r5359) @@ -35,7 +35,7 @@ print_debug("======================================\n"); } -void hcf(void) +static void hcf(void) { print_emerg("DIE\n"); /* this guarantees we flush the UART fifos (if any) and also Modified: trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c ============================================================================== --- trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c Tue Apr 6 21:50:21 2010 (r5359) @@ -35,7 +35,7 @@ enable_cf9_x(sbbusn, sbdn); } -static void hard_reset(void) +void hard_reset(void) { set_bios_reset(); /* reset */ @@ -68,7 +68,7 @@ } -static void soft_reset(void) +void soft_reset(void) { unsigned sblk = get_sblk(); Modified: trunk/src/southbridge/amd/cs5536/cs5536_ide.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536_ide.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/southbridge/amd/cs5536/cs5536_ide.c Tue Apr 6 21:50:21 2010 (r5359) @@ -46,13 +46,6 @@ pci_write_config32(dev, IDE_CFG, ide_cfg); } -static void ide_enable(struct device *dev) -{ - - printk(BIOS_SPEW, "cs5536_ide: %s\n", __func__); - -} - static struct device_operations ide_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, Modified: trunk/src/southbridge/amd/rs780/rs780_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_early_setup.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/southbridge/amd/rs780/rs780_early_setup.c Tue Apr 6 21:50:21 2010 (r5359) @@ -371,10 +371,9 @@ #endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */ #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */ -void fam10_optimization(void) +static void fam10_optimization(void) { device_t cpu_f0, cpu_f2, cpu_f3; - msr_t msr; u32 val; printk(BIOS_INFO, "fam10_optimization()\n"); @@ -634,16 +633,16 @@ } /* enable CFG access to Dev8, which is the SB P2P Bridge */ -static void enable_rs780_dev8() +static void enable_rs780_dev8(void) { set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x00, 1 << 6, 1 << 6); } -static void rs780_before_pci_init() +static void rs780_before_pci_init(void) { } -static void rs780_early_setup() +static void rs780_early_setup(void) { device_t nb_dev = PCI_DEV(0, 0, 0); printk(BIOS_INFO, "rs780_early_setup()\n"); Modified: trunk/src/southbridge/amd/sb700/sb700_smbus.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_smbus.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/southbridge/amd/sb700/sb700_smbus.c Tue Apr 6 21:50:21 2010 (r5359) @@ -205,7 +205,7 @@ /* space = 0: AX_INDXC, AX_DATAC * space = 1: AX_INDXP, AX_DATAP */ -static void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, +static inline void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val) { u32 tmp; Modified: trunk/src/southbridge/amd/sb700/sb700_smbus.h ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_smbus.h Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/southbridge/amd/sb700/sb700_smbus.h Tue Apr 6 21:50:21 2010 (r5359) @@ -20,8 +20,6 @@ #ifndef SB700_SMBUS_H #define SB700_SMBUS_H -//#include <stdint.h> - #define SMBHSTSTAT 0x0 #define SMBSLVSTAT 0x1 #define SMBHSTCTRL 0x2 Modified: trunk/src/southbridge/via/vt8237r/vt8237_fadt.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237_fadt.c Tue Apr 6 21:49:31 2010 (r5358) +++ trunk/src/southbridge/via/vt8237r/vt8237_fadt.c Tue Apr 6 21:50:21 2010 (r5359) @@ -51,8 +51,8 @@ memcpy(header->asl_compiler_id, "CORE", 4); header->asl_compiler_revision = 42; - fadt->firmware_ctrl = facs; - fadt->dsdt = dsdt; + fadt->firmware_ctrl = (u32)facs; + fadt->dsdt = (u32)dsdt; fadt->preferred_pm_profile = 0; fadt->sci_int = 9; fadt->smi_cmd = 0; @@ -108,9 +108,9 @@ fadt->reset_reg.addrh = 0x0; fadt->reset_value = 0; - fadt->x_firmware_ctl_l = facs; + fadt->x_firmware_ctl_l = (u32)facs; fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = dsdt; + fadt->x_dsdt_l = (u32)dsdt; fadt->x_dsdt_h = 0; fadt->x_pm1a_evt_blk.space_id = 1;

2 1

[commit] r5358 - trunk/src/northbridge/amd/amdfam10
by repository service 06 Apr '10

06 Apr '10

Author: stepan Date: Tue Apr 6 21:49:31 2010 New Revision: 5358 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5358 Log: fam10 acpi fix Signed-off-by: Stefan Reinauer<stepan(a)coresystems.de> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/northbridge/amd/amdfam10/amdfam10_acpi.c Modified: trunk/src/northbridge/amd/amdfam10/amdfam10_acpi.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/amdfam10_acpi.c Mon Apr 5 19:47:34 2010 (r5357) +++ trunk/src/northbridge/amd/amdfam10/amdfam10_acpi.c Tue Apr 6 21:49:31 2010 (r5358) @@ -296,10 +296,10 @@ for(i=0;i<sysconf.p_state_num;i++) { struct p_state_t *p_state = &sysconf.p_state[nodeid * 5 + i]; - intx_to_stream(COREFREQ + i*offset, 2, p_state->corefreq); - intx_to_stream(POWER + i*offset, 3, p_state->power); - intx_to_stream(TRANSITION_LAT + i*offset, 2, p_state->transition_lat); - intx_to_stream(BUSMASTER_LAT + i*offset, 2, p_state->busmaster_lat); + intx_to_stream(p_state->corefreq, 2, COREFREQ + i*offset); + intx_to_stream(p_state->power, 3, POWER + i*offset); + intx_to_stream(p_state->transition_lat, 2, TRANSITION_LAT + i*offset); + intx_to_stream(p_state->busmaster_lat, 2, BUSMASTER_LAT + i*offset); *((u8 *)(CONTROL + i*offset)) =(u8) p_state->control; *((u8 *)(STATUS + i*offset)) =(u8) p_state->status; }

1 0

GSOC: thoughts on projects
by austinro＠msu.edu 06 Apr '10

06 Apr '10

Hi. My name's Rob Austin, I'm a computer engineering major at Michigan State University. I got on IRC for a bit a week or so ago and chatted with a few people about some of the proposed ideas. I've had some time to think and read more about what I could do for coreboot, and I'd like to get a little more feedback. - First, the "tianocore" idea. What do you see as the end result of getting tianocore working well as a payload? I've been reading about it and it sounds interesting, but I need to say something more on the application as to "why" this is a worthwhile project. What can we boot with EFI that we can't boot with a traditional bios, besides maybe OSX? - Second, just how difficult would the port to the Marvell chipset be? I'm familiar with the ARM architecture and assembly, more so than x86, and realistically in my future I'll probably be working more with embedded devices than PCs, so this might be the more valuable experience to put on a resume. Also, I was planning on applying both to coreboot and beagleboard (my fallback), doing largely the same thing. For beagleboard's GSOC project page, they have "Improve bootloader support" http://elinux.org/BeagleBoard/GSoC/Ideas#Improve_bootloader_support listed as an idea. If someone could port coreboot to one ARM device, it would probably be considerably easier to then port it to other ARM devices. I want to be up front about my ignorance here: I don't know much about BIOSes. There seems to be a hole in my computer engineering curriculum. With all the required classes, I've started understanding computers from the bottom (transistor physics and digital logic), and built up from that (combinational logic, VLSI design, computer architecture) --the hardware--, and at the same time I've been learning about them from the top down --high level languages, then assembler and operating systems, the software side. Ideally they would meet in the middle and teach about the bios, but they don't. I've asked. I don't feel that my education would be complete without this knowledge. I don't like the idea that there's hardware, software, and some magical binary blob in the middle that connects them. I want to understand it, and I want it to be open. You can't trust a blob. So that's why I want to work at the bios/hardware-initialization/bootloader level. There are only two projects for GSOC that focus on the hardware-software interface, and I'd be happy to work on either one. There are other reasons: I want to become a good programmer, and reading and writing code every day for a whole summer will do that; I want to do something meaningful that people will actually use, to give back to the open-source community after benefitting from it for so many years. So having said all that, I would appreciate any feedback as far as what the devs think is more doable/would be more useful. I'm interested in both projects, but if following one path will lead to a summer of banging my head against the wall and failure, I'd rather choose the other. Writing "I spent 3 months participating in GSOC and accomplished nothing" doesn't look so hot. Thanks. Rob Austin

3 2

[PATCH] Quick and dirty Asrock 939A785GMH support
by Rudolf Marek 05 Apr '10

05 Apr '10

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hi all, I have started a port of AMD Mahogony board to Asrock 939A785GMH. It boots kernel, IDE works, ethernet too. No VGA output need to check why the VGA BIOS extracted from orig image hangs. http://www.asrock.com/mb/overview.asp?Model=939A785GMH/128M&s=939 It has 1MB socketed SPI flash chip, serial header. There are some overclocking GPIO options hopefully now just set to safe values, check sio_init for details. http://www.assembler.cz/asrock_boots2.txt Patch is quite big because the ACPI stuff is just copied. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkugBdEACgkQ3J9wPJqZRNVjCwCgjS74JJC7LDIJ//nMcg+r9M3q vgMAniiZX/Wp3iHeXDBUzv67thDTwDOS =oP4D -----END PGP SIGNATURE-----

2 7

[commit] r5357 - in trunk/src/mainboard: . asrock asrock/939a785gmh asrock/939a785gmh/acpi
by repository service 05 Apr '10

05 Apr '10

Author: ruik Date: Mon Apr 5 21:47:34 2010 New Revision: 5357 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5357 Log: Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Add Asrock 939a785gmh motherboard. The ACPI needs more cleanup, could be done when cleaning the Mahagony board. The SidePort mode does not work because AMD hardcoded memory type in rs780_gfx.c The UMA is enabled instead. The board boots, network and int VGA works, IDE too. Added: trunk/src/mainboard/asrock/ trunk/src/mainboard/asrock/939a785gmh/ trunk/src/mainboard/asrock/939a785gmh/Kconfig trunk/src/mainboard/asrock/939a785gmh/acpi/ trunk/src/mainboard/asrock/939a785gmh/acpi/debug.asl trunk/src/mainboard/asrock/939a785gmh/acpi/globutil.asl trunk/src/mainboard/asrock/939a785gmh/acpi/ide.asl trunk/src/mainboard/asrock/939a785gmh/acpi/routing.asl trunk/src/mainboard/asrock/939a785gmh/acpi/sata.asl trunk/src/mainboard/asrock/939a785gmh/acpi/statdef.asl trunk/src/mainboard/asrock/939a785gmh/acpi/usb.asl trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c trunk/src/mainboard/asrock/939a785gmh/chip.h trunk/src/mainboard/asrock/939a785gmh/cmos.layout trunk/src/mainboard/asrock/939a785gmh/devicetree.cb trunk/src/mainboard/asrock/939a785gmh/dsdt.asl trunk/src/mainboard/asrock/939a785gmh/fadt.c trunk/src/mainboard/asrock/939a785gmh/get_bus_conf.c trunk/src/mainboard/asrock/939a785gmh/irq_tables.c trunk/src/mainboard/asrock/939a785gmh/mainboard.c trunk/src/mainboard/asrock/939a785gmh/mptable.c trunk/src/mainboard/asrock/939a785gmh/resourcemap.c trunk/src/mainboard/asrock/939a785gmh/romstage.c trunk/src/mainboard/asrock/Kconfig Modified: trunk/src/mainboard/Kconfig Modified: trunk/src/mainboard/Kconfig ============================================================================== --- trunk/src/mainboard/Kconfig Mon Apr 5 21:21:18 2010 (r5356) +++ trunk/src/mainboard/Kconfig Mon Apr 5 21:47:34 2010 (r5357) @@ -16,6 +16,8 @@ bool "Artec Group" config VENDOR_ASI bool "ASI" +config VENDOR_ASROCK + bool "ASROCK" config VENDOR_ASUS bool "ASUS" config VENDOR_A_TREND @@ -131,6 +133,11 @@ config MAINBOARD_VENDOR string + default "ASROCK" + depends on VENDOR_ASROCK + +config MAINBOARD_VENDOR + string default "ASUS" depends on VENDOR_ASUS @@ -366,6 +373,7 @@ source "src/mainboard/arima/Kconfig" source "src/mainboard/artecgroup/Kconfig" source "src/mainboard/asi/Kconfig" +source "src/mainboard/asrock/Kconfig" source "src/mainboard/asus/Kconfig" source "src/mainboard/axus/Kconfig" source "src/mainboard/azza/Kconfig" Added: trunk/src/mainboard/asrock/939a785gmh/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/939a785gmh/Kconfig Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,123 @@ +config BOARD_ASROCK_939A785GMH + bool "939A785GMH/128M" + select ARCH_X86 + select CPU_AMD_SOCKET_939 + select K8_HT_FREQ_1G_SUPPORT + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_AMD_RS780 + select SOUTHBRIDGE_AMD_SB700 + select SUPERIO_WINBOND_W83627DHG + select BOARD_HAS_FADT + select GENERATE_ACPI_TABLES + select GENERATE_MP_TABLE + select GENERATE_PIRQ_TABLE + select HAVE_MAINBOARD_RESOURCES + select HAVE_BUS_CONFIG + select LIFT_BSP_APIC_ID + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select HAVE_HARD_RESET + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + select BOARD_ROMSIZE_KB_1024 + select GFXUMA + +config MAINBOARD_DIR + string + default asrock/939a785gmh + depends on BOARD_ASROCK_939A785GMH + +config HAVE_HIGH_TABLES + bool + default n + depends on BOARD_ASROCK_939A785GMH + +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on BOARD_ASROCK_939A785GMH + +config DCACHE_RAM_SIZE + hex + default 0x08000 + depends on BOARD_ASROCK_939A785GMH + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x01000 + depends on BOARD_ASROCK_939A785GMH + +config APIC_ID_OFFSET + hex + default 0x0 + depends on BOARD_ASROCK_939A785GMH + +config LB_CKS_RANGE_END + int + default 122 + depends on BOARD_ASROCK_939A785GMH + +config LB_CKS_LOC + int + default 123 + depends on BOARD_ASROCK_939A785GMH + +config MAINBOARD_PART_NUMBER + string + default "939A785GMH" + depends on BOARD_ASROCK_939A785GMH + +config HW_MEM_HOLE_SIZEK + hex + default 0x100000 + depends on BOARD_ASROCK_939A785GMH + +config MAX_CPUS + int + default 8 + depends on BOARD_ASROCK_939A785GMH + +config MAX_PHYSICAL_CPUS + int + default 2 + depends on BOARD_ASROCK_939A785GMH + +config HW_MEM_HOLE_SIZE_AUTO_INC + bool + default n + depends on BOARD_ASROCK_939A785GMH + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + depends on BOARD_ASROCK_939A785GMH + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x1 + depends on BOARD_ASROCK_939A785GMH + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + depends on BOARD_ASROCK_939A785GMH + +config USE_INIT + bool + default n + depends on BOARD_ASROCK_939A785GMH + +config IRQ_SLOT_COUNT + int + default 11 + depends on BOARD_ASROCK_939A785GMH + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1022 + depends on BOARD_ASROCK_939A785GMH + +config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID + hex + default 0x3060 + depends on BOARD_ASROCK_939A785GMH Added: trunk/src/mainboard/asrock/939a785gmh/acpi/debug.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/939a785gmh/acpi/debug.asl Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,198 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + DefinitionBlock ( + "DSDT.AML", + "DSDT", + 0x01, + "XXXXXX", + "XXXXXXXX", + 0x00010001 + ) + { + #include "debug.asl" + } +*/ + +/* +* 0x80: POST_BASE +* 0x3F8: DEBCOM_BASE +* X80: POST_REGION +* P80: PORT80 +* +* CREG: DEBCOM_REGION +* CUAR: DEBCOM_UART +* CDAT: DEBCOM_DATA +* CDLM: DEBCOM_DLM +* DLCR: DEBCOM_LCR +* CMCR: DEBCOM_MCR +* CLSR: DEBCOM_LSR +* +* DEBUG_INIT DINI +*/ + +OperationRegion(X80, SystemIO, 0x80, 1) + Field(X80, ByteAcc, NoLock, Preserve) +{ + P80, 8 +} + +OperationRegion(CREG, SystemIO, 0x3F8, 8) + Field(CREG, ByteAcc, NoLock, Preserve) +{ + CDAT, 8, + CDLM, 8,, 8, DLCR, 8, CMCR, 8, CLSR, 8 +} + +/* +* DINI +* Initialize the COM port to 115,200 8-N-1 +*/ +Method(DINI) +{ + store(0x83, DLCR) + store(0x01, CDAT) /* 115200 baud (low) */ + store(0x00, CDLM) /* 115200 baud (high) */ + store(0x03, DLCR) /* word=8 stop=1 parity=none */ + store(0x03, CMCR) /* DTR=1 RTS=1 Out2=Off Loop=Off */ + store(0x00, CDLM) /* turn off interrupts */ +} + +/* +* THRE +* Wait for COM port transmitter holding register to go empty +*/ +Method(THRE) +{ + and(CLSR, 0x20, local0) + while (Lequal(local0, Zero)) { + and(CLSR, 0x20, local0) + } +} + +/* +* OUTX +* Send a single raw character +*/ +Method(OUTX, 1) +{ + THRE() + store(Arg0, CDAT) +} + +/* +* OUTC +* Send a single character, expanding LF into CR/LF +*/ +Method(OUTC, 1) +{ + if (LEqual(Arg0, 0x0a)) { + OUTX(0x0d) + } + OUTX(Arg0) +} + +/* +* DBGN +* Send a single hex nibble +*/ +Method(DBGN, 1) +{ + and(Arg0, 0x0f, Local0) + if (LLess(Local0, 10)) { + add(Local0, 0x30, Local0) + } else { + add(Local0, 0x37, Local0) + } + OUTC(Local0) +} + +/* +* DBGB +* Send a hex byte +*/ +Method(DBGB, 1) +{ + ShiftRight(Arg0, 4, Local0) + DBGN(Local0) + DBGN(Arg0) +} + +/* +* DBGW +* Send a hex word +*/ +Method(DBGW, 1) +{ + ShiftRight(Arg0, 8, Local0) + DBGB(Local0) + DBGB(Arg0) +} + +/* +* DBGD +* Send a hex Dword +*/ +Method(DBGD, 1) +{ + ShiftRight(Arg0, 16, Local0) + DBGW(Local0) + DBGW(Arg0) +} + +/* +* DBGO +* Send either a string or an integer +*/ +Method(DBGO, 1) +{ + /* DINI() */ + if (LEqual(ObjectType(Arg0), 1)) { + if (LGreater(Arg0, 0xffff)) { + DBGD(Arg0) + } else { + if (LGreater(Arg0, 0xff)) { + DBGW(Arg0) + } else { + DBGB(Arg0) + } + } + } else { + Name(BDBG, Buffer(80) {}) + store(Arg0, BDBG) + store(0, Local1) + while (One) { + store(GETC(BDBG, Local1), Local0) + if (LEqual(Local0, 0)) { + return (0) + } + OUTC(Local0) + Increment(Local1) + } + } + return (0) +} + +/* Get a char from a string */ +Method(GETC, 2) +{ + CreateByteField(Arg0, Arg1, DBGC) + return (DBGC) +} Added: trunk/src/mainboard/asrock/939a785gmh/acpi/globutil.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/939a785gmh/acpi/globutil.asl Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,118 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope(\_SB) { + #include "globutil.asl" +} +*/ + +/* string compare functions */ +Method(MIN, 2) +{ + if (LLess(Arg0, Arg1)) { + Return(Arg0) + } else { + Return(Arg1) + } +} + +Method(SLEN, 1) +{ + Store(Arg0, Local0) + Return(Sizeof(Local0)) +} + +Method(S2BF, 1) +{ + Add(SLEN(Arg0), One, Local0) + Name(BUFF, Buffer(Local0) {}) + Store(Arg0, BUFF) + Return(BUFF) +} + +/* Strong string compare. Checks both length and content */ +Method(SCMP, 2) +{ + Store(S2BF(Arg0), Local0) + Store(S2BF(Arg1), Local1) + Store(Zero, Local4) + Store(SLEN(Arg0), Local5) + Store(SLEN(Arg1), Local6) + Store(MIN(Local5, Local6), Local7) + + While(LLess(Local4, Local7)) { + Store(Derefof(Index(Local0, Local4)), Local2) + Store(Derefof(Index(Local1, Local4)), Local3) + if (LGreater(Local2, Local3)) { + Return(One) + } else { + if (LLess(Local2, Local3)) { + Return(Ones) + } + } + Increment(Local4) + } + if (LLess(Local4, Local5)) { + Return(One) + } else { + if (LLess(Local4, Local6)) { + Return(Ones) + } else { + Return(Zero) + } + } +} + +/* Weak string compare. Checks to find Arg1 at beginning of Arg0. +* Fails if length(Arg0) < length(Arg1). Returns 0 on Fail, 1 on +* Pass. +*/ +Method(WCMP, 2) +{ + Store(S2BF(Arg0), Local0) + Store(S2BF(Arg1), Local1) + if (LLess(SLEN(Arg0), SLEN(Arg1))) { + Return(0) + } + Store(Zero, Local2) + Store(SLEN(Arg1), Local3) + + While(LLess(Local2, Local3)) { + if (LNotEqual(Derefof(Index(Local0, Local2)), + Derefof(Index(Local1, Local2)))) { + Return(0) + } + Increment(Local2) + } + Return(One) +} + +/* ARG0 = IRQ Number(0-15) +* Returns Bit Map +*/ +Method(I2BM, 1) +{ + Store(0, Local0) + if (LNotEqual(ARG0, 0)) { + Store(1, Local1) + ShiftLeft(Local1, ARG0, Local0) + } + Return(Local0) +} Added: trunk/src/mainboard/asrock/939a785gmh/acpi/ide.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/939a785gmh/acpi/ide.asl Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,244 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "ide.asl" + } + } +} +*/ + +/* Some timing tables */ +Name(UDTT, Package(){ /* Udma timing table */ + 120, 90, 60, 45, 30, 20, 15, 0 /* UDMA modes 0 -> 6 */ +}) + +Name(MDTT, Package(){ /* MWDma timing table */ + 480, 150, 120, 0 /* Legacy DMA modes 0 -> 2 */ +}) + +Name(POTT, Package(){ /* Pio timing table */ + 600, 390, 270, 180, 120, 0 /* PIO modes 0 -> 4 */ +}) + +/* Some timing register value tables */ +Name(MDRT, Package(){ /* MWDma timing register table */ + 0x77, 0x21, 0x20, 0xFF /* Legacy DMA modes 0 -> 2 */ +}) + +Name(PORT, Package(){ + 0x99, 0x47, 0x34, 0x22, 0x20, 0x99 /* PIO modes 0 -> 4 */ +}) + +OperationRegion(ICRG, PCI_Config, 0x40, 0x20) /* ide control registers */ + Field(ICRG, AnyAcc, NoLock, Preserve) +{ + PPTS, 8, /* Primary PIO Slave Timing */ + PPTM, 8, /* Primary PIO Master Timing */ + OFFSET(0x04), PMTS, 8, /* Primary MWDMA Slave Timing */ + PMTM, 8, /* Primary MWDMA Master Timing */ + OFFSET(0x08), PPCR, 8, /* Primary PIO Control */ + OFFSET(0x0A), PPMM, 4, /* Primary PIO master Mode */ + PPSM, 4, /* Primary PIO slave Mode */ + OFFSET(0x14), PDCR, 2, /* Primary UDMA Control */ + OFFSET(0x16), PDMM, 4, /* Primary UltraDMA Mode */ + PDSM, 4, /* Primary UltraDMA Mode */ +} + +Method(GTTM, 1) /* get total time*/ +{ + Store(And(Arg0, 0x0F), Local0) /* Recovery Width */ + Increment(Local0) + Store(ShiftRight(Arg0, 4), Local1) /* Command Width */ + Increment(Local1) + Return(Multiply(30, Add(Local0, Local1))) +} + +Device(PRID) +{ + Name (_ADR, Zero) + Method(_GTM, 0) + { + NAME(OTBF, Buffer(20) { /* out buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(OTBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(OTBF, 4, DSD0) /* DMA spd0 */ + CreateDwordField(OTBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(OTBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(OTBF, 16, BFFG) /* buffer flags */ + + /* Just return if the channel is disabled */ + If(And(PPCR, 0x01)) { /* primary PIO control */ + Return(OTBF) + } + + /* Always tell them independent timing available and IOChannelReady used on both drives */ + Or(BFFG, 0x1A, BFFG) + + Store(GTTM(PPTM), PSD0) /* save total time of primary PIO master timming to PIO spd0 */ + Store(GTTM(PPTS), PSD1) /* save total time of primary PIO slave Timing to PIO spd1 */ + + If(And(PDCR, 0x01)) { /* It's under UDMA mode */ + Or(BFFG, 0x01, BFFG) + Store(DerefOf(Index(UDTT, PDMM)), DSD0) + } + Else { + Store(GTTM(PMTM), DSD0) /* Primary MWDMA Master Timing, DmaSpd0 */ + } + + If(And(PDCR, 0x02)) { /* It's under UDMA mode */ + Or(BFFG, 0x04, BFFG) + Store(DerefOf(Index(UDTT, PDSM)), DSD1) + } + Else { + Store(GTTM(PMTS), DSD1) /* Primary MWDMA Slave Timing, DmaSpd0 */ + } + + Return(OTBF) /* out buffer */ + } /* End Method(_GTM) */ + + Method(_STM, 3, NotSerialized) + { + NAME(INBF, Buffer(20) { /* in buffer */ + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00 + }) + + CreateDwordField(INBF, 0, PSD0) /* PIO spd0 */ + CreateDwordField(INBF, 4, DSD0) /* PIO spd0 */ + CreateDwordField(INBF, 8, PSD1) /* PIO spd1 */ + CreateDwordField(INBF, 12, DSD1) /* DMA spd1 */ + CreateDwordField(INBF, 16, BFFG) /*buffer flag */ + + Store(Match(POTT, MLE, PSD0, MTR, 0, 0), Local0) + Divide(Local0, 5, PPMM,) /* Primary PIO master Mode */ + Store(Match(POTT, MLE, PSD1, MTR, 0, 0), Local1) + Divide(Local1, 5, PPSM,) /* Primary PIO slave Mode */ + + Store(DerefOf(Index(PORT, Local0)), PPTM) /* Primary PIO Master Timing */ + Store(DerefOf(Index(PORT, Local1)), PPTS) /* Primary PIO Slave Timing */ + + If(And(BFFG, 0x01)) { /* Drive 0 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD0, MTR, 0, 0), Local0) + Divide(Local0, 7, PDMM,) + Or(PDCR, 0x01, PDCR) + } + Else { + If(LNotEqual(DSD0, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD0, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTM) + } + } + + If(And(BFFG, 0x04)) { /* Drive 1 is under UDMA mode */ + Store(Match(UDTT, MLE, DSD1, MTR, 0, 0), Local0) + Divide(Local0, 7, PDSM,) + Or(PDCR, 0x02, PDCR) + } + Else { + If(LNotEqual(DSD1, 0xFFFFFFFF)) { + Store(Match(MDTT, MLE, DSD1, MTR, 0, 0), Local0) + Store(DerefOf(Index(MDRT, Local0)), PMTS) + } + } + /* Return(INBF) */ + } /*End Method(_STM) */ + Device(MST) + { + Name(_ADR, 0) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xA0, CMDA) + Store(0xA0, CMDB) + Store(0xA0, CMDC) + + Or(PPMM, 0x08, POMD) + + If(And(PDCR, 0x01)) { + Or(PDMM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTM), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(MST) */ + + Device(SLAV) + { + Name(_ADR, 1) + Method(_GTF) { + Name(CMBF, Buffer(21) { + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x03, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xEF, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5 + }) + CreateByteField(CMBF, 1, POMD) + CreateByteField(CMBF, 8, DMMD) + CreateByteField(CMBF, 5, CMDA) + CreateByteField(CMBF, 12, CMDB) + CreateByteField(CMBF, 19, CMDC) + + Store(0xB0, CMDA) + Store(0xB0, CMDB) + Store(0xB0, CMDC) + + Or(PPSM, 0x08, POMD) + + If(And(PDCR, 0x02)) { + Or(PDSM, 0x40, DMMD) + } + Else { + Store(Match + (MDTT, MLE, GTTM(PMTS), + MTR, 0, 0), Local0) + If(LLess(Local0, 3)) { + Or(0x20, Local0, DMMD) + } + } + Return(CMBF) + } + } /* End Device(SLAV) */ +} Added: trunk/src/mainboard/asrock/939a785gmh/acpi/routing.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/939a785gmh/acpi/routing.asl Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,307 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "routing.asl" + } +*/ + +/* Routing is in System Bus scope */ +Scope(\_SB) { + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Package(){0x0005FFFF, 0, INTB, 0 }, */ + /* Package(){0x0005FFFF, 1, INTC, 0 }, */ + /* Package(){0x0005FFFF, 2, INTD, 0 }, */ + /* Package(){0x0005FFFF, 3, INTA, 0 }, */ + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + Package(){0x0006FFFF, 0, INTC, 0 }, + Package(){0x0006FFFF, 1, INTD, 0 }, + Package(){0x0006FFFF, 2, INTA, 0 }, + Package(){0x0006FFFF, 3, INTB, 0 }, + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + Package(){0x0007FFFF, 0, INTD, 0 }, + Package(){0x0007FFFF, 1, INTA, 0 }, + Package(){0x0007FFFF, 2, INTB, 0 }, + Package(){0x0007FFFF, 3, INTC, 0 }, + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices */ + /* Bus 0, Dev 17 - SATA controller #2 */ + /* Bus 0, Dev 18 - SATA controller #1 */ + Package(){0x0011FFFF, 0, INTA, 0 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package(){0x0012FFFF, 0, INTA, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + Package(){0x0012FFFF, 2, INTC, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTD, 0 }, + Package(){0x0013FFFF, 2, INTA, 0 }, + + /* Package(){0x0014FFFF, 1, INTA, 0 }, */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - RS780 Host Controller */ + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics */ + /* Package(){0x0001FFFF, 0, 0, 18 }, */ + /* package(){0x0001FFFF, 1, 0, 19 }, */ + + /* Bus 0, Dev 2 - PCIe Bridge for x8 PCIe Slot (GFX0) */ + Package(){0x0002FFFF, 0, 0, 18 }, + /* Package(){0x0002FFFF, 1, 0, 19 }, */ + /* Package(){0x0002FFFF, 2, 0, 16 }, */ + /* Package(){0x0002FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + Package(){0x0003FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ + Package(){0x0004FFFF, 0, 0, 16 }, + /* Package(){0x0004FFFF, 1, 0, 17 }, */ + /* Package(){0x0004FFFF, 2, 0, 18 }, */ + /* Package(){0x0004FFFF, 3, 0, 19 }, */ + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Package(){0x0005FFFF, 0, 0, 17 }, */ + /* Package(){0x0005FFFF, 1, 0, 18 }, */ + /* Package(){0x0005FFFF, 2, 0, 19 }, */ + /* Package(){0x0005FFFF, 3, 0, 16 }, */ + + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + /* Package(){0x0006FFFF, 0, 0, 18 }, */ + /* Package(){0x0006FFFF, 1, 0, 19 }, */ + /* Package(){0x0006FFFF, 2, 0, 16 }, */ + /* Package(){0x0006FFFF, 3, 0, 17 }, */ + + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + /* Package(){0x0007FFFF, 0, 0, 19 }, */ + /* Package(){0x0007FFFF, 1, 0, 16 }, */ + /* Package(){0x0007FFFF, 2, 0, 17 }, */ + /* Package(){0x0007FFFF, 3, 0, 18 }, */ + + /* Bus 0, Dev 9 - PCIe Bridge for network card */ + Package(){0x0009FFFF, 0, 0, 17 }, + /* Package(){0x0009FFFF, 1, 0, 16 }, */ + /* Package(){0x0009FFFF, 2, 0, 17 }, */ + /* Package(){0x0009FFFF, 3, 0, 18 }, */ + /* Bus 0, Dev A - PCIe Bridge for network card */ + Package(){0x000AFFFF, 0, 0, 18 }, + /* Package(){0x000AFFFF, 1, 0, 16 }, */ + /* Package(){0x000AFFFF, 2, 0, 17 }, */ + /* Package(){0x000AFFFF, 3, 0, 18 }, */ + /* Bus 0, Funct 8 - Southbridge port (normally hidden) */ + + /* SB devices in APIC mode */ + /* Bus 0, Dev 17 - SATA controller #2 */ + /* Bus 0, Dev 18 - SATA controller #1 */ + Package(){0x0011FFFF, 0, 0, 22 }, + + /* Bus 0, Dev 19 - USB: OHCI, dev 18,19 func 0-2, dev 20 func 5; + * EHCI, dev 18, 19 func 2 */ + Package(){0x0012FFFF, 0, 0, 16 }, + Package(){0x0012FFFF, 1, 0, 17 }, + Package(){0x0012FFFF, 2, 0, 18 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 19 }, + Package(){0x0013FFFF, 2, 0, 16 }, + + /* Package(){0x00140000, 0, 0, 16 }, */ + + /* Package(){0x00130004, 2, 0, 18 }, */ + /* Package(){0x00130005, 3, 0, 19 }, */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + /* Package(){0x00140004, 2, 0, 18 }, */ + /* Package(){0x00140004, 3, 0, 19 }, */ + /* Package(){0x00140005, 1, 0, 17 }, */ + /* Package(){0x00140006, 1, 0, 17 }, */ + }) + + Name(PR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, INTA, 0 }, + Package(){0x0005FFFF, 1, INTB, 0 }, + Package(){0x0005FFFF, 2, INTC, 0 }, + Package(){0x0005FFFF, 3, INTD, 0 }, + }) + + Name(APR1, Package(){ + /* Internal graphics - RS780 VGA, Bus1, Dev5 */ + Package(){0x0005FFFF, 0, 0, 18 }, + Package(){0x0005FFFF, 1, 0, 19 }, + /* Package(){0x0005FFFF, 2, 0, 20 }, */ + /* Package(){0x0005FFFF, 3, 0, 17 }, */ + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + Name(PS9, Package(){ + /* PCIe slot - Hooked to PCIe slot 9 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS9, Package(){ + /* PCIe slot - Hooked to PCIe slot 9 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + Name(PSa, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APSa, Package(){ + /* PCIe slot - Hooked to PCIe slot 10 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PCIB, Package(){ + /* PCI slots: slot 0, slot 1, behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + Package(){0x0006FFFF, 0, 0, 0x15 }, + Package(){0x0006FFFF, 1, 0, 0x16 }, + Package(){0x0006FFFF, 2, 0, 0x17 }, + Package(){0x0006FFFF, 3, 0, 0x14 }, + }) +} Added: trunk/src/mainboard/asrock/939a785gmh/acpi/sata.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/939a785gmh/acpi/sata.asl Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,149 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ + +/* +Scope (_SB) { + Device(PCI0) { + Device(SATA) { + Name(_ADR, 0x00120000) + #include "sata.asl" + } + } +} +*/ + +Name(STTM, Buffer(20) { + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x78, 0x00, 0x00, 0x00, 0x0f, 0x00, 0x00, 0x00, + 0x1f, 0x00, 0x00, 0x00 +}) + +/* Start by clearing the PhyRdyChg bits */ +Method(_INI) { + \_GPE._L1F() +} + +Device(PMRY) +{ + Name(_ADR, 0) + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(PMST) { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P0IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + }/* end of PMST */ + + Device(PSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P1IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of PSLA */ +} /* end of PMRY */ + + +Device(SEDY) +{ + Name(_ADR, 1) /* IDE Scondary Channel */ + Method(_GTM, 0x0, NotSerialized) { + Return(STTM) + } + Method(_STM, 0x3, NotSerialized) {} + + Device(SMST) + { + Name(_ADR, 0) + Method(_STA,0) { + if (LGreater(P2IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SMST */ + + Device(SSLA) + { + Name(_ADR, 1) + Method(_STA,0) { + if (LGreater(P3IS,0)) { + return (0x0F) /* sata is visible */ + } + else { + return (0x00) /* sata is missing */ + } + } + } /* end of SSLA */ +} /* end of SEDY */ + +/* SATA Hot Plug Support */ +Scope(\_GPE) { + Method(_L1F,0x0,NotSerialized) { + if (\_SB.P0PR) { + if (LGreater(\_SB.P0IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P0PR) + } + + if (\_SB.P1PR) { + if (LGreater(\_SB.P1IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.PMRY.PSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P1PR) + } + + if (\_SB.P2PR) { + if (LGreater(\_SB.P2IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SMST, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P2PR) + } + + if (\_SB.P3PR) { + if (LGreater(\_SB.P3IS,0)) { + sleep(32) + } + Notify(\_SB.PCI0.STCR.SEDY.SSLA, 0x01) /* NOTIFY_DEVICE_CHECK */ + store(one, \_SB.P3PR) + } + } +} Added: trunk/src/mainboard/asrock/939a785gmh/acpi/statdef.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/939a785gmh/acpi/statdef.asl Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +/* Status and notification definitions */ + +#define STA_MISSING 0x00 +#define STA_PRESENT 0x01 +#define STA_ENABLED 0x03 +#define STA_DISABLED 0x09 +#define STA_INVISIBLE 0x0B +#define STA_UNAVAILABLE 0x0D +#define STA_VISIBLE 0x0F + +/* SMBus status codes */ +#define SMB_OK 0x00 +#define SMB_UnknownFail 0x07 +#define SMB_DevAddrNAK 0x10 +#define SMB_DeviceError 0x11 +#define SMB_DevCmdDenied 0x12 +#define SMB_UnknownErr 0x13 +#define SMB_DevAccDenied 0x17 +#define SMB_Timeout 0x18 +#define SMB_HstUnsuppProtocol 0x19 +#define SMB_Busy 0x1A +#define SMB_PktChkError 0x1F + +/* Device Object Notification Values */ +#define NOTIFY_BUS_CHECK 0x00 +#define NOTIFY_DEVICE_CHECK 0x01 +#define NOTIFY_DEVICE_WAKE 0x02 +#define NOTIFY_EJECT_REQUEST 0x03 +#define NOTIFY_DEVICE_CHECK_JR 0x04 +#define NOTIFY_FREQUENCY_ERROR 0x05 +#define NOTIFY_BUS_MODE 0x06 +#define NOTIFY_POWER_FAULT 0x07 +#define NOTIFY_CAPABILITIES 0x08 +#define NOTIFY_PLD_CHECK 0x09 +#define NOTIFY_SLIT_UPDATE 0x0B + +/* Battery Device Notification Values */ +#define NOTIFY_BAT_STATUSCHG 0x80 +#define NOTIFY_BAT_INFOCHG 0x81 +#define NOTIFY_BAT_MAINTDATA 0x82 + +/* Power Source Object Notification Values */ +#define NOTIFY_PWR_STATUSCHG 0x80 + +/* Thermal Zone Object Notification Values */ +#define NOTIFY_TZ_STATUSCHG 0x80 +#define NOTIFY_TZ_TRIPPTCHG 0x81 +#define NOTIFY_TZ_DEVLISTCHG 0x82 +#define NOTIFY_TZ_RELTBLCHG 0x83 + +/* Power Button Notification Values */ +#define NOTIFY_POWER_BUTTON 0x80 + +/* Sleep Button Notification Values */ +#define NOTIFY_SLEEP_BUTTON 0x80 + +/* Lid Notification Values */ +#define NOTIFY_LID_STATUSCHG 0x80 + +/* Processor Device Notification Values */ +#define NOTIFY_CPU_PPCCHG 0x80 +#define NOTIFY_CPU_CSTATECHG 0x81 +#define NOTIFY_CPU_THROTLCHG 0x82 + +/* User Presence Device Notification Values */ +#define NOTIFY_USR_PRESNCECHG 0x80 + +/* Battery Device Notification Values */ +#define NOTIFY_ALS_ILLUMCHG 0x80 +#define NOTIFY_ALS_COLORTMPCHG 0x81 +#define NOTIFY_ALS_RESPCHG 0x82 + + Added: trunk/src/mainboard/asrock/939a785gmh/acpi/usb.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/939a785gmh/acpi/usb.asl Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* simple name description */ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 + ) + { + #include "usb.asl" + } +*/ +Method(UCOC, 0) { + Sleep(20) + Store(0x13,CMTI) + Store(0,GPSL) +} + +/* USB Port 0 overcurrent uses Gpm 0 */ +If(LLessEqual(UOM0,9)) { + Scope (\_GPE) { + Method (_L13) { + UCOC() + if(LEqual(GPB0,PLC0)) { + Not(PLC0,PLC0) + Store(PLC0, \_SB.PT0D) + } + } + } +} + +/* USB Port 1 overcurrent uses Gpm 1 */ +If (LLessEqual(UOM1,9)) { + Scope (\_GPE) { + Method (_L14) { + UCOC() + if (LEqual(GPB1,PLC1)) { + Not(PLC1,PLC1) + Store(PLC1, \_SB.PT1D) + } + } + } +} + +/* USB Port 2 overcurrent uses Gpm 2 */ +If (LLessEqual(UOM2,9)) { + Scope (\_GPE) { + Method (_L15) { + UCOC() + if (LEqual(GPB2,PLC2)) { + Not(PLC2,PLC2) + Store(PLC2, \_SB.PT2D) + } + } + } +} + +/* USB Port 3 overcurrent uses Gpm 3 */ +If (LLessEqual(UOM3,9)) { + Scope (\_GPE) { + Method (_L16) { + UCOC() + if (LEqual(GPB3,PLC3)) { + Not(PLC3,PLC3) + Store(PLC3, \_SB.PT3D) + } + } + } +} + +/* USB Port 4 overcurrent uses Gpm 4 */ +If (LLessEqual(UOM4,9)) { + Scope (\_GPE) { + Method (_L19) { + UCOC() + if (LEqual(GPB4,PLC4)) { + Not(PLC4,PLC4) + Store(PLC4, \_SB.PT4D) + } + } + } +} + +/* USB Port 5 overcurrent uses Gpm 5 */ +If (LLessEqual(UOM5,9)) { + Scope (\_GPE) { + Method (_L1A) { + UCOC() + if (LEqual(GPB5,PLC5)) { + Not(PLC5,PLC5) + Store(PLC5, \_SB.PT5D) + } + } + } +} + +/* USB Port 6 overcurrent uses Gpm 6 */ +If (LLessEqual(UOM6,9)) { + Scope (\_GPE) { + /* Method (_L1C) { */ + Method (_L06) { + UCOC() + if (LEqual(GPB6,PLC6)) { + Not(PLC6,PLC6) + Store(PLC6, \_SB.PT6D) + } + } + } +} + +/* USB Port 7 overcurrent uses Gpm 7 */ +If (LLessEqual(UOM7,9)) { + Scope (\_GPE) { + /* Method (_L1D) { */ + Method (_L07) { + UCOC() + if (LEqual(GPB7,PLC7)) { + Not(PLC7,PLC7) + Store(PLC7, \_SB.PT7D) + } + } + } +} + +/* USB Port 8 overcurrent uses Gpm 8 */ +If (LLessEqual(UOM8,9)) { + Scope (\_GPE) { + Method (_L17) { + if (LEqual(G8IS,PLC8)) { + Not(PLC8,PLC8) + Store(PLC8, \_SB.PT8D) + } + } + } +} + +/* USB Port 9 overcurrent uses Gpm 9 */ +If (LLessEqual(UOM9,9)) { + Scope (\_GPE) { + Method (_L0E) { + if (LEqual(G9IS,0)) { + Store(1,\_SB.PT9D) + } + } + } +} Added: trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,274 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <cpu/amd/amdk8_sysconf.h> +#include <../../../northbridge/amd/amdk8/amdk8_acpi.h> +#include <arch/cpu.h> +#include <cpu/amd/model_fxx_powernow.h> + +extern u16 pm_base; + +#define DUMP_ACPI_TABLES 0 + +/* +* Assume the max pstate number is 8 +* 0x21(33 bytes) is one package length of _PSS package +*/ + +#define Maxpstate 8 +#define Defpkglength 0x21 + +#if DUMP_ACPI_TABLES == 1 +static void dump_mem(u32 start, u32 end) +{ + + u32 i; + print_debug("dump_mem:"); + for (i = start; i < end; i++) { + if ((i & 0xf) == 0) { + printk(BIOS_DEBUG, "\n%08x:", i); + } + printk(BIOS_DEBUG, " %02x", (u8)*((u8 *)i)); + } + print_debug("\n"); +} +#endif + +extern const acpi_header_t AmlCode; + +#if CONFIG_ACPI_SSDTX_NUM >= 1 +extern const acpi_header_t AmlCode_ssdt2; +extern const acpi_header_t AmlCode_ssdt3; +extern const acpi_header_t AmlCode_ssdt4; +extern const acpi_header_t AmlCode_ssdt5; +#endif + +#define IO_APIC_ADDR 0xfec00000UL + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write SB700 IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 2, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edige-triggered, Active high */ + + /* create all subtables for processors */ + /* current = acpi_create_madt_lapic_nmis(current, 5, 1); */ + /* 1: LINT1 connect to NMI */ + + return current; +} + +extern void get_bus_conf(void); + +#if CONFIG_ACPI_SSDTX_NUM >= 1 +static void update_ssdtx(void *ssdtx, int i) +{ + u8 *PCI; + u8 *HCIN; + u8 *UID; + + PCI = ssdtx + 0x32; + HCIN = ssdtx + 0x39; + UID = ssdtx + 0x40; + + if (i < 7) { + *PCI = (u8) ('4' + i - 1); + } else { + *PCI = (u8) ('A' + i - 1 - 6); + } + *HCIN = (u8) i; + *UID = (u8) (i + 3); + + /* FIXME: need to update the GSI id in the ssdtx too */ + +} +#endif + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_rsdt_t *rsdt; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_header_t *dsdt; + acpi_header_t *ssdt; +#if CONFIG_ACPI_SSDTX_NUM >= 1 + acpi_header_t *ssdtx; + acpi_header_t const *p; + int i; +#endif + + get_bus_conf(); /* it will get sblk, pci1234, hcdn, and sbdn */ + + /* Align ACPI tables to 16 bytes */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT Table */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* clear all table memory */ + memset((void *)start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* + * We explicitly add these tables later on: + */ + /* If we want to use HPET Timers Linux wants an MADT */ + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, "DYNADATA"); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + +#if CONFIG_ACPI_SSDTX_NUM >= 1 + + /* same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table */ + + for (i = 1; i < sysconf.hc_possible_num; i++) { /* 0: is hc sblink */ + if ((sysconf.pci1234[i] & 1) != 1) + continue; + u8 c; + if (i < 7) { + c = (u8) ('4' + i - 1); + } else { + c = (u8) ('A' + i - 1 - 6); + } + printk(BIOS_DEBUG, "ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); /* pci0 and pci1 are in dsdt */ + current = (current + 0x07) & -0x08; + ssdtx = (acpi_header_t *) current; + switch (sysconf.hcid[i]) { + case 1: /* 8132 */ + p = &AmlCode_ssdt2; + break; + case 2: /* 8151 */ + p = &AmlCode_ssdt3; + break; + case 3: /* 8131 */ + p = &AmlCode_ssdt4; + break; + default: + /* HTX no io apic */ + p = &AmlCode_ssdt5; + break; + } + current += p->length; + memcpy((void *)ssdtx, p, p->length); + update_ssdtx((void *)ssdtx, i); + ssdtx->checksum = 0; + ssdtx->checksum = acpi_checksum((u8 *)ssdtx, ssdtx->length); + acpi_add_table(rsdp, ssdtx); + } +#endif + + /* FACS */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + /* DSDT */ + printk(BIOS_DEBUG, "ACPI: * DSDT\n"); + dsdt = (acpi_header_t *) current; + memcpy((void *)dsdt, &AmlCode, AmlCode.length); + current += dsdt->length; + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, dsdt->length); + /* FADT */ + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + +#if DUMP_ACPI_TABLES == 1 + printk(BIOS_DEBUG, "rsdp\n"); + dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t)); + + printk(BIOS_DEBUG, "rsdt\n"); + dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t)); + + printk(BIOS_DEBUG, "madt\n"); + dump_mem(madt, ((void *)madt) + madt->header.length); + + printk(BIOS_DEBUG, "ssdt\n"); + dump_mem(ssdt, ((void *)ssdt) + ssdt->length); + + printk(BIOS_DEBUG, "fadt\n"); + dump_mem(fadt, ((void *)fadt) + fadt->header.length); +#endif + + printk(BIOS_INFO, "ACPI: done.\n"); + return current; +} Added: trunk/src/mainboard/asrock/939a785gmh/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/939a785gmh/chip.h Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config +{ + u32 uma_size; /* How many UMA should be used in memory for TOP. */ +}; + Added: trunk/src/mainboard/asrock/939a785gmh/cmos.layout ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/939a785gmh/cmos.layout Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,119 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Advanced Micro Devices, Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## +## +## + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 dual_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + Added: trunk/src/mainboard/asrock/939a785gmh/devicetree.cb ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/939a785gmh/devicetree.cb Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,133 @@ +#Define gpp_configuration, A=0, B=1, C=2, D=3, E=4(default) +#Define port_enable, (bit map): GFX(2,3), GPP(4,5,6,7) +#Define gfx_dev2_dev3, 0: a link will never be established on Dev2 or Dev3, +# 1: the system allows a PCIE link to be established on Dev2 or Dev3. +#Define gfx_dual_slot, 0: single slot, 1: dual slot +#Define gfx_lane_reversal, 0: disable lane reversal, 1: enable +#Define gfx_tmds, 0: didn't support TMDS, 1: support +#Define gfx_compliance, 0: didn't support compliance, 1: support +#Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration +#Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 +chip northbridge/amd/amdk8/root_complex + device apic_cluster 0 on + chip cpu/amd/socket_939 + device apic 0 on end + end + end + device pci_domain 0 on + chip northbridge/amd/amdk8 + device pci 18.0 on # southbridge + chip southbridge/amd/rs780 + device pci 0.0 on end # HT 0x9600 + device pci 1.0 on end # Internal Graphics P2P bridge 0x9602 + device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603 + device pci 3.0 on end # PCIE P2P bridge 0x960b + device pci 4.0 on end # PCIE P2P bridge 0x9604 + device pci 5.0 off end # PCIE P2P bridge 0x9605 + device pci 6.0 off end # PCIE P2P bridge 0x9606 + device pci 7.0 off end # PCIE P2P bridge 0x9607 + device pci 8.0 off end # NB/SB Link P2P bridge + device pci 9.0 on end # + device pci a.0 on end # + register "gppsb_configuration" = "1" # Configuration B + register "gpp_configuration" = "3" # Configuration D default + register "port_enable" = "0x6fc" + register "gfx_dev2_dev3" = "1" + register "gfx_dual_slot" = "1" + register "gfx_lane_reversal" = "0" + register "gfx_tmds" = "0" + register "gfx_compliance" = "0" + register "gfx_reconfiguration" = "1" + register "gfx_link_width" = "0" + end + chip southbridge/amd/sb700 # it is under NB/SB Link, but on the same pri bus + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.1 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.1 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic #dimm 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic #dimm 0-1-1 + device i2c 53 on end + end + end # SM + device pci 14.1 on end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + + chip superio/winbond/w83627dhg + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + #device pnp 2e.6 off # SPI + #end + device pnp 2e.307 off # GPIO6 + end + device pnp 2e.8 on # WDTO#, PLED + end + device pnp 2e.009 on # GPIO2 + end + device pnp 2e.109 on # GPIO3 + end + device pnp 2e.209 on # GPIO4 + end + device pnp 2e.309 off # GPIO5 + end + device pnp 2e.a off # ACPI + end + device pnp 2e.b on # HWM + io 0x60 = 0x290 + end + device pnp 2e.c off # PECI, SST + end + end #superio/winbond/w8362 + + end #LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 2 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "boot_switch_sata_ide" = "0" # 0: boot from SATA. 1: IDE + register "hda_viddid" = "0x10ec0882" + end #southbridge/amd/sb700 + end # device pci 18.0 + + device pci 18.0 on end + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end #northbridge/amd/amdk8 + end #pci_domain +end #northbridge/amd/amdk8/root_complex + Added: trunk/src/mainboard/asrock/939a785gmh/dsdt.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/939a785gmh/dsdt.asl Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,1807 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "ASROCK", /* OEMID */ + "939A785GM", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include "acpi/debug.asl" */ /* Include global debug methods if needed */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, 0xE0000000) /* Base address of PCIe config space */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* USB overcurrent mapping pins. */ + Name(UOM0, 0) + Name(UOM1, 2) + Name(UOM2, 0) + Name(UOM3, 7) + Name(UOM4, 2) + Name(UOM5, 2) + Name(UOM6, 6) + Name(UOM7, 2) + Name(UOM8, 6) + Name(UOM9, 6) + + /* Some global data */ + Name(OSTP, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ + + /* PIC IRQ mapping registers, C00h-C01h */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ + } + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PINA, 0x00000008, /* Index 0 */ + PINB, 0x00000008, /* Index 1 */ + PINC, 0x00000008, /* Index 2 */ + PIND, 0x00000008, /* Index 3 */ + AINT, 0x00000008, /* Index 4 */ + SINT, 0x00000008, /* Index 5 */ + , 0x00000008, /* Index 6 */ + AAUD, 0x00000008, /* Index 7 */ + AMOD, 0x00000008, /* Index 8 */ + PINE, 0x00000008, /* Index 9 */ + PINF, 0x00000008, /* Index A */ + PING, 0x00000008, /* Index B */ + PINH, 0x00000008, /* Index C */ + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers */ + OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, + } + IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0x00), /* MiscControl */ + , 1, + T1EE, 1, + T2EE, 1, + Offset(0x01), /* MiscStatus */ + , 1, + T1E, 1, + T2E, 1, + Offset(0x04), /* SmiWakeUpEventEnable3 */ + , 7, + SSEN, 1, + Offset(0x07), /* SmiWakeUpEventStatus3 */ + , 7, + CSSM, 1, + Offset(0x10), /* AcpiEnable */ + , 6, + PWDE, 1, + Offset(0x1C), /* ProgramIoEnable */ + , 3, + MKME, 1, + IO3E, 1, + IO2E, 1, + IO1E, 1, + IO0E, 1, + Offset(0x1D), /* IOMonitorStatus */ + , 3, + MKMS, 1, + IO3S, 1, + IO2S, 1, + IO1S, 1, + IO0S,1, + Offset(0x20), /* AcpiPmEvtBlk */ + APEB, 16, + Offset(0x36), /* GEvtLevelConfig */ + , 6, + ELC6, 1, + ELC7, 1, + Offset(0x37), /* GPMLevelConfig0 */ + , 3, + PLC0, 1, + PLC1, 1, + PLC2, 1, + PLC3, 1, + PLC8, 1, + Offset(0x38), /* GPMLevelConfig1 */ + , 1, + PLC4, 1, + PLC5, 1, + , 1, + PLC6, 1, + PLC7, 1, + Offset(0x3B), /* PMEStatus1 */ + GP0S, 1, + GM4S, 1, + GM5S, 1, + APS, 1, + GM6S, 1, + GM7S, 1, + GP2S, 1, + STSS, 1, + Offset(0x55), /* SoftPciRst */ + SPRE, 1, + , 1, + , 1, + PNAT, 1, + PWMK, 1, + PWNS, 1, + + /* Offset(0x61), */ /* Options_1 */ + /* ,7, */ + /* R617,1, */ + + Offset(0x65), /* UsbPMControl */ + , 4, + URRE, 1, + Offset(0x68), /* MiscEnable68 */ + , 3, + TMTE, 1, + , 1, + Offset(0x92), /* GEVENTIN */ + , 7, + E7IS, 1, + Offset(0x96), /* GPM98IN */ + G8IS, 1, + G9IS, 1, + Offset(0x9A), /* EnhanceControl */ + ,7, + HPDE, 1, + Offset(0xA8), /* PIO7654Enable */ + IO4E, 1, + IO5E, 1, + IO6E, 1, + IO7E, 1, + Offset(0xA9), /* PIO7654Status */ + IO4S, 1, + IO5S, 1, + IO6S, 1, + IO7S, 1, + } + + /* PM1 Event Block + * First word is PM1_Status, Second word is PM1_Enable + */ + OperationRegion(P1EB, SystemIO, APEB, 0x04) + Field(P1EB, ByteAcc, NoLock, Preserve) { + TMST, 1, + , 3, + BMST, 1, + GBST, 1, + Offset(0x01), + PBST, 1, + , 1, + RTST, 1, + , 3, + PWST, 1, + SPWS, 1, + Offset(0x02), + TMEN, 1, + , 4, + GBEN, 1, + Offset(0x03), + PBEN, 1, + , 1, + RTEN, 1, + , 3, + PWDA, 1, + } + + Scope(\_SB) { + /* PCIe Configuration Space for 16 busses */ + OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + } + + + #include "acpi/routing.asl" + + Scope(\_SB) { + + Method(CkOT, 0){ + + if(LNotEqual(OSTP, Ones)) {Return(OSTP)} /* OS version was already detected */ + + if(CondRefOf(\_OSI,Local1)) + { + Store(1, OSTP) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSTP) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSTP) /* Linux */ + } Else { + Store(4, OSTP) /* Gotta be WinCE */ + } + } + Return(OSTP) + } + + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + \_SB.CIRQ() + } + Store(Arg0, PMOD) + } + Method(CIRQ, 0x00, NotSerialized){ + Store(0, PINA) + Store(0, PINB) + Store(0, PINC) + Store(0, PIND) + Store(0, PINE) + Store(0, PINF) + Store(0, PING) + Store(0, PINH) + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PINA) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKA\\_DIS\n") */ + Store(0, PINA) + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKA\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINA, IRQN) + Return(IRQB) + } /* Method(_SB.INTA._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINA) + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PINB) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKB\\_DIS\n") */ + Store(0, PINB) + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKB\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINB, IRQN) + Return(IRQB) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PINC) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKC\\_DIS\n") */ + Store(0, PINC) + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKC\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINC, IRQN) + Return(IRQB) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIND) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKD\\_DIS\n") */ + Store(0, PIND) + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKD\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIND, IRQN) + Return(IRQB) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIND) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PINE) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKE\\_DIS\n") */ + Store(0, PINE) + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKE\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTE._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINE, IRQN) + Return(IRQB) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PINF) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKF\\_DIS\n") */ + Store(0, PINF) + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKF\\_PRS\n") */ + Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINF, IRQN) + Return(IRQB) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + Method(_STA, 0) { + if (PING) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTG._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKG\\_DIS\n") */ + Store(0, PING) + } /* End Method(_SB.INTG._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKG\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTG._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PING, IRQN) + Return(IRQB) + } /* Method(_SB.INTG._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PING) + } /* End Method(_SB.INTG._SRS) */ + } /* End Device(INTG) */ + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + Method(_STA, 0) { + if (PINH) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTH._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKH\\_DIS\n") */ + Store(0, PINH) + } /* End Method(_SB.INTH._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKH\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTH._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PINH, IRQN) + Return(IRQB) + } /* Method(_SB.INTH._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PINH) + } /* End Method(_SB.INTH._SRS) */ + } /* End Device(INTH) */ + + } /* End Scope(_SB) */ + + + /* Supported sleep states: */ + Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + + If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ + } + If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ + } + If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ + } + If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ + } + + Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + + Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ + Name(CSMS, 0) /* Current System State */ + + /* Wake status package */ + Name(WKST,Package(){Zero, Zero}) + + /* + * \_PTS - Prepare to Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2, etc + * + * Exit: + * -none- + * + * The _PTS control method is executed at the beginning of the sleep process + * for S1-S5. The sleeping value is passed to the _PTS control method. This + * control method may be executed a relatively long time before entering the + * sleep state and the OS may abort the operation without notification to + * the ACPI driver. This method cannot modify the configuration or power + * state of any device in the system. + */ + Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Don't allow PCIRST# to reset USB */ + if (LEqual(Arg0,3)){ + Store(0,URRE) + } + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + \_SB.PCI0.SIOS (Arg0) + } /* End Method(\_PTS) */ + + /* + * The following method results in a "not a valid reserved NameSeg" + * warning so I have commented it out for the duration. It isn't + * used, so it could be removed. + * + * + * \_GTS OEM Going To Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + * + * Method(\_GTS, 1) { + * DBGO("\\_GTS\n") + * DBGO("From S0 to S") + * DBGO(Arg0) + * DBGO("\n") + * } + */ + + /* + * \_BFS OEM Back From Sleep method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * -none- + */ + Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + } + + /* + * \_WAK System Wake method + * + * Entry: + * Arg0=The value of the sleeping state S1=1, S2=2 + * + * Exit: + * Return package of 2 DWords + * Dword 1 - Status + * 0x00000000 wake succeeded + * 0x00000001 Wake was signaled but failed due to lack of power + * 0x00000002 Wake was signaled but failed due to thermal condition + * Dword 2 - Power Supply state + * if non-zero the effective S-state the power supply entered + */ + Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + /* Re-enable HPET */ + Store(1,HPDE) + + /* Restore PCIRST# so it resets USB */ + if (LEqual(Arg0,3)){ + Store(1,URRE) + } + + /* Arbitrarily clear PciExpWakeStatus */ + Store(PWST, PWST) + + /* if(DeRefOf(Index(WKST,0))) { + * Store(0, Index(WKST,1)) + * } else { + * Store(Arg0, Index(WKST,1)) + * } + */ + \_SB.PCI0.SIOW (Arg0) + Return(WKST) + } /* End Method(\_WAK) */ + + Scope(\_GPE) { /* Start Scope GPE */ + /* General event 0 */ + /* Method(_L00) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 1 */ + /* Method(_L01) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 2 */ + /* Method(_L02) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* General event 4 */ + /* Method(_L04) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 5 */ + /* Method(_L05) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 6 - Used for GPM6, moved to USB.asl */ + /* Method(_L06) { + * DBGO("\\_GPE\\_L00\n") + * } + */ + + /* General event 7 - Used for GPM7, moved to USB.asl */ + /* Method(_L07) { + * DBGO("\\_GPE\\_L07\n") + * } + */ + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + Notify (\_TZ.TZ00, 0x80) + } + + /* Reserved */ + /* Method(_L0A) { + * DBGO("\\_GPE\\_L0A\n") + * } + */ + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* AC97 controller PME# */ + /* Method(_L0C) { + * DBGO("\\_GPE\\_L0C\n") + * } + */ + + /* OtherTherm PME# */ + /* Method(_L0D) { + * DBGO("\\_GPE\\_L0D\n") + * } + */ + + /* GPM9 SCI event - Moved to USB.asl */ + /* Method(_L0E) { + * DBGO("\\_GPE\\_L0E\n") + * } + */ + + /* PCIe HotPlug event */ + /* Method(_L0F) { + * DBGO("\\_GPE\\_L0F\n") + * } + */ + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* PCIe PME# event */ + /* Method(_L12) { + * DBGO("\\_GPE\\_L12\n") + * } + */ + + /* GPM0 SCI event - Moved to USB.asl */ + /* Method(_L13) { + * DBGO("\\_GPE\\_L13\n") + * } + */ + + /* GPM1 SCI event - Moved to USB.asl */ + /* Method(_L14) { + * DBGO("\\_GPE\\_L14\n") + * } + */ + + /* GPM2 SCI event - Moved to USB.asl */ + /* Method(_L15) { + * DBGO("\\_GPE\\_L15\n") + * } + */ + + /* GPM3 SCI event - Moved to USB.asl */ + /* Method(_L16) { + * DBGO("\\_GPE\\_L16\n") + * } + */ + + /* GPM8 SCI event - Moved to USB.asl */ + /* Method(_L17) { + * DBGO("\\_GPE\\_L17\n") + * } + */ + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM4 SCI event - Moved to USB.asl */ + /* Method(_L19) { + * DBGO("\\_GPE\\_L19\n") + * } + */ + + /* GPM5 SCI event - Moved to USB.asl */ + /* Method(_L1A) { + * DBGO("\\_GPE\\_L1A\n") + * } + */ + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* GPM6 SCI event - Reassigned to _L06 */ + /* Method(_L1C) { + * DBGO("\\_GPE\\_L1C\n") + * } + */ + + /* GPM7 SCI event - Reassigned to _L07 */ + /* Method(_L1D) { + * DBGO("\\_GPE\\_L1D\n") + * } + */ + + /* GPIO2 or GPIO66 SCI event */ + /* Method(_L1E) { + * DBGO("\\_GPE\\_L1E\n") + * } + */ + + /* SATA SCI event - Moved to sata.asl */ + /* Method(_L1F) { + * DBGO("\\_GPE\\_L1F\n") + * } + */ + + } /* End Scope GPE */ + + #include "acpi/usb.asl" + + /* South Bridge */ + Scope(\_SB) { /* Start \_SB scope */ + #include "acpi/globutil.asl" /* global utility methods expected within the \_SB scope */ + + /* _SB.PCI0 */ + /* Note: Only need HID on Primary Bus */ + Device(PCI0) { + External (TOM1) + External (TOM2) + Name(_HID, EISAID("PNP0A03")) + Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ + Method(_BBN, 0) { /* Bus number = 0 */ + Return(0) + } + Method(_STA, 0) { + /* DBGO("\\_SB\\PCI0\\_STA\n") */ + Return(0x0B) /* Status is visible */ + } + + Method(_PRT,0) { + If(PMOD){ Return(APR0) } /* APIC mode */ + Return (PR0) /* PIC Mode */ + } /* end _PRT */ + + /* Describe the Northbridge devices */ + Device(AMRT) { + Name(_ADR, 0x00000000) + } /* end AMRT */ + + /* The internal GFX bridge */ + Device(AGPB) { + Name(_ADR, 0x00010000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + Return (APR1) + } + } /* end AGPB */ + + /* The external GFX bridge */ + Device(PBR2) { + Name(_ADR, 0x00020000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS2) } /* APIC mode */ + Return (PS2) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR2 */ + + /* Dev3 is also an external GFX bridge, not used in Herring */ + + Device(PBR4) { + Name(_ADR, 0x00040000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS4) } /* APIC mode */ + Return (PS4) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR4 */ + + Device(PBR5) { + Name(_ADR, 0x00050000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS5) } /* APIC mode */ + Return (PS5) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR5 */ + + Device(PBR6) { + Name(_ADR, 0x00060000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS6) } /* APIC mode */ + Return (PS6) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR6 */ + + /* The onboard EtherNet chip */ + Device(PBR7) { + Name(_ADR, 0x00070000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS7) } /* APIC mode */ + Return (PS7) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR7 */ + + /* GPP */ + Device(PBR9) { + Name(_ADR, 0x00090000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APS9) } /* APIC mode */ + Return (PS9) /* PIC Mode */ + } /* end _PRT */ + } /* end PBR9 */ + + Device(PBRa) { + Name(_ADR, 0x000A0000) + Name(_PRW, Package() {0x18, 4}) + Method(_PRT,0) { + If(PMOD){ Return(APSa) } /* APIC mode */ + Return (PSa) /* PIC Mode */ + } /* end _PRT */ + } /* end PBRa */ + + + /* PCI slot 1, 2, 3 */ + Device(PIBR) { + Name(_ADR, 0x00140004) + Name(_PRW, Package() {0x18, 4}) + + Method(_PRT, 0) { + Return (PCIB) + } + } + + /* Describe the Southbridge devices */ + Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" + } /* end STCR */ + + Device(UOH1) { + Name(_ADR, 0x00130000) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH1 */ + + Device(UOH2) { + Name(_ADR, 0x00130001) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH2 */ + + Device(UOH3) { + Name(_ADR, 0x00130002) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH3 */ + + Device(UOH4) { + Name(_ADR, 0x00130003) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH4 */ + + Device(UOH5) { + Name(_ADR, 0x00130004) + Name(_PRW, Package() {0x0B, 3}) + } /* end UOH5 */ + + Device(UEH1) { + Name(_ADR, 0x00130005) + Name(_PRW, Package() {0x0B, 3}) + } /* end UEH1 */ + + Device(SBUS) { + Name(_ADR, 0x00140000) + } /* end SBUS */ + + /* Primary (and only) IDE channel */ + Device(IDEC) { + Name(_ADR, 0x00140001) + #include "acpi/ide.asl" + } /* end IDEC */ + + Device(AZHD) { + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + offset (0x44), + IPCR, 4, + offset (0x54), + PWST, 2, + , 6, + PMEB, 1, + , 6, + PMST, 1, + offset (0x62), + MMCR, 1, + offset (0x64), + MMLA, 32, + offset (0x68), + MMHA, 32, + offset (0x6C), + MMDT, 16, + } + + Method(_INI) { + If(LEqual(OSTP,3)){ /* If we are running Linux */ + Store(zero, NSEN) + Store(one, NSDO) + Store(one, NSDI) + } + } + } /* end AZHD */ + + Device(LIBR) { + Name(_ADR, 0x00140003) + /* Method(_INI) { + * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") + } */ /* End Method(_SB.SBRDG._INI) */ + + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){8} + IO(Decode16,0x0070, 0x0070, 0, 2) + /* IO(Decode16,0x0070, 0x0070, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){0} + IO(Decode16, 0x0040, 0x0040, 0, 4) + /* IO(Decode16, 0x0048, 0x0048, 0, 4) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + /* IO(Decode16, 0x00D0, 0x00D0, 0x10, 0x02) */ + /* IO(Decode16, 0x04D0, 0x04D0, 0x10, 0x02) */ + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x10, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x10, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x10, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x10, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + + Device(HPTM) { + Name(_HID,EISAID("PNP0103")) + Name(CRS,ResourceTemplate() { + Memory32Fixed(ReadOnly,0xFED00000, 0x00000400, HPT) /* 1kb reserved space */ + }) + Method(_STA, 0) { + Return(0x0F) /* sata is visible */ + } + Method(_CRS, 0) { + CreateDwordField(CRS, ^HPT._BAS, HPBA) + Store(HPBA, HPBA) + Return(CRS) + } + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + } /* end LIBR */ + + Device(HPBR) { + Name(_ADR, 0x00140004) + } /* end HostPciBr */ + + Device(ACAD) { + Name(_ADR, 0x00140005) + } /* end Ac97audio */ + + Device(ACMD) { + Name(_ADR, 0x00140006) + } /* end Ac97modem */ + + /* ITE8718 Support */ + OperationRegion (IOID, SystemIO, 0x2E, 0x02) /* sometimes it is 0x4E */ + Field (IOID, ByteAcc, NoLock, Preserve) + { + SIOI, 8, SIOD, 8 /* 0x2E and 0x2F */ + } + + IndexField (SIOI, SIOD, ByteAcc, NoLock, Preserve) + { + Offset (0x07), + LDN, 8, /* Logical Device Number */ + Offset (0x20), + CID1, 8, /* Chip ID Byte 1, 0x87 */ + CID2, 8, /* Chip ID Byte 2, 0x12 */ + Offset (0x30), + ACTR, 8, /* Function activate */ + Offset (0xF0), + APC0, 8, /* APC/PME Event Enable Register */ + APC1, 8, /* APC/PME Status Register */ + APC2, 8, /* APC/PME Control Register 1 */ + APC3, 8, /* Environment Controller Special Configuration Register */ + APC4, 8 /* APC/PME Control Register 2 */ + } + + /* Enter the 8718 MB PnP Mode */ + Method (EPNP) + { + Store(0x87, SIOI) + Store(0x01, SIOI) + Store(0x55, SIOI) + Store(0x55, SIOI) /* 8718 magic number */ + } + /* Exit the 8718 MB PnP Mode */ + Method (XPNP) + { + Store (0x02, SIOI) + Store (0x02, SIOD) + } + /* + * Keyboard PME is routed to SB600 Gevent3. We can wake + * up the system by pressing the key. + */ + Method (SIOS, 1) + { + /* We only enable KBD PME for S5. */ + If (LLess (Arg0, 0x05)) + { + EPNP() + /* DBGO("8718F\n") */ + + Store (0x4, LDN) + Store (One, ACTR) /* Enable EC */ + /* + Store (0x4, LDN) + Store (0x04, APC4) + */ /* falling edge. which mode? Not sure. */ + + Store (0x4, LDN) + Store (0x08, APC1) /* clear PME status, Use 0x18 for mouse & KBD */ + Store (0x4, LDN) + Store (0x08, APC0) /* enable PME, Use 0x18 for mouse & KBD */ + + XPNP() + } + } + Method (SIOW, 1) + { + EPNP() + Store (0x4, LDN) + Store (Zero, APC0) /* disable keyboard PME */ + Store (0x4, LDN) + Store (0xFF, APC1) /* clear keyboard PME status */ + XPNP() + } + + Name(CRES, ResourceTemplate() { + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + Memory32Fixed(READWRITE, 0, 0xA0000, BSMM) + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + Memory32Fixed(READONLY, 0x000E0000, 0x00020000, RDBS) /* BIOS ROM area */ + + /* DRAM Memory from 1MB to TopMem */ + Memory32Fixed(READWRITE, 0x00100000, 0, DMLO) /* 1MB to TopMem */ + + /* BIOS space just below 4GB */ + DWORDMemory( + ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000000, /* Max-Min, RLEN */ + ,, + PCBM + ) + + /* DRAM memory from 4GB to TopMem2 */ + QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0xFFFFFFFF, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000000, /* Max-Min, RLEN */ + ,, + DMHI + ) + + /* BIOS space just below 16EB */ + QWORDMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0xFFFFFFFF, /* Granularity */ + 0x00000000, /* Min */ + 0x00000000, /* Max */ + 0x00000000, /* Translation */ + 0x00000000, /* Max-Min, RLEN */ + ,, + PEBM + ) + + }) /* End Name(_SB.PCI0.CRES) */ + + Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ + + CreateDWordField(CRES, ^EMM1._BAS, EM1B) + CreateDWordField(CRES, ^EMM1._LEN, EM1L) + CreateDWordField(CRES, ^DMLO._BAS, DMLB) + CreateDWordField(CRES, ^DMLO._LEN, DMLL) + CreateDWordField(CRES, ^PCBM._MIN, PBMB) + CreateDWordField(CRES, ^PCBM._LEN, PBML) + + CreateQWordField(CRES, ^DMHI._MIN, DMHB) + CreateQWordField(CRES, ^DMHI._LEN, DMHL) + CreateQWordField(CRES, ^PEBM._MIN, EBMB) + CreateQWordField(CRES, ^PEBM._LEN, EBML) + + If(LGreater(LOMH, 0xC0000)){ + Store(0xC0000, EM1B) /* Hole above C0000 and below E0000 */ + Subtract(LOMH, 0xC0000, EM1L) /* subtract start, assumes allocation from C0000 going up */ + } + + /* Set size of memory from 1MB to TopMem */ + Subtract(TOM1, 0x100000, DMLL) + + /* + * If(LNotEqual(TOM2, 0x00000000)){ + * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 + * Subtract(TOM2, 0x100000000, DMHL) + * } + */ + + /* If there is no memory above 4GB, put the BIOS just below 4GB */ + If(LEqual(TOM2, 0x00000000)){ + Store(PBAD,PBMB) /* Reserve the "BIOS" space */ + Store(PBLN,PBML) + } + Else { /* Otherwise, put the BIOS just below 16EB */ + ShiftLeft(PBAD,16,EBMB) /* Reserve the "BIOS" space */ + Store(PBLN,EBML) + } + + Return(CRES) /* note to change the Name buffer */ + } /* end of Method(_SB.PCI0._CRS) */ + + /* + * + * FIRST METHOD CALLED UPON BOOT + * + * 1. If debugging, print current OS and ACPI interpreter. + * 2. Get PCI Interrupt routing from ACPI VSM, this + * value is based on user choice in BIOS setup. + */ + Method(_INI, 0) { + /* DBGO("\\_SB\\_INI\n") */ + /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(__DATE__) */ + /* DBGO(" ") */ + /* DBGO(__TIME__) */ + /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n") */ + /* DBGO(" \\_OS=") */ + /* DBGO(\_OS) */ + /* DBGO("\n \\_REV=") */ + /* DBGO(\_REV) */ + /* DBGO("\n") */ + + /* Determine the OS we're running on */ + CkOT() + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\SBRI, 0x13)) { + * Store(0,\PWDE) + * } + */ + } /* End Method(_SB._INI) */ + } /* End Device(PCI0) */ + + Device(PWRB) { /* Start Power button device */ + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) /* wake from S1-S4 */ + Name(_STA, 0x0B) /* sata is invisible */ + } + } /* End \_SB scope */ + + Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ + + /* SMBUS Support */ + Mutex (SBX0, 0x00) + OperationRegion (SMB0, SystemIO, 0xB00, 0x0C) + Field (SMB0, ByteAcc, NoLock, Preserve) { + HSTS, 8, /* SMBUS status */ + SSTS, 8, /* SMBUS slave status */ + HCNT, 8, /* SMBUS control */ + HCMD, 8, /* SMBUS host cmd */ + HADD, 8, /* SMBUS address */ + DAT0, 8, /* SMBUS data0 */ + DAT1, 8, /* SMBUS data1 */ + BLKD, 8, /* SMBUS block data */ + SCNT, 8, /* SMBUS slave control */ + SCMD, 8, /* SMBUS shaow cmd */ + SEVT, 8, /* SMBUS slave event */ + SDAT, 8 /* SMBUS slave data */ + } + + Method (WCLR, 0, NotSerialized) { /* clear SMBUS status register */ + Store (0x1E, HSTS) + Store (0xFA, Local0) + While (LAnd (LNotEqual (And (HSTS, 0x1E), Zero), LGreater (Local0, Zero))) { + Stall (0x64) + Decrement (Local0) + } + + Return (Local0) + } + + Method (SWTC, 1, NotSerialized) { + Store (Arg0, Local0) + Store (0x07, Local2) + Store (One, Local1) + While (LEqual (Local1, One)) { + Store (And (HSTS, 0x1E), Local3) + If (LNotEqual (Local3, Zero)) { /* read sucess */ + If (LEqual (Local3, 0x02)) { + Store (Zero, Local2) + } + + Store (Zero, Local1) + } + Else { + If (LLess (Local0, 0x0A)) { /* read failure */ + Store (0x10, Local2) + Store (Zero, Local1) + } + Else { + Sleep (0x0A) /* 10 ms, try again */ + Subtract (Local0, 0x0A, Local0) + } + } + } + + Return (Local2) + } + + Method (SMBR, 3, NotSerialized) { + Store (0x07, Local0) + If (LEqual (Acquire (SBX0, 0xFFFF), Zero)) { + Store (WCLR (), Local0) /* clear SMBUS status register before read data */ + If (LEqual (Local0, Zero)) { + Release (SBX0) + Return (0x0) + } + + Store (0x1F, HSTS) + Store (Or (ShiftLeft (Arg1, One), One), HADD) + Store (Arg2, HCMD) + If (LEqual (Arg0, 0x07)) { + Store (0x48, HCNT) /* read byte */ + } + + Store (SWTC (0x03E8), Local1) /* 1000 ms */ + If (LEqual (Local1, Zero)) { + If (LEqual (Arg0, 0x07)) { + Store (DAT0, Local0) + } + } + Else { + Store (Local1, Local0) + } + + Release (SBX0) + } + + /* DBGO("the value of SMBusData0 register ") */ + /* DBGO(Arg2) */ + /* DBGO(" is ") */ + /* DBGO(Local0) */ + /* DBGO("\n") */ + + Return (Local0) + } + + /* THERMAL */ + Scope(\_TZ) { + Name (KELV, 2732) + Name (THOT, 800) + Name (TCRT, 850) + + ThermalZone(TZ00) { + Method(_AC0,0) { /* Active Cooling 0 (0=highest fan speed) */ + /* DBGO("\\_TZ\\TZ00\\_AC0\n") */ + Return(Add(0, 2730)) + } + Method(_AL0,0) { /* Returns package of cooling device to turn on */ + /* DBGO("\\_TZ\\TZ00\\_AL0\n") */ + Return(Package() {\_TZ.TZ00.FAN0}) + } + Device (FAN0) { + Name(_HID, EISAID("PNP0C0B")) + Name(_PR0, Package() {PFN0}) + } + + PowerResource(PFN0,0,0) { + Method(_STA) { + Store(0xF,Local0) + Return(Local0) + } + Method(_ON) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _ON\n") */ + } + Method(_OFF) { + /* DBGO("\\_TZ\\TZ00\\FAN0 _OFF\n") */ + } + } + + Method(_HOT,0) { /* return hot temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_HOT\n") */ + Return (Add (THOT, KELV)) + } + Method(_CRT,0) { /* return critical temp in tenths degree Kelvin */ + /* DBGO("\\_TZ\\TZ00\\_CRT\n") */ + Return (Add (TCRT, KELV)) + } + Method(_TMP,0) { /* return current temp of this zone */ + Store (SMBR (0x07, 0x4C,, 0x00), Local0) + If (LGreater (Local0, 0x10)) { + Store (Local0, Local1) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400, KELV)) + } + + Store (SMBR (0x07, 0x4C, 0x01), Local0) + /* only the two MSBs in the external temperature low byte are used, resolution 0.25. We ignore it */ + /* Store (SMBR (0x07, 0x4C, 0x10), Local2) */ + If (LGreater (Local0, 0x10)) { + If (LGreater (Local0, Local1)) { + Store (Local0, Local1) + } + + Multiply (Local1, 10, Local1) + Return (Add (Local1, KELV)) + } + Else { + Add (Local0, THOT, Local0) + Return (Add (400 , KELV)) + } + } /* end of _TMP */ + } /* end of TZ00 */ + } +} +/* End of ASL file */ Added: trunk/src/mainboard/asrock/939a785gmh/fadt.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/939a785gmh/fadt.c Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,201 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + */ + +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <device/device.h> +#include <../southbridge/amd/sb700/sb700.h> + +/*extern*/ u16 pm_base = 0x800; +/* pm_base should be set in sb acpi */ +/* pm_base should be got from bar2 of rs780. Here I compact ACPI + * registers into 32 bytes limit. + * */ + +#define ACPI_PM_EVT_BLK (pm_base + 0x00) /* 4 bytes */ +#define ACPI_PM1_CNT_BLK (pm_base + 0x04) /* 2 bytes */ +#define ACPI_PMA_CNT_BLK (pm_base + 0x0F) /* 1 byte */ +#define ACPI_PM_TMR_BLK (pm_base + 0x18) /* 4 bytes */ +#define ACPI_GPE0_BLK (pm_base + 0x10) /* 8 bytes */ +#define ACPI_CPU_CONTORL (pm_base + 0x08) /* 6 bytes */ + +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + pm_base &= 0xFFFF; + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", pm_base); + + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = 244; + header->revision = 1; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, "COREBOOT", 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + fadt->firmware_ctrl = (u32) facs; + fadt->dsdt = (u32) dsdt; + /* 3=Workstation,4=Enterprise Server, 7=Performance Server */ + fadt->preferred_pm_profile = 0x03; + fadt->sci_int = 9; + /* disable system management mode by setting to 0: */ + fadt->smi_cmd = 0; + fadt->acpi_enable = 0xf0; + fadt->acpi_disable = 0xf1; + fadt->s4bios_req = 0x0; + fadt->pstate_cnt = 0xe2; + + pm_iowrite(0x20, ACPI_PM_EVT_BLK & 0xFF); + pm_iowrite(0x21, ACPI_PM_EVT_BLK >> 8); + pm_iowrite(0x22, ACPI_PM1_CNT_BLK & 0xFF); + pm_iowrite(0x23, ACPI_PM1_CNT_BLK >> 8); + pm_iowrite(0x24, ACPI_PM_TMR_BLK & 0xFF); + pm_iowrite(0x25, ACPI_PM_TMR_BLK >> 8); + pm_iowrite(0x28, ACPI_GPE0_BLK & 0xFF); + pm_iowrite(0x29, ACPI_GPE0_BLK >> 8); + + /* CpuControl is in \_PR.CPU0, 6 bytes */ + pm_iowrite(0x26, ACPI_CPU_CONTORL & 0xFF); + pm_iowrite(0x27, ACPI_CPU_CONTORL >> 8); + + pm_iowrite(0x2A, 0); /* AcpiSmiCmdLo */ + pm_iowrite(0x2B, 0); /* AcpiSmiCmdHi */ + + pm_iowrite(0x2C, ACPI_PMA_CNT_BLK & 0xFF); + pm_iowrite(0x2D, ACPI_PMA_CNT_BLK >> 8); + + pm_iowrite(0x0E, 1<<3 | 0<<2); /* AcpiDecodeEnable, When set, SB uses + * the contents of the PM registers at + * index 20-2B to decode ACPI I/O address. + * AcpiSmiEn & SmiCmdEn*/ + pm_iowrite(0x10, 1<<1 | 1<<3| 1<<5); /* RTC_En_En, TMR_En_En, GBL_EN_EN */ + outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ + + fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = ACPI_PMA_CNT_BLK; + fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; + fadt->gpe0_blk = ACPI_GPE0_BLK; + fadt->gpe1_blk = 0x0000; /* we dont have gpe1 block, do we? */ + + fadt->pm1_evt_len = 4; + fadt->pm1_cnt_len = 2; + fadt->pm2_cnt_len = 1; + fadt->pm_tmr_len = 4; + fadt->gpe0_blk_len = 8; + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + + fadt->cst_cnt = 0xe3; + fadt->p_lvl2_lat = 101; + fadt->p_lvl3_lat = 1001; + fadt->flush_size = 0; + fadt->flush_stride = 0; + fadt->duty_offset = 1; + fadt->duty_width = 3; + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alrm work */ + fadt->iapc_boot_arch = 0x3; /* See table 5-11 */ + fadt->flags = 0x0001c1a5;/* 0x25; */ + + fadt->res2 = 0; + + fadt->reset_reg.space_id = 1; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.resv = 0; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + fadt->x_firmware_ctl_l = (u32) facs; + fadt->x_firmware_ctl_h = 0; + fadt->x_dsdt_l = (u32) dsdt; + fadt->x_dsdt_h = 0; + + fadt->x_pm1a_evt_blk.space_id = 1; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.resv = 0; + fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = 1; + fadt->x_pm1b_evt_blk.bit_width = 4; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.resv = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + fadt->x_pm1a_cnt_blk.space_id = 1; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.resv = 0; + fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = 1; + fadt->x_pm1b_cnt_blk.bit_width = 2; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.resv = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + fadt->x_pm2_cnt_blk.space_id = 1; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.resv = 0; + fadt->x_pm2_cnt_blk.addrl = ACPI_PMA_CNT_BLK; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + fadt->x_pm_tmr_blk.space_id = 1; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.resv = 0; + fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; + fadt->x_pm_tmr_blk.addrh = 0x0; + + fadt->x_gpe0_blk.space_id = 1; + fadt->x_gpe0_blk.bit_width = 32; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.resv = 0; + fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; + fadt->x_gpe0_blk.addrh = 0x0; + + fadt->x_gpe1_blk.space_id = 1; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.resv = 0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); +} Added: trunk/src/mainboard/asrock/939a785gmh/get_bus_conf.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/939a785gmh/get_bus_conf.c Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,139 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> +#include <stdint.h> +#include <stdlib.h> +#if CONFIG_LOGICAL_CPUS==1 +#include <cpu/amd/multicore.h> +#endif + +#include <cpu/amd/amdk8_sysconf.h> + +/* Global variables for MB layouts and these will be shared by irqtable mptable +* and acpi_tables busnum is default. +*/ +u8 bus_isa; +u8 bus_rs780[11]; +u8 bus_sb700[2]; +u32 apicid_sb700; + +/* +* Here you only need to set value in pci1234 for HT-IO that could be installed or not +* You may need to preset pci1234 for HTIO board, +* please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail +*/ +u32 pci1234x[] = { + 0x0000ff0, +}; + +/* +* HT Chain device num, actually it is unit id base of every ht device in chain, +* assume every chain only have 4 ht device at most +*/ +u32 hcdnx[] = { + 0x20202020, +}; + +u32 bus_type[256]; + +u32 sbdn_rs780; +u32 sbdn_sb700; + +extern void get_sblk_pci1234(void); + +static u32 get_bus_conf_done = 0; + +void get_bus_conf(void); + +void get_bus_conf(void) +{ + u32 apicid_base; + device_t dev; + int i, j; + + if (get_bus_conf_done == 1) + return; /* do it only once */ + get_bus_conf_done = 1; + + sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); + for (i = 0; i < sysconf.hc_possible_num; i++) { + sysconf.pci1234[i] = pci1234x[i]; + sysconf.hcdn[i] = hcdnx[i]; + } + + get_sblk_pci1234(); + + sysconf.sbdn = (sysconf.hcdn[0] & 0xff); + sbdn_rs780 = sysconf.sbdn; + sbdn_sb700 = 0; + + for (i = 0; i < 2; i++) { + bus_sb700[i] = 0; + } + for (i = 0; i < ARRAY_SIZE(bus_rs780); i++) { + bus_rs780[i] = 0; + } + + for (i = 0; i < 256; i++) { + bus_type[i] = 0; /* default ISA bus. */ + } + + bus_type[0] = 1; /* pci */ + + bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff; + bus_sb700[0] = bus_rs780[0]; + + bus_type[bus_rs780[0]] = 1; + + /* sb700 */ + dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4)); + if (dev) { + bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + for (j = bus_sb700[1]; j < bus_isa; j++) + bus_type[j] = 1; + } + + /* rs780 */ + for (i = 1; i < ARRAY_SIZE(bus_rs780); i++) { + dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0)); + if (dev) { + bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + if(255 != bus_rs780[i]) { + bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); + bus_isa++; + bus_type[bus_rs780[i]] = 1; /* PCI bus. */ + } + } + } + + /* I/O APICs: APIC ID Version State Address */ + bus_isa = 10; +#if CONFIG_LOGICAL_CPUS==1 + apicid_base = get_apicid_base(1); +#else + apicid_base = CONFIG_MAX_PHYSICAL_CPUS; +#endif + apicid_sb700 = apicid_base + 0; +} Added: trunk/src/mainboard/asrock/939a785gmh/irq_tables.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/939a785gmh/irq_tables.c Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* This file was generated by getpir.c, do not modify! + (but if you do, please run checkpir on it to verify) + Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up + + Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM +*/ +#include <console/console.h> +#include <device/pci.h> +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> + +#include <cpu/amd/amdk8_sysconf.h> + +extern void get_bus_conf(void); + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} +extern u8 bus_isa; +extern u8 bus_rs780[8]; +extern u8 bus_sb700[2]; +extern unsigned long sbdn_sb700; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + get_bus_conf(); /* it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c */ + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be betweeen 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = bus_sb700[0]; + pirq->rtr_devfn = ((sbdn_sb700 + 0x14) << 3) | 4; + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, bus_sb700[0], ((sbdn_sb700 + 0x14) << 3) | 4, + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} Added: trunk/src/mainboard/asrock/939a785gmh/mainboard.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/939a785gmh/mainboard.c Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,174 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <arch/io.h> +#include <boot/coreboot_tables.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/mtrr.h> +#include <device/pci_def.h> +#include <arch/coreboot_tables.h> +#include <../southbridge/amd/sb700/sb700.h> +#include "chip.h" + +#define SMBUS_IO_BASE 0x6000 + +extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, + uint64_t start, uint64_t size); + +uint64_t uma_memory_base, uma_memory_size; + +void set_pcie_dereset(void); +void set_pcie_reset(void); + +/* + * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to + * pull it up before training the slot. + ***/ +void set_pcie_dereset() +{ + u16 word; + device_t sm_dev; + /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ + sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + + word = pci_read_config16(sm_dev, 0xA8); + word |= (1 << 0) | (1 << 2); /* Set Gpio6,4 as output */ + word &= ~((1 << 8) | (1 << 10)); + pci_write_config16(sm_dev, 0xA8, word); +} + +void set_pcie_reset() +{ + u16 word; + device_t sm_dev; + /* GPIO 6 reset PCIe slot, GPIO 4 reset GFX PCIe */ + sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + + word = pci_read_config16(sm_dev, 0xA8); + word &= ~((1 << 0) | (1 << 2)); /* Set Gpio6,4 as output */ + word &= ~((1 << 8) | (1 << 10)); + pci_write_config16(sm_dev, 0xA8, word); +} + +#if 0 /* not tested yet */ +/******************************************************** +* mahogany uses SB700 GPIO9 to detect IDE_DMA66. +* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to +* get the cable type, 40 pin or 80 pin? +********************************************************/ +static void get_ide_dma66(void) +{ + u8 byte; + /*u32 sm_dev, ide_dev; */ + device_t sm_dev, ide_dev; + + sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + + byte = pci_read_config8(sm_dev, 0xA9); + byte |= (1 << 5); /* Set Gpio9 as input */ + pci_write_config8(sm_dev, 0xA9, byte); + + ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1)); + byte = pci_read_config8(ide_dev, 0x56); + byte &= ~(7 << 0); + if ((1 << 5) & pci_read_config8(sm_dev, 0xAA)) + byte |= 2 << 0; /* mode 2 */ + else + byte |= 5 << 0; /* mode 5 */ + pci_write_config8(ide_dev, 0x56, byte); +} +#endif /* get_ide_dma66 */ + +/************************************************* +* enable the dedicated function in mahogany board. +* This function called early than rs780_enable. +*************************************************/ +static void mahogany_enable(device_t dev) +{ + /* Leave it for future. */ + /* struct mainboard_config *mainboard = + (struct mainboard_config *)dev->chip_info;*/ + + printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev); + +#if (CONFIG_GFXUMA == 1) + msr_t msr, msr2; + + /* TOP_MEM: the top of DRAM below 4G */ + msr = rdmsr(TOP_MEM); + printk + (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", + __func__, msr.lo, msr.hi); + + /* TOP_MEM2: the top of DRAM above 4G */ + msr2 = rdmsr(TOP_MEM2); + printk + (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n", + __func__, msr2.lo, msr2.hi); + + /* refer to UMA Size Consideration in 780 BDG. */ + switch (msr.lo) { + case 0x10000000: /* 256M system memory */ + uma_memory_size = 0x4000000; /* 64M recommended UMA */ + break; + + case 0x20000000: /* 512M system memory */ + uma_memory_size = 0x8000000; /* 128M recommended UMA */ + break; + + default: /* 1GB and above system memory */ + uma_memory_size = 0x10000000; /* 256M recommended UMA */ + break; + } + + uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */ + printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", + __func__, uma_memory_size, uma_memory_base); + + /* TODO: TOP_MEM2 */ +#else + uma_memory_size = 0x8000000; /* 128M recommended UMA */ + uma_memory_base = 0x38000000; /* 1GB system memory supposed */ +#endif + + set_pcie_dereset(); + /* get_ide_dma66(); */ +} + +int add_mainboard_resources(struct lb_memory *mem) +{ + /* UMA is removed from system memory in the northbridge code, but + * in some circumstances we want the memory mentioned as reserved. + */ +#if (CONFIG_GFXUMA == 1) + printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n", + uma_memory_base, uma_memory_size); + lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, + uma_memory_size); +#endif + return 0; +} + +struct chip_operations mainboard_ops = { + CHIP_NAME("AMD MAHOGANY Mainboard") + .enable_dev = mahogany_enable, +}; Added: trunk/src/mainboard/asrock/939a785gmh/mptable.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/939a785gmh/mptable.c Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,219 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + + +#include <console/console.h> +#include <arch/smp/mpspec.h> +#include <device/pci.h> +#include <arch/io.h> +#include <string.h> +#include <stdint.h> + +#include <cpu/amd/amdk8_sysconf.h> + +extern u8 bus_isa; +extern u8 bus_rs780[11]; +extern u8 bus_sb700[2]; + +extern u32 apicid_sb700; + +extern u32 bus_type[256]; +extern u32 sbdn_rs780; +extern u32 sbdn_sb700; + +extern void get_bus_conf(void); + +static void *smp_write_config_table(void *v) +{ + static const char sig[4] = "PCMP"; + static const char oem[8] = "AMD "; + static const char productid[12] = "MAHOGANY "; + struct mp_config_table *mc; + int j; + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + memset(mc, 0, sizeof(*mc)); + + memcpy(mc->mpc_signature, sig, sizeof(sig)); + mc->mpc_length = sizeof(*mc); /* initially just the header */ + mc->mpc_spec = 0x04; + mc->mpc_checksum = 0; /* not yet computed */ + memcpy(mc->mpc_oem, oem, sizeof(oem)); + memcpy(mc->mpc_productid, productid, sizeof(productid)); + mc->mpc_oemptr = 0; + mc->mpc_oemsize = 0; + mc->mpc_entry_count = 0; /* No entries yet... */ + mc->mpc_lapic = LAPIC_ADDR; + mc->mpe_length = 0; + mc->mpe_checksum = 0; + mc->reserved = 0; + + smp_write_processors(mc); + + get_bus_conf(); + + /* Bus: Bus ID Type */ + /* define bus and isa numbers */ + for (j = 0; j < bus_isa; j++) { + smp_write_bus(mc, j, (char *)"PCI "); + } + smp_write_bus(mc, bus_isa, (char *)"ISA "); + + /* I/O APICs: APIC ID Version State Address */ + { + device_t dev; + u32 dword; + u8 byte; + + dev = + dev_find_slot(bus_sb700[0], + PCI_DEVFN(sbdn_sb700 + 0x14, 0)); + if (dev) { + dword = pci_read_config32(dev, 0x74) & 0xfffffff0; + smp_write_ioapic(mc, apicid_sb700, 0x11, dword); + + /* Initialize interrupt mapping */ + /* aza */ + byte = pci_read_config8(dev, 0x63); + byte &= 0xf8; + byte |= 0; /* 0: INTA, ...., 7: INTH */ + pci_write_config8(dev, 0x63, byte); + + /* SATA */ + dword = pci_read_config32(dev, 0xac); + dword &= ~(7 << 26); + dword |= 6 << 26; /* 0: INTA, ...., 7: INTH */ + /* dword |= 1<<22; PIC and APIC co exists */ + pci_write_config32(dev, 0xac, dword); + + /* + * 00:12.0: PROG SATA : INT F + * 00:13.0: INTA USB_0 + * 00:13.1: INTB USB_1 + * 00:13.2: INTC USB_2 + * 00:13.3: INTD USB_3 + * 00:13.4: INTC USB_4 + * 00:13.5: INTD USB2 + * 00:14.1: INTA IDE + * 00:14.2: Prog HDA : INT E + * 00:14.5: INTB ACI + * 00:14.6: INTB MCI + */ + } + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_intsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + + IO_LOCAL_INT(mp_ExtINT, 0x0, apicid_sb700, 0x0); + + /* ISA ints are edge-triggered, and usually originate from the ISA bus, + * or its remainings. + */ +#define ISA_INT(intr, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, (intr), apicid_sb700, (pin)) + + ISA_INT(0x1, 0x1); + ISA_INT(0x0, 0x2); + ISA_INT(0x3, 0x3); + ISA_INT(0x4, 0x4); + ISA_INT(0x6, 0x6); + ISA_INT(0x7, 0x7); + ISA_INT(0xc, 0xc); + ISA_INT(0xd, 0xd); + ISA_INT(0xe, 0xe); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#if CONFIG_GENERATE_ACPI_TABLES == 0 +#define PCI_INT(bus, dev, fn, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(fn)), apicid_sb700, (pin)) +#else +#define PCI_INT(bus, dev, fn, pin) +#endif + + /* usb */ + PCI_INT(0x0, 0x12, 0x0, 0x10); /* USB */ + PCI_INT(0x0, 0x12, 0x1, 0x11); + PCI_INT(0x0, 0x13, 0x0, 0x12); + PCI_INT(0x0, 0x13, 0x1, 0x13); + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, 0x16); + + /* HD Audio: b0:d20:f1:reg63 should be 0. */ + /* PCI_INT(0x0, 0x14, 0x2, 0x12); */ + + /* on board NIC & Slot PCIE. */ + /* PCI_INT(bus_rs780[0x1], 0x5, 0x0, 0x12); */ +/* PCI_INT(bus_rs780[0x1], 0x5, 0x1, 0x13); */ + PCI_INT(bus_rs780[0x2], 0x0, 0x0, 0x12); /* Dev 2, external GFX */ + /* PCI_INT(bus_rs780[0x3], 0x0, 0x0, 0x13); */ + PCI_INT(bus_rs780[0x4], 0x0, 0x0, 0x10); + /* configuration B doesnt need dev 5,6,7 */ + /* + * PCI_INT(bus_rs780[0x5], 0x0, 0x0, 0x11); + * PCI_INT(bus_rs780[0x6], 0x0, 0x0, 0x12); + * PCI_INT(bus_rs780[0x7], 0x0, 0x0, 0x13); + */ + PCI_INT(bus_rs780[0x9], 0x0, 0x0, 0x11); + PCI_INT(bus_rs780[0xA], 0x0, 0x0, 0x12); /* NIC */ + + /* PCI slots */ + /* PCI_SLOT 0. */ + PCI_INT(bus_sb700[1], 0x5, 0x0, 0x14); + PCI_INT(bus_sb700[1], 0x5, 0x1, 0x15); + PCI_INT(bus_sb700[1], 0x5, 0x2, 0x16); + PCI_INT(bus_sb700[1], 0x5, 0x3, 0x17); + + /* PCI_SLOT 1. */ + PCI_INT(bus_sb700[1], 0x6, 0x0, 0x15); + PCI_INT(bus_sb700[1], 0x6, 0x1, 0x16); + PCI_INT(bus_sb700[1], 0x6, 0x2, 0x17); + PCI_INT(bus_sb700[1], 0x6, 0x3, 0x14); + + /* PCI_SLOT 2. */ + PCI_INT(bus_sb700[1], 0x7, 0x0, 0x16); + PCI_INT(bus_sb700[1], 0x7, 0x1, 0x17); + PCI_INT(bus_sb700[1], 0x7, 0x2, 0x14); + PCI_INT(bus_sb700[1], 0x7, 0x3, 0x15); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0x0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + mc->mpe_checksum = + smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + printk(BIOS_DEBUG, "Wrote the mp table end at: %p - %p\n", + mc, smp_next_mpe_entry(mc)); + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} Added: trunk/src/mainboard/asrock/939a785gmh/resourcemap.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/939a785gmh/resourcemap.c Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,278 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static void setup_939a785gmh_resource_map(void) +{ + static const unsigned int register_values[] = { + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001, + PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002, + PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003, + PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004, + PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005, + PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006, + PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007, + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [13:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000, + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff00, + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003, + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff000, + PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000, + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ + PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003, + PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000, + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration regin i + */ + PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x08000003, + PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000, + PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000, + }; + + int max; + max = ARRAY_SIZE(register_values); + setup_resource_map(register_values, max); +} Added: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,248 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define RAMINIT_SYSINFO 1 +#define K8_SET_FIDVID 1 +#define QRANK_DIMM_SUPPORT 1 +#if CONFIG_LOGICAL_CPUS==1 +#define SET_NB_CFG_54 1 +#endif + +#define RC0 (6<<8) +#define RC1 (7<<8) + +#define DIMM0 0x50 +#define DIMM1 0x51 + +#define ICS951462_ADDRESS 0x69 +#define SMBUS_HUB 0x71 + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/x86/lapic.h> +#include "option_table.h" +#include "pc80/mc146818rtc_early.c" +#include "pc80/serial.c" +#include "console/console.c" + +#include <cpu/amd/model_fxx_rev.h> +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" + +#include "cpu/x86/lapic/boot_cpu.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "superio/winbond/w83627dhg/w83627dhg_early_serial.c" + +#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/bist.h" + +#include "northbridge/amd/amdk8/setup_resource_map.c" + +#include "southbridge/amd/rs780/rs780_early_setup.c" +#include "southbridge/amd/sb700/sb700_early_setup.c" +#include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */ + +#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) +#define GPIO6_DEV PNP_DEV(0x2e, W83627DHG_GPIO6) +#define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345) + +/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ +static void memreset(int controllers, const struct mem_controller *ctrl) +{ +} + +/* called in raminit_f.c */ +static inline void activate_spd_rom(const struct mem_controller *ctrl) +{ +} + +/*called in raminit_f.c */ +static inline int spd_read_byte(u32 device, u32 address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/raminit.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "lib/generic_sdram.c" +#include "resourcemap.c" + +#include "cpu/amd/dualcore/dualcore.c" + +#include "cpu/amd/car/copy_and_run.c" +#include "cpu/amd/car/post_cache_as_ram.c" + +#include "cpu/amd/model_fxx/init_cpus.c" + +#include "cpu/amd/model_fxx/fidvid.c" + +#include "northbridge/amd/amdk8/early_ht.c" + +void sio_init(void) +{ + u8 reg; + + pnp_enter_ext_func_mode(GPIO2345_DEV); + pnp_set_logical_device(GPIO2345_DEV); + + /* Pin 119 ~ 120 GP21, GP20 */ + reg = pnp_read_config(GPIO2345_DEV, 0x29); + pnp_write_config(GPIO2345_DEV, 0x29, (reg | 2)); + + /* todo document this */ + pnp_write_config(GPIO2345_DEV, 0x2c, 0x1); + pnp_write_config(GPIO2345_DEV, 0x2d, 0x1); + + +//idx 30 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f0 f1 f2 f3 f4 f5 f6 f7 fe +//val 07 XX XX XX f6 0e 00 00 00 00 ff d6 96 00 40 d0 83 00 00 07 + +//GPO20 - 1 = 1.82 0 = 1.92 sideport voltage +//mGPUV GPO40 | GPO41 | GPIO23 - 000 - 1.45V step 0.05 -- 111 - 1.10V +//DDR voltage 44 45 46 + + /* GPO20 - sideport voltage GPO23 - mgpuV */ + pnp_write_config(GPIO2345_DEV, 0x30, 0x07); /* Enable GPIO 2,3,4. */ + pnp_write_config(GPIO2345_DEV, 0xe3, 0xf6); /* dir of GPIO2 11110110*/ + pnp_write_config(GPIO2345_DEV, 0xe4, 0x0e); /* data */ + pnp_write_config(GPIO2345_DEV, 0xe5, 0x00); /* No inversion */ + + /* GPO30 GPO33 GPO35 */ + //GPO35 - loadline control 0 - enabled + //GPIO30 - unknown + //GPIO33 - unknown + pnp_write_config(GPIO2345_DEV, 0xf0, 0xd6); /* dir of GPIO3 11010110*/ + pnp_write_config(GPIO2345_DEV, 0xf1, 0x96); /* data */ + pnp_write_config(GPIO2345_DEV, 0xf2, 0x00); /* No inversion */ + + /* GPO40 GPO41 GPO42 GPO43 PO45 */ + pnp_write_config(GPIO2345_DEV, 0xf4, 0xd0); /* dir of GPIO4 11010000 */ + pnp_write_config(GPIO2345_DEV, 0xf5, 0x83); /* data */ + pnp_write_config(GPIO2345_DEV, 0xf6, 0x00); /* No inversion */ + + pnp_write_config(GPIO2345_DEV, 0xf7, 0x00); /* MFC */ + pnp_write_config(GPIO2345_DEV, 0xf8, 0x00); /* MFC */ + pnp_write_config(GPIO2345_DEV, 0xfe, 0x07); /* trig type */ + pnp_exit_ext_func_mode(GPIO2345_DEV); +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; + int needs_reset = 0; + u32 bsp_apicid = 0; + msr_t msr; + struct cpuid_result cpuid1; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb700_lpc_port80(); */ + sb700_pci_port80(); + } + + if (bist == 0) { + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + } + + enable_rs780_dev8(); + sb700_lpc_init(); + + sio_init(); + w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); + console_init(); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + printk(BIOS_DEBUG, "bsp_apicid=0x%x\n", bsp_apicid); + + setup_939a785gmh_resource_map(); + + setup_coherent_ht_domain(); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched */ + wait_all_core0_started(); + start_other_cores(); +#endif + wait_all_aps_started(bsp_apicid); + + ht_setup_chains_x(sysinfo); + + /* run _early_setup before soft-reset. */ + rs780_early_setup(); + sb700_early_setup(); + + /* Check to see if processor is capable of changing FIDVID */ + /* otherwise it will throw a GP# when reading FIDVID_STATUS */ + cpuid1 = cpuid(0x80000007); + if( (cpuid1.edx & 0x6) == 0x6 ) { + + /* Read FIDVID_STATUS */ + msr=rdmsr(0xc0010042); + printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + + enable_fid_change(); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + init_fidvid_bsp(bsp_apicid); + + /* show final fid and vid */ + msr=rdmsr(0xc0010042); + printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); + + } else { + printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); + } + + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + rs780_htinit(); + printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); + + if (needs_reset) { + print_info("ht reset -\n"); + soft_reset(); + } + + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now; */ + printk(BIOS_DEBUG, "sysinfo->nodes: %2x sysinfo->ctrl: %p spd_addr: %p\n", + sysinfo->nodes, sysinfo->ctrl, spd_addr); + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + + rs780_before_pci_init(); + sb700_before_pci_init(); + + post_cache_as_ram(); +} + Added: trunk/src/mainboard/asrock/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asrock/Kconfig Mon Apr 5 21:47:34 2010 (r5357) @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 Uwe Hermann <uwe(a)hermann-uwe.de> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_ASROCK + +source "src/mainboard/asrock/939a785gmh/Kconfig" + +endchoice +

1 0

[commit] r5356 - in trunk/src: include/device southbridge/amd/rs780
by repository service 05 Apr '10

05 Apr '10

Author: ruik Date: Mon Apr 5 21:21:18 2010 New Revision: 5356 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5356 Log: Add RS785G, looks like it works although it is RV620. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/include/device/pci_ids.h trunk/src/southbridge/amd/rs780/rs780_gfx.c Modified: trunk/src/include/device/pci_ids.h ============================================================================== --- trunk/src/include/device/pci_ids.h Sat Apr 3 17:41:27 2010 (r5355) +++ trunk/src/include/device/pci_ids.h Mon Apr 5 21:21:18 2010 (r5356) @@ -340,6 +340,7 @@ #define PCI_DEVICE_ID_ATI_RS780M_INT_GFX 0x9612 #define PCI_DEVICE_ID_ATI_RS780MC_INT_GFX 0x9613 #define PCI_DEVICE_ID_ATI_RS780E_INT_GFX 0x9615 +#define PCI_DEVICE_ID_ATI_RS785G_INT_GFX 0x9710 #define PCI_VENDOR_ID_VLSI 0x1004 #define PCI_DEVICE_ID_VLSI_82C592 0x0005 Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_gfx.c Sat Apr 3 17:41:27 2010 (r5355) +++ trunk/src/southbridge/amd/rs780/rs780_gfx.c Mon Apr 5 21:21:18 2010 (r5356) @@ -25,6 +25,7 @@ * RS780M: 0x9612 * RS780MC:0x9613 * RS780E: 0x9615 + * RS785G: 0x9710 - just works, not much tested */ #include <console/console.h> #include <device/device.h> @@ -815,6 +816,11 @@ .vendor = PCI_VENDOR_ID_ATI, .device = PCI_DEVICE_ID_ATI_RS780E_INT_GFX, }; +static const struct pci_driver pcie_driver_785g __pci_driver = { + .ops = &pcie_ops, + .vendor = PCI_VENDOR_ID_ATI, + .device = PCI_DEVICE_ID_ATI_RS785G_INT_GFX, +}; /* step 12 ~ step 14 from rpr */ static void single_port_configuration(device_t nb_dev, device_t dev)

1 0

PATCH: Add code to initialize PIIX4 ACPI/PM/SMBus device
by Keith Hui 05 Apr '10

05 Apr '10

The attached patch adds code required for initializing the ACPI/power management/SMBus subdevice of PIIX4. This is required for properly placing the I/O ports for power management functionalities, which in turn will be required for future ACPI work. Speaking of which, I based these ports at 0xe400, after my P2B-LS board. This support is far from complete, but one step at a time. One other change I should propose (but is not in this patch) is that the definition for SMBUS_IO_BASE be moved to i82371eb.h from i82371eb_early_smbus.c. Makes more sense for a definition that may be referenced from some other places. I was thinking to ask if someone know where to set this I/O base address, and turns out no initialization whatsoever was being done. :-O Enjoy. Signed-off-by: Keith Hui <buurin(a)gmail.com>

3 3

Support of the MS-7091 mainboard
by Michael Rodin 05 Apr '10

05 Apr '10

Hello, I would like to now whether my motherboard is (could be) supported by coreboot. As suggested in the FAQ, i send the following informations: Step 1: Motherboard is a MS-7091 (OEM-Board by MEDION) with a P4 processor. ================================================================================== Step 2: "lspci -tvnn" output: -[0000:00]-+-00.0 Intel Corporation 82915G/P/GV/GL/PL/910GL Memory Controller Hub [8086:2580] +-01.0-[0000:01]--+-00.0 ATI Technologies Inc RV410 [Radeon X700 Pro (PCIE)] [1002:5e4b] | \-00.1 ATI Technologies Inc RV410 [Radeon X700 Pro (PCIE)] (Secondary) [1002:5e6b] +-1b.0 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) High Definition Audio Controller [8086:2668] +-1c.0-[0000:02]-- +-1d.0 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #1 [8086:2658] +-1d.1 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #2 [8086:2659] +-1d.2 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #3 [8086:265a] +-1d.3 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB UHCI #4 [8086:265b] +-1d.7 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) USB2 EHCI Controller [8086:265c] +-1e.0-[0000:03]--+-01.0 Philips Semiconductors SAA7134/SAA7135HL Video Broadcast Decoder [1131:7134] | +-03.0 VIA Technologies, Inc. VT6306 Fire II IEEE 1394 OHCI Link Layer Controller [1106:3044] | +-04.0 Philips Semiconductors SAA7134/SAA7135HL Video Broadcast Decoder [1131:7134] | +-05.0 Agere Systems V.92 56K WinModem [11c1:048c] | \-06.0 VIA Technologies, Inc. VT6105/VT6106S [Rhine-III] [1106:3106] +-1f.0 Intel Corporation 82801FB/FR (ICH6/ICH6R) LPC Interface Bridge [8086:2640] +-1f.1 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) IDE Controller [8086:266f] +-1f.2 Intel Corporation 82801FR/FRW (ICH6R/ICH6RW) SATA Controller [8086:2652] \-1f.3 Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6 Family) SMBus Controller [8086:266a] ================================================================================== Step 3: "superiotool -dV" output: superiotool r3844 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xc4f8, id=0xa170 Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0x70a1, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0x70/0x0f, rev=0xa1 Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff No Super I/O found ================================================================================== Step 4: "flashrom -V" output: flashrom v0.9.1-r706 No coreboot table found. Found chipset "Intel ICH6/ICH6R", enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... 775M loops per second, 100 myus = 175 us. OK. Probing for AMD Am29F010A/B, 128 KB: probe_29f040b: id1 0x00, id2 0x18 Probing for AMD Am29F002(N)BB, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for AMD Am29F002(N)BT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d Probing for AMD Am29F080B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d Probing for AMD Am29LV081B, 1024 KB: probe_29f040b: id1 0x49, id2 0x4d Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: probe_jedec: id1 0xda, id2 0x34 Probing for Atmel AT29C010A, 128 KB: probe_jedec: id1 0xda, id2 0x34 Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0xda, id2 0x34 Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0xda, id2 0x34 Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for Atmel AT49F002(N), 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for Atmel AT49F002(N)T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for AMIC A25L40P, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: probe_29f002: id1 0xda, id2 0x34 Probing for AMIC A29002T, 256 KB: probe_29f002: id1 0xda, id2 0x34 Probing for AMIC A29040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d Probing for AMIC A49LF040A, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for EMST F49B002UA, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for Eon EN25B05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for EON EN29F002(A)(N)T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for Fujitsu MBM29F004BC, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for Fujitsu MBM29F004TC, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0x49, id2 0x44 Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x49, id2 0x44 Probing for Intel 28F001BX-B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for Intel 28F001BX-T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x49, id2 0x4d Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0x49, id2 0x4d Probing for Macronix MX25L512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: probe_29f002: id1 0xda, id2 0x34 Probing for Macronix MX29F001T, 128 KB: probe_29f002: id1 0xda, id2 0x34 Probing for Macronix MX29F002B, 256 KB: probe_29f002: id1 0xda, id2 0x34 Probing for Macronix MX29F002T, 256 KB: probe_29f002: id1 0xda, id2 0x34 Probing for Macronix MX29LV040, 512 KB: probe_29f002: id1 0xda, id2 0x34 Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm29F0002T, 256 KB: probe_29f040b: id1 0x99, id2 0x47 Probing for PMC Pm29F0002B, 256 KB: probe_29f040b: id1 0x99, id2 0x47 Probing for PMC Pm39LV010, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for PMC Pm49FL002, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for PMC Pm49FL004, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for Sharp LHF00L04, 1024 KB: probe_lhf00l04: id1 0x49, id2 0x4d Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: probe_28sf040: id1 0x49, id2 0x4d Probing for SST SST29EE010, 128 KB: probe_jedec: id1 0xda, id2 0x34 Probing for SST SST29LE010, 128 KB: probe_jedec: id1 0xda, id2 0x34 Probing for SST SST29EE020A, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for SST SST29LE020, 256 KB: probe_jedec: id1 0xda, id2 0x34 Probing for SST SST39SF010A, 128 KB: probe_jedec: id1 0xda, id2 0x34 Probing for SST SST39SF020A, 256 KB: probe_jedec: id1 0xda, id2 0x34 Probing for SST SST39SF040, 512 KB: probe_jedec: id1 0xda, id2 0x34 Probing for SST SST39VF512, 64 KB: probe_jedec: id1 0xda, id2 0x34 Probing for SST SST39VF010, 128 KB: probe_jedec: id1 0xda, id2 0x34 Probing for SST SST39VF020, 256 KB: probe_jedec: id1 0xda, id2 0x34 Probing for SST SST39VF040, 512 KB: probe_jedec: id1 0xda, id2 0x34 Probing for SST SST39VF080, 1024 KB: probe_jedec: id1 0xda, id2 0x34 Probing for SST SST49LF002A/B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for SST SST49LF003A/B, 384 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for SST SST49LF004A/B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for SST SST49LF004C, 512 KB: probe_49lfxxxc: id1 0x49, id2 0x4d Probing for SST SST49LF008A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for SST SST49LF008C, 1024 KB: probe_49lfxxxc: id1 0x49, id2 0x4d Probing for SST SST49LF016C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for SST SST49LF020, 256 KB: probe_jedec: id1 0xda, id2 0x34 Probing for SST SST49LF020A, 256 KB: probe_jedec: id1 0xda, id2 0x34 Probing for SST SST49LF040, 512 KB: probe_jedec: id1 0xda, id2 0x34 Probing for SST SST49LF040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for SST SST49LF160C, 2048 KB: probe_49lfxxxc: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for ST M29F002T/NT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for ST M29F040B, 512 KB: probe_29f040b: id1 0x49, id2 0x4d Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x49, id2 0x44 Probing for ST M29W010B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for ST M29W040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for ST M50FLW040A, 512 KB: probe_stm50flw0x0x: id1 0xda, id2 0x34 Probing for ST M50FLW040B, 512 KB: probe_stm50flw0x0x: id1 0xda, id2 0x34 Probing for ST M50FLW080A, 1024 KB: probe_stm50flw0x0x: id1 0xda, id2 0x34 Probing for ST M50FLW080B, 1024 KB: probe_stm50flw0x0x: id1 0xda, id2 0x34 Probing for ST M50FW002, 256 KB: probe_49lfxxxc: id1 0x99, id2 0x47 Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x49, id2 0x4d Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0x49, id2 0x4d Probing for ST M50LPW116, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C31004T, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for SyncMOS S29C51001T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for SyncMOS S29C51002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for SyncMOS S29C51004T, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for TI TMS29F002RB, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for TI TMS29F002RT, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for Winbond W25x10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for Winbond W29C020C, 256 KB: probe_jedec: id1 0xda, id2 0x34 Probing for Winbond W29C040P, 512 KB: probe_jedec: id1 0xda, id2 0x34 Probing for Winbond W29EE011, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec: id1 0xda, id2 0x34 Probing for Winbond W39V040B, 512 KB: probe_jedec: id1 0xda, id2 0x34 Probing for Winbond W39V040C, 512 KB: probe_w39v040c: id1 0xda, id2 0x34 Probing for Winbond W39V040FA, 512 KB: probe_jedec: id1 0xda, id2 0x34 Found chip "Winbond W39V040FA" (512 KB, FWH) at physical address 0xfff80000. Probing for Winbond W39V080A, 1024 KB: probe_jedec: id1 0xda, id2 0x34 Probing for Winbond W49F002U, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for Winbond W49V002A, 256 KB: probe_jedec: id1 0xda, id2 0x34 Probing for Winbond W49V002FA, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xda, id2 0x34 Probing for Winbond W39V080FA, 1024 KB: probe_winbond_fwhub: id1 0xda, id2 0x34 Probing for Winbond W39V080FA (dual mode), 512 KB: probe_winbond_fwhub: id1 0xda, id2 0x34 Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. No operations were specified. ================================================================================== Step 5: I could not find the mainboard at the MSI or MEDION homepage :-( Regards, Michael Internet-Tipps für jedermann und jedefrau - jetzt aktuell und kostenfrei auf arcor.de: http://www.arcor.de/rd/footer.inettipps

1 0

Asrock Mainboard Support
by ataya65＠googlemail.com 05 Apr '10

05 Apr '10

As suggested in your homepage i would like to send you the outputs of lspci; lspci -tvnn; superiotool -dV; flashrom -V, further i attached the BIOS-Information, output of dmesg and specificationd i got from the (Hardware lister). The URL to my Mainboard manf. is: http://www.asrock.com/mb/overview.asp?Model=K10N78 *_BIOS:_* vendor: American Megatrends Inc. version: P1.90 (12/30/2009) size: 64KiB capacity: 960KiB capabilities: PCI bus, BIOS EEPROM can be upgraded, BIOS shadowing, Booting from CD-ROM/DVD, Selectable boot path, BIOS ROM is socketed, Enhanced Disk Drive extensions, 5.25" 1.2MB floppy, 3.5" 720KB floppy, 3.5" 2.88MB floppy, Print Screen key, i8042 keyboard controller, INT14 serial line control, INT17 printer control, INT10 CGA/Mono video, ACPI, USB legacy emulation, Booting from LS-120, Booting from ATAPI ZIP, BIOS boot specification, Function-key initiated network service boot *_lspci -tvnn_* -[0000:00]-+-00.0 nVidia Corporation MCP78S [GeForce 8200] Memory Controller [10de:0754] +-01.0 nVidia Corporation MCP78S [GeForce 8200] LPC Bridge [10de:075c] +-01.1 nVidia Corporation MCP78S [GeForce 8200] SMBus [10de:0752] +-01.2 nVidia Corporation MCP78S [GeForce 8200] Memory Controller [10de:0751] +-01.3 nVidia Corporation MCP78S [GeForce 8200] Co-Processor [10de:0753] +-01.4 nVidia Corporation MCP78S [GeForce 8200] Memory Controller [10de:0568] +-02.0 nVidia Corporation MCP78S [GeForce 8200] OHCI USB 1.1 Controller [10de:077b] +-02.1 nVidia Corporation MCP78S [GeForce 8200] EHCI USB 2.0 Controller [10de:077c] +-04.0 nVidia Corporation MCP78S [GeForce 8200] OHCI USB 1.1 Controller [10de:077d] +-04.1 nVidia Corporation MCP78S [GeForce 8200] EHCI USB 2.0 Controller [10de:077e] +-06.0 nVidia Corporation MCP78S [GeForce 8200] IDE [10de:0759] +-07.0 nVidia Corporation MCP72XE/MCP72P/MCP78U/MCP78S High Definition Audio [10de:0774] +-08.0-[01]-- +-09.0 nVidia Corporation MCP78S [GeForce 8200] AHCI Controller [10de:0ad4] +-0a.0 nVidia Corporation MCP77 Ethernet [10de:0760] +-0b.0-[02]----00.0 nVidia Corporation GeForce 8200 [10de:0849] +-10.0-[03]----00.0 nVidia Corporation GeForce 8400 GS [10de:0422] +-12.0-[04]-- +-13.0-[05]-- +-14.0-[06]-- +-18.0 Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] HyperTransport Configuration [1022:1200] +-18.1 Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Address Map [1022:1201] +-18.2 Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] DRAM Controller [1022:1202] +-18.3 Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Miscellaneous Control [1022:1203] \-18.4 Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Link Control [1022:1204] *_lspci_* 00:00.0 RAM memory: nVidia Corporation MCP78S [GeForce 8200] Memory Controller (rev a2) 00:01.0 ISA bridge: nVidia Corporation MCP78S [GeForce 8200] LPC Bridge (rev a2) 00:01.1 SMBus: nVidia Corporation MCP78S [GeForce 8200] SMBus (rev a1) 00:01.2 RAM memory: nVidia Corporation MCP78S [GeForce 8200] Memory Controller (rev a1) 00:01.3 Co-processor: nVidia Corporation MCP78S [GeForce 8200] Co-Processor (rev a2) 00:01.4 RAM memory: nVidia Corporation MCP78S [GeForce 8200] Memory Controller (rev a1) 00:02.0 USB Controller: nVidia Corporation MCP78S [GeForce 8200] OHCI USB 1.1 Controller (rev a1) 00:02.1 USB Controller: nVidia Corporation MCP78S [GeForce 8200] EHCI USB 2.0 Controller (rev a1) 00:04.0 USB Controller: nVidia Corporation MCP78S [GeForce 8200] OHCI USB 1.1 Controller (rev a1) 00:04.1 USB Controller: nVidia Corporation MCP78S [GeForce 8200] EHCI USB 2.0 Controller (rev a1) 00:06.0 IDE interface: nVidia Corporation MCP78S [GeForce 8200] IDE (rev a1) 00:07.0 Audio device: nVidia Corporation MCP72XE/MCP72P/MCP78U/MCP78S High Definition Audio (rev a1) 00:08.0 PCI bridge: nVidia Corporation MCP78S [GeForce 8200] PCI Bridge (rev a1) 00:09.0 SATA controller: nVidia Corporation MCP78S [GeForce 8200] AHCI Controller (rev a2) 00:0a.0 Ethernet controller: nVidia Corporation MCP77 Ethernet (rev a2) 00:0b.0 PCI bridge: nVidia Corporation MCP78S [GeForce 8200] PCI Express Bridge (rev a1) 00:10.0 PCI bridge: nVidia Corporation MCP78S [GeForce 8200] PCI Express Bridge (rev a1) 00:12.0 PCI bridge: nVidia Corporation MCP78S [GeForce 8200] PCI Express Bridge (rev a1) 00:13.0 PCI bridge: nVidia Corporation MCP78S [GeForce 8200] PCI Bridge (rev a1) 00:14.0 PCI bridge: nVidia Corporation MCP78S [GeForce 8200] PCI Bridge (rev a1) 00:18.0 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] HyperTransport Configuration 00:18.1 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Address Map 00:18.2 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] DRAM Controller 00:18.3 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Miscellaneous Control 00:18.4 Host bridge: Advanced Micro Devices [AMD] Family 10h [Opteron, Athlon64, Sempron] Link Control 02:00.0 VGA compatible controller: nVidia Corporation GeForce 8200 (rev a2) 03:00.0 VGA compatible controller: nVidia Corporation GeForce 8400 GS (rev a1) _*superiotool -dV*_ superiotool r4931 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x0400, id=0x6388 Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x8863, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Found Winbond W83627EHF/EF/EHG/EG (id=0x88, rev=0x63) at 0x2e Register dump: idx 20 21 22 23 24 25 26 27 28 29 2a 2b 2c 2d 2e 2f val 88 63 ff 00 04 00 00 ff 70 03 00 00 02 40 00 ff def 88 MM ff 00 MM 00 MM RR 50 04 00 RR 00 21 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val 00 00 00 00 02 0e 00 ff 00 00 def 01 03 f0 06 02 8e 00 ff 00 00 LDN 0x01 (Parallel port) idx 30 60 61 70 74 f0 val 00 03 78 07 04 3f def 01 03 78 07 04 3f LDN 0x02 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 00 def 01 03 f8 04 00 LDN 0x03 (COM2) idx 30 60 61 70 f0 f1 val 00 00 00 00 00 00 def 01 02 f8 03 00 00 LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 72 f0 val 01 00 60 00 64 01 0c 82 def 01 00 60 00 64 01 0c 83 LDN 0x06 (Serial flash interface) idx 30 62 63 val 00 ff ff def 00 00 00 LDN 0x07 (GPIO 1, GPIO 6, game port, MIDI port) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 f7 val 01 02 01 03 30 00 e1 04 00 00 ff ff ff 00 def 00 02 01 03 30 09 ff 00 00 00 ff 00 00 00 LDN 0x08 (WDTO#, PLED) idx 30 f5 f6 f7 val 01 00 00 00 def 00 00 00 00 LDN 0x09 (GPIO 2, GPIO 3, GPIO 4, GPIO 5, SUSLED) idx 30 e0 e1 e2 e3 e4 e5 f0 f1 f2 f3 f4 f5 f6 f7 val 05 ff ff ff ff 09 00 ff ff ff 40 4f cc 00 00 def 00 ff 00 00 ff 00 00 ff 00 00 00 ff 00 00 00 LDN 0x0a (ACPI) idx 30 70 e0 e1 e2 e3 e4 e5 e6 e7 e8 f2 f3 f4 f6 f7 val 00 00 01 00 00 03 00 00 0c 00 09 7c 00 00 00 00 def 00 00 01 00 ff 08 00 RR 00 00 RR 7c 00 00 00 00 LDN 0x0b (Hardware monitor) idx 30 60 61 70 f0 f1 val 01 02 90 00 c1 3f def 00 00 00 00 c1 00 Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff _*flashrom -V*_ flashrom v0.9.1-r931 No coreboot table found. DMI string system-manufacturer: "To Be Filled By O.E.M." DMI string system-product-name: "To Be Filled By O.E.M." DMI string system-version: "To Be Filled By O.E.M." DMI string baseboard-manufacturer: "ASRock" DMI string baseboard-product-name: "K10N78" DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found chipset "NVIDIA MCP78S", enabling flash write... This chipset is not really supported yet. Guesswork... ISA/LPC bridge reg 0x8a contents: 0x40, bit 6 is 1, bit 5 is 0 Guessed flash bus type is SPI Found SMBus device 10de:0752 at 00:01:1 SPI BAR is at 0xf8e80000, after clearing low bits BAR is at 0xf8e80000 Mapping MCP67 SPI at 0xf8e80000, unaligned size 0x544. SPI control is 0xc04a, enable=0, idle=0 Please send the output of "flashrom -V" to flashrom(a)flashrom.org to help us finish support for your chipset. Thanks. SPI on this chipset is not supported yet. OK. This chipset supports the following protocols: None. Calibrating delay loop... 702M loops per second, 100 myus = 199 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for EMST F49B002UA, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Eon EN29F010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Intel 82802AC, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Macronix MX25L512, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for PMC Pm49FL004, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF003A/B, 384 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF004A/B, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF004C, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF008A, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF008C, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF016C, 2048 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for SST SST49LF020, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF020A, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF040, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF040B, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF080A, 1024 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SST SST49LF160C, 2048 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for ST M25P05-A, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW040B, 512 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080A, 1024 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FLW080B, 1024 KB: skipped. Host bus type None and chip bus type LPC,FWH are incompatible. Probing for ST M50FW002, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW016, 2048 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW040, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50FW080, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for ST M50LPW116, 2048 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040B, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040C, 512 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W39V040FA, 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080A, 1024 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W49F002U, 256 KB: skipped. Host bus type None and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: skipped. Host bus type None and chip bus type LPC are incompatible. Probing for Winbond W49V002FA, 256 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080FA, 1024 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Winbond W39V080FA (dual mode), 512 KB: skipped. Host bus type None and chip bus type FWH are incompatible. Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type None and chip bus type SPI are incompatible. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically.

2 1

Do you recommend flashing coreboot on ASUS P5PD2 deluxe?
by Adrian George Sav 04 Apr '10

04 Apr '10

Step 1 Board vendor: ASUS Board name: P5LD2 Deluxe CPU: Intel Pentium D830, 3.0 GHz North Bridge: Intel 945 chipset South bridge: ICH7R Step 2 "lspci -tvnn" -[0000:00]-+-00.0 Intel Corporation 82945G/GZ/P/PL Memory Controller Hub [8086:2770] +-01.0-[04]----00.0 nVidia Corporation G92 [GeForce 9800 GT] [10de:0614] +-1b.0 Intel Corporation N10/ICH 7 Family High Definition Audio Controller [8086:27d8] +-1c.0-[03]-- +-1c.4-[02]----00.0 Marvell Technology Group Ltd. 88E8053 PCI-E Gigabit Ethernet Controller [11ab:4362] +-1d.0 Intel Corporation N10/ICH7 Family USB UHCI Controller #1 [8086:27c8] +-1d.1 Intel Corporation N10/ICH 7 Family USB UHCI Controller #2 [8086:27c9] +-1d.2 Intel Corporation N10/ICH 7 Family USB UHCI Controller #3 [8086:27ca] +-1d.3 Intel Corporation N10/ICH 7 Family USB UHCI Controller #4 [8086:27cb] +-1d.7 Intel Corporation N10/ICH 7 Family USB2 EHCI Controller [8086:27cc] +-1e.0-[01]-- +-1f.0 Intel Corporation 82801GB/GR (ICH7 Family) LPC Interface Bridge [8086:27b8] +-1f.1 Intel Corporation 82801G (ICH7 Family) IDE Controller [8086:27df] +-1f.2 Intel Corporation N10/ICH7 Family SATA IDE Controller [8086:27c0] \-1f.3 Intel Corporation N10/ICH 7 Family SMBus Controller [8086:27da] Step 3 Winbond W83627EHG-A Step 4 flashrom -V flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "System manufacturer" DMI string system-product-name: "System Product Name" DMI string system-version: "System Version" DMI string baseboard-manufacturer: "ASUSTeK Computer INC." DMI string baseboard-product-name: "P5LD2-Deluxe" DMI string baseboard-version: "Rev 1.xx" DMI string chassis-type: "<OUT OF SPEC>" Found chipset "Intel ICH7/ICH7R", enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode disabled 0xffe00000/0xffa00000 FWH decode disabled 0xffd80000/0xff980000 FWH decode disabled 0xffd00000/0xff900000 FWH decode disabled 0xffc80000/0xff880000 FWH decode disabled 0xffc00000/0xff800000 FWH decode disabled 0xff700000/0xff300000 FWH decode disabled 0xff600000/0xff200000 FWH decode disabled 0xff500000/0xff100000 FWH decode disabled 0xff400000/0xff000000 FWH decode disabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 Root Complex Register Block address = 0xfed1c000 GCS = 0x200c64: BIOS Interface Lock-Down: disabled, BOOT BIOS Straps: 0x3 (LPC) Top Swap : not enabled OK. This chipset supports the following protocols: FWH. Calibrating delay loop... 799M loops per second, 100 myus = 200 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for EMST F49B002UA, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN29F010, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x43, id2 0x5d Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Macronix MX25L512, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5a Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5a Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5a Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xbf, id2 0x5a Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5a Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x43, id2 0x5d Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xbf, id2 0x5a Found chip "SST SST49LF008A" (1024 KB, FWH) at physical address 0xfff00000. Lock status for 0x000000 (size 0x010000) is 00, full access Lock status for 0x010000 (size 0x010000) is 00, full access Lock status for 0x020000 (size 0x010000) is 00, full access Lock status for 0x030000 (size 0x010000) is 00, full access Lock status for 0x040000 (size 0x010000) is 00, full access Lock status for 0x050000 (size 0x010000) is 00, full access Lock status for 0x060000 (size 0x010000) is 00, full access Lock status for 0x070000 (size 0x010000) is 00, full access Lock status for 0x080000 (size 0x010000) is 00, full access Lock status for 0x090000 (size 0x010000) is 00, full access Lock status for 0x0a0000 (size 0x010000) is 00, full access Lock status for 0x0b0000 (size 0x010000) is 00, full access Lock status for 0x0c0000 (size 0x010000) is 00, full access Lock status for 0x0d0000 (size 0x010000) is 00, full access Lock status for 0x0e0000 (size 0x010000) is 00, full access Lock status for 0x0f0000 (size 0x010000) is 00, full access Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for SST SST49LF016C, 2048 KB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff Probing for SST SST49LF020, 256 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for SST SST49LF020A, 256 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for SST SST49LF040, 512 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for SST SST49LF040B, 512 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for SST SST49LF080A, 1024 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for SST SST49LF160C, 2048 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for ST M25P05-A, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x43, id2 0x5d Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x43, id2 0x5d Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0x24, id2 0xfc Probing for ST M50FW016, 2048 KB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x43, id2 0x5d Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50LPW116, 2048 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for Winbond W39V040B, 512 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for Winbond W39V040C, 512 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xbf, id2 0x5a Probing for Winbond W39V080A, 1024 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for Winbond W49F002U, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xbf, id2 0x5a Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0x5a Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xbf, id2 0x5a Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. === This flash part has status UNTESTED for operations: ERASE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === No operations were specified. Step 5 http://www.asus.com/Product.aspx?P_ID=qFHXXacaSsviIIxI

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coreboot April 2010