coreboot April 2010

coreboot@coreboot.org

64 participants
402 discussions

[commit] r5382 - in trunk/src: cpu/amd/model_10xxx cpu/amd/model_fxx include/cpu/amd northbridge/amd/amdfam10 northbridge/amd/amdmct/mct
by repository service 08 Apr '10

08 Apr '10

Author: myles Date: Thu Apr 8 17:12:18 2010 New Revision: 5382 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5382 Log: Cosmetically make init_cpus more similar for fam10 and K8. Remove some fam10 warnings. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c trunk/src/cpu/amd/model_fxx/init_cpus.c trunk/src/include/cpu/amd/model_10xxx_msr.h trunk/src/include/cpu/amd/model_fxx_rev.h trunk/src/northbridge/amd/amdfam10/northbridge.c trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c trunk/src/northbridge/amd/amdmct/mct/mct_d.h trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c trunk/src/northbridge/amd/amdmct/mct/mctsrc.c Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Thu Apr 8 17:09:53 2010 (r5381) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Thu Apr 8 17:12:18 2010 (r5382) @@ -26,33 +26,10 @@ #ifndef SET_FIDVID_CORE0_ONLY /* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, - Need to do every AP to set common FID/VID*/ + Need to do every AP to set common FID/VID */ #define SET_FIDVID_CORE0_ONLY 0 #endif -static void print_initcpu8 (const char *strval, u8 val) -{ - printk(BIOS_DEBUG, "%s%02x\n", strval, val); -} - -static void print_initcpu8_nocr (const char *strval, u8 val) -{ - printk(BIOS_DEBUG, "%s%02x", strval, val); -} - - -static void print_initcpu16 (const char *strval, u16 val) -{ - printk(BIOS_DEBUG, "%s%04x\n", strval, val); -} - - -static void print_initcpu(const char *strval, u32 val) -{ - printk(BIOS_DEBUG, "%s%08x\n", strval, val); -} - - void update_microcode(u32 cpu_deviceid); static void prep_fid_change(void); static void init_fidvid_stage2(u32 apicid, u32 nodeid); @@ -65,14 +42,13 @@ msr_t msr; msr = rdmsr(NB_CFG_MSR); // EnableCf8ExtCfg: We need that to access CONFIG_PCI_IO_CFG_EXT 4K range - msr.hi |= (1<<(46-32)); + msr.hi |= (1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); } #else static void set_EnableCf8ExtCfg(void) { } #endif - /*[39:8] */ #define PCI_MMIO_BASE 0xfe000000 /* because we will use gs to store hi, so need to make sure lo can start @@ -85,34 +61,31 @@ msr = rdmsr(0xc0010058); msr.lo &= ~(0xfff00000 | (0xf << 2)); // 256 bus per segment, MMIO reg will be 4G , enable MMIO Config space - msr.lo |= ((8+CONFIG_PCI_BUS_SEGN_BITS) << 2) | (1 << 0); + msr.lo |= ((8 + CONFIG_PCI_BUS_SEGN_BITS) << 2) | (1 << 0); msr.hi &= ~(0x0000ffff); - msr.hi |= (PCI_MMIO_BASE >> (32-8)); - wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg + msr.hi |= (PCI_MMIO_BASE >> (32 - 8)); + wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg //mtrr for that range? // set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE); set_wrap32dis(); - msr.hi = (PCI_MMIO_BASE >> (32-8)); + msr.hi = (PCI_MMIO_BASE >> (32 - 8)); msr.lo = 0; - wrmsr(0xc0000101, msr); //GS_Base Reg - - + wrmsr(0xc0000101, msr); //GS_Base Reg #endif } - -typedef void (*process_ap_t)(u32 apicid, void *gp); +typedef void (*process_ap_t) (u32 apicid, void *gp); //core_range = 0 : all cores //core range = 1 : core 0 only //core range = 2 : cores other than core0 -static void for_each_ap(u32 bsp_apicid, u32 core_range, - process_ap_t process_ap, void *gp) +static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap, + void *gp) { // here assume the OS don't change our apicid u32 ap_apicid; @@ -122,7 +95,7 @@ u32 disable_siblings; u32 cores_found; u32 nb_cfg_54; - int i,j; + int i, j; u32 ApicIdCoreIdSize; /* get_nodes define in ht_wrapper.c */ @@ -130,8 +103,8 @@ disable_siblings = !CONFIG_LOGICAL_CPUS; -#if CONFIG_LOGICAL_CPUS == 1 - if(read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 mean multi core +#if CONFIG_LOGICAL_CPUS == 1 && CONFIG_HAVE_OPTION_TABLE == 1 + if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 mean multi core disable_siblings = 1; } #endif @@ -141,10 +114,10 @@ nb_cfg_54 = read_nb_cfg_54(); ApicIdCoreIdSize = (cpuid_ecx(0x80000008) >> 12 & 0xf); - if(ApicIdCoreIdSize) { + if (ApicIdCoreIdSize) { siblings = ((1 << ApicIdCoreIdSize) - 1); } else { - siblings = 3; //quad core + siblings = 3; //quad core } for (i = 0; i < nodes; i++) { @@ -158,24 +131,26 @@ jstart = 0; } - if (disable_siblings || (core_range==1)) { + if (disable_siblings || (core_range == 1)) { jend = 0; } else { jend = cores_found; } - for (j = jstart; j <= jend; j++) { - ap_apicid = i * (nb_cfg_54 ? (siblings + 1):1) + j * (nb_cfg_54 ? 1:64); + ap_apicid = + i * (nb_cfg_54 ? (siblings + 1) : 1) + + j * (nb_cfg_54 ? 1 : 64); - #if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0) - #if CONFIG_LIFT_BSP_APIC_ID == 0 - if( (i != 0) || (j != 0)) /* except bsp */ - #endif +#if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0) +#if CONFIG_LIFT_BSP_APIC_ID == 0 + if ((i != 0) || (j != 0)) /* except bsp */ +#endif ap_apicid += CONFIG_APIC_ID_OFFSET; - #endif +#endif - if(ap_apicid == bsp_apicid) continue; + if (ap_apicid == bsp_apicid) + continue; process_ap(ap_apicid, gp); @@ -183,8 +158,7 @@ } } -/* FIXME: Duplicate of what is in lapic.h? */ -static int lapic_remote_read(int apicid, int reg, u32 *pvalue) +static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue) { int timeout; u32 status; @@ -192,8 +166,9 @@ lapic_wait_icr_idle(); lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); lapic_write(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4)); - timeout = 0; +/* Extra busy check compared to lapic.h */ + timeout = 0; do { status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; } while (status == LAPIC_ICR_BUSY && timeout++ < 1000); @@ -212,31 +187,33 @@ return result; } - /* Use the LAPIC timer count register to hold each cores init status */ #define LAPIC_MSG_REG 0x380 - #if SET_FIDVID == 1 static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid); #endif -static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id, const char *str) +static inline __attribute__ ((always_inline)) +void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id, + const char *str) { - printk(BIOS_DEBUG, "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, apicid, id.nodeid, id.coreid); + printk(BIOS_DEBUG, + "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, + apicid, id.nodeid, id.coreid); } - -static unsigned wait_cpu_state(u32 apicid, u32 state) +static u32 wait_cpu_state(u32 apicid, u32 state) { u32 readback = 0; u32 timeout = 1; int loop = 4000000; while (--loop > 0) { - if (lapic_remote_read(apicid, LAPIC_MSG_REG, &readback) != 0) continue; + if (lapic_remote_read(apicid, LAPIC_MSG_REG, &readback) != 0) + continue; if ((readback & 0x3f) == state) { timeout = 0; - break; //target cpu is in stage started + break; //target cpu is in stage started } } if (timeout) { @@ -248,30 +225,26 @@ return timeout; } - -static void wait_ap_started(u32 ap_apicid, void *gp ) +static void wait_ap_started(u32 ap_apicid, void *gp) { u32 timeout; - timeout = wait_cpu_state(ap_apicid, 0x13); // started - if(timeout) { - print_initcpu8_nocr("* AP ", ap_apicid); - print_initcpu(" didn't start timeout:", timeout); - } - else { - print_initcpu8_nocr("AP started: ", ap_apicid); + timeout = wait_cpu_state(ap_apicid, 0x13); // started + printk(BIOS_DEBUG, "* AP %02x", ap_apicid); + if (timeout) { + printk(BIOS_DEBUG, " timed out:%08x\n", timeout); + } else { + printk(BIOS_DEBUG, "started\n"); } } - static void wait_all_other_cores_started(u32 bsp_apicid) { // all aps other than core0 - print_debug("started ap apicid: "); - for_each_ap(bsp_apicid, 2 , wait_ap_started, (void *)0); - print_debug("\n"); + printk(BIOS_DEBUG, "started ap apicid: "); + for_each_ap(bsp_apicid, 2, wait_ap_started, (void *)0); + printk(BIOS_DEBUG, "\n"); } - static void allow_all_aps_stop(u32 bsp_apicid) { /* Called by the BSP to indicate AP can stop */ @@ -292,7 +265,6 @@ pci_write_config32(NODE_HT(node), 0x68, val); } - static void STOP_CAR_AND_CPU(void) { msr_t msr; @@ -302,12 +274,13 @@ msr.lo &= ~(1 << ClLinesToNbDis); wrmsr(BU_CFG2, msr); - disable_cache_as_ram(); // inline + disable_cache_as_ram(); // inline + /* stop all cores except node0/core0 the bsp .... */ stop_this_cpu(); } #if RAMINIT_SYSINFO == 1 -static u32 init_cpus(u32 cpu_init_detectedx ,struct sys_info *sysinfo) +static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) #else static u32 init_cpus(u32 cpu_init_detectedx) #endif @@ -320,7 +293,7 @@ * already set early mtrr in cache_as_ram.inc */ - /* enable access pci conf via mmio*/ + /* enable access pci conf via mmio */ set_pci_mmio_conf_reg(); /* that is from initial apicid, we need nodeid and coreid @@ -328,36 +301,35 @@ id = get_node_core_id_x(); /* NB_CFG MSR is shared between cores, so we need make sure - core0 is done at first --- use wait_all_core0_started */ - if(id.coreid == 0) { - set_apicid_cpuid_lo(); /* only set it on core0 */ - set_EnableCf8ExtCfg(); /* only set it on core0 */ - #if (CONFIG_ENABLE_APIC_EXT_ID == 1) + core0 is done at first --- use wait_all_core0_started */ + if (id.coreid == 0) { + set_apicid_cpuid_lo(); /* only set it on core0 */ + set_EnableCf8ExtCfg(); /* only set it on core0 */ +#if (CONFIG_ENABLE_APIC_EXT_ID == 1) enable_apic_ext_id(id.nodeid); - #endif +#endif } enable_lapic(); - #if (CONFIG_ENABLE_APIC_EXT_ID == 1) && (CONFIG_APIC_ID_OFFSET > 0) u32 initial_apicid = get_initial_apicid(); - #if CONFIG_LIFT_BSP_APIC_ID == 0 - if( initial_apicid != 0 ) // other than bsp - #endif +#if CONFIG_LIFT_BSP_APIC_ID == 0 + if (initial_apicid != 0) // other than bsp +#endif { /* use initial apic id to lift it */ u32 dword = lapic_read(LAPIC_ID); dword &= ~(0xff << 24); - dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff) << 24); + dword |= + (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff) << 24); lapic_write(LAPIC_ID, dword); } - - #if CONFIG_LIFT_BSP_APIC_ID == 1 +#if CONFIG_LIFT_BSP_APIC_ID == 1 bsp_apicid += CONFIG_APIC_ID_OFFSET; - #endif +#endif #endif @@ -365,31 +337,28 @@ apicid = lapicid(); // show our apicid, nodeid, and coreid - if( id.coreid==0 ) { - if (id.nodeid!=0) //all core0 except bsp + if (id.coreid == 0) { + if (id.nodeid != 0) //all core0 except bsp print_apicid_nodeid_coreid(apicid, id, " core0: "); - } - else { //all other cores + } else { //all other cores print_apicid_nodeid_coreid(apicid, id, " corex: "); } - if (cpu_init_detectedx) { - print_apicid_nodeid_coreid(apicid, id, "\n\n\nINIT detected from "); - print_debug("\nIssuing SOFT_RESET...\n"); + print_apicid_nodeid_coreid(apicid, id, + "\n\n\nINIT detected from "); + printk(BIOS_DEBUG, "\nIssuing SOFT_RESET...\n"); soft_reset(); } - if(id.coreid == 0) { - if(!(warm_reset_detect(id.nodeid))) //FIXME: INIT is checked above but check for more resets? - distinguish_cpu_resets(id.nodeid); // Also indicates we are started + if (id.coreid == 0) { + if (!(warm_reset_detect(id.nodeid))) //FIXME: INIT is checked above but check for more resets? + distinguish_cpu_resets(id.nodeid); // Also indicates we are started } - // Mark the core as started. lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x13); - - if(apicid != bsp_apicid) { + if (apicid != bsp_apicid) { /* Setup each AP's cores MSRs. * This happens after HTinit. * The BSP runs this code in it's own path. @@ -397,20 +366,24 @@ update_microcode(cpuid_eax(1)); cpuSetAMDMSR(); - #if SET_FIDVID == 1 - #if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1) +#if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1) // Run on all AP for proper FID/VID setup. - if(id.coreid == 0 ) // only need set fid for core0 - #endif + if (id.coreid == 0) // only need set fid for core0 +#endif { - // check warm(bios) reset to call stage2 otherwise do stage1 + // check warm(bios) reset to call stage2 otherwise do stage1 if (warm_reset_detect(id.nodeid)) { - printk(BIOS_DEBUG, "init_fidvid_stage2 apicid: %02x\n", apicid); + printk(BIOS_DEBUG, + "init_fidvid_stage2 apicid: %02x\n", + apicid); init_fidvid_stage2(apicid, id.nodeid); } else { - printk(BIOS_DEBUG, "init_fidvid_ap(stage1) apicid: %02x\n", apicid); - init_fidvid_ap(bsp_apicid, apicid, id.nodeid, id.coreid); + printk(BIOS_DEBUG, + "init_fidvid_ap(stage1) apicid: %02x\n", + apicid); + init_fidvid_ap(bsp_apicid, apicid, id.nodeid, + id.coreid); } } #endif @@ -424,13 +397,14 @@ set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); STOP_CAR_AND_CPU(); - printk(BIOS_DEBUG, "\nAP %02x should be halted but you are reading this....\n", apicid); + printk(BIOS_DEBUG, + "\nAP %02x should be halted but you are reading this....\n", + apicid); } return bsp_apicid; } - static u32 is_core0_started(u32 nodeid) { u32 htic; @@ -441,21 +415,22 @@ return htic; } - static void wait_all_core0_started(void) { /* When core0 is started, it will distingush_cpu_resets - . So wait for that to finish */ + * So wait for that to finish */ u32 i; u32 nodes = get_nodes(); - printk(BIOS_DEBUG, "Wait all core0s started \n"); - for(i=1;i<nodes;i++) { // skip bsp, because it is running on bsp - while(!is_core0_started(i)) {} - print_initcpu8(" Core0 started on node: ", i); + printk(BIOS_DEBUG, "core0 started: "); + for (i = 1; i < nodes; i++) { // skip bsp, because it is running on bsp + while (!is_core0_started(i)) { + } + printk(BIOS_DEBUG, " %02x", i); } - printk(BIOS_DEBUG, "Wait all core0s started done\n"); + printk(BIOS_DEBUG, "\n"); } + #if CONFIG_MAX_PHYSICAL_CPUS > 1 /** * void start_node(u32 node) @@ -480,14 +455,13 @@ #endif /* Allow APs to make requests (ROM fetch) */ - val=pci_read_config32(NODE_HT(node), 0x6c); + val = pci_read_config32(NODE_HT(node), 0x6c); val &= ~(1 << 1); pci_write_config32(NODE_HT(node), 0x6c, val); printk(BIOS_DEBUG, " done.\n"); } - /** * static void setup_remote_node(u32 node) * @@ -517,7 +491,7 @@ printk(BIOS_DEBUG, "setup_remote_node: %02x", node); /* copy the default resource map from node 0 */ - for(i = 0; i < ARRAY_SIZE(pci_reg); i++) { + for (i = 0; i < ARRAY_SIZE(pci_reg); i++) { u32 value; u16 reg; reg = pci_reg[i]; @@ -527,7 +501,7 @@ } printk(BIOS_DEBUG, " done\n"); } -#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */ +#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */ static void AMD_Errata281(u8 node, u32 revision, u32 platform) { @@ -546,7 +520,8 @@ /* For each node we need to check for a "broken" node */ if (!(revision & (AMD_DR_B0 | AMD_DR_B1))) { for (i = 0; i < nodes; i++) { - if (mctGetLogicalCPUID(i) & (AMD_DR_B0 | AMD_DR_B1)) { + if (mctGetLogicalCPUID(i) & + (AMD_DR_B0 | AMD_DR_B1)) { mixed = 1; break; } @@ -590,7 +565,6 @@ } } - static void AMD_Errata298(void) { /* Workaround for L2 Eviction May Occur during operation to @@ -612,36 +586,35 @@ if (affectedRev) { msr = rdmsr(HWCR); - msr.lo |= 0x08; /* Set TlbCacheDis bit[3] */ + msr.lo |= 0x08; /* Set TlbCacheDis bit[3] */ wrmsr(HWCR, msr); msr = rdmsr(BU_CFG); - msr.lo |= 0x02; /* Set TlbForceMemTypeUc bit[1] */ + msr.lo |= 0x02; /* Set TlbForceMemTypeUc bit[1] */ wrmsr(BU_CFG, msr); msr = rdmsr(OSVW_ID_Length); - msr.lo |= 0x01; /* OS Visible Workaround - MSR */ + msr.lo |= 0x01; /* OS Visible Workaround - MSR */ wrmsr(OSVW_ID_Length, msr); msr = rdmsr(OSVW_Status); - msr.lo |= 0x01; /* OS Visible Workaround - MSR */ + msr.lo |= 0x01; /* OS Visible Workaround - MSR */ wrmsr(OSVW_Status, msr); } if (!affectedRev && (mctGetLogicalCPUID(0xFF) & AMD_DR_B3)) { msr = rdmsr(OSVW_ID_Length); - msr.lo |= 0x01; /* OS Visible Workaround - MSR */ + msr.lo |= 0x01; /* OS Visible Workaround - MSR */ wrmsr(OSVW_ID_Length, msr); } } - -u32 get_platform_type(void) +static u32 get_platform_type(void) { u32 ret = 0; - switch(SYSTEM_TYPE) { + switch (SYSTEM_TYPE) { case 1: ret |= AMD_PTYPE_DSK; break; @@ -663,8 +636,7 @@ return ret; } - -void AMD_SetupPSIVID_d (u32 platform_type, u8 node) +static void AMD_SetupPSIVID_d(u32 platform_type, u8 node) { u32 dword; int i; @@ -672,27 +644,26 @@ if (platform_type & (AMD_PTYPE_MOB | AMD_PTYPE_DSK)) { - /* The following code sets the PSIVID to the lowest support P state - * assuming that the VID for the lowest power state is below - * the VDD voltage regulator threshold. (This also assumes that there - * is a Pstate lower than P0) - */ + /* The following code sets the PSIVID to the lowest support P state + * assuming that the VID for the lowest power state is below + * the VDD voltage regulator threshold. (This also assumes that there + * is a Pstate lower than P0) + */ - for( i = 4; i >= 0; i--) { + for (i = 4; i >= 0; i--) { msr = rdmsr(PS_REG_BASE + i); /* Pstate valid? */ if (msr.hi & PS_EN_MASK) { - dword = pci_read_config32(NODE_PCI(i,3), 0xA0); + dword = pci_read_config32(NODE_PCI(i, 3), 0xA0); dword &= ~0x7F; dword |= (msr.lo >> 9) & 0x7F; - pci_write_config32(NODE_PCI(i,3), 0xA0, dword); + pci_write_config32(NODE_PCI(i, 3), 0xA0, dword); break; } } } } - /** * AMD_CpuFindCapability - Traverse PCI capability list to find host HT links. * HT Phy operations are not valid on links that aren't present, so this @@ -700,29 +671,29 @@ * * Returns the offset of the link register. */ -BOOL AMD_CpuFindCapability (u8 node, u8 cap_count, u8 *offset) +static BOOL AMD_CpuFindCapability(u8 node, u8 cap_count, u8 * offset) { - u32 reg; + u32 reg; u32 val; /* get start of CPU HT Host Capabilities */ val = pci_read_config32(NODE_PCI(node, 0), 0x34); - val &= 0xFF; //reg offset of first link + val &= 0xFF; //reg offset of first link cap_count++; /* Traverse through the capabilities. */ do { - reg = pci_read_config32(NODE_PCI(node, 0), val); + reg = pci_read_config32(NODE_PCI(node, 0), val); /* Is the capability block a HyperTransport capability block? */ - if ((reg & 0xFF) == 0x08) { + if ((reg & 0xFF) == 0x08) { /* Is the HT capability block an HT Host Capability? */ - if ((reg & 0xE0000000) == (1 << 29)) + if ((reg & 0xE0000000) == (1 << 29)) cap_count--; } - if(cap_count) - val = (reg >> 8) & 0xFF; //update reg offset + if (cap_count) + val = (reg >> 8) & 0xFF; //update reg offset } while (cap_count && val); *offset = (u8) val; @@ -734,14 +705,13 @@ return FALSE; } - /** * AMD_checkLinkType - Compare desired link characteristics using a logical * link type mask. * * Returns the link characteristic mask. */ -u32 AMD_checkLinkType (u8 node, u8 link, u8 regoff) +static u32 AMD_checkLinkType(u8 node, u8 link, u8 regoff) { u32 val; u32 linktype = 0; @@ -765,11 +735,10 @@ else linktype |= HTPHY_LINKTYPE_HT1; - /* Check ganged */ val = pci_read_config32(NODE_PCI(node, 0), (link << 2) + 0x170); - if ( val & 1) + if (val & 1) linktype |= HTPHY_LINKTYPE_GANGED; else linktype |= HTPHY_LINKTYPE_UNGANGED; @@ -777,12 +746,11 @@ return linktype; } - /** * AMD_SetHtPhyRegister - Use the HT link's HT Phy portal registers to update * a phy setting for that link. */ -void AMD_SetHtPhyRegister (u8 node, u8 link, u8 entry) +static void AMD_SetHtPhyRegister(u8 node, u8 link, u8 entry) { u32 phyReg; u32 phyBase; @@ -792,8 +760,7 @@ if (link > 3) link -= 4; - phyBase = ((u32)link << 3) | 0x180; - + phyBase = ((u32) link << 3) | 0x180; /* Get the portal control register's initial value * and update it to access the desired phy register @@ -834,7 +801,6 @@ } while (!(val & HTPHY_IS_COMPLETE_MASK)); } - void cpuSetAMDMSR(void) { /* This routine loads the CPU with default settings in fam10_msr_default @@ -852,7 +818,7 @@ revision = mctGetLogicalCPUID(0xFF); platform = get_platform_type(); - for(i = 0; i < ARRAY_SIZE(fam10_msr_default); i++) { + for (i = 0; i < ARRAY_SIZE(fam10_msr_default); i++) { if ((fam10_msr_default[i].revision & revision) && (fam10_msr_default[i].platform & platform)) { msr = rdmsr(fam10_msr_default[i].msr); @@ -868,8 +834,7 @@ printk(BIOS_DEBUG, " done\n"); } - -void cpuSetAMDPCI(u8 node) +static void cpuSetAMDPCI(u8 node) { /* This routine loads the CPU with default settings in fam10_pci_default * table . It must be run after Cache-As-RAM has been enabled, and @@ -883,39 +848,41 @@ printk(BIOS_DEBUG, "cpuSetAMDPCI %02d", node); - revision = mctGetLogicalCPUID(node); platform = get_platform_type(); AMD_SetupPSIVID_d(platform, node); /* Set PSIVID offset which is not table driven */ - for(i = 0; i < ARRAY_SIZE(fam10_pci_default); i++) { + for (i = 0; i < ARRAY_SIZE(fam10_pci_default); i++) { if ((fam10_pci_default[i].revision & revision) && (fam10_pci_default[i].platform & platform)) { val = pci_read_config32(NODE_PCI(node, - fam10_pci_default[i].function), - fam10_pci_default[i].offset); + fam10_pci_default[i]. + function), + fam10_pci_default[i].offset); val &= ~fam10_pci_default[i].mask; val |= fam10_pci_default[i].data; pci_write_config32(NODE_PCI(node, - fam10_pci_default[i].function), - fam10_pci_default[i].offset, val); + fam10_pci_default[i]. + function), + fam10_pci_default[i].offset, val); } } - for(i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) { + for (i = 0; i < ARRAY_SIZE(fam10_htphy_default); i++) { if ((fam10_htphy_default[i].revision & revision) && (fam10_htphy_default[i].platform & platform)) { /* HT Phy settings either apply to both sublinks or have * separate registers for sublink zero and one, so there * will be two table entries. So, here we only loop - cd t * through the sublink zeros in function zero. + cd t * through the sublink zeros in function zero. */ for (j = 0; j < 4; j++) { if (AMD_CpuFindCapability(node, j, &offset)) { if (AMD_checkLinkType(node, j, offset) & fam10_htphy_default[i].linktype) { - AMD_SetHtPhyRegister(node, j, i); + AMD_SetHtPhyRegister(node, j, + i); } } else { /* No more capabilities, @@ -932,14 +899,13 @@ AMD_Errata281(node, revision, platform); /* FIXME: if the dct phy doesn't init correct it needs to reset. - if (revision & (AMD_DR_B2 | AMD_DR_B3)) - dctPhyDiag(); */ + if (revision & (AMD_DR_B2 | AMD_DR_B3)) + dctPhyDiag(); */ printk(BIOS_DEBUG, " done\n"); } - -void cpuInitializeMCA(void) +static void cpuInitializeMCA(void) { /* Clears Machine Check Architecture (MCA) registers, which power on * containing unknown data, on currently running processor. @@ -951,30 +917,29 @@ u32 reg; u8 i; - if (cpuid_edx(1) & 0x4080) { /* MCE and MCA (edx[7] and edx[14]) */ + if (cpuid_edx(1) & 0x4080) { /* MCE and MCA (edx[7] and edx[14]) */ msr = rdmsr(MCG_CAP); - if (msr.lo & MCG_CTL_P){ /* MCG_CTL_P bit is set? */ + if (msr.lo & MCG_CTL_P) { /* MCG_CTL_P bit is set? */ msr.lo &= 0xFF; msr.lo--; - msr.lo <<= 2; /* multiply the count by 4 */ + msr.lo <<= 2; /* multiply the count by 4 */ reg = MC0_STA + msr.lo; msr.lo = msr.hi = 0; - for (i=0; i < 4; i++) { - wrmsr (reg, msr); - reg -=4; /* Touch status regs for each bank */ + for (i = 0; i < 4; i++) { + wrmsr(reg, msr); + reg -= 4; /* Touch status regs for each bank */ } } } } - /** * finalize_node_setup() * * Do any additional post HT init * */ -void finalize_node_setup(struct sys_info *sysinfo) +static void finalize_node_setup(struct sys_info *sysinfo) { u8 i; u8 nodes = get_nodes(); @@ -983,13 +948,12 @@ #if RAMINIT_SYSINFO == 1 /* read Node0 F0_0x64 bit [8:10] to find out SbLink # */ reg = pci_read_config32(NODE_HT(0), 0x64); - sysinfo->sblk = (reg>>8) & 7; + sysinfo->sblk = (reg >> 8) & 7; sysinfo->sbbusn = 0; sysinfo->nodes = nodes; sysinfo->sbdn = get_sbdn(sysinfo->sbbusn); #endif - for (i = 0; i < nodes; i++) { cpuSetAMDPCI(i); } @@ -1001,10 +965,9 @@ #if CONFIG_MAX_PHYSICAL_CPUS > 1 /* Skip the BSP, start at node 1 */ - for(i=1; i<nodes; i++) { + for (i = 1; i < nodes; i++) { setup_remote_node(i); start_node(i); } #endif } - Modified: trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c Thu Apr 8 17:09:53 2010 (r5381) +++ trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c Thu Apr 8 17:12:18 2010 (r5382) @@ -38,13 +38,9 @@ #include <cpu/amd/model_10xxx_msr.h> extern device_t get_node_pci(u32 nodeid, u32 fn); -extern int init_processor_name(void); - - #define MCI_STATUS 0x401 - msr_t rdmsr_amd(u32 index) { msr_t result; @@ -67,7 +63,7 @@ } -void model_10xxx_init(device_t dev) +static void model_10xxx_init(device_t dev) { u8 i; msr_t msr; Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/init_cpus.c Thu Apr 8 17:09:53 2010 (r5381) +++ trunk/src/cpu/amd/model_fxx/init_cpus.c Thu Apr 8 17:12:18 2010 (r5382) @@ -1,357 +1,344 @@ //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID #ifndef SET_FIDVID - #if CONFIG_K8_REV_F_SUPPORT == 0 - #define SET_FIDVID 0 - #else +#if CONFIG_K8_REV_F_SUPPORT == 0 + #define SET_FIDVID 0 +#else // for rev F, need to set FID to max - #define SET_FIDVID 1 - #endif - + #define SET_FIDVID 1 #endif -#ifndef SET_FIDVID_CORE0_ONLY - /* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, so may don't need to do twice*/ - #define SET_FIDVID_CORE0_ONLY 1 #endif -static inline void print_initcpu8 (const char *strval, unsigned val) -{ - printk(BIOS_DEBUG, "%s%02x\n", strval, val); -} - -static inline void print_initcpu8_nocr (const char *strval, unsigned val) -{ - printk(BIOS_DEBUG, "%s%02x", strval, val); -} - - -static inline void print_initcpu16 (const char *strval, unsigned val) -{ - printk(BIOS_DEBUG, "%s%04x\n", strval, val); -} - -static inline void print_initcpu(const char *strval, unsigned val) -{ - printk(BIOS_DEBUG, "%s%08x\n", strval, val); -} +#ifndef SET_FIDVID_CORE0_ONLY + /* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, so may don't need to do twice */ + #define SET_FIDVID_CORE0_ONLY 1 +#endif -typedef void (*process_ap_t)(unsigned apicid, void *gp); +typedef void (*process_ap_t) (u32 apicid, void *gp); //core_range = 0 : all cores //core range = 1 : core 0 only //core range = 2 : cores other than core0 -static void for_each_ap(unsigned bsp_apicid, unsigned core_range, process_ap_t process_ap, void *gp) + +static void for_each_ap(u32 bsp_apicid, u32 core_range, process_ap_t process_ap, + void *gp) { // here assume the OS don't change our apicid - unsigned ap_apicid; + u32 ap_apicid; - unsigned nodes; - unsigned siblings = 0; - unsigned disable_siblings; - unsigned e0_later_single_core; - unsigned nb_cfg_54; - int i,j; + u32 nodes; + u32 siblings = 0; + u32 disable_siblings; + u32 e0_later_single_core; + u32 nb_cfg_54; + int i, j; /* get_nodes define in in_coherent_ht.c */ nodes = get_nodes(); - disable_siblings = !CONFIG_LOGICAL_CPUS; + disable_siblings = !CONFIG_LOGICAL_CPUS; + #if CONFIG_LOGICAL_CPUS == 1 && CONFIG_HAVE_OPTION_TABLE == 1 - if(read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 mean multi core - disable_siblings = 1; - } + if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 mean multi core + disable_siblings = 1; + } #endif /* here I assume that all node are same stepping, otherwise we can use use nb_cfg_54 from bsp for all nodes */ - nb_cfg_54 = read_nb_cfg_54(); + nb_cfg_54 = read_nb_cfg_54(); - - for(i=0; i<nodes;i++) { + for (i = 0; i < nodes; i++) { e0_later_single_core = 0; - j = ((pci_read_config32(PCI_DEV(0, 0x18+i, 3), 0xe8) >> 12) & 3); - if(nb_cfg_54) { - if(j == 0 ){ // if it is single core, we need to increase siblings for apic calculation - #if CONFIG_K8_REV_F_SUPPORT == 0 - e0_later_single_core = is_e0_later_in_bsp(i); // single core - #else - e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 - #endif - } - if(e0_later_single_core) { - j=1; - } - } - siblings = j; - - unsigned jstart, jend; - - if(core_range == 2) { - jstart = 1; - } - else { + j = ((pci_read_config32(PCI_DEV(0, 0x18 + i, 3), 0xe8) >> 12) & + 3); + if (nb_cfg_54) { + if (j == 0) { // if it is single core, we need to increase siblings for apic calculation +#if CONFIG_K8_REV_F_SUPPORT == 0 + e0_later_single_core = is_e0_later_in_bsp(i); // single core +#else + e0_later_single_core = is_cpu_f0_in_bsp(i); // We can read cpuid(1) from Func3 +#endif + } + if (e0_later_single_core) { + j = 1; + } + } + siblings = j; + + u32 jstart, jend; + + if (core_range == 2) { + jstart = 1; + } else { jstart = 0; } - if(e0_later_single_core || disable_siblings || (core_range==1)) { - jend = 0; - } else { - jend = siblings; - } - - - for(j=jstart; j<=jend; j++) { - - ap_apicid = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8); - - #if (CONFIG_ENABLE_APIC_EXT_ID == 1) - #if CONFIG_LIFT_BSP_APIC_ID == 0 - if( (i!=0) || (j!=0)) /* except bsp */ - #endif - ap_apicid += CONFIG_APIC_ID_OFFSET; - #endif - - if(ap_apicid == bsp_apicid) continue; - - process_ap(ap_apicid, gp); - - } - } -} + if (e0_later_single_core || disable_siblings + || (core_range == 1)) { + jend = 0; + } else { + jend = siblings; + } + + for (j = jstart; j <= jend; j++) { + ap_apicid = + i * (nb_cfg_54 ? (siblings + 1) : 1) + + j * (nb_cfg_54 ? 1 : 8); + +#if (CONFIG_ENABLE_APIC_EXT_ID == 1) +#if CONFIG_LIFT_BSP_APIC_ID == 0 + if ((i != 0) || (j != 0)) /* except bsp */ +#endif + ap_apicid += CONFIG_APIC_ID_OFFSET; +#endif + + if (ap_apicid == bsp_apicid) + continue; + process_ap(ap_apicid, gp); -static inline int lapic_remote_read(int apicid, int reg, unsigned *pvalue) -{ - int timeout; - unsigned status; - int result; - lapic_wait_icr_idle(); - lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); - lapic_write(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4)); - timeout = 0; - - do { - status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; - } while (status == LAPIC_ICR_BUSY && timeout++ < 1000); - - timeout = 0; - do { - status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK; - } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000); - - result = -1; - if (status == LAPIC_ICR_RR_VALID) { - *pvalue = lapic_read(LAPIC_RRR); - result = 0; - } - return result; + } + } } -#define LAPIC_MSG_REG 0x380 +static inline int lapic_remote_read(int apicid, int reg, u32 *pvalue) +{ + int timeout; + u32 status; + int result; + lapic_wait_icr_idle(); + lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid)); + lapic_write(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4)); + +/* Extra busy check compared to lapic.h */ + timeout = 0; + do { + status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY; + } while (status == LAPIC_ICR_BUSY && timeout++ < 1000); + + timeout = 0; + do { + status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK; + } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000); + + result = -1; + + if (status == LAPIC_ICR_RR_VALID) { + *pvalue = lapic_read(LAPIC_RRR); + result = 0; + } + return result; +} +#define LAPIC_MSG_REG 0x380 #if SET_FIDVID == 1 -static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid); +static void init_fidvid_ap(u32 bsp_apicid, u32 apicid); #endif -static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id, const char *str) +static inline __attribute__ ((always_inline)) +void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id, + const char *str) { - printk(BIOS_DEBUG, "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, apicid, id.nodeid, id.coreid); + printk(BIOS_DEBUG, + "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, + apicid, id.nodeid, id.coreid); } - -static unsigned wait_cpu_state(unsigned apicid, unsigned state) +static u32 wait_cpu_state(u32 apicid, u32 state) { - unsigned readback = 0; - unsigned timeout = 1; + u32 readback = 0; + u32 timeout = 1; int loop = 2000000; - while(--loop>0) { - if(lapic_remote_read(apicid, LAPIC_MSG_REG, &readback)!=0) continue; - if((readback & 0xff) == state) { + while (--loop > 0) { + if (lapic_remote_read(apicid, LAPIC_MSG_REG, &readback) != 0) + continue; + if ((readback & 0xff) == state) { timeout = 0; - break; //target cpu is in stage started + break; //target cpu is in stage started } - } - if(timeout) { - if(readback) { + } + if (timeout) { + if (readback) { timeout = readback; } } return timeout; } -static void wait_ap_started(unsigned ap_apicid, void *gp ) + +static void wait_ap_started(u32 ap_apicid, void *gp) { - unsigned timeout; - timeout = wait_cpu_state(ap_apicid, 0x33); // started - if(timeout) { - print_initcpu8_nocr("*", ap_apicid); - print_initcpu("*", timeout); - } - else { - print_initcpu8_nocr(" ", ap_apicid); + u32 timeout; + timeout = wait_cpu_state(ap_apicid, 0x33); // started + printk(BIOS_DEBUG, "* AP %02x", ap_apicid); + if (timeout) { + printk(BIOS_DEBUG, " timed out:%08x\n", timeout); + } else { + printk(BIOS_DEBUG, "started\n"); } } -static void wait_all_aps_started(unsigned bsp_apicid) +static void wait_all_aps_started(u32 bsp_apicid) { - for_each_ap(bsp_apicid, 0 , wait_ap_started, (void *)0); + for_each_ap(bsp_apicid, 0, wait_ap_started, (void *)0); } -static void wait_all_other_cores_started(unsigned bsp_apicid) // all aps other than core0 +static void wait_all_other_cores_started(u32 bsp_apicid) { - print_debug("started ap apicid: "); - for_each_ap(bsp_apicid, 2 , wait_ap_started, (void *)0); - print_debug("\n"); + // all aps other than core0 + printk(BIOS_DEBUG, "started ap apicid: "); + for_each_ap(bsp_apicid, 2, wait_ap_started, (void *)0); + printk(BIOS_DEBUG, "\n"); } -static void allow_all_aps_stop(unsigned bsp_apicid) +static void allow_all_aps_stop(u32 bsp_apicid) { - lapic_write(LAPIC_MSG_REG, (bsp_apicid<<24) | 0x44); // allow aps to stop + // allow aps to stop + + lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 0x44); } static void STOP_CAR_AND_CPU(void) { - disable_cache_as_ram(); // inline - stop_this_cpu(); // inline, it will stop all cores except node0/core0 the bsp .... + disable_cache_as_ram(); // inline + /* stop all cores except node0/core0 the bsp .... */ + stop_this_cpu(); } -#if CONFIG_MEM_TRAIN_SEQ == 1 -static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall); -#endif - #if RAMINIT_SYSINFO == 1 -static unsigned init_cpus(unsigned cpu_init_detectedx ,struct sys_info *sysinfo) +static u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo) #else -static unsigned init_cpus(unsigned cpu_init_detectedx) +static u32 init_cpus(u32 cpu_init_detectedx) #endif { - unsigned bsp_apicid = 0; - unsigned apicid; - struct node_core_id id; - - /* - * already set early mtrr in cache_as_ram.inc - */ - - /* that is from initial apicid, we need nodeid and coreid later */ - id = get_node_core_id_x(); - - - /* NB_CFG MSR is shared between cores, so we need make sure core0 is done at first --- use wait_all_core0_started */ - if(id.coreid == 0) { - set_apicid_cpuid_lo(); /* only set it on core0 */ - #if CONFIG_ENABLE_APIC_EXT_ID == 1 - enable_apic_ext_id(id.nodeid); - #endif - } - - enable_lapic(); -// init_timer(); // We need TMICT to pass msg for FID/VID change - - #if (CONFIG_ENABLE_APIC_EXT_ID == 1) - unsigned initial_apicid = get_initial_apicid(); - #if CONFIG_LIFT_BSP_APIC_ID == 0 - if( initial_apicid != 0 ) // other than bsp - #endif - { - /* use initial apic id to lift it */ - uint32_t dword = lapic_read(LAPIC_ID); - dword &= ~(0xff<<24); - dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff)<<24); - - lapic_write(LAPIC_ID, dword); - } - - #if CONFIG_LIFT_BSP_APIC_ID == 1 - bsp_apicid += CONFIG_APIC_ID_OFFSET; - #endif - - #endif - - /* get the apicid, it may be lifted already */ - apicid = lapicid(); - -#if 0 - // show our apicid, nodeid, and coreid - if( id.coreid==0 ) { - if (id.nodeid!=0) //all core0 except bsp - print_apicid_nodeid_coreid(apicid, id, " core0: "); - } - #if 0 - else { //all core1 - print_apicid_nodeid_coreid(apicid, id, " core1: "); - } - #endif + u32 bsp_apicid = 0; + u32 apicid; + struct node_core_id id; + + /* + * already set early mtrr in cache_as_ram.inc + */ + + /* that is from initial apicid, we need nodeid and coreid + later */ + id = get_node_core_id_x(); + + /* NB_CFG MSR is shared between cores, so we need make sure + core0 is done at first --- use wait_all_core0_started */ + if (id.coreid == 0) { + set_apicid_cpuid_lo(); /* only set it on core0 */ +#if (CONFIG_ENABLE_APIC_EXT_ID == 1) + enable_apic_ext_id(id.nodeid); +#endif + } + + enable_lapic(); + // init_timer(); // We need TMICT to pass msg for FID/VID change +#if (CONFIG_ENABLE_APIC_EXT_ID == 1) + u32 initial_apicid = get_initial_apicid(); + +#if CONFIG_LIFT_BSP_APIC_ID == 0 + if (initial_apicid != 0) // other than bsp #endif + { + /* use initial apic id to lift it */ + u32 dword = lapic_read(LAPIC_ID); + dword &= ~(0xff << 24); + dword |= + (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff) << 24); - if (cpu_init_detectedx) { - print_apicid_nodeid_coreid(apicid, id, "\n\n\nINIT detected from "); - print_debug("\nIssuing SOFT_RESET...\n"); - soft_reset(); - } - - if(id.coreid==0) { - distinguish_cpu_resets(id.nodeid); - // start_other_core(id.nodeid); // start second core in first cpu, only allowed for nb_cfg_54 is not set - } + lapic_write(LAPIC_ID, dword); + } +#if CONFIG_LIFT_BSP_APIC_ID == 1 + bsp_apicid += CONFIG_APIC_ID_OFFSET; +#endif - //here don't need to wait - lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x33); // mark the cpu is started +#endif - if(apicid != bsp_apicid) { - unsigned timeout=1; - unsigned loop = 100; - #if SET_FIDVID == 1 - #if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1) - if(id.coreid == 0 ) // only need set fid for core0 - #endif - init_fidvid_ap(bsp_apicid, apicid); - #endif - - // We need to stop the CACHE as RAM for this CPU, really? - while(timeout && (loop-->0)) { - timeout = wait_cpu_state(bsp_apicid, 0x44); - } - if(timeout) { - print_initcpu8("while waiting for BSP signal to STOP, timeout in ap ", apicid); - } - lapic_write(LAPIC_MSG_REG, (apicid<<24) | 0x44); // bsp can not check it before stop_this_cpu - set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); - #if CONFIG_MEM_TRAIN_SEQ == 1 - train_ram_on_node(id.nodeid, id.coreid, sysinfo, - (unsigned) STOP_CAR_AND_CPU); - #endif + /* get the apicid, it may be lifted already */ + apicid = lapicid(); - STOP_CAR_AND_CPU(); - } +#if 0 + // show our apicid, nodeid, and coreid + if (id.coreid == 0) { + if (id.nodeid != 0) //all core0 except bsp + print_apicid_nodeid_coreid(apicid, id, " core0: "); + } else { //all other cores + print_apicid_nodeid_coreid(apicid, id, " corex: "); + } +#endif - return bsp_apicid; -} + if (cpu_init_detectedx) { + print_apicid_nodeid_coreid(apicid, id, + "\n\n\nINIT detected from "); + printk(BIOS_DEBUG, "\nIssuing SOFT_RESET...\n"); + soft_reset(); + } + + if (id.coreid == 0) { + distinguish_cpu_resets(id.nodeid); +// start_other_core(id.nodeid); // start second core in first cpu, only allowed for nb_cfg_54 is not set + } + //here don't need to wait + lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x33); // mark the cpu is started + + if (apicid != bsp_apicid) { + u32 timeout = 1; + u32 loop = 100; + +#if SET_FIDVID == 1 +#if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1) + if (id.coreid == 0) // only need set fid for core0 +#endif + init_fidvid_ap(bsp_apicid, apicid); +#endif + + // We need to stop the CACHE as RAM for this CPU, really? + while (timeout && (loop-- > 0)) { + timeout = wait_cpu_state(bsp_apicid, 0x44); + } + if (timeout) { + printk(BIOS_DEBUG, + "while waiting for BSP signal to STOP, timeout in ap %02x\n", + apicid); + } + lapic_write(LAPIC_MSG_REG, (apicid << 24) | 0x44); // bsp can not check it before stop_this_cpu + set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); +#if CONFIG_MEM_TRAIN_SEQ == 1 + train_ram_on_node(id.nodeid, id.coreid, sysinfo, + (unsigned)STOP_CAR_AND_CPU); +#endif + + STOP_CAR_AND_CPU(); + } + return bsp_apicid; +} -static unsigned is_core0_started(unsigned nodeid) +static u32 is_core0_started(u32 nodeid) { - uint32_t htic; - device_t device; - device = PCI_DEV(0, 0x18 + nodeid, 0); - htic = pci_read_config32(device, HT_INIT_CONTROL); - htic &= HTIC_INIT_Detect; - return htic; + u32 htic; + device_t device; + device = PCI_DEV(0, 0x18 + nodeid, 0); + htic = pci_read_config32(device, HT_INIT_CONTROL); + htic &= HTIC_INIT_Detect; + return htic; } static void wait_all_core0_started(void) { - //When core0 is started, it will distingush_cpu_resets. So wait for that - unsigned i; - unsigned nodes = get_nodes(); - - print_debug("core0 started: "); - for(i=1;i<nodes;i++) { // skip bsp, because it is running on bsp - while(!is_core0_started(i)) {} - print_initcpu8_nocr(" ", i); - } - print_debug("\n"); - + /* When core0 is started, it will distingush_cpu_resets + * So wait for that to finish */ + u32 i; + u32 nodes = get_nodes(); + + printk(BIOS_DEBUG, "core0 started: "); + for (i = 1; i < nodes; i++) { // skip bsp, because it is running on bsp + while (!is_core0_started(i)) { + } + printk(BIOS_DEBUG, " %02x", i); + } + printk(BIOS_DEBUG, "\n"); } - Modified: trunk/src/include/cpu/amd/model_10xxx_msr.h ============================================================================== --- trunk/src/include/cpu/amd/model_10xxx_msr.h Thu Apr 8 17:09:53 2010 (r5381) +++ trunk/src/include/cpu/amd/model_10xxx_msr.h Thu Apr 8 17:12:18 2010 (r5382) @@ -33,4 +33,7 @@ #define LOGICAL_CPUS_NUM_MSR 0xC001100d #define CPU_ID_EXT_FEATURES_MSR 0xC0011005 +msr_t rdmsr_amd(u32 index); +void wrmsr_amd(u32 index, msr_t msr); + #endif /* CPU_AMD_MODEL_10XXX_MSR_H */ Modified: trunk/src/include/cpu/amd/model_fxx_rev.h ============================================================================== --- trunk/src/include/cpu/amd/model_fxx_rev.h Thu Apr 8 17:09:53 2010 (r5381) +++ trunk/src/include/cpu/amd/model_fxx_rev.h Thu Apr 8 17:12:18 2010 (r5382) @@ -98,7 +98,7 @@ #ifdef __PRE_RAM__ //AMD_F0_SUPPORT -static int is_cpu_f0_in_bsp(int nodeid) +static inline int is_cpu_f0_in_bsp(int nodeid) { uint32_t dword; device_t dev; @@ -106,7 +106,7 @@ dword = pci_read_config32(dev, 0xfc); return (dword & 0xfff00) == 0x40f00; } -static int is_cpu_pre_f2_in_bsp(int nodeid) +static inline int is_cpu_pre_f2_in_bsp(int nodeid) { uint32_t dword; device_t dev; Modified: trunk/src/northbridge/amd/amdfam10/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/northbridge.c Thu Apr 8 17:09:53 2010 (r5381) +++ trunk/src/northbridge/amd/amdfam10/northbridge.c Thu Apr 8 17:12:18 2010 (r5382) @@ -153,7 +153,9 @@ device_t devx; u32 busses; u32 segn = max>>8; +#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 1 u32 busn = max&0xff; +#endif u32 max_devfn; #if CONFIG_HT3_SUPPORT==1 @@ -332,7 +334,7 @@ u32 goal_link) { struct resource *res; - u32 nodeid, link; + u32 nodeid, link = 0; int result; res = 0; for(nodeid = 0; !res && (nodeid < NODE_NUMS); nodeid++) { @@ -646,9 +648,7 @@ static void amdfam10_domain_read_resources(device_t dev) { - struct resource *resource; unsigned reg; - unsigned link; /* Find the already assigned resource pairs */ get_fx_devs(); @@ -658,19 +658,19 @@ limit = f1_read_config32(reg + 0x04); /* Is this register allocated? */ if ((base & 3) != 0) { - unsigned nodeid, link; + unsigned nodeid, reg_link; device_t reg_dev; if(reg<0xc0) { // mmio nodeid = (limit & 0xf) + (base&0x30); } else { // io nodeid = (limit & 0xf) + ((base>>4)&0x30); } - link = (limit >> 4) & 7; + reg_link = (limit >> 4) & 7; reg_dev = __f0_dev[nodeid]; if (reg_dev) { /* Reserve the resource */ struct resource *reg_resource; - reg_resource = new_resource(reg_dev, IOINDEX(0x1000 + reg, link)); + reg_resource = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); if (reg_resource) { reg_resource->flags = 1; } @@ -683,6 +683,8 @@ #if CONFIG_PCI_64BIT_PREF_MEM == 0 pci_domain_read_resources(dev); #else + unsigned link; + struct resource *resource; for(link=0; link<dev->links; link++) { /* Initialize the system wide io space constraints */ resource = new_resource(dev, 0|(link<<2)); @@ -1215,7 +1217,9 @@ { struct bus *cpu_bus; device_t dev_mc; +#if CONFIG_CBB device_t pci_domain; +#endif int i,j; int nodes; unsigned nb_cfg_54; @@ -1309,7 +1313,7 @@ /* Find which cpus are present */ cpu_bus = &dev->link[0]; for(i = 0; i < nodes; i++) { - device_t dev, cpu; + device_t cdb_dev, cpu; struct device_path cpu_path; unsigned busn, devn; struct bus *pbus; @@ -1326,47 +1330,47 @@ #endif /* Find the cpu's pci device */ - dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); - if (!dev) { + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 0)); + if (!cdb_dev) { /* If I am probing things in a weird order * ensure all of the cpu's pci devices are found. */ - int j; - for(j = 0; j <= 5; j++) { //FBDIMM? - dev = pci_probe_dev(NULL, pbus, - PCI_DEVFN(devn, j)); + int fn; + for(fn = 0; fn <= 5; fn++) { //FBDIMM? + cdb_dev = pci_probe_dev(NULL, pbus, + PCI_DEVFN(devn, fn)); } - dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); } - if(dev) { + if(cdb_dev) { /* Ok, We need to set the links for that device. * otherwise the device under it will not be scanned */ - int j; + int link; int linknum; #if CONFIG_HT3_SUPPORT==1 linknum = 8; #else linknum = 4; #endif - if(dev->links < linknum) { - for(j=dev->links; j<linknum; j++) { - dev->link[j].link = j; - dev->link[j].dev = dev; + if(cdb_dev->links < linknum) { + for(link=cdb_dev->links; link<linknum; link++) { + cdb_dev->link[link].link = link; + cdb_dev->link[link].dev = cdb_dev; } - dev->links = linknum; - printk(BIOS_DEBUG, "%s links increase to %d\n", dev_path(dev), dev->links); + cdb_dev->links = linknum; + printk(BIOS_DEBUG, "%s links increase to %d\n", dev_path(cdb_dev), cdb_dev->links); } } cores_found = 0; // one core - dev = dev_find_slot(busn, PCI_DEVFN(devn, 3)); - if (dev && dev->enabled) { - j = pci_read_config32(dev, 0xe8); + cdb_dev = dev_find_slot(busn, PCI_DEVFN(devn, 3)); + if (cdb_dev && cdb_dev->enabled) { + j = pci_read_config32(cdb_dev, 0xe8); cores_found = (j >> 12) & 3; // dev is func 3 if (siblings > 3) cores_found |= (j >> 13) & 4; - printk(BIOS_DEBUG, " %s siblings=%d\n", dev_path(dev), cores_found); + printk(BIOS_DEBUG, " %s siblings=%d\n", dev_path(cdb_dev), cores_found); } u32 jj; @@ -1387,7 +1391,7 @@ cpu = find_dev_path(cpu_bus, &cpu_path); /* Enable the cpu if I have the processor */ - if (dev && dev->enabled) { + if (cdb_dev && cdb_dev->enabled) { if (!cpu) { cpu = alloc_dev(cpu_bus, &cpu_path); } @@ -1397,7 +1401,7 @@ } /* Disable the cpu if I don't have the processor */ - if (cpu && (!dev || !dev->enabled)) { + if (cpu && (!cdb_dev || !cdb_dev->enabled)) { cpu->enabled = 0; } Modified: trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Thu Apr 8 17:09:53 2010 (r5381) +++ trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Thu Apr 8 17:12:18 2010 (r5382) @@ -17,23 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -static void print_raminit(const char *strval, u32 val) -{ - printk(BIOS_DEBUG, "%s%08x\n", strval, val); -} - static void print_tx(const char *strval, u32 val) { #if CONFIG_DEBUG_RAM_SETUP - print_raminit(strval, val); + printk(BIOS_DEBUG, "%s%08x\n", strval, val); #endif } static void print_t(const char *strval) { #if CONFIG_DEBUG_RAM_SETUP - print_debug(strval); + printk(BIOS_DEBUG, "%s", strval); #endif } #include "amdfam10.h" Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct_d.h Thu Apr 8 17:09:53 2010 (r5381) +++ trunk/src/northbridge/amd/amdmct/mct/mct_d.h Thu Apr 8 17:12:18 2010 (r5382) @@ -726,13 +726,16 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void InterleaveChannels_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); -static void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 ChipSel); +void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 ChipSel); void phyAssistedMemFnceTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA); u8 mct_SaveRcvEnDly_D_1Pass(struct DCTStatStruc *pDCTstat, u8 pass); -static void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request); -static u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct); -static void mct_Wait(u32 cycles); +u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct); +u8 mct_AdjustDQSPosDelay_D(struct DCTStatStruc *pDCTstat, u8 dly); +void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request); +u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct); +void mct_Wait(u32 cycles); u8 mct_RcvrRankEnabled_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 Channel, u8 ChipSel); u32 mct_GetRcvrSysAddr_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 channel, u8 receiver, u8 *valid); void mct_Read1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 addr); +void EarlySampleSupport_D(void); #endif Modified: trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c Thu Apr 8 17:09:53 2010 (r5381) +++ trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c Thu Apr 8 17:12:18 2010 (r5382) @@ -582,8 +582,8 @@ } -static void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, - struct DCTStatStruc *pDCTstat, u8 ChipSel) +void StoreDQSDatStrucVal_D(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstat, u8 ChipSel) { /* Store the DQSDelay value, found during a training sweep, into the DCT * status structure for this node Modified: trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c Thu Apr 8 17:09:53 2010 (r5381) +++ trunk/src/northbridge/amd/amdmct/mct/mctpro_d.c Thu Apr 8 17:12:18 2010 (r5382) @@ -17,15 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -static u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct); -static u8 mct_AdjustDQSPosDelay_D(struct DCTStatStruc *pDCTstat, u8 dly); - void EarlySampleSupport_D(void) { } - u32 procOdtWorkaround(struct DCTStatStruc *pDCTstat, u32 dct, u32 val) { u32 tmp; @@ -251,7 +246,7 @@ } -static u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct) +u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct) { u32 ret = 0; u32 lo, hi; @@ -362,7 +357,7 @@ } -static u8 mct_AdjustDQSPosDelay_D(struct DCTStatStruc *pDCTstat, u8 dly) +u8 mct_AdjustDQSPosDelay_D(struct DCTStatStruc *pDCTstat, u8 dly) { u8 skip = 0; @@ -393,8 +388,7 @@ return 0; } - -static void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request) { +void mct_AdjustScrub_D(struct DCTStatStruc *pDCTstat, u16 *scrub_request) { /* Erratum #202: disable DCache scrubber for Ax parts */ @@ -403,4 +397,3 @@ pDCTstat->ErrStatus |= 1 << SB_DCBKScrubDis; } } - Modified: trunk/src/northbridge/amd/amdmct/mct/mctsrc.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctsrc.c Thu Apr 8 17:09:53 2010 (r5381) +++ trunk/src/northbridge/amd/amdmct/mct/mctsrc.c Thu Apr 8 17:12:18 2010 (r5382) @@ -502,7 +502,7 @@ } -static u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct) +u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct) { if (pDCTstat->DIMMValidDCT[dct] == 0 ) { return 8; @@ -1080,7 +1080,7 @@ } -static void mct_Wait(u32 cycles) +void mct_Wait(u32 cycles) { u32 saved; u32 hi, lo, msr;

1 0

[commit] r5381 - in trunk/src: cpu/amd/model_10xxx cpu/amd/model_fxx mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/serengeti_cheeta...
by repository service 08 Apr '10

08 Apr '10

Author: myles Date: Thu Apr 8 17:09:53 2010 New Revision: 5381 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5381 Log: Clean up fidvid files using indent. Remove some special print statements. In general, make them easier to compare. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/model_fxx/fidvid.c trunk/src/cpu/amd/model_fxx/init_cpus.c trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/pistachio/romstage.c trunk/src/mainboard/amd/serengeti_cheetah/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/asrock/939a785gmh/romstage.c trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/asus/m2v-mx_se/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Thu Apr 8 17:09:53 2010 (r5381) @@ -17,41 +17,39 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if FAM10_SET_FIDVID == 1 +#if SET_FIDVID == 1 #include "../../../northbridge/amd/amdht/AsPsDefs.h" -#define FAM10_SET_FIDVID_DEBUG 1 +#define SET_FIDVID_DEBUG 1 // if we are tight of CAR stack, disable it -#define FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST 1 +#define SET_FIDVID_STORE_AP_APICID_AT_FIRST 1 static inline void print_debug_fv(const char *str, u32 val) { -#if FAM10_SET_FIDVID_DEBUG == 1 - printk(BIOS_DEBUG, "%s%x\n", str, val); +#if SET_FIDVID_DEBUG == 1 + printk(BIOS_DEBUG, "%s%x\n", str, val); #endif } static inline void print_debug_fv_8(const char *str, u8 val) { -#if FAM10_SET_FIDVID_DEBUG == 1 - printk(BIOS_DEBUG, "%s%02x\n", str, val); +#if SET_FIDVID_DEBUG == 1 + printk(BIOS_DEBUG, "%s%02x\n", str, val); #endif } static inline void print_debug_fv_64(const char *str, u32 val, u32 val2) { -#if FAM10_SET_FIDVID_DEBUG == 1 - printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); +#if SET_FIDVID_DEBUG == 1 + printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); #endif } - struct fidvid_st { u32 common_fid; }; - static void enable_fid_change(u8 fid) { u32 dword; @@ -61,24 +59,24 @@ nodes = get_nodes(); - for(i = 0; i < nodes; i++) { - dev = NODE_PCI(i,3); + for (i = 0; i < nodes; i++) { + dev = NODE_PCI(i, 3); dword = pci_read_config32(dev, 0xd4); dword &= ~0x1F; dword |= (u32) fid & 0x1F; dword |= 1 << 5; // enable pci_write_config32(dev, 0xd4, dword); - printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i, dword); + printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i, + dword); } } - static void recalculateVsSlamTimeSettingOnCorePre(device_t dev) { u8 pviModeFlag; u8 highVoltageVid, lowVoltageVid, bValue; u16 minimumSlamTime; - u16 vSlamTimes[7]={1000,2000,3000,4000,6000,10000,20000}; /* Reg settings scaled by 100 */ + u16 vSlamTimes[7] = { 1000, 2000, 3000, 4000, 6000, 10000, 20000 }; /* Reg settings scaled by 100 */ u32 dtemp; msr_t msr; @@ -94,12 +92,10 @@ * decimals. */ - - /* Determine if this is a PVI or SVI system */ dtemp = pci_read_config32(dev, 0xA0); - if( dtemp & PVI_MODE ) + if (dtemp & PVI_MODE) pviModeFlag = 1; else pviModeFlag = 0; @@ -113,7 +109,7 @@ */ if (pviModeFlag) { bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F); - if( highVoltageVid > bValue ) + if (highVoltageVid > bValue) highVoltageVid = bValue; } @@ -130,7 +126,7 @@ */ if (pviModeFlag) { bValue = (u8) ((msr.lo >> PS_NB_VID_SHFT) & 0x7F); - if( lowVoltageVid > bValue ) + if (lowVoltageVid > bValue) lowVoltageVid = bValue; } @@ -139,13 +135,13 @@ bValue = (u8) (dtemp & BIT_MASK_7); /* Use the VID with the lowest voltage (higher VID) */ - if( lowVoltageVid < bValue ) + if (lowVoltageVid < bValue) lowVoltageVid = bValue; /* If Vids are 7Dh - 7Fh, force 7Ch to keep calculations linear */ if (lowVoltageVid > 0x7C) { lowVoltageVid = 0x7C; - if(highVoltageVid > 0x7C) + if (highVoltageVid > 0x7C) highVoltageVid = 0x7C; } @@ -161,8 +157,8 @@ * Note that if we don't find a value, we * will fall through to a value of 7 */ - for(bValue=0; bValue < 7; bValue++) { - if(minimumSlamTime <= vSlamTimes[bValue]) + for (bValue = 0; bValue < 7; bValue++) { + if (minimumSlamTime <= vSlamTimes[bValue]) break; } @@ -173,7 +169,6 @@ pci_write_config32(dev, 0xd8, dtemp); } - static void prep_fid_change(void) { u32 dword, dtemp; @@ -185,9 +180,9 @@ nodes = get_nodes(); - for(i = 0; i < nodes; i++) { + for (i = 0; i < nodes; i++) { printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i); - dev = NODE_PCI(i,3); + dev = NODE_PCI(i, 3); dword = pci_read_config32(dev, 0xd8); dword &= VSRAMP_MASK; @@ -214,20 +209,18 @@ */ dword = pci_read_config32(dev, 0xd4); dword &= CPTC0_MASK; - dword |= NB_CLKDID_ALL | NB_CLKDID | PW_STP_UP50 | PW_STP_DN50 | - LNK_PLL_LOCK; /* per BKDG */ + dword |= NB_CLKDID_ALL | NB_CLKDID | PW_STP_UP50 | PW_STP_DN50 | LNK_PLL_LOCK; /* per BKDG */ pci_write_config32(dev, 0xd4, dword); } else { dword = pci_read_config32(dev, 0xd4); dword &= CPTC0_MASK; /* get number of cores for PowerStepUp & PowerStepDown in server - 1 core - 400nS - 0000b - 2 cores - 200nS - 0010b - 3 cores - 133nS -> 100nS - 0011b - 4 cores - 100nS - 0011b - */ - switch(get_core_num_in_bsp(i)) - { + 1 core - 400nS - 0000b + 2 cores - 200nS - 0010b + 3 cores - 133nS -> 100nS - 0011b + 4 cores - 100nS - 0011b + */ + switch (get_core_num_in_bsp(i)) { case 0: dword |= PW_STP_UP400 | PW_STP_DN400; break; @@ -248,12 +241,12 @@ /* check PVI/SVI */ dword = pci_read_config32(dev, 0xA0); - if(dword & PVI_MODE) { /* PVI */ + if (dword & PVI_MODE) { /* PVI */ /* set slamVidMode to 0 for PVI */ dword &= VID_SLAM_OFF | PLLLOCK_OFF; dword |= PLLLOCK_DFT_L; pci_write_config32(dev, 0xA0, dword); - } else { /* SVI */ + } else { /* SVI */ /* set slamVidMode to 1 for SVI */ dword &= PLLLOCK_OFF; dword |= PLLLOCK_DFT_L | VID_SLAM_ON; @@ -264,7 +257,7 @@ /* Program F3xD8[PwrPlanes] according F3xA0[DulaVdd] */ dword = pci_read_config32(dev, 0xD8); - if( dtemp & DUAL_VDD_BIT) + if (dtemp & DUAL_VDD_BIT) dword |= PWR_PLN_ON; else dword &= PWR_PLN_OFF; @@ -275,7 +268,7 @@ * function setFidVidRegs() */ dword = pci_read_config32(dev, 0xDc); - dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */ + dword |= 0x5 << 12; /* NbsynPtrAdj set to 0x5 per BKDG (needs reset) */ pci_write_config32(dev, 0xdc, dword); /* Rev B settings - FIXME: support other revs. */ @@ -313,20 +306,18 @@ nbVid = (msr.lo & PS_CPU_VID_M_ON) >> PS_CPU_VID_SHFT; cpuVid = (msr.lo & PS_NB_VID_M_ON) >> PS_NB_VID_SHFT; - if( nbVid != cpuVid ) { - if(nbVid > cpuVid) + if (nbVid != cpuVid) { + if (nbVid > cpuVid) nbVid = cpuVid; msr.lo = msr.lo & PS_BOTH_VID_OFF; - msr.lo = msr.lo | (u32)((nbVid) << PS_NB_VID_SHFT); - msr.lo = msr.lo | (u32)((nbVid) << PS_CPU_VID_SHFT); + msr.lo = msr.lo | (u32) ((nbVid) << PS_NB_VID_SHFT); + msr.lo = msr.lo | (u32) ((nbVid) << PS_CPU_VID_SHFT); wrmsr(PS_REG_BASE + i, msr); } } } - - static void fixPsNbVidBeforeWR(u32 newNbVid, u32 coreid) { msr_t msr; @@ -343,7 +334,7 @@ */ msr = rdmsr(0xc0010071); - startup_pstate = (msr.hi >> (32-32)) & 0x07; + startup_pstate = (msr.hi >> (32 - 32)) & 0x07; /* Copy startup pstate to P1 and P0 MSRs. Set the maxvid for this node in P0. * Then transition to P1 for corex and P0 for core0. @@ -379,8 +370,7 @@ } } - -static void coreDelay (void) +static void coreDelay(void) { u32 saved; u32 hi, lo, msr; @@ -390,23 +380,22 @@ This seems like a hack to me... It would be nice to have a central delay function. */ - cycles = 8000 << 3; /* x8 (number of 1.25ns ticks) */ + cycles = 8000 << 3; /* x8 (number of 1.25ns ticks) */ - msr = 0x10; /* TSC */ + msr = 0x10; /* TSC */ _RDMSR(msr, &lo, &hi); saved = lo; do { _RDMSR(msr, &lo, &hi); - } while (lo - saved < cycles ); + } while (lo - saved < cycles); } - static void transitionVid(u32 targetVid, u8 dev, u8 isNb) { u32 currentVid, dtemp; msr_t msr; u8 vsTimecode; - u16 timeTable[8]={10, 20, 30, 40, 60, 100, 200, 500}; + u16 timeTable[8] = { 10, 20, 30, 40, 60, 100, 200, 500 }; int vsTime; /* This function steps or slam the Nb VID to the target VID. @@ -416,7 +405,7 @@ /* get the current VID */ msr = rdmsr(0xC0010071); - if(isNb) + if (isNb) currentVid = (msr.lo >> NB_VID_POS) & BIT_MASK_7; else currentVid = (msr.lo >> CPU_VID_POS) & BIT_MASK_7; @@ -426,11 +415,11 @@ /* check PVI/SPI */ dtemp = pci_read_config32(dev, 0xA0); - if (dtemp & PVI_MODE) { /* PVI, step VID */ + if (dtemp & PVI_MODE) { /* PVI, step VID */ if (currentVid < targetVid) { while (currentVid < targetVid) { currentVid++; - if(isNb) + if (isNb) msr.lo = (msr.lo & NB_VID_MASK_OFF) | (currentVid << NB_VID_POS); else msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (currentVid << CPU_VID_POS); @@ -438,17 +427,17 @@ /* read F3xD8[VSRampTime] */ dtemp = pci_read_config32(dev, 0xD8); - vsTimecode = (u8)((dtemp >> VS_RAMP_T) & 0x7); - vsTime = (int) timeTable[vsTimecode]; + vsTimecode = (u8) ((dtemp >> VS_RAMP_T) & 0x7); + vsTime = (int)timeTable[vsTimecode]; do { coreDelay(); - vsTime -=40; - } while(vsTime > 0); + vsTime -= 40; + } while (vsTime > 0); } } else if (currentVid > targetVid) { while (currentVid > targetVid) { currentVid--; - if(isNb) + if (isNb) msr.lo = (msr.lo & NB_VID_MASK_OFF) | (currentVid << NB_VID_POS); else msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (currentVid << CPU_VID_POS); @@ -456,16 +445,16 @@ /* read F3xD8[VSRampTime] */ dtemp = pci_read_config32(dev, 0xD8); - vsTimecode = (u8)((dtemp >> VS_RAMP_T) & 0x7); - vsTime = (int) timeTable[vsTimecode]; + vsTimecode = (u8) ((dtemp >> VS_RAMP_T) & 0x7); + vsTime = (int)timeTable[vsTimecode]; do { coreDelay(); - vsTime -=40; - } while(vsTime > 0); + vsTime -= 40; + } while (vsTime > 0); } } } else { /* SVI, slam VID */ - if(isNb) + if (isNb) msr.lo = (msr.lo & NB_VID_MASK_OFF) | (targetVid << NB_VID_POS); else msr.lo = (msr.lo & CPU_VID_MASK_OFF) | (targetVid << CPU_VID_POS); @@ -473,12 +462,12 @@ /* read F3xD8[VSRampTime] */ dtemp = pci_read_config32(dev, 0xD8); - vsTimecode = (u8)((dtemp >> VS_RAMP_T) & 0x7); - vsTime = (int) timeTable[vsTimecode]; + vsTimecode = (u8) ((dtemp >> VS_RAMP_T) & 0x7); + vsTime = (int)timeTable[vsTimecode]; do { coreDelay(); - vsTime -=40; - } while(vsTime > 0); + vsTime -= 40; + } while (vsTime > 0); } } @@ -505,13 +494,13 @@ nodes = get_nodes(); nb_cof_vid_update = 0; for (i = 0; i < nodes; i++) { - if (pci_read_config32(NODE_PCI(i,3), 0x1FC) & 1) { + if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) { nb_cof_vid_update = 1; break; } } - dev = NODE_PCI(nodeid,3); + dev = NODE_PCI(nodeid, 3); pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1; reg1fc = pci_read_config32(dev, 0x1FC); @@ -537,7 +526,7 @@ } send = (nb_cof_vid_update << 16) | (fid_max << 8); - send |= (apicid << 24); // ap apicid + send |= (apicid << 24); // ap apicid // Send signal to BSP about this AP max fid // This also indicates this AP is ready for warm reset (if required). @@ -553,50 +542,50 @@ fidmax_new = (fid_packed_new >> 8) & 0xFF; - if(fidmax > fidmax_new) { + if (fidmax > fidmax_new) { fidmax = fidmax_new; } fid_packed &= 0xFF << 16; fid_packed |= (fidmax << 8); - fid_packed |= fid_packed_new & (0xFF << 16); // set nb_cof_vid_update + fid_packed |= fid_packed_new & (0xFF << 16); // set nb_cof_vid_update return fid_packed; } - -static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp ) +static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp) { - u32 readback = 0; - u32 timeout = 1; + u32 readback = 0; + u32 timeout = 1; - struct fidvid_st *fvp = gp; - int loop; + struct fidvid_st *fvp = gp; + int loop; - print_debug_fv("Wait for AP stage 1: ap_apicid = ", ap_apicid); - - loop = 100000; - while(--loop > 0) { - if(lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0) continue; - if((readback & 0x3f) == 1) { - timeout = 0; - break; //target ap is in stage 1 - } - } + print_debug_fv("Wait for AP stage 1: ap_apicid = ", ap_apicid); - if(timeout) { - print_initcpu8("fidvid_bsp_stage1: time out while reading from ap ", ap_apicid); - return; + loop = 100000; + while (--loop > 0) { + if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0) + continue; + if ((readback & 0x3f) == 1) { + timeout = 0; + break; /* target ap is in stage 1 */ } + } - print_debug_fv("\treadback = ", readback); + if (timeout) { + printk(BIOS_DEBUG, "%s: timed out reading from ap %02x\n", + __func__, ap_apicid); + return; + } - fvp->common_fid = calc_common_fid(fvp->common_fid, readback); + print_debug_fv("\treadback = ", readback); - print_debug_fv("\tcommon_fid(packed) = ", fvp->common_fid); + fvp->common_fid = calc_common_fid(fvp->common_fid, readback); -} + print_debug_fv("\tcommon_fid(packed) = ", fvp->common_fid); +} static void updateSviPsNbVidAfterWR(u32 newNbVid) { @@ -607,7 +596,7 @@ * for SVI mode. */ - for( i = 0; i < 5; i++) { + for (i = 0; i < 5; i++) { msr = rdmsr(0xC0010064 + i); if ((msr.hi >> 31) & 1) { /* PstateEn? */ msr.lo &= ~(0x7F << 25); @@ -632,13 +621,13 @@ */ /* write newNbVid to P-state Reg's NbVid if its NbDid=0 */ - for( i = 0; i < 5; i++) { + for (i = 0; i < 5; i++) { msr = rdmsr(0xC0010064 + i); /* NbDid (bit 22 of P-state Reg) == 0 or NbVidUpdatedAll = 1 */ if ((((msr.lo >> 22) & 1) == 0) || NbVidUpdatedAll) { msr.lo &= ~(0x7F << 25); msr.lo |= (newNbVid & 0x7F) << 25; - wrmsr (0xC0010064 + i, msr); + wrmsr(0xC0010064 + i, msr); } } @@ -651,13 +640,12 @@ msr.lo = StartupPstate; wrmsr(0xC0010062, msr); - /* Wait for StartupPstate to set.*/ + /* Wait for StartupPstate to set. */ do { msr = rdmsr(0xC0010063); } while (msr.lo != StartupPstate); } - static void set_p0(void) { msr_t msr; @@ -673,8 +661,8 @@ } while (msr.lo != 0); } - -static void finalPstateChange (void) { +static void finalPstateChange(void) +{ /* Enble P0 on all cores for best performance. * Linux can slow them down later if need be. * It is safe since they will be in C1 halt @@ -683,7 +671,6 @@ set_p0(); } - static void init_fidvid_stage2(u32 apicid, u32 nodeid) { msr_t msr; @@ -703,13 +690,13 @@ nodes = get_nodes(); nb_cof_vid_update = 0; for (i = 0; i < nodes; i++) { - if (pci_read_config32(NODE_PCI(i,3), 0x1FC) & 1) { + if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) { nb_cof_vid_update = 1; break; } } - dev = NODE_PCI(nodeid,3); + dev = NODE_PCI(nodeid, 3); pvimode = (pci_read_config32(dev, 0xA0) >> 8) & 1; reg1fc = pci_read_config32(dev, 0x1FC); nbvid = (reg1fc >> 7) & 0x7F; @@ -724,7 +711,7 @@ nbvid = ((reg1fc >> 7) & 0x7F) - ((reg1fc >> 17) & 0x1F); updateSviPsNbVidAfterWR(nbvid); } - } else { /* !nb_cof_vid_update */ + } else { /* !nb_cof_vid_update */ if (pvimode) UpdateSinglePlaneNbVid(); } @@ -742,7 +729,7 @@ } -#if FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 struct ap_apicid_st { u32 num; // it could use 256 bytes for 64 node quad core system @@ -761,7 +748,7 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) { -#if FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 struct ap_apicid_st ap_apicidx; u32 i; #endif @@ -785,7 +772,7 @@ /* If any node has nb_cof_vid_update set all nodes need an update. */ nb_cof_vid_update = 0; for (i = 0; i < nodes; i++) { - if (pci_read_config32(NODE_PCI(i,3), 0x1FC) & 1) { + if (pci_read_config32(NODE_PCI(i, 3), 0x1FC) & 1) { nb_cof_vid_update = 1; break; } @@ -810,29 +797,29 @@ /* fid setup is handled by the BSP at the end. */ - } else { /* ! nb_cof_vid_update */ + } else { /* ! nb_cof_vid_update */ /* Use max values */ if (pvimode) UpdateSinglePlaneNbVid(); } - fv.common_fid = (nb_cof_vid_update << 16) | (fid_max << 8) ; + fv.common_fid = (nb_cof_vid_update << 16) | (fid_max << 8); print_debug_fv("BSP fid = ", fv.common_fid); -#if FAM10_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 && FAM10_SET_FIDVID_CORE0_ONLY == 0 +#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 && SET_FIDVID_CORE0_ONLY == 0 /* For all APs (We know the APIC ID of all APs even when the APIC ID is lifted) remote read from AP LAPIC_MSG_REG about max fid. Then calculate the common max fid that can be used for all APs and BSP */ ap_apicidx.num = 0; - for_each_ap(bsp_apicid, FAM10_SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx); + for_each_ap(bsp_apicid, SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx); - for(i = 0; i < ap_apicidx.num; i++) { + for (i = 0; i < ap_apicidx.num; i++) { init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv); } #else - for_each_ap(bsp_apicid, FAM10_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); + for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); #endif print_debug_fv("common_fid = ", fv.common_fid); @@ -846,6 +833,6 @@ return 1; } - return 0; // No FID/VID changes. Don't reset + return 0; // No FID/VID changes. Don't reset } #endif Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Thu Apr 8 17:09:53 2010 (r5381) @@ -20,14 +20,14 @@ #include "defaults.h" //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID -#ifndef FAM10_SET_FIDVID - #define FAM10_SET_FIDVID 1 +#ifndef SET_FIDVID + #define SET_FIDVID 1 #endif -#ifndef FAM10_SET_FIDVID_CORE0_ONLY +#ifndef SET_FIDVID_CORE0_ONLY /* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, Need to do every AP to set common FID/VID*/ - #define FAM10_SET_FIDVID_CORE0_ONLY 0 + #define SET_FIDVID_CORE0_ONLY 0 #endif static void print_initcpu8 (const char *strval, u8 val) @@ -217,7 +217,7 @@ #define LAPIC_MSG_REG 0x380 -#if FAM10_SET_FIDVID == 1 +#if SET_FIDVID == 1 static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid); #endif @@ -398,8 +398,8 @@ cpuSetAMDMSR(); -#if FAM10_SET_FIDVID == 1 - #if (CONFIG_LOGICAL_CPUS == 1) && (FAM10_SET_FIDVID_CORE0_ONLY == 1) +#if SET_FIDVID == 1 + #if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1) // Run on all AP for proper FID/VID setup. if(id.coreid == 0 ) // only need set fid for core0 #endif @@ -994,7 +994,7 @@ cpuSetAMDPCI(i); } -#if FAM10_SET_FIDVID == 1 +#if SET_FIDVID == 1 // Prep each node for FID/VID setup. prep_fid_change(); #endif Modified: trunk/src/cpu/amd/model_fxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/fidvid.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/cpu/amd/model_fxx/fidvid.c Thu Apr 8 17:09:53 2010 (r5381) @@ -1,10 +1,10 @@ -#if K8_SET_FIDVID == 1 +#if SET_FIDVID == 1 -#define K8_SET_FIDVID_DEBUG 0 +#define SET_FIDVID_DEBUG 0 -#define K8_SET_FIDVID_ONE_BY_ONE 1 +#define SET_FIDVID_ONE_BY_ONE 1 -#define K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST 1 +#define SET_FIDVID_STORE_AP_APICID_AT_FIRST 1 #ifndef SB_VFSMAF #define SB_VFSMAF 1 @@ -12,78 +12,77 @@ #define FX_SUPPORT 1 -static inline void print_debug_fv(const char *str, unsigned val) +static inline void print_debug_fv(const char *str, u32 val) { -#if K8_SET_FIDVID_DEBUG == 1 - printk(BIOS_DEBUG, "%s%x\n", str, val); +#if SET_FIDVID_DEBUG == 1 + printk(BIOS_DEBUG, "%s%x\n", str, val); #endif } -static inline void print_debug_fv_8(const char *str, unsigned val) +static inline void print_debug_fv_8(const char *str, u8 val) { -#if K8_SET_FIDVID_DEBUG == 1 - printk(BIOS_DEBUG, "%s%02x\n", str, val); +#if SET_FIDVID_DEBUG == 1 + printk(BIOS_DEBUG, "%s%02x\n", str, val); #endif } -static inline void print_debug_fv_64(const char *str, unsigned val, unsigned val2) +static inline void print_debug_fv_64(const char *str, u32 val, u32 val2) { -#if K8_SET_FIDVID_DEBUG == 1 - printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); +#if SET_FIDVID_DEBUG == 1 + printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); #endif } - static void enable_fid_change(void) { - uint32_t dword; - unsigned nodes; + u32 dword; + u32 nodes; int i; nodes = ((pci_read_config32(PCI_DEV(0, 0x18, 0), 0x60) >> 4) & 7) + 1; for (i = 0; i < nodes; i++) { - dword = pci_read_config32(PCI_DEV(0, 0x18+i, 3), 0xd8); + dword = pci_read_config32(PCI_DEV(0, 0x18 + i, 3), 0xd8); dword &= 0x8ff00000; dword |= (2 << 28) | (0x02710); - pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0xd8, dword); + pci_write_config32(PCI_DEV(0, 0x18 + i, 3), 0xd8, dword); dword = 0x04e2a707; - pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0xd4, dword); + pci_write_config32(PCI_DEV(0, 0x18 + i, 3), 0xd4, dword); /* disable the DRAM interface at first, it will be enabled * by raminit again */ - dword = pci_read_config32(PCI_DEV(0, 0x18+i, 2), 0x94); + dword = pci_read_config32(PCI_DEV(0, 0x18 + i, 2), 0x94); dword |= (1 << 14); - pci_write_config32(PCI_DEV(0, 0x18+i, 2), 0x94, dword); + pci_write_config32(PCI_DEV(0, 0x18 + i, 2), 0x94, dword); - dword = 0x23070700; /* enable FID/VID change */ -// dword = 0x00070000; /* enable FID/VID change */ - pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0x80, dword); + dword = 0x23070700; /* enable FID/VID change */ +// dword = 0x00070000; /* enable FID/VID change */ + pci_write_config32(PCI_DEV(0, 0x18 + i, 3), 0x80, dword); #if CONFIG_HAVE_ACPI_RESUME dword = 0x21132113; #else dword = 0x00132113; #endif - pci_write_config32(PCI_DEV(0, 0x18+i, 3), 0x84, dword); + pci_write_config32(PCI_DEV(0, 0x18 + i, 3), 0x84, dword); } } -#if K8_SET_FIDVID_ONE_BY_ONE == 0 +#if SET_FIDVID_ONE_BY_ONE == 0 static unsigned set_fidvid_without_init(unsigned fidvid) { msr_t msr; - uint32_t vid; - uint32_t fid; + u32 vid; + u32 fid; fid = (fidvid >> 8) & 0x3f; vid = (fidvid >> 16) & 0x3f; /* set new FID/VID */ msr.hi = 1; - msr.lo = (vid<<8) | fid; + msr.lo = (vid << 8) | fid; wrmsr(0xc0010041, msr); return fidvid; } @@ -117,12 +116,12 @@ }; msr_t msr; - uint32_t vid_new; - uint32_t fid_new; - uint32_t vid_max; - uint32_t fid_max; - uint32_t vid_cur; - uint32_t fid_cur; + u32 vid_new; + u32 fid_new; + u32 vid_max; + u32 fid_max; + u32 vid_cur; + u32 fid_cur; unsigned apicidx; int step_limit; @@ -131,7 +130,9 @@ apicidx = lapicid(); if (apicid != apicidx) { - printk(BIOS_ERR, "wrong apicid, we want change %x, but it is %x\n", apicid, apicidx); + printk(BIOS_ERR, + "wrong apicid, we want change %x, but it is %x\n", + apicid, apicidx); return fidvid; } @@ -146,14 +147,14 @@ if ((vid_cur == vid_new) && (fid_cur == fid_new)) return fidvid; - vid_max = (msr.hi >> (48-32)) & 0x3f; - fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */ + vid_max = (msr.hi >> (48 - 32)) & 0x3f; + fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */ #if FX_SUPPORT - if (fid_max >= ((25 - 4) * 2)) { /* FX max fid is 5G */ - fid_max = ((msr.lo >> 8) & 0x3f) + 5 * 2; /* max FID is min fid + 1G */ - if (fid_max >= ((25-4) * 2)) { - fid_max = (10-4) * 2; /* hard set to 2G */ + if (fid_max >= ((25 - 4) * 2)) { /* FX max fid is 5G */ + fid_max = ((msr.lo >> 8) & 0x3f) + 5 * 2; /* max FID is min fid + 1G */ + if (fid_max >= ((25 - 4) * 2)) { + fid_max = (10 - 4) * 2; /* hard set to 2G */ } } #endif @@ -162,25 +163,24 @@ /* TODO - make this more correct. Not a big deal for setting max... * BKDG figure 11 * if TargetFID > InitialFID - * TargetVID = FinalVID - RVO + * TargetVID = FinalVID - RVO * else - * if CurrentVID > FinalVID - * TargetVID = FinalVID - RVO - * else - * TargetVID = CurrentVIDD - RVO + * if CurrentVID > FinalVID + * TargetVID = FinalVID - RVO + * else + * TargetVID = CurrentVIDD - RVO */ msr.hi = 1; msr.lo = (vid_max << 8) | (fid_cur); #if SB_VFSMAF == 1 - msr.lo |= (1 << 16); /* init changes */ + msr.lo |= (1 << 16); /* init changes */ #endif wrmsr(0xc0010041, msr); #if SB_VFSMAF == 0 ldtstop_sb(); #endif - - for (loop=0; loop < 100000; loop++){ + for (loop = 0; loop < 100000; loop++) { msr = rdmsr(0xc0010042); if (!(msr.lo & (1 << 31))) break; @@ -201,19 +201,20 @@ * transition to target fid */ - printk(BIOS_DEBUG, "Current fid_cur: 0x%x, fid_max: 0x%x\n", fid_cur, fid_max); + printk(BIOS_DEBUG, "Current fid_cur: 0x%x, fid_max: 0x%x\n", fid_cur, + fid_max); printk(BIOS_DEBUG, "Requested fid_new: 0x%x\n", fid_new); - step_limit = 8; /* max 8 steps just in case... */ + step_limit = 8; /* max 8 steps just in case... */ while ((fid_cur != fid_new) && (step_limit--)) { u32 fid_temp; int step; if (fid_cur < fid_new) /* Force Fid steps even. step == 0 means 100MHz step */ - step = ((fid_new/2) - (fid_cur/2)) * 2; + step = ((fid_new / 2) - (fid_cur / 2)) * 2; else - step = ((fid_cur/2) - (fid_new/2)) * 2; + step = ((fid_cur / 2) - (fid_new / 2)) * 2; /* If 200Mhz step OR past 3200 max table value */ if ((step == 2) || (fid_new >= 0x18 || fid_cur >= 0x18)) { @@ -226,23 +227,23 @@ else fid_temp = fid_cur - 2; - - } else if ( step > 2) { /* If more than a 200Mhz step */ + } else if (step > 2) { /* If more than a 200Mhz step */ int temp; /* look it up in the table */ printk(BIOS_DEBUG, "FidVid table step "); - temp = next_fid_200[((fid_new/2) * 13) + (fid_cur/2)]; + temp = + next_fid_200[((fid_new / 2) * 13) + (fid_cur / 2)]; if (temp > 0) - fid_temp = (temp-4) * 2; /* Table 108 */ + fid_temp = (temp - 4) * 2; /* Table 108 */ else if (temp == 0) fid_temp = fid_new; else - break; /* table error */ + break; /* table error */ - } else { /* step < 2 (100MHZ) */ + } else { /* step < 2 (100MHZ) */ printk(BIOS_DEBUG, "100MHZ step "); /* The table adjust in 200MHz increments. If requested, @@ -256,41 +257,41 @@ } } - if(fid_temp > fid_max) { - printk(BIOS_DEBUG, "fid_temp 0x%x > fid_max 0x%x\n", fid_temp, fid_max); + if (fid_temp > fid_max) { + printk(BIOS_DEBUG, "fid_temp 0x%x > fid_max 0x%x\n", + fid_temp, fid_max); break; } printk(BIOS_DEBUG, "fidvid: 0x%x\n", fid_temp); /* set target fid */ - msr.hi = 0x190; /* 2 us for AMD NPT Family 0Fh Processors */ + msr.hi = 0x190; /* 2 us for AMD NPT Family 0Fh Processors */ msr.lo = (vid_cur << 8) | fid_temp; #if SB_VFSMAF == 1 - msr.lo |= (1 << 16); /* init changes */ + msr.lo |= (1 << 16); /* init changes */ #endif wrmsr(0xc0010041, msr); #if SB_VFSMAF == 0 ldtstop_sb(); #endif - -#if K8_SET_FIDVID_DEBUG == 1 +#if SET_FIDVID_DEBUG == 1 if (showmessage) { print_debug_fv_8("set_fidvid APICID = ", apicid); print_debug_fv_64("fidvid ctrl msr ", msr.hi, msr.lo); } #endif - for (loop = 0; loop < 100000; loop++){ + for (loop = 0; loop < 100000; loop++) { msr = rdmsr(0xc0010042); if (!(msr.lo & (1 << 31))) break; } fid_cur = msr.lo & 0x3f; -#if K8_SET_FIDVID_DEBUG == 1 - if (showmessage) { +#if SET_FIDVID_DEBUG == 1 + if (showmessage) { print_debug_fv_64("fidvid status msr ", msr.hi, msr.lo); } #endif @@ -310,14 +311,14 @@ msr.hi = 1; msr.lo = (vid_new << 8) | (fid_cur); #if SB_VFSMAF == 1 - msr.lo |= (1 << 16); // init changes + msr.lo |= (1 << 16); // init changes #endif wrmsr(0xc0010041, msr); #if SB_VFSMAF == 0 ldtstop_sb(); #endif - for (loop = 0; loop < 100000; loop++){ + for (loop = 0; loop < 100000; loop++) { msr = rdmsr(0xc0010042); if (!(msr.lo & (1 << 31))) break; @@ -328,10 +329,12 @@ if (showmessage) { if (vid_new != vid_cur) { - print_err("set vid failed for apicid ="); print_err_hex8(apicidx); print_err("\n"); + printk(BIOS_ERR, "set vid failed for apicid =%02x\n", + apicidx); } if (fid_new != fid_cur) { - print_err("set fid failed for apicid ="); print_err_hex8(apicidx); print_err("\n"); + printk(BIOS_ERR, "set fid failed for apicid =%02x\n", + apicidx); } } @@ -341,35 +344,35 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid) { - uint32_t send; - uint32_t readback = 0; + u32 send; + u32 readback = 0; unsigned timeout = 1; msr_t msr; - uint32_t vid_cur; - uint32_t fid_cur; - uint32_t fid_max; + u32 vid_cur; + u32 fid_cur; + u32 fid_max; int loop; - msr = rdmsr(0xc0010042); - fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */ + msr = rdmsr(0xc0010042); + fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */ #if FX_SUPPORT - if (fid_max >= ((25-4) * 2)) { /* FX max fid is 5G */ - fid_max = ((msr.lo>>8) & 0x3f) + 5*2; /* maxFID = minFID + 1G */ - if (fid_max >= ((25-4) * 2)) { - fid_max = (10-4) * 2; // hard set to 2G + if (fid_max >= ((25 - 4) * 2)) { /* FX max fid is 5G */ + fid_max = ((msr.lo >> 8) & 0x3f) + 5 * 2; /* maxFID = minFID + 1G */ + if (fid_max >= ((25 - 4) * 2)) { + fid_max = (10 - 4) * 2; // hard set to 2G } } #endif - send = fid_max<<8; + send = fid_max << 8; - send |= ((msr.hi >> (48-32)) & 0x3f) << 16; /* max vid */ - send |= (apicid << 24); /* ap apicid */ + send |= ((msr.hi >> (48 - 32)) & 0x3f) << 16; /* max vid */ + send |= (apicid << 24); /* ap apicid */ -#if K8_SET_FIDVID_ONE_BY_ONE == 1 +#if SET_FIDVID_ONE_BY_ONE == 1 vid_cur = msr.hi & 0x3f; fid_cur = msr.lo & 0x3f; - /* set to current */ + /* set to current */ msr.hi = 1; msr.lo = (vid_cur << 8) | (fid_cur); wrmsr(0xc0010041, msr); @@ -377,52 +380,55 @@ timeout = wait_cpu_state(bsp_apicid, 1); if (timeout) { - print_initcpu8("fidvid_ap_stage1: time out while reading from BSP on ", apicid); + printk(BIOS_DEBUG, "fidvid_ap_stage1: time out while reading" + " from BSP on %02x\n", apicid); } /* send signal to BSP about this AP max fid and vid */ /* AP at state 1 that sent our fid and vid */ lapic_write(LAPIC_MSG_REG, send | 1); -// wait_cpu_state(bsp_apicid, 2); /* don't need we can use apicid directly */ +// wait_cpu_state(bsp_apicid, 2); /* don't need we can use apicid directly */ loop = 1000000; while (--loop > 0) { /* remote read BSP signal that include vid/fid that need to set */ - if (lapic_remote_read(bsp_apicid, LAPIC_MSG_REG, &readback)!=0) + if (lapic_remote_read(bsp_apicid, LAPIC_MSG_REG, &readback) != + 0) continue; if (((readback >> 24) & 0xff) == apicid) - break; /* it is this cpu turn */ + break; /* it is this cpu turn */ } if (loop > 0) { - #if K8_SET_FIDVID_ONE_BY_ONE == 1 - readback = set_fidvid(apicid, readback & 0xffff00, 1); // this AP - #else - readback = set_fidvid_without_init(readback & 0xffff00); // this AP - #endif +#if SET_FIDVID_ONE_BY_ONE == 1 + readback = set_fidvid(apicid, readback & 0xffff00, 1); // this AP +#else + readback = set_fidvid_without_init(readback & 0xffff00); // this AP +#endif /* send signal to BSP that this AP fid/vid is set */ /* allow to change state2 is together with apicid */ /* AP at state that We set the requested fid/vid */ - send = (apicid<<24) | (readback & 0x00ffff00); + send = (apicid << 24) | (readback & 0x00ffff00); } else { - print_initcpu8("fidvid_ap_stage2: time out while reading from BSP on ", apicid); + printk(BIOS_DEBUG, "%s: time out while reading from BSP on %02x", + __func__, apicid); } - lapic_write(LAPIC_MSG_REG, send | 2); + lapic_write(LAPIC_MSG_REG, send | 2); timeout = wait_cpu_state(bsp_apicid, 3); if (timeout) { - print_initcpu8("fidvid_ap_stage3: time out while reading from BSP on ", apicid); + printk(BIOS_DEBUG, "%s: time out while reading from BSP on %02x", + __func__, apicid); } } -static unsigned calc_common_fidvid(unsigned fidvid, unsigned fidvidx) +static u32 calc_common_fidvid(unsigned fidvid, unsigned fidvidx) { /* FIXME: need to check the change path to verify if it is reachable * when common fid is small than 1.6G */ if ((fidvid & 0xff00) <= (fidvidx & 0xff00)) { return fidvid; - } - else { + } else { return fidvidx; } } @@ -431,10 +437,10 @@ unsigned common_fidvid; }; -static void init_fidvid_bsp_stage1(unsigned ap_apicid, void *gp ) +static void init_fidvid_bsp_stage1(u32 ap_apicid, void *gp) { - unsigned readback = 0; - unsigned timeout = 1; + u32 readback = 0; + u32 timeout = 1; struct fidvid_st *fvp = gp; int loop; @@ -443,19 +449,21 @@ loop = 1000000; while (--loop > 0) { - if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback)!=0) + if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0) continue; if ((readback & 0xff) == 1) { timeout = 0; - break; /* target ap is in stage 1 */ + break; /* target ap is in stage 1 */ } } + if (timeout) { - print_initcpu8("fidvid_bsp_stage1: time out while reading from ap ", ap_apicid); + printk(BIOS_DEBUG, "%s: timed out reading from ap %02x\n", + __func__, ap_apicid); return; } - print_debug_fv("\treadback=", readback); + print_debug_fv("\treadback = ", readback); fvp->common_fidvid = calc_common_fidvid(fvp->common_fidvid, readback & 0xffff00); @@ -473,31 +481,31 @@ print_debug_fv("state 2: ap_apicid=", ap_apicid); /* all set to state2 */ - lapic_write(LAPIC_MSG_REG, fvp->common_fidvid | (ap_apicid<<24) | 2); + lapic_write(LAPIC_MSG_REG, fvp->common_fidvid | (ap_apicid << 24) | 2); loop = 1000000; while (--loop > 0) { - if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback)!=0) + if (lapic_remote_read(ap_apicid, LAPIC_MSG_REG, &readback) != 0) continue; if ((readback & 0xff) == 2) { timeout = 0; - break; /* target ap is stage 2, it's FID has beed set */ + break; /* target ap is stage 2, it's FID has beed set */ } } if (timeout) { - print_initcpu8("fidvid_bsp_stage2: time out while reading from ap ", ap_apicid); + printk(BIOS_DEBUG, "%s: time out while reading from ap %02x", + __func__, ap_apicid); return; } print_debug_fv("\treadback=", readback); } -#if K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 struct ap_apicid_st { - unsigned num; - unsigned apicid[16]; /* 8 way dual core need 16 */ - /* FIXME: 32 node quad core, may need 128 */ + u32 num; + unsigned apicid[16]; /* 8 way dual core need 16 */ }; static void store_ap_apicid(unsigned ap_apicid, void *gp) @@ -511,77 +519,75 @@ static void init_fidvid_bsp(unsigned bsp_apicid) { - uint32_t vid_max; - uint32_t fid_max; + u32 vid_max; + u32 fid_max; struct fidvid_st fv; -#if K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 struct ap_apicid_st ap_apicidx; unsigned i; #endif msr_t msr; - msr = rdmsr(0xc0010042); - fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */ + msr = rdmsr(0xc0010042); + fid_max = ((msr.lo >> 16) & 0x3f); /* max fid */ #if FX_SUPPORT == 1 - if (fid_max >= ((25-4) * 2)) { /* FX max fid is 5G */ - fid_max = ((msr.lo >> 8) & 0x3f) + 5*2; /* maxFID = minFID + 1G */ - if (fid_max >= ((25-4) * 2)) { - fid_max = (10-4) * 2; /* hard set to 2G */ + if (fid_max >= ((25 - 4) * 2)) { /* FX max fid is 5G */ + fid_max = ((msr.lo >> 8) & 0x3f) + 5 * 2; /* maxFID = minFID + 1G */ + if (fid_max >= ((25 - 4) * 2)) { + fid_max = (10 - 4) * 2; /* hard set to 2G */ } } #endif - vid_max = ((msr.hi>>(48-32)) & 0x3f); //max vid - fv.common_fidvid = (fid_max << 8)|(vid_max << 16); - + vid_max = ((msr.hi >> (48 - 32)) & 0x3f); //max vid + fv.common_fidvid = (fid_max << 8) | (vid_max << 16); /* for all APs (We know the APIC ID of all APs even the APIC ID is lifted) * remote read from AP about max fid/vid */ /* let all ap trains to state 1 */ - lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 1); + lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 1); /* calculate the common max fid/vid that could be used for * all APs and BSP */ -#if K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 ap_apicidx.num = 0; - for_each_ap(bsp_apicid, K8_SET_FIDVID_CORE0_ONLY, store_ap_apicid, &ap_apicidx); + for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, store_ap_apicid, &ap_apicidx); for (i = 0; i < ap_apicidx.num; i++) { init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv); } #else - for_each_ap(bsp_apicid, K8_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); + for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); #endif - #if 0 unsigned fid, vid; /* Can we use max only? So we can only set fid in one around, * otherwise we need to set that to max after raminit */ /* set fid vid to DQS training required */ - fid = (fv.common_fidvid >> 8) & 0x3f; + fid = (fv.common_fidvid >> 8) & 0x3f; vid = (fv.common_fidvid >> 16) & 0x3f; - if (fid > (10-4) * 2) { - fid = (10-4) * 2; // x10 + if (fid > (10 - 4) * 2) { + fid = (10 - 4) * 2; // x10 } if (vid >= 0x1f) { - vid += 4; /* unit is 12.5mV */ + vid += 4; /* unit is 12.5mV */ } else { - vid += 2; /* unit is 25mV */ + vid += 2; /* unit is 25mV */ } - fv.common_fidvid = (fid<<8) | (vid<<16); + fv.common_fidvid = (fid << 8) | (vid << 16); print_debug_fv("common_fidvid=", fv.common_fidvid); #endif -#if K8_SET_FIDVID_ONE_BY_ONE == 1 +#if SET_FIDVID_ONE_BY_ONE == 1 /* set BSP fid and vid */ print_debug_fv("bsp apicid=", bsp_apicid); fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1); @@ -595,15 +601,15 @@ fv.common_fidvid &= 0xffff00; /* set state 2 allow is in init_fidvid_bsp_stage2 */ -#if K8_SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 for (i = 0; i < ap_apicidx.num; i++) { init_fidvid_bsp_stage2(ap_apicidx.apicid[i], &fv); } #else - for_each_ap(bsp_apicid, K8_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv); + for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv); #endif -#if K8_SET_FIDVID_ONE_BY_ONE == 0 +#if SET_FIDVID_ONE_BY_ONE == 0 /* set BSP fid and vid */ print_debug_fv("bsp apicid=", bsp_apicid); fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1); @@ -616,7 +622,5 @@ /* here wait a while, so last ap could read pack, and stop it, don't * call init_timer too early or just don't use init_timer */ - } - #endif Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/init_cpus.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/cpu/amd/model_fxx/init_cpus.c Thu Apr 8 17:09:53 2010 (r5381) @@ -1,17 +1,17 @@ //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID -#ifndef K8_SET_FIDVID +#ifndef SET_FIDVID #if CONFIG_K8_REV_F_SUPPORT == 0 - #define K8_SET_FIDVID 0 + #define SET_FIDVID 0 #else // for rev F, need to set FID to max - #define K8_SET_FIDVID 1 + #define SET_FIDVID 1 #endif #endif -#ifndef K8_SET_FIDVID_CORE0_ONLY +#ifndef SET_FIDVID_CORE0_ONLY /* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, so may don't need to do twice*/ - #define K8_SET_FIDVID_CORE0_ONLY 1 + #define SET_FIDVID_CORE0_ONLY 1 #endif static inline void print_initcpu8 (const char *strval, unsigned val) @@ -149,7 +149,7 @@ #define LAPIC_MSG_REG 0x380 -#if K8_SET_FIDVID == 1 +#if SET_FIDVID == 1 static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid); #endif @@ -302,8 +302,8 @@ if(apicid != bsp_apicid) { unsigned timeout=1; unsigned loop = 100; - #if K8_SET_FIDVID == 1 - #if (CONFIG_LOGICAL_CPUS == 1) && (K8_SET_FIDVID_CORE0_ONLY == 1) + #if SET_FIDVID == 1 + #if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1) if(id.coreid == 0 ) // only need set fid for core0 #endif init_fidvid_ap(bsp_apicid, apicid); Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -18,7 +18,7 @@ */ #define RAMINIT_SYSINFO 1 -#define K8_SET_FIDVID 1 +#define SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/amd/mahogany/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -18,7 +18,7 @@ */ #define RAMINIT_SYSINFO 1 -#define K8_SET_FIDVID 1 +#define SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -34,8 +34,8 @@ #define FAM10_ALLOCATE_IO_RANGE 0 //used by init_cpus and fidvid -#define FAM10_SET_FIDVID 1 -#define FAM10_SET_FIDVID_CORE_RANGE 0 +#define SET_FIDVID 1 +#define SET_FIDVID_CORE_RANGE 0 #include <stdint.h> #include <string.h> @@ -208,7 +208,7 @@ rs780_early_setup(); sb700_early_setup(); - #if FAM10_SET_FIDVID == 1 + #if SET_FIDVID == 1 msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); Modified: trunk/src/mainboard/amd/pistachio/romstage.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/amd/pistachio/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -18,7 +18,7 @@ */ #define RAMINIT_SYSINFO 1 -#define K8_SET_FIDVID 1 +#define SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -10,9 +10,9 @@ //#define K8_ALLOCATE_IO_RANGE 1 //used by init_cpus and fidvid -#define K8_SET_FIDVID 0 +#define SET_FIDVID 0 //if we want to wait for core1 done before DQS training, set it to 0 -#define K8_SET_FIDVID_CORE0_ONLY 1 +#define SET_FIDVID_CORE0_ONLY 1 #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 @@ -164,7 +164,7 @@ int needs_reset; unsigned bsp_apicid = 0; -#if K8_SET_FIDVID == 1 +#if SET_FIDVID == 1 struct cpuid_result cpuid1; #endif @@ -228,7 +228,7 @@ needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif -#if K8_SET_FIDVID == 1 +#if SET_FIDVID == 1 /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ cpuid1 = cpuid(0x80000007); Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -34,8 +34,8 @@ #define FAM10_ALLOCATE_IO_RANGE 0 //used by init_cpus and fidvid -#define FAM10_SET_FIDVID 1 -#define FAM10_SET_FIDVID_CORE_RANGE 0 +#define SET_FIDVID 1 +#define SET_FIDVID_CORE_RANGE 0 #include <stdint.h> #include <string.h> @@ -211,7 +211,7 @@ post_code(0x38); - #if FAM10_SET_FIDVID == 1 + #if SET_FIDVID == 1 msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -19,7 +19,7 @@ */ #define RAMINIT_SYSINFO 1 -#define K8_SET_FIDVID 1 +#define SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -32,10 +32,10 @@ #define QRANK_DIMM_SUPPORT 1 /* Used by init_cpus and fidvid */ -#define K8_SET_FIDVID 1 +#define SET_FIDVID 1 /* If we want to wait for core1 done before DQS training, set it to 0. */ -#define K8_SET_FIDVID_CORE0_ONLY 1 +#define SET_FIDVID_CORE0_ONLY 1 #include <stdint.h> #include <string.h> Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -32,10 +32,10 @@ #define QRANK_DIMM_SUPPORT 1 /* Used by init_cpus and fidvid */ -#define K8_SET_FIDVID 1 +#define SET_FIDVID 1 /* If we want to wait for core1 done before DQS training, set it to 0. */ -#define K8_SET_FIDVID_CORE0_ONLY 1 +#define SET_FIDVID_CORE0_ONLY 1 #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -32,9 +32,9 @@ #endif //used by init_cpus and fidvid -#define K8_SET_FIDVID 1 +#define SET_FIDVID 1 //if we want to wait for core1 done before DQS training, set it to 0 -#define K8_SET_FIDVID_CORE0_ONLY 1 +#define SET_FIDVID_CORE0_ONLY 1 #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 @@ -235,7 +235,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if K8_SET_FIDVID == 1 +#if SET_FIDVID == 1 { msr_t msr; Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -30,9 +30,9 @@ #endif //used by init_cpus and fidvid -#define K8_SET_FIDVID 1 +#define SET_FIDVID 1 //if we want to wait for core1 done before DQS training, set it to 0 -#define K8_SET_FIDVID_CORE0_ONLY 1 +#define SET_FIDVID_CORE0_ONLY 1 #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 @@ -249,7 +249,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if K8_SET_FIDVID == 1 +#if SET_FIDVID == 1 { msr_t msr; Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -36,9 +36,9 @@ #endif //used by init_cpus and fidvid -#define K8_SET_FIDVID 1 +#define SET_FIDVID 1 //if we want to wait for core1 done before DQS training, set it to 0 -#define K8_SET_FIDVID_CORE0_ONLY 1 +#define SET_FIDVID_CORE0_ONLY 1 #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 @@ -252,7 +252,7 @@ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn bcm5785_early_setup(); -#if K8_SET_FIDVID == 1 +#if SET_FIDVID == 1 { msr_t msr; msr=rdmsr(0xc0010042); Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -10,9 +10,9 @@ //#define K8_ALLOCATE_IO_RANGE 1 //used by init_cpus and fidvid -#define K8_SET_FIDVID 0 +#define SET_FIDVID 0 //if we want to wait for core1 done before DQS training, set it to 0 -#define K8_SET_FIDVID_CORE0_ONLY 1 +#define SET_FIDVID_CORE0_ONLY 1 #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 @@ -188,7 +188,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if K8_SET_FIDVID == 1 +#if SET_FIDVID == 1 { msr_t msr; Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -10,9 +10,9 @@ //#define K8_ALLOCATE_IO_RANGE 1 //used by init_cpus and fidvid -#define K8_SET_FIDVID 0 +#define SET_FIDVID 0 //if we want to wait for core1 done before DQS training, set it to 0 -#define K8_SET_FIDVID_CORE0_ONLY 1 +#define SET_FIDVID_CORE0_ONLY 1 #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 @@ -188,7 +188,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if K8_SET_FIDVID == 1 +#if SET_FIDVID == 1 { msr_t msr; Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -10,9 +10,9 @@ //#define K8_ALLOCATE_IO_RANGE 1 //used by init_cpus and fidvid -#define K8_SET_FIDVID 0 +#define SET_FIDVID 0 //if we want to wait for core1 done before DQS training, set it to 0 -#define K8_SET_FIDVID_CORE0_ONLY 1 +#define SET_FIDVID_CORE0_ONLY 1 #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 @@ -188,7 +188,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if K8_SET_FIDVID == 1 +#if SET_FIDVID == 1 { msr_t msr; Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/kontron/kt690/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -19,7 +19,7 @@ */ #define RAMINIT_SYSINFO 1 -#define K8_SET_FIDVID 1 +#define SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/msi/ms7260/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -33,10 +33,10 @@ #endif /* Used by init_cpus and fidvid. */ -#define K8_SET_FIDVID 1 +#define SET_FIDVID 1 /* If we want to wait for core1 done before DQS training, set it to 0. */ -#define K8_SET_FIDVID_CORE0_ONLY 1 +#define SET_FIDVID_CORE0_ONLY 1 #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 @@ -214,7 +214,7 @@ /* Set up chains and store link pair for optimization later. */ ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ -#if K8_SET_FIDVID == 1 +#if SET_FIDVID == 1 { msr_t msr = rdmsr(0xc0010042); print_debug("begin msr fid, vid "); Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/msi/ms9185/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -35,9 +35,9 @@ //#define K8_ALLOCATE_IO_RANGE 1 //used by init_cpus and fidvid -#define K8_SET_FIDVID 1 +#define SET_FIDVID 1 //if we want to wait for core1 done before DQS training, set it to 0 -#define K8_SET_FIDVID_CORE0_ONLY 1 +#define SET_FIDVID_CORE0_ONLY 1 #include <stdint.h> #include <string.h> @@ -221,7 +221,7 @@ needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif -#if K8_SET_FIDVID == 1 +#if SET_FIDVID == 1 { msr_t msr; Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/msi/ms9282/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -31,9 +31,9 @@ #define QRANK_DIMM_SUPPORT 1 //used by init_cpus and fidvid -#define K8_SET_FIDVID 1 +#define SET_FIDVID 1 //if we want to wait for core1 done before DQS training, set it to 0 -#define K8_SET_FIDVID_CORE0_ONLY 1 +#define SET_FIDVID_CORE0_ONLY 1 #include <stdint.h> #include <string.h> Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -30,8 +30,8 @@ #define SET_NB_CFG_54 1 #endif -#define FAM10_SET_FIDVID 1 -#define FAM10_SET_FIDVID_CORE_RANGE 0 +#define SET_FIDVID 1 +#define SET_FIDVID_CORE_RANGE 0 #define DBGP_DEFAULT 7 @@ -248,7 +248,7 @@ post_code(0x38); -#if FAM10_SET_FIDVID == 1 +#if SET_FIDVID == 1 msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -30,9 +30,9 @@ #endif //used by init_cpus and fidvid -#define K8_SET_FIDVID 0 +#define SET_FIDVID 0 //if we want to wait for core1 done before DQS training, set it to 0 -#define K8_SET_FIDVID_CORE0_ONLY 1 +#define SET_FIDVID_CORE0_ONLY 1 #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 @@ -236,7 +236,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if K8_SET_FIDVID == 1 +#if SET_FIDVID == 1 { msr_t msr; Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -27,9 +27,9 @@ #endif // used by init_cpus and fidvid -#define K8_SET_FIDVID 1 +#define SET_FIDVID 1 //if we want to wait for core1 done before DQS training, set it to 0 -#define K8_SET_FIDVID_CORE0_ONLY 1 +#define SET_FIDVID_CORE0_ONLY 1 #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 @@ -295,7 +295,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if K8_SET_FIDVID == 1 +#if SET_FIDVID == 1 { msr_t msr; Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -30,9 +30,9 @@ #endif //used by init_cpus and fidvid -#define K8_SET_FIDVID 1 +#define SET_FIDVID 1 //if we want to wait for core1 done before DQS training, set it to 0 -#define K8_SET_FIDVID_CORE0_ONLY 1 +#define SET_FIDVID_CORE0_ONLY 1 #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 @@ -223,7 +223,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if K8_SET_FIDVID == 1 +#if SET_FIDVID == 1 { msr_t msr; Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -30,8 +30,8 @@ #define SET_NB_CFG_54 1 #endif -#define FAM10_SET_FIDVID 1 -#define FAM10_SET_FIDVID_CORE_RANGE 0 +#define SET_FIDVID 1 +#define SET_FIDVID_CORE_RANGE 0 #include <stdint.h> #include <string.h> @@ -235,7 +235,7 @@ post_code(0x38); -#if FAM10_SET_FIDVID == 1 +#if SET_FIDVID == 1 msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -30,8 +30,8 @@ #define SET_NB_CFG_54 1 #endif -#define FAM10_SET_FIDVID 1 -#define FAM10_SET_FIDVID_CORE_RANGE 0 +#define SET_FIDVID 1 +#define SET_FIDVID_CORE_RANGE 0 #include <stdint.h> #include <string.h> @@ -280,7 +280,7 @@ post_code(0x38); -#if FAM10_SET_FIDVID == 1 +#if SET_FIDVID == 1 msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -18,7 +18,7 @@ */ #define RAMINIT_SYSINFO 1 -#define K8_SET_FIDVID 1 +#define SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -18,7 +18,7 @@ */ #define RAMINIT_SYSINFO 1 -#define K8_SET_FIDVID 1 +#define SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/tyan/s2912/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -30,9 +30,9 @@ #endif //used by init_cpus and fidvid -#define K8_SET_FIDVID 0 +#define SET_FIDVID 0 //if we want to wait for core1 done before DQS training, set it to 0 -#define K8_SET_FIDVID_CORE0_ONLY 1 +#define SET_FIDVID_CORE0_ONLY 1 #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 @@ -232,7 +232,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if K8_SET_FIDVID == 1 +#if SET_FIDVID == 1 { msr_t msr; Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Thu Apr 8 17:06:44 2010 (r5380) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Thu Apr 8 17:09:53 2010 (r5381) @@ -30,8 +30,8 @@ #define SET_NB_CFG_54 1 #endif -#define FAM10_SET_FIDVID 1 -#define FAM10_SET_FIDVID_CORE_RANGE 0 +#define SET_FIDVID 1 +#define SET_FIDVID_CORE_RANGE 0 #define DBGP_DEFAULT 7 @@ -243,7 +243,7 @@ post_code(0x38); -#if FAM10_SET_FIDVID == 1 +#if SET_FIDVID == 1 msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

1 0

[commit] r5380 - in trunk/src: cpu/amd/dualcore cpu/amd/model_10xxx cpu/amd/model_fxx cpu/amd/quadcore mainboard/amd/db800 mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 ...
by repository service 08 Apr '10

08 Apr '10

Author: myles Date: Thu Apr 8 17:06:44 2010 New Revision: 5380 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5380 Log: Replace dual_core and quad_core CMOS (nvram) options with multi_core. Fix some white space. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/cpu/amd/dualcore/amd_sibling.c trunk/src/cpu/amd/dualcore/dualcore.c trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/model_fxx/init_cpus.c trunk/src/cpu/amd/quadcore/amd_sibling.c trunk/src/cpu/amd/quadcore/quadcore.c trunk/src/mainboard/amd/db800/cmos.layout trunk/src/mainboard/amd/dbm690t/cmos.layout trunk/src/mainboard/amd/mahogany/cmos.layout trunk/src/mainboard/amd/mahogany_fam10/cmos.layout trunk/src/mainboard/amd/norwich/cmos.layout trunk/src/mainboard/amd/pistachio/cmos.layout trunk/src/mainboard/amd/rumba/cmos.layout trunk/src/mainboard/amd/serengeti_cheetah/cmos.layout trunk/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout trunk/src/mainboard/arima/hdama/cmos.layout trunk/src/mainboard/artecgroup/dbe61/cmos.layout trunk/src/mainboard/asrock/939a785gmh/cmos.layout trunk/src/mainboard/asus/a8n_e/cmos.layout trunk/src/mainboard/asus/a8v-e_se/cmos.layout trunk/src/mainboard/asus/m2v-mx_se/cmos.layout trunk/src/mainboard/asus/mew-vm/cmos.layout trunk/src/mainboard/bcom/winnetp680/cmos.layout trunk/src/mainboard/broadcom/blast/cmos.layout trunk/src/mainboard/dell/s1850/cmos.layout trunk/src/mainboard/digitallogic/adl855pc/cmos.layout trunk/src/mainboard/digitallogic/msm586seg/cmos.layout trunk/src/mainboard/digitallogic/msm800sev/cmos.layout trunk/src/mainboard/eaglelion/5bcm/cmos.layout trunk/src/mainboard/emulation/qemu-x86/cmos.layout trunk/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout trunk/src/mainboard/gigabyte/m57sli/cmos.layout trunk/src/mainboard/hp/dl145_g3/cmos.layout trunk/src/mainboard/ibm/e325/cmos.layout trunk/src/mainboard/ibm/e326/cmos.layout trunk/src/mainboard/iei/juki-511p/cmos.layout trunk/src/mainboard/iei/nova4899r/cmos.layout trunk/src/mainboard/intel/jarrell/cmos.layout trunk/src/mainboard/intel/xe7501devkit/cmos.layout trunk/src/mainboard/iwill/dk8_htx/cmos.layout trunk/src/mainboard/iwill/dk8s2/cmos.layout trunk/src/mainboard/iwill/dk8x/cmos.layout trunk/src/mainboard/jetway/j7f24/cmos.layout trunk/src/mainboard/kontron/kt690/cmos.layout trunk/src/mainboard/lippert/frontrunner/cmos.layout trunk/src/mainboard/msi/ms7135/cmos.layout trunk/src/mainboard/msi/ms7260/cmos.layout trunk/src/mainboard/msi/ms9185/cmos.layout trunk/src/mainboard/msi/ms9282/cmos.layout trunk/src/mainboard/msi/ms9652_fam10/cmos.layout trunk/src/mainboard/newisys/khepri/cmos.layout trunk/src/mainboard/nvidia/l1_2pvv/cmos.layout trunk/src/mainboard/olpc/btest/cmos.layout trunk/src/mainboard/olpc/rev_a/cmos.layout trunk/src/mainboard/pcengines/alix1c/cmos.layout trunk/src/mainboard/sunw/ultra40/cmos.layout trunk/src/mainboard/supermicro/h8dme/cmos.layout trunk/src/mainboard/supermicro/h8dmr/cmos.layout trunk/src/mainboard/supermicro/h8dmr_fam10/cmos.layout trunk/src/mainboard/supermicro/h8qme_fam10/cmos.layout trunk/src/mainboard/supermicro/x6dai_g/cmos.layout trunk/src/mainboard/supermicro/x6dhe_g/cmos.layout trunk/src/mainboard/supermicro/x6dhe_g2/cmos.layout trunk/src/mainboard/supermicro/x6dhr_ig/cmos.layout trunk/src/mainboard/supermicro/x6dhr_ig2/cmos.layout trunk/src/mainboard/technexion/tim5690/cmos.layout trunk/src/mainboard/technexion/tim8690/cmos.layout trunk/src/mainboard/technologic/ts5300/cmos.layout trunk/src/mainboard/tyan/s2735/cmos.layout trunk/src/mainboard/tyan/s2850/cmos.layout trunk/src/mainboard/tyan/s2875/cmos.layout trunk/src/mainboard/tyan/s2880/cmos.layout trunk/src/mainboard/tyan/s2881/cmos.layout trunk/src/mainboard/tyan/s2882/cmos.layout trunk/src/mainboard/tyan/s2885/cmos.layout trunk/src/mainboard/tyan/s2891/cmos.layout trunk/src/mainboard/tyan/s2892/cmos.layout trunk/src/mainboard/tyan/s2895/cmos.layout trunk/src/mainboard/tyan/s2912/cmos.layout trunk/src/mainboard/tyan/s2912_fam10/cmos.layout trunk/src/mainboard/tyan/s4880/cmos.layout trunk/src/mainboard/tyan/s4882/cmos.layout trunk/src/mainboard/via/epia-cn/cmos.layout trunk/src/mainboard/via/epia-m/cmos.layout trunk/src/mainboard/via/epia-m700/cmos.layout trunk/src/mainboard/via/epia-n/cmos.layout trunk/src/mainboard/via/epia/cmos.layout trunk/src/mainboard/winent/pl6064/cmos.layout trunk/src/northbridge/amd/amdfam10/northbridge.c trunk/src/northbridge/amd/amdk8/coherent_ht.c trunk/src/northbridge/amd/amdk8/northbridge.c Modified: trunk/src/cpu/amd/dualcore/amd_sibling.c ============================================================================== --- trunk/src/cpu/amd/dualcore/amd_sibling.c Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/cpu/amd/dualcore/amd_sibling.c Thu Apr 8 17:06:44 2010 (r5380) @@ -61,7 +61,7 @@ unsigned nb_cfg_54; int bsp_apic_id = lapicid(); // bsp apicid - get_option(&disable_siblings, "dual_core"); + get_option(&disable_siblings, "multi_core"); //get the nodes number dev = dev_find_slot(0, PCI_DEVFN(0x18,0)); @@ -129,7 +129,7 @@ /* On the bootstrap processor see if I want sibling cpus enabled */ if (first_time) { first_time = 0; - get_option(&disable_siblings, "dual_core"); + get_option(&disable_siblings, "multi_core"); } result = cpuid(0x80000008); /* See how many sibling cpus we have */ Modified: trunk/src/cpu/amd/dualcore/dualcore.c ============================================================================== --- trunk/src/cpu/amd/dualcore/dualcore.c Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/cpu/amd/dualcore/dualcore.c Thu Apr 8 17:06:44 2010 (r5380) @@ -57,8 +57,8 @@ unsigned nodeid; if (CONFIG_HAVE_OPTION_TABLE && - read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { - return; // disable dual_core + read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { + return; // disable multi_core } nodes = get_nodes(); Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Thu Apr 8 17:06:44 2010 (r5380) @@ -131,7 +131,7 @@ disable_siblings = !CONFIG_LOGICAL_CPUS; #if CONFIG_LOGICAL_CPUS == 1 - if(read_option(CMOS_VSTART_quad_core, CMOS_VLEN_quad_core, 0) != 0) { // 0 mean quad core + if(read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 mean multi core disable_siblings = 1; } #endif Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/init_cpus.c Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/cpu/amd/model_fxx/init_cpus.c Thu Apr 8 17:06:44 2010 (r5380) @@ -57,7 +57,7 @@ disable_siblings = !CONFIG_LOGICAL_CPUS; #if CONFIG_LOGICAL_CPUS == 1 && CONFIG_HAVE_OPTION_TABLE == 1 - if(read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) != 0) { // 0 mean dual core + if(read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { // 0 mean multi core disable_siblings = 1; } #endif Modified: trunk/src/cpu/amd/quadcore/amd_sibling.c ============================================================================== --- trunk/src/cpu/amd/quadcore/amd_sibling.c Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/cpu/amd/quadcore/amd_sibling.c Thu Apr 8 17:06:44 2010 (r5380) @@ -82,7 +82,7 @@ u32 disable_siblings = !CONFIG_LOGICAL_CPUS; - get_option(&disable_siblings, "quad_core"); + get_option(&disable_siblings, "multi_core"); siblings = get_max_siblings(sysconf.nodes); Modified: trunk/src/cpu/amd/quadcore/quadcore.c ============================================================================== --- trunk/src/cpu/amd/quadcore/quadcore.c Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/cpu/amd/quadcore/quadcore.c Thu Apr 8 17:06:44 2010 (r5380) @@ -86,8 +86,8 @@ u32 nodes; u32 nodeid; - // disable quad_core - if (read_option(CMOS_VSTART_quad_core, CMOS_VLEN_quad_core, 0) != 0) { + // disable multi_core + if (read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) != 0) { printk(BIOS_DEBUG, "Skip additional core init\n"); return; } Modified: trunk/src/mainboard/amd/db800/cmos.layout ============================================================================== --- trunk/src/mainboard/amd/db800/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/amd/db800/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/amd/dbm690t/cmos.layout ============================================================================== --- trunk/src/mainboard/amd/dbm690t/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/amd/dbm690t/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -53,14 +53,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/amd/mahogany/cmos.layout ============================================================================== --- trunk/src/mainboard/amd/mahogany/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/amd/mahogany/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -53,14 +53,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/amd/mahogany_fam10/cmos.layout ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/amd/mahogany_fam10/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 quad_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/amd/norwich/cmos.layout ============================================================================== --- trunk/src/mainboard/amd/norwich/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/amd/norwich/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,8 +35,8 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 1 e 0 dcon_present +432 8 h 0 boot_countdown +440 1 e 0 dcon_present 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/amd/pistachio/cmos.layout ============================================================================== --- trunk/src/mainboard/amd/pistachio/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/amd/pistachio/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -53,14 +53,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/amd/rumba/cmos.layout ============================================================================== --- trunk/src/mainboard/amd/rumba/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/amd/rumba/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/amd/serengeti_cheetah/cmos.layout ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/amd/serengeti_cheetah/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 quad_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/arima/hdama/cmos.layout ============================================================================== --- trunk/src/mainboard/arima/hdama/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/arima/hdama/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/artecgroup/dbe61/cmos.layout ============================================================================== --- trunk/src/mainboard/artecgroup/dbe61/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/artecgroup/dbe61/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/asrock/939a785gmh/cmos.layout ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/asrock/939a785gmh/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -53,14 +53,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/asus/a8n_e/cmos.layout ============================================================================== --- trunk/src/mainboard/asus/a8n_e/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/asus/a8n_e/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -31,7 +31,7 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock - 399 1 e 2 dual_core + 399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first Modified: trunk/src/mainboard/asus/a8v-e_se/cmos.layout ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/asus/a8v-e_se/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,7 +32,7 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first Modified: trunk/src/mainboard/asus/m2v-mx_se/cmos.layout ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/asus/m2v-mx_se/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,7 +32,7 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first Modified: trunk/src/mainboard/asus/mew-vm/cmos.layout ============================================================================== --- trunk/src/mainboard/asus/mew-vm/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/asus/mew-vm/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/bcom/winnetp680/cmos.layout ============================================================================== --- trunk/src/mainboard/bcom/winnetp680/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/bcom/winnetp680/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/broadcom/blast/cmos.layout ============================================================================== --- trunk/src/mainboard/broadcom/blast/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/broadcom/blast/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/dell/s1850/cmos.layout ============================================================================== --- trunk/src/mainboard/dell/s1850/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/dell/s1850/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -36,7 +36,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers Modified: trunk/src/mainboard/digitallogic/adl855pc/cmos.layout ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/digitallogic/adl855pc/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/digitallogic/msm586seg/cmos.layout ============================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/digitallogic/msm586seg/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/digitallogic/msm800sev/cmos.layout ============================================================================== --- trunk/src/mainboard/digitallogic/msm800sev/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/digitallogic/msm800sev/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/eaglelion/5bcm/cmos.layout ============================================================================== --- trunk/src/mainboard/eaglelion/5bcm/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/eaglelion/5bcm/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/emulation/qemu-x86/cmos.layout ============================================================================== --- trunk/src/mainboard/emulation/qemu-x86/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/emulation/qemu-x86/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -53,14 +53,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/gigabyte/m57sli/cmos.layout ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/gigabyte/m57sli/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -53,14 +53,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/hp/dl145_g3/cmos.layout ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/hp/dl145_g3/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/ibm/e325/cmos.layout ============================================================================== --- trunk/src/mainboard/ibm/e325/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/ibm/e325/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/ibm/e326/cmos.layout ============================================================================== --- trunk/src/mainboard/ibm/e326/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/ibm/e326/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/iei/juki-511p/cmos.layout ============================================================================== --- trunk/src/mainboard/iei/juki-511p/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/iei/juki-511p/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/iei/nova4899r/cmos.layout ============================================================================== --- trunk/src/mainboard/iei/nova4899r/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/iei/nova4899r/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/intel/jarrell/cmos.layout ============================================================================== --- trunk/src/mainboard/intel/jarrell/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/intel/jarrell/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -24,7 +24,7 @@ #95 1 r 0 disable_clock_updates #96 288 r 0 temporary_filler 0 376 r 0 reserved_memory -376 1 e 1 power_up_watchdog +376 1 e 1 power_up_watchdog 384 1 e 4 boot_option 385 1 e 4 last_boot 386 1 e 1 ECC_memory @@ -38,7 +38,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers Modified: trunk/src/mainboard/intel/xe7501devkit/cmos.layout ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/intel/xe7501devkit/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -1,16 +1,16 @@ # NOTE: This file must be in UNIX format (not DOS) or build_opt_tbl fails: -# "Error - Name is an invalid identifier in line" +# "Error - Name is an invalid identifier in line" entries #start-bit length config config-ID name -0 512 r 0 reserved_memory1 # We know nothing about the factory BIOS -512 512 r 0 reserved_memory2 # More factory BIOS +0 512 r 0 reserved_memory1 # We know nothing about the factory BIOS +512 512 r 0 reserved_memory2 # More factory BIOS # Work in progress. # This is where we would put the LB RTC_BOOT_BYTE options once the code # supports finding them there. -#1024 1 e 4 boot_option +#1024 1 e 4 boot_option #1025 1 e 4 last_boot #1026 1 e 1 ECC_memory #1028 4 r 0 reboot_bits Modified: trunk/src/mainboard/iwill/dk8_htx/cmos.layout ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/iwill/dk8_htx/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/iwill/dk8s2/cmos.layout ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/iwill/dk8s2/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/iwill/dk8x/cmos.layout ============================================================================== --- trunk/src/mainboard/iwill/dk8x/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/iwill/dk8x/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/jetway/j7f24/cmos.layout ============================================================================== --- trunk/src/mainboard/jetway/j7f24/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/jetway/j7f24/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/kontron/kt690/cmos.layout ============================================================================== --- trunk/src/mainboard/kontron/kt690/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/kontron/kt690/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -53,14 +53,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/lippert/frontrunner/cmos.layout ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/lippert/frontrunner/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/msi/ms7135/cmos.layout ============================================================================== --- trunk/src/mainboard/msi/ms7135/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/msi/ms7135/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/msi/ms7260/cmos.layout ============================================================================== --- trunk/src/mainboard/msi/ms7260/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/msi/ms7260/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -54,14 +54,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/msi/ms9185/cmos.layout ============================================================================== --- trunk/src/mainboard/msi/ms9185/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/msi/ms9185/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,7 +32,7 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first Modified: trunk/src/mainboard/msi/ms9282/cmos.layout ============================================================================== --- trunk/src/mainboard/msi/ms9282/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/msi/ms9282/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,7 +32,7 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first Modified: trunk/src/mainboard/msi/ms9652_fam10/cmos.layout ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/msi/ms9652_fam10/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -53,7 +53,7 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 quad_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first Modified: trunk/src/mainboard/newisys/khepri/cmos.layout ============================================================================== --- trunk/src/mainboard/newisys/khepri/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/newisys/khepri/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/nvidia/l1_2pvv/cmos.layout ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/nvidia/l1_2pvv/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -53,7 +53,7 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first Modified: trunk/src/mainboard/olpc/btest/cmos.layout ============================================================================== --- trunk/src/mainboard/olpc/btest/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/olpc/btest/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,8 +35,8 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 1 e 0 dcon_present +432 8 h 0 boot_countdown +440 1 e 0 dcon_present 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/olpc/rev_a/cmos.layout ============================================================================== --- trunk/src/mainboard/olpc/rev_a/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/olpc/rev_a/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,8 +35,8 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 1 e 0 dcon_present +432 8 h 0 boot_countdown +440 1 e 0 dcon_present 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/pcengines/alix1c/cmos.layout ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/pcengines/alix1c/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/sunw/ultra40/cmos.layout ============================================================================== --- trunk/src/mainboard/sunw/ultra40/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/sunw/ultra40/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/supermicro/h8dme/cmos.layout ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/supermicro/h8dme/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -53,14 +53,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/supermicro/h8dmr/cmos.layout ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/supermicro/h8dmr/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -53,14 +53,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/cmos.layout ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -53,14 +53,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 quad_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/supermicro/h8qme_fam10/cmos.layout ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/supermicro/h8qme_fam10/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -53,14 +53,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 quad_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/supermicro/x6dai_g/cmos.layout ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/supermicro/x6dai_g/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -36,7 +36,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers Modified: trunk/src/mainboard/supermicro/x6dhe_g/cmos.layout ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/supermicro/x6dhe_g/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -36,7 +36,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers Modified: trunk/src/mainboard/supermicro/x6dhe_g2/cmos.layout ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/supermicro/x6dhe_g2/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -36,7 +36,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers Modified: trunk/src/mainboard/supermicro/x6dhr_ig/cmos.layout ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/supermicro/x6dhr_ig/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -36,7 +36,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/cmos.layout ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -36,7 +36,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers Modified: trunk/src/mainboard/technexion/tim5690/cmos.layout ============================================================================== --- trunk/src/mainboard/technexion/tim5690/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/technexion/tim5690/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -53,14 +53,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/technexion/tim8690/cmos.layout ============================================================================== --- trunk/src/mainboard/technexion/tim8690/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/technexion/tim8690/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -53,14 +53,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/technologic/ts5300/cmos.layout ============================================================================== --- trunk/src/mainboard/technologic/ts5300/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/technologic/ts5300/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/tyan/s2735/cmos.layout ============================================================================== --- trunk/src/mainboard/tyan/s2735/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/tyan/s2735/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -38,7 +38,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown #440 4 e 9 slow_cpu 444 1 e 1 nmi 728 256 h 0 user_data Modified: trunk/src/mainboard/tyan/s2850/cmos.layout ============================================================================== --- trunk/src/mainboard/tyan/s2850/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/tyan/s2850/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/tyan/s2875/cmos.layout ============================================================================== --- trunk/src/mainboard/tyan/s2875/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/tyan/s2875/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/tyan/s2880/cmos.layout ============================================================================== --- trunk/src/mainboard/tyan/s2880/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/tyan/s2880/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/tyan/s2881/cmos.layout ============================================================================== --- trunk/src/mainboard/tyan/s2881/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/tyan/s2881/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/tyan/s2882/cmos.layout ============================================================================== --- trunk/src/mainboard/tyan/s2882/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/tyan/s2882/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/tyan/s2885/cmos.layout ============================================================================== --- trunk/src/mainboard/tyan/s2885/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/tyan/s2885/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/tyan/s2891/cmos.layout ============================================================================== --- trunk/src/mainboard/tyan/s2891/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/tyan/s2891/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/tyan/s2892/cmos.layout ============================================================================== --- trunk/src/mainboard/tyan/s2892/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/tyan/s2892/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/tyan/s2895/cmos.layout ============================================================================== --- trunk/src/mainboard/tyan/s2895/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/tyan/s2895/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/tyan/s2912/cmos.layout ============================================================================== --- trunk/src/mainboard/tyan/s2912/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/tyan/s2912/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -53,7 +53,7 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first Modified: trunk/src/mainboard/tyan/s2912_fam10/cmos.layout ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/tyan/s2912_fam10/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -53,7 +53,7 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 quad_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first Modified: trunk/src/mainboard/tyan/s4880/cmos.layout ============================================================================== --- trunk/src/mainboard/tyan/s4880/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/tyan/s4880/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/tyan/s4882/cmos.layout ============================================================================== --- trunk/src/mainboard/tyan/s4882/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/tyan/s4882/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -32,14 +32,14 @@ 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock -399 1 e 2 dual_core +399 1 e 2 multi_core 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 iommu Modified: trunk/src/mainboard/via/epia-cn/cmos.layout ============================================================================== --- trunk/src/mainboard/via/epia-cn/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/via/epia-cn/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/via/epia-m/cmos.layout ============================================================================== --- trunk/src/mainboard/via/epia-m/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/via/epia-m/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/via/epia-m700/cmos.layout ============================================================================== --- trunk/src/mainboard/via/epia-m700/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/via/epia-m700/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/via/epia-n/cmos.layout ============================================================================== --- trunk/src/mainboard/via/epia-n/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/via/epia-n/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/via/epia/cmos.layout ============================================================================== --- trunk/src/mainboard/via/epia/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/via/epia/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/mainboard/winent/pl6064/cmos.layout ============================================================================== --- trunk/src/mainboard/winent/pl6064/cmos.layout Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/mainboard/winent/pl6064/cmos.layout Thu Apr 8 17:06:44 2010 (r5380) @@ -35,7 +35,7 @@ 420 4 e 7 boot_second 424 4 e 7 boot_third 428 4 h 0 boot_index -432 8 h 0 boot_countdown +432 8 h 0 boot_countdown 1008 16 h 0 check_sum enumerations Modified: trunk/src/northbridge/amd/amdfam10/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/northbridge.c Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/northbridge/amd/amdfam10/northbridge.c Thu Apr 8 17:06:44 2010 (r5380) @@ -1234,7 +1234,7 @@ disable_siblings = !CONFIG_LOGICAL_CPUS; #if CONFIG_LOGICAL_CPUS == 1 - get_option(&disable_siblings, "quad_core"); + get_option(&disable_siblings, "multi_core"); #endif // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it Modified: trunk/src/northbridge/amd/amdk8/coherent_ht.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/coherent_ht.c Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/northbridge/amd/amdk8/coherent_ht.c Thu Apr 8 17:06:44 2010 (r5380) @@ -1595,7 +1595,7 @@ unsigned total_cpus; if ((!CONFIG_HAVE_OPTION_TABLE) || - read_option(CMOS_VSTART_dual_core, CMOS_VLEN_dual_core, 0) == 0) { /* dual_core */ + read_option(CMOS_VSTART_multi_core, CMOS_VLEN_multi_core, 0) == 0) { /* multi_core */ total_cpus = verify_dualcore(nodes); } else { Modified: trunk/src/northbridge/amd/amdk8/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/northbridge.c Thu Apr 8 17:02:39 2010 (r5379) +++ trunk/src/northbridge/amd/amdk8/northbridge.c Thu Apr 8 17:06:44 2010 (r5380) @@ -1142,7 +1142,7 @@ disable_siblings = !CONFIG_LOGICAL_CPUS; #if CONFIG_LOGICAL_CPUS == 1 - get_option(&disable_siblings, "dual_core"); + get_option(&disable_siblings, "multi_core"); #endif // for pre_e0, nb_cfg_54 can not be set, ( even set, when you read it still be 0)

1 0

[commit] r5379 - in trunk/src: . northbridge/amd northbridge/amd/amdht
by repository service 08 Apr '10

08 Apr '10

Author: myles Date: Thu Apr 8 17:02:39 2010 New Revision: 5379 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5379 Log: Move Kconfig for HT limits to northbridge/amd/Kconfig. Guard the code with CONFIG_EXPERT to remove warnings. Make it only show up for fam10, since it isn't implemented for K8 yet. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/Kconfig trunk/src/northbridge/amd/Kconfig trunk/src/northbridge/amd/amdht/h3finit.c Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Thu Apr 8 15:16:32 2010 (r5378) +++ trunk/src/Kconfig Thu Apr 8 17:02:39 2010 (r5379) @@ -90,96 +90,6 @@ comment "CPU" source src/cpu/Kconfig comment "Northbridge" - -menu "HyperTransport setup" - depends on (NORTHBRIDGE_AMD_AMDK8 || NORTHBRIDGE_AMD_AMDFAM10) && EXPERT - -choice - prompt "HyperTransport frequency" - default LIMIT_HT_SPEED_AUTO - help - This option sets the maximum permissible HyperTransport link - frequency. - - Use of this option will only limit the autodetected HT frequency. - It will not (and cannot) increase the frequency beyond the - autodetected limits. - - This is primarily used to work around poorly designed or laid out - HT traces on certain motherboards. - -config LIMIT_HT_SPEED_200 - bool "Limit HT frequency to 200MHz" -config LIMIT_HT_SPEED_400 - bool "Limit HT frequency to 400MHz" -config LIMIT_HT_SPEED_600 - bool "Limit HT frequency to 600MHz" -config LIMIT_HT_SPEED_800 - bool "Limit HT frequency to 800MHz" -config LIMIT_HT_SPEED_1000 - bool "Limit HT frequency to 1.0GHz" -config LIMIT_HT_SPEED_1200 - bool "Limit HT frequency to 1.2GHz" -config LIMIT_HT_SPEED_1400 - bool "Limit HT frequency to 1.4GHz" -config LIMIT_HT_SPEED_1600 - bool "Limit HT frequency to 1.6GHz" -config LIMIT_HT_SPEED_1800 - bool "Limit HT frequency to 1.8GHz" -config LIMIT_HT_SPEED_2000 - bool "Limit HT frequency to 2.0GHz" -config LIMIT_HT_SPEED_2200 - bool "Limit HT frequency to 2.2GHz" -config LIMIT_HT_SPEED_2400 - bool "Limit HT frequency to 2.4GHz" -config LIMIT_HT_SPEED_2600 - bool "Limit HT frequency to 2.6GHz" -config LIMIT_HT_SPEED_AUTO - bool "Autodetect HT frequency" -endchoice - -choice - prompt "HyperTransport downlink width" - default LIMIT_HT_DOWN_WIDTH_16 - help - This option sets the maximum permissible HyperTransport - downlink width. - - Use of this option will only limit the autodetected HT width. - It will not (and cannot) increase the width beyond the autodetected - limits. - - This is primarily used to work around poorly designed or laid out HT - traces on certain motherboards. - -config LIMIT_HT_DOWN_WIDTH_8 - bool "8 bits" -config LIMIT_HT_DOWN_WIDTH_16 - bool "16 bits" -endchoice - -choice - prompt "HyperTransport uplink width" - default LIMIT_HT_UP_WIDTH_16 - help - This option sets the maximum permissible HyperTransport - uplink width. - - Use of this option will only limit the autodetected HT width. - It will not (and cannot) increase the width beyond the autodetected - limits. - - This is primarily used to work around poorly designed or laid out HT - traces on certain motherboards. - -config LIMIT_HT_UP_WIDTH_8 - bool "8 bits" -config LIMIT_HT_UP_WIDTH_16 - bool "16 bits" -endchoice - -endmenu - source src/northbridge/Kconfig comment "Southbridge" source src/southbridge/Kconfig Modified: trunk/src/northbridge/amd/Kconfig ============================================================================== --- trunk/src/northbridge/amd/Kconfig Thu Apr 8 15:16:32 2010 (r5378) +++ trunk/src/northbridge/amd/Kconfig Thu Apr 8 17:02:39 2010 (r5379) @@ -3,3 +3,92 @@ source src/northbridge/amd/gx2/Kconfig source src/northbridge/amd/amdfam10/Kconfig source src/northbridge/amd/lx/Kconfig +menu "HyperTransport setup" + #could be implemented for K8 (NORTHBRIDGE_AMD_AMDK8) + depends on (NORTHBRIDGE_AMD_AMDFAM10) && EXPERT + +choice + prompt "HyperTransport frequency" + default LIMIT_HT_SPEED_AUTO + help + This option sets the maximum permissible HyperTransport link + frequency. + + Use of this option will only limit the autodetected HT frequency. + It will not (and cannot) increase the frequency beyond the + autodetected limits. + + This is primarily used to work around poorly designed or laid out + HT traces on certain motherboards. + +config LIMIT_HT_SPEED_200 + bool "Limit HT frequency to 200MHz" +config LIMIT_HT_SPEED_400 + bool "Limit HT frequency to 400MHz" +config LIMIT_HT_SPEED_600 + bool "Limit HT frequency to 600MHz" +config LIMIT_HT_SPEED_800 + bool "Limit HT frequency to 800MHz" +config LIMIT_HT_SPEED_1000 + bool "Limit HT frequency to 1.0GHz" +config LIMIT_HT_SPEED_1200 + bool "Limit HT frequency to 1.2GHz" +config LIMIT_HT_SPEED_1400 + bool "Limit HT frequency to 1.4GHz" +config LIMIT_HT_SPEED_1600 + bool "Limit HT frequency to 1.6GHz" +config LIMIT_HT_SPEED_1800 + bool "Limit HT frequency to 1.8GHz" +config LIMIT_HT_SPEED_2000 + bool "Limit HT frequency to 2.0GHz" +config LIMIT_HT_SPEED_2200 + bool "Limit HT frequency to 2.2GHz" +config LIMIT_HT_SPEED_2400 + bool "Limit HT frequency to 2.4GHz" +config LIMIT_HT_SPEED_2600 + bool "Limit HT frequency to 2.6GHz" +config LIMIT_HT_SPEED_AUTO + bool "Autodetect HT frequency" +endchoice + +choice + prompt "HyperTransport downlink width" + default LIMIT_HT_DOWN_WIDTH_16 + help + This option sets the maximum permissible HyperTransport + downlink width. + + Use of this option will only limit the autodetected HT width. + It will not (and cannot) increase the width beyond the autodetected + limits. + + This is primarily used to work around poorly designed or laid out HT + traces on certain motherboards. + +config LIMIT_HT_DOWN_WIDTH_8 + bool "8 bits" +config LIMIT_HT_DOWN_WIDTH_16 + bool "16 bits" +endchoice + +choice + prompt "HyperTransport uplink width" + default LIMIT_HT_UP_WIDTH_16 + help + This option sets the maximum permissible HyperTransport + uplink width. + + Use of this option will only limit the autodetected HT width. + It will not (and cannot) increase the width beyond the autodetected + limits. + + This is primarily used to work around poorly designed or laid out HT + traces on certain motherboards. + +config LIMIT_HT_UP_WIDTH_8 + bool "8 bits" +config LIMIT_HT_UP_WIDTH_16 + bool "16 bits" +endchoice + +endmenu Modified: trunk/src/northbridge/amd/amdht/h3finit.c ============================================================================== --- trunk/src/northbridge/amd/amdht/h3finit.c Thu Apr 8 15:16:32 2010 (r5378) +++ trunk/src/northbridge/amd/amdht/h3finit.c Thu Apr 8 17:02:39 2010 (r5379) @@ -1327,47 +1327,47 @@ for (i = 0; i < pDat->TotalLinks*2; i += 2) { -#if CONFIG_LIMIT_HT_SPEED_200 +#if CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_200 cbPCBFreqLimit = 0x0001; -#elif CONFIG_LIMIT_HT_SPEED_300 +#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_300 cbPCBFreqLimit = 0x0003; -#elif CONFIG_LIMIT_HT_SPEED_400 +#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_400 cbPCBFreqLimit = 0x0007; -#elif CONFIG_LIMIT_HT_SPEED_500 +#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_500 cbPCBFreqLimit = 0x000F; -#elif CONFIG_LIMIT_HT_SPEED_600 +#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_600 cbPCBFreqLimit = 0x001F; -#elif CONFIG_LIMIT_HT_SPEED_800 +#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_800 cbPCBFreqLimit = 0x003F; -#elif CONFIG_LIMIT_HT_SPEED_1000 +#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_1000 cbPCBFreqLimit = 0x007F; -#elif CONFIG_LIMIT_HT_SPEED_1200 +#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_1200 cbPCBFreqLimit = 0x00FF; -#elif CONFIG_LIMIT_HT_SPEED_1400 +#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_1400 cbPCBFreqLimit = 0x01FF; -#elif CONFIG_LIMIT_HT_SPEED_1600 +#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_1600 cbPCBFreqLimit = 0x03FF; -#elif CONFIG_LIMIT_HT_SPEED_1800 +#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_1800 cbPCBFreqLimit = 0x07FF; -#elif CONFIG_LIMIT_HT_SPEED_2000 +#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_2000 cbPCBFreqLimit = 0x0FFF; -#elif CONFIG_LIMIT_HT_SPEED_2200 +#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_2200 cbPCBFreqLimit = 0x1FFF; -#elif CONFIG_LIMIT_HT_SPEED_2400 +#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_2400 cbPCBFreqLimit = 0x3FFF; -#elif CONFIG_LIMIT_HT_SPEED_2600 +#elif CONFIG_EXPERT && CONFIG_LIMIT_HT_SPEED_2600 cbPCBFreqLimit = 0x7FFF; #else cbPCBFreqLimit = 0xFFFF; // Maximum allowed by autoconfiguration #endif -#if CONFIG_LIMIT_HT_DOWN_WIDTH_8 +#if CONFIG_EXPERT && CONFIG_LIMIT_HT_DOWN_WIDTH_8 cbPCBABDownstreamWidth = 8; #else cbPCBABDownstreamWidth = 16; #endif -#if CONFIG_LIMIT_HT_UP_WIDTH_8 +#if CONFIG_EXPERT && CONFIG_LIMIT_HT_UP_WIDTH_8 cbPCBBAUpstreamWidth = 8; #else cbPCBBAUpstreamWidth = 16;

1 0

build service results for r5378
by coreboot information 08 Apr '10

08 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5378 to the coreboot repository. This caused the following changes: Change Log: output cosmetics Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:norwich has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

build service results for r5377
by coreboot information 08 Apr '10

08 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 5377 to the coreboot repository. This caused the following changes: Change Log: Remove #line statements in processed parser source, to avoid clutter in revision history. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Build Log: Compilation of amd:norwich has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5377&device=norwich&vendor… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5378 - in trunk: . util/sconfig
by repository service 08 Apr '10

08 Apr '10

Author: stepan Date: Thu Apr 8 15:16:32 2010 New Revision: 5378 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5378 Log: output cosmetics Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/Makefile trunk/util/sconfig/Makefile.inc Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Thu Apr 8 14:59:41 2010 (r5377) +++ trunk/Makefile Thu Apr 8 15:16:32 2010 (r5378) @@ -150,6 +150,7 @@ # needed objects that every mainboard uses # Creation of these is architecture and mainboard independent $(obj)/mainboard/$(MAINBOARDDIR)/static.c: $(src)/mainboard/$(MAINBOARDDIR)/devicetree.cb $(obj)/util/sconfig/sconfig + @printf " SCONFIG $(subst $(src)/,,$(<))\n" mkdir -p $(obj)/mainboard/$(MAINBOARDDIR) $(obj)/util/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR) Modified: trunk/util/sconfig/Makefile.inc ============================================================================== --- trunk/util/sconfig/Makefile.inc Thu Apr 8 14:59:41 2010 (r5377) +++ trunk/util/sconfig/Makefile.inc Thu Apr 8 15:16:32 2010 (r5378) @@ -27,5 +27,5 @@ cp $< $@ $(obj)/util/sconfig/sconfig: $(obj)/util/sconfig $(addprefix $(obj)/util/sconfig/,$(sconfigobj)) - printf " HOSTCXX $(subst $(obj)/,,$(@)) (link)\n" - $(HOSTCXX) $(SCONFIGFLAGS) -o $@ $(addprefix $(obj)/util/sconfig/,$(sconfigobj)) + printf " HOSTCC $(subst $(obj)/,,$(@)) (link)\n" + $(HOSTCC) $(SCONFIGFLAGS) -o $@ $(addprefix $(obj)/util/sconfig/,$(sconfigobj))

1 0

[commit] r5377 - trunk/util/sconfig
by repository service 08 Apr '10

08 Apr '10

Author: oxygene Date: Thu Apr 8 14:59:41 2010 New Revision: 5377 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5377 Log: Remove #line statements in processed parser source, to avoid clutter in revision history. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/util/sconfig/Makefile.inc trunk/util/sconfig/lex.yy.c_shipped trunk/util/sconfig/sconfig.tab.c_shipped trunk/util/sconfig/sconfig.tab.h_shipped Modified: trunk/util/sconfig/Makefile.inc ============================================================================== --- trunk/util/sconfig/Makefile.inc Thu Apr 8 14:47:35 2010 (r5376) +++ trunk/util/sconfig/Makefile.inc Thu Apr 8 14:59:41 2010 (r5377) @@ -11,12 +11,12 @@ ifdef SCONFIG_GENPARSER $(top)/util/sconfig/lex.yy.c_shipped: $(top)/util/sconfig/sconfig.l - flex -o $@ $< + flex -L -o $@ $< # the .c rule also creates .h $(top)/util/sconfig/sconfig.tab.h_shipped: $(top)/util/sconfig/sconfig.tab.c_shipped $(top)/util/sconfig/sconfig.tab.c_shipped: $(top)/util/sconfig/sconfig.y - bison --defines=$(top)/util/sconfig/sconfig.tab.h_shipped -o $@ $< + bison -l --defines=$(top)/util/sconfig/sconfig.tab.h_shipped -o $@ $< endif Modified: trunk/util/sconfig/lex.yy.c_shipped ============================================================================== --- trunk/util/sconfig/lex.yy.c_shipped Thu Apr 8 14:47:35 2010 (r5376) +++ trunk/util/sconfig/lex.yy.c_shipped Thu Apr 8 14:59:41 2010 (r5377) @@ -1,6 +1,5 @@ -#line 2 "/home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped" -#line 4 "/home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped" +#line 3 "/home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped" #define YY_INT_ALIGNED short int @@ -508,8 +507,6 @@ #define YY_MORE_ADJ 0 #define YY_RESTORE_YY_MORE_OFFSET char *yytext; -#line 1 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" -#line 2 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" /* * sconfig, coreboot device tree compiler * @@ -533,7 +530,6 @@ #include "sconfig.tab.h" int linenum = 0; -#line 537 "/home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped" #define INITIAL 0 @@ -715,10 +711,6 @@ register char *yy_cp, *yy_bp; register int yy_act; -#line 27 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" - -#line 721 "/home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped" - if ( !(yy_init) ) { (yy_init) = 1; @@ -802,133 +794,107 @@ case 1: YY_RULE_SETUP -#line 28 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {} YY_BREAK case 2: /* rule 2 can match eol */ YY_RULE_SETUP -#line 29 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {linenum++;} YY_BREAK case 3: /* rule 3 can match eol */ YY_RULE_SETUP -#line 30 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {linenum++;} YY_BREAK case 4: YY_RULE_SETUP -#line 31 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {return(CHIP);} YY_BREAK case 5: YY_RULE_SETUP -#line 32 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {return(DEVICE);} YY_BREAK case 6: YY_RULE_SETUP -#line 33 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {return(REGISTER);} YY_BREAK case 7: YY_RULE_SETUP -#line 34 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {yylval.number=1; return(BOOL);} YY_BREAK case 8: YY_RULE_SETUP -#line 35 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {yylval.number=0; return(BOOL);} YY_BREAK case 9: YY_RULE_SETUP -#line 36 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {yylval.number=PCI; return(BUS);} YY_BREAK case 10: YY_RULE_SETUP -#line 37 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {yylval.number=PNP; return(BUS);} YY_BREAK case 11: YY_RULE_SETUP -#line 38 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {yylval.number=I2C; return(BUS);} YY_BREAK case 12: YY_RULE_SETUP -#line 39 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {yylval.number=APIC; return(BUS);} YY_BREAK case 13: YY_RULE_SETUP -#line 40 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {yylval.number=APIC_CLUSTER; return(BUS);} YY_BREAK case 14: YY_RULE_SETUP -#line 41 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {yylval.number=PCI_DOMAIN; return(BUS);} YY_BREAK case 15: YY_RULE_SETUP -#line 42 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {yylval.number=IRQ; return(RESOURCE);} YY_BREAK case 16: YY_RULE_SETUP -#line 43 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {yylval.number=DRQ; return(RESOURCE);} YY_BREAK case 17: YY_RULE_SETUP -#line 44 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {yylval.number=IO; return(RESOURCE);} YY_BREAK case 18: YY_RULE_SETUP -#line 45 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {return(END);} YY_BREAK case 19: YY_RULE_SETUP -#line 46 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {return(EQUALS);} YY_BREAK case 20: YY_RULE_SETUP -#line 47 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 21: YY_RULE_SETUP -#line 48 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 22: YY_RULE_SETUP -#line 49 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 23: /* rule 23 can match eol */ YY_RULE_SETUP -#line 50 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} YY_BREAK case 24: YY_RULE_SETUP -#line 51 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" {yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} YY_BREAK case 25: YY_RULE_SETUP -#line 52 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" ECHO; YY_BREAK -#line 932 "/home/Patrick/work/coreboot/util/sconfig/lex.yy.c_shipped" case YY_STATE_EOF(INITIAL): yyterminate(); @@ -1926,7 +1892,3 @@ #define YYTABLES_NAME "yytables" -#line 52 "/home/Patrick/work/coreboot/util/sconfig/sconfig.l" - - - Modified: trunk/util/sconfig/sconfig.tab.c_shipped ============================================================================== --- trunk/util/sconfig/sconfig.tab.c_shipped Thu Apr 8 14:47:35 2010 (r5376) +++ trunk/util/sconfig/sconfig.tab.c_shipped Thu Apr 8 14:59:41 2010 (r5377) @@ -67,8 +67,6 @@ /* Copy the first part of user declarations. */ -/* Line 189 of yacc.c */ -#line 1 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" /* * sconfig, coreboot device tree compiler @@ -194,8 +192,6 @@ } -/* Line 189 of yacc.c */ -#line 199 "/home/Patrick/work/coreboot/util/sconfig/sconfig.tab.c_shipped" /* Enabling traces. */ #ifndef YYDEBUG @@ -251,8 +247,6 @@ typedef union YYSTYPE { -/* Line 214 of yacc.c */ -#line 125 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" struct device *device; char *string; @@ -260,8 +254,6 @@ -/* Line 214 of yacc.c */ -#line 265 "/home/Patrick/work/coreboot/util/sconfig/sconfig.tab.c_shipped" } YYSTYPE; # define YYSTYPE_IS_TRIVIAL 1 # define yystype YYSTYPE /* obsolescent; will be withdrawn */ @@ -272,8 +264,6 @@ /* Copy the second part of user declarations. */ -/* Line 264 of yacc.c */ -#line 277 "/home/Patrick/work/coreboot/util/sconfig/sconfig.tab.c_shipped" #ifdef short # undef short @@ -1476,8 +1466,6 @@ { case 2: -/* Line 1455 of yacc.c */ -#line 132 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" { root.next_sibling = root.children; root.next_sibling->next_sibling = root.next_sibling->children; @@ -1501,8 +1489,6 @@ case 11: -/* Line 1455 of yacc.c */ -#line 158 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" { (yyval.device) = new_dev(); (yyval.device)->chiph_exists = 1; @@ -1536,8 +1522,6 @@ case 12: -/* Line 1455 of yacc.c */ -#line 187 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" { cur_parent = (yyvsp[(3) - (5)].device)->parent; @@ -1569,8 +1553,6 @@ case 13: -/* Line 1455 of yacc.c */ -#line 215 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" { (yyval.device) = new_dev(); (yyval.device)->bustype = (yyvsp[(2) - (4)].number); @@ -1625,8 +1607,6 @@ case 14: -/* Line 1455 of yacc.c */ -#line 265 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" { cur_parent = (yyvsp[(5) - (7)].device)->parent; cur_bus = (yyvsp[(5) - (7)].device)->bus; @@ -1659,8 +1639,6 @@ case 15: -/* Line 1455 of yacc.c */ -#line 295 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" { struct resource *r = malloc(sizeof(struct resource)); memset (r, 0, sizeof(struct resource)); @@ -1680,8 +1658,6 @@ case 16: -/* Line 1455 of yacc.c */ -#line 313 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" { struct reg *r = malloc(sizeof(struct reg)); memset (r, 0, sizeof(struct reg)); @@ -1711,8 +1687,6 @@ -/* Line 1455 of yacc.c */ -#line 1716 "/home/Patrick/work/coreboot/util/sconfig/sconfig.tab.c_shipped" default: break; } YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc); @@ -1923,8 +1897,6 @@ -/* Line 1675 of yacc.c */ -#line 340 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" void pass0(FILE *fil, struct device *ptr) { if ((ptr->type == device) && (ptr->id != 0) && (!ptr->used)) Modified: trunk/util/sconfig/sconfig.tab.h_shipped ============================================================================== --- trunk/util/sconfig/sconfig.tab.h_shipped Thu Apr 8 14:47:35 2010 (r5376) +++ trunk/util/sconfig/sconfig.tab.h_shipped Thu Apr 8 14:59:41 2010 (r5377) @@ -68,8 +68,6 @@ typedef union YYSTYPE { -/* Line 1676 of yacc.c */ -#line 125 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" struct device *device; char *string; @@ -77,8 +75,6 @@ -/* Line 1676 of yacc.c */ -#line 82 "/home/Patrick/work/coreboot/util/sconfig/sconfig.tab.h_shipped" } YYSTYPE; # define YYSTYPE_IS_TRIVIAL 1 # define yystype YYSTYPE /* obsolescent; will be withdrawn */

1 0

[commit] r5376 - trunk/src/mainboard/emulation/qemu-x86
by repository service 08 Apr '10

08 Apr '10

Author: oxygene Date: Thu Apr 8 14:47:35 2010 New Revision: 5376 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5376 Log: cpu/emulation/qemu-x86 doesn't exist anymore, as this is folded into mainboard/emulation/qemu-x86. Adapt code. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/emulation/qemu-x86/chip.h trunk/src/mainboard/emulation/qemu-x86/devicetree.cb trunk/src/mainboard/emulation/qemu-x86/northbridge.c Modified: trunk/src/mainboard/emulation/qemu-x86/chip.h ============================================================================== --- trunk/src/mainboard/emulation/qemu-x86/chip.h Thu Apr 8 14:46:18 2010 (r5375) +++ trunk/src/mainboard/emulation/qemu-x86/chip.h Thu Apr 8 14:47:35 2010 (r5376) @@ -3,9 +3,9 @@ struct mainboard_config { }; -struct cpu_emulation_qemu_x86_config +struct mainboard_emulation_qemu_x86_config { }; -extern struct chip_operations cpu_emulation_qemu_x86_ops; +extern struct chip_operations mainboard_emulation_qemu_x86_ops; Modified: trunk/src/mainboard/emulation/qemu-x86/devicetree.cb ============================================================================== --- trunk/src/mainboard/emulation/qemu-x86/devicetree.cb Thu Apr 8 14:46:18 2010 (r5375) +++ trunk/src/mainboard/emulation/qemu-x86/devicetree.cb Thu Apr 8 14:47:35 2010 (r5376) @@ -1,4 +1,4 @@ -chip cpu/emulation/qemu-x86 +chip mainboard/emulation/qemu-x86 device pci_domain 0 on device pci 0.0 on end Modified: trunk/src/mainboard/emulation/qemu-x86/northbridge.c ============================================================================== --- trunk/src/mainboard/emulation/qemu-x86/northbridge.c Thu Apr 8 14:46:18 2010 (r5375) +++ trunk/src/mainboard/emulation/qemu-x86/northbridge.c Thu Apr 8 14:47:35 2010 (r5376) @@ -152,7 +152,7 @@ } } -struct chip_operations cpu_emulation_qemu_x86_ops = { +struct chip_operations mainboard_emulation_qemu_x86_ops = { CHIP_NAME("QEMU Northbridge") .enable_dev = enable_dev, };

1 0

[commit] r5375 - trunk/util/sconfig
by repository service 08 Apr '10

08 Apr '10

Author: oxygene Date: Thu Apr 8 14:46:18 2010 New Revision: 5375 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5375 Log: sconfig: Mangle - to _ for struct names, too. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/util/sconfig/sconfig.tab.c_shipped trunk/util/sconfig/sconfig.y Modified: trunk/util/sconfig/sconfig.tab.c_shipped ============================================================================== --- trunk/util/sconfig/sconfig.tab.c_shipped Thu Apr 8 14:00:35 2010 (r5374) +++ trunk/util/sconfig/sconfig.tab.c_shipped Thu Apr 8 14:46:18 2010 (r5375) @@ -562,7 +562,7 @@ static const yytype_uint16 yyrline[] = { 0, 132, 132, 152, 152, 154, 154, 154, 156, 156, - 156, 158, 158, 214, 214, 293, 311 + 156, 158, 158, 215, 215, 294, 312 }; #endif @@ -1511,6 +1511,7 @@ char *c; for (c = (yyval.device)->name_underscore; *c; c++) { if (*c == '/') *c = '_'; + if (*c == '-') *c = '_'; } (yyval.device)->type = chip; (yyval.device)->chip = (yyval.device); @@ -1536,7 +1537,7 @@ case 12: /* Line 1455 of yacc.c */ -#line 186 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" +#line 187 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" { cur_parent = (yyvsp[(3) - (5)].device)->parent; @@ -1569,7 +1570,7 @@ case 13: /* Line 1455 of yacc.c */ -#line 214 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" +#line 215 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" { (yyval.device) = new_dev(); (yyval.device)->bustype = (yyvsp[(2) - (4)].number); @@ -1625,7 +1626,7 @@ case 14: /* Line 1455 of yacc.c */ -#line 264 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" +#line 265 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" { cur_parent = (yyvsp[(5) - (7)].device)->parent; cur_bus = (yyvsp[(5) - (7)].device)->bus; @@ -1659,7 +1660,7 @@ case 15: /* Line 1455 of yacc.c */ -#line 294 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" +#line 295 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" { struct resource *r = malloc(sizeof(struct resource)); memset (r, 0, sizeof(struct resource)); @@ -1680,7 +1681,7 @@ case 16: /* Line 1455 of yacc.c */ -#line 312 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" +#line 313 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" { struct reg *r = malloc(sizeof(struct reg)); memset (r, 0, sizeof(struct reg)); @@ -1711,7 +1712,7 @@ /* Line 1455 of yacc.c */ -#line 1715 "/home/Patrick/work/coreboot/util/sconfig/sconfig.tab.c_shipped" +#line 1716 "/home/Patrick/work/coreboot/util/sconfig/sconfig.tab.c_shipped" default: break; } YY_SYMBOL_PRINT ("-> $$ =", yyr1[yyn], &yyval, &yyloc); @@ -1923,7 +1924,7 @@ /* Line 1675 of yacc.c */ -#line 339 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" +#line 340 "/home/Patrick/work/coreboot/util/sconfig/sconfig.y" void pass0(FILE *fil, struct device *ptr) { if ((ptr->type == device) && (ptr->id != 0) && (!ptr->used)) Modified: trunk/util/sconfig/sconfig.y ============================================================================== --- trunk/util/sconfig/sconfig.y Thu Apr 8 14:00:35 2010 (r5374) +++ trunk/util/sconfig/sconfig.y Thu Apr 8 14:46:18 2010 (r5375) @@ -163,6 +163,7 @@ char *c; for (c = $<device>$->name_underscore; *c; c++) { if (*c == '/') *c = '_'; + if (*c == '-') *c = '_'; } $<device>$->type = chip; $<device>$->chip = $<device>$;

1 0

← Newer
1
...
31
32
33
34
35
36
37
...
41
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot April 2010