coreboot April 2010

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build service results for r5398
by coreboot information 09 Apr '10

09 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5398 to the coreboot repository. This caused the following changes: Change Log: zero warning days. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of asus:a8v-e_se has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r5397
by coreboot information 09 Apr '10

09 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5397 to the coreboot repository. This caused the following changes: Change Log: fix the broken nvidia chipset boards, remove more warnings. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of asus:a8n_e has been fixed Compilation of asus:a8v-e_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5397&device=a8v-e_se&vendo… Compilation of tyan:s2891 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5398 - in trunk/src/mainboard: asus/a8v-e_se tyan/s2891
by repository service 09 Apr '10

09 Apr '10

Author: stepan Date: Fri Apr 9 17:39:21 2010 New Revision: 5398 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5398 Log: zero warning days. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/tyan/s2891/romstage.c Modified: trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c Fri Apr 9 17:29:13 2010 (r5397) +++ trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c Fri Apr 9 17:39:21 2010 (r5398) @@ -86,6 +86,7 @@ acpi_rsdp_t *rsdp; acpi_srat_t *srat; acpi_rsdt_t *rsdt; + acpi_madt_t *madt; acpi_mcfg_t *mcfg; acpi_fadt_t *fadt; acpi_facs_t *facs; Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Fri Apr 9 17:29:13 2010 (r5397) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Fri Apr 9 17:39:21 2010 (r5398) @@ -117,11 +117,6 @@ #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/resourcemap.c" -void hard_reset(void) -{ - print_info("NO HARD RESET. FIX ME!\n"); -} - unsigned int get_sbdn(unsigned bus) { device_t dev; Modified: trunk/src/mainboard/tyan/s2891/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/romstage.c Fri Apr 9 17:29:13 2010 (r5397) +++ trunk/src/mainboard/tyan/s2891/romstage.c Fri Apr 9 17:39:21 2010 (r5398) @@ -79,8 +79,6 @@ static void sio_setup(void) { - - unsigned value; uint32_t dword; uint8_t byte; @@ -102,9 +100,7 @@ dword = pci_read_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa4, dword); - #endif - } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)

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[commit] r5397 - in trunk/src: arch/i386/include/arch mainboard/asus/a8v-e_se mainboard/asus/m2v-mx_se mainboard/broadcom/blast northbridge/amd/amdk8 southbridge/broadcom/bcm5785 southbridge/intel/...
by repository service 09 Apr '10

09 Apr '10

Author: stepan Date: Fri Apr 9 17:29:13 2010 New Revision: 5397 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5397 Log: fix the broken nvidia chipset boards, remove more warnings. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/arch/i386/include/arch/stages.h trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c trunk/src/mainboard/asus/a8v-e_se/mptable.c trunk/src/mainboard/asus/m2v-mx_se/mainboard.c trunk/src/mainboard/broadcom/blast/mptable.c trunk/src/mainboard/broadcom/blast/romstage.c trunk/src/northbridge/amd/amdk8/setup_resource_map.c trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h Modified: trunk/src/arch/i386/include/arch/stages.h ============================================================================== --- trunk/src/arch/i386/include/arch/stages.h Fri Apr 9 16:46:51 2010 (r5396) +++ trunk/src/arch/i386/include/arch/stages.h Fri Apr 9 17:29:13 2010 (r5397) @@ -1,5 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __ARCH_STAGES_H +#define __ARCH_STAGES_H void cbfs_and_run_core(const char *filename, unsigned int ebp); void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset); void __attribute__((regparm(0))) copy_and_run_ap_code_in_car(unsigned ret_addr); - - +#endif Modified: trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c Fri Apr 9 16:46:51 2010 (r5396) +++ trunk/src/mainboard/asus/a8v-e_se/acpi_tables.c Fri Apr 9 17:29:13 2010 (r5397) @@ -87,8 +87,6 @@ acpi_srat_t *srat; acpi_rsdt_t *rsdt; acpi_mcfg_t *mcfg; - acpi_hpet_t *hpet; - acpi_madt_t *madt; acpi_fadt_t *fadt; acpi_facs_t *facs; acpi_header_t *dsdt; Modified: trunk/src/mainboard/asus/a8v-e_se/mptable.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/mptable.c Fri Apr 9 16:46:51 2010 (r5396) +++ trunk/src/mainboard/asus/a8v-e_se/mptable.c Fri Apr 9 17:29:13 2010 (r5397) @@ -29,7 +29,6 @@ static const char oem[8] = "LNXB "; static const char productid[12] = "A8V-E SE "; struct mp_config_table *mc; - unsigned int conforms = 0; int bus_isa = 42; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); Modified: trunk/src/mainboard/asus/m2v-mx_se/mainboard.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/mainboard.c Fri Apr 9 16:46:51 2010 (r5396) +++ trunk/src/mainboard/asus/m2v-mx_se/mainboard.c Fri Apr 9 17:29:13 2010 (r5397) @@ -21,8 +21,9 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <boot/tables.h> +#include <arch/coreboot_tables.h> #include "chip.h" -#include <../../../southbridge/via/k8t890/k8t890.h> +#include <southbridge/via/k8t890/k8t890.h> int add_mainboard_resources(struct lb_memory *mem) { Modified: trunk/src/mainboard/broadcom/blast/mptable.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/mptable.c Fri Apr 9 16:46:51 2010 (r5396) +++ trunk/src/mainboard/broadcom/blast/mptable.c Fri Apr 9 17:29:13 2010 (r5397) @@ -62,7 +62,6 @@ /*I/O APICs: APIC ID Version State Address*/ { device_t dev = 0; - int i; struct resource *res; for(i=0; i<3; i++) { dev = dev_find_device(0x1166, 0x0235, dev); Modified: trunk/src/mainboard/broadcom/blast/romstage.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/romstage.c Fri Apr 9 16:46:51 2010 (r5396) +++ trunk/src/mainboard/broadcom/blast/romstage.c Fri Apr 9 17:29:13 2010 (r5397) @@ -50,10 +50,10 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x71 - int ret,i; unsigned device=(ctrl->channel0[0])>>8; smbus_send_byte(SMBUS_HUB, device); } + #if 0 static inline void change_i2c_mux(unsigned device) { @@ -99,10 +99,8 @@ static const uint16_t spd_addr[] = { RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 RC1|DIMM0, RC1|DIMM2, 0, 0, RC1|DIMM1, RC1|DIMM3, 0, 0, -#endif }; int needs_reset; Modified: trunk/src/northbridge/amd/amdk8/setup_resource_map.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/setup_resource_map.c Fri Apr 9 16:46:51 2010 (r5396) +++ trunk/src/northbridge/amd/amdk8/setup_resource_map.c Fri Apr 9 17:29:13 2010 (r5397) @@ -112,7 +112,7 @@ #endif } -#if defined(SOUTHBRIDGE_NVIDIA_MCP55) || defined(SOUTHBRIDGE_NVIDIA_CK804) +#if defined(CONFIG_SOUTHBRIDGE_NVIDIA_MCP55) || defined(CONFIG_SOUTHBRIDGE_NVIDIA_CK804) static void setup_resource_map_x(const unsigned int *register_values, int max) { int i; Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c Fri Apr 9 16:46:51 2010 (r5396) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_setup.c Fri Apr 9 17:29:13 2010 (r5397) @@ -3,6 +3,7 @@ * by yinghai.lu(a)amd.com */ +#include <reset.h> static void bcm5785_enable_rom(void) { unsigned char byte; Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h ============================================================================== --- trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h Fri Apr 9 16:46:51 2010 (r5396) +++ trunk/src/southbridge/intel/i82801ax/i82801ax_smbus.h Fri Apr 9 17:29:13 2010 (r5397) @@ -110,24 +110,21 @@ return byte; } -/* This function is neither used nor tested by me (Corey Osgood), the author -(Yinghai) probably tested/used it on i82801er */ static int do_smbus_write_block(unsigned device, unsigned length, unsigned cmd, unsigned data1, unsigned data2) { -#warning "do_smbus_write_block is commented out" - print_err("Untested smbus_write_block called\n"); -#if 0 unsigned char global_control_register; unsigned char global_status_register; unsigned char byte; unsigned char stat; int i; + print_err("Untested smbus_write_block called\n"); + /* Clear the PM timeout flags, SECOND_TO_STS */ - outw(inw(0x0400 + 0x66), 0x0400 + 0x66); + outw(inw(PMBASE_ADDR + 0x66), PMBASE_ADDR + 0x66); - if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { + if (smbus_wait_until_ready() < 0) { return -2; } @@ -159,9 +156,8 @@ SMBUS_IO_BASE + SMBHSTCTL); for (i = 0; i < length; i++) { - /* Poll for transaction completion */ - if (smbus_wait_until_blk_done(SMBUS_IO_BASE) < 0) { + if (smbus_wait_until_blk_done() < 0) { return -3; } @@ -179,5 +175,4 @@ print_debug("SMBUS Block complete\n"); return 0; -#endif }

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build service results for r5396
by coreboot information 09 Apr '10

09 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5396 to the coreboot repository. This caused the following changes: Change Log: zero warnings days. The tyan s2895 is down to 3 warnings, 2 of which are caused by #warning. The 1000 ways of how the AMD code waits for the cores to be started up are a real pain for the brain. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of asus:a8n_e has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5396&device=a8n_e&vendor=a… Compilation of asus:a8v-e_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5396&device=a8v-e_se&vendo… Compilation of tyan:s2891 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5396&device=s2891&vendor=t… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5396 - in trunk/src: cpu/x86/mtrr mainboard/tyan/s2895 northbridge/amd/amdk8 southbridge/nvidia/ck804 superio/smsc/lpc47b397
by repository service 09 Apr '10

09 Apr '10

Author: stepan Date: Fri Apr 9 16:46:51 2010 New Revision: 5396 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5396 Log: zero warnings days. The tyan s2895 is down to 3 warnings, 2 of which are caused by #warning. The 1000 ways of how the AMD code waits for the cores to be started up are a real pain for the brain. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c trunk/src/mainboard/tyan/s2895/romstage.c trunk/src/northbridge/amd/amdk8/debug.c trunk/src/northbridge/amd/amdk8/incoherent_ht.c trunk/src/northbridge/amd/amdk8/northbridge.c trunk/src/northbridge/amd/amdk8/raminit.c trunk/src/northbridge/amd/amdk8/raminit.h trunk/src/northbridge/amd/amdk8/setup_resource_map.c trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c trunk/src/southbridge/nvidia/ck804/ck804_smbus.h trunk/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c ============================================================================== --- trunk/src/cpu/x86/mtrr/earlymtrr.c Fri Apr 9 15:49:48 2010 (r5395) +++ trunk/src/cpu/x86/mtrr/earlymtrr.c Fri Apr 9 16:46:51 2010 (r5396) @@ -97,7 +97,7 @@ } -static void early_mtrr_init(void) +static inline void early_mtrr_init(void) { static const unsigned long mtrr_msrs[] = { /* fixed mtrr */ Modified: trunk/src/mainboard/tyan/s2895/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/romstage.c Fri Apr 9 15:49:48 2010 (r5395) +++ trunk/src/mainboard/tyan/s2895/romstage.c Fri Apr 9 16:46:51 2010 (r5396) @@ -15,35 +15,26 @@ #include <cpu/x86/lapic.h> #include "option_table.h" #include "pc80/mc146818rtc_early.c" - #include "pc80/serial.c" #include "console/console.c" #include "lib/ramtest.c" - #include <cpu/amd/model_fxx_rev.h> - #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c" #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c" #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT) - #define SUPERIO_GPIO_IO_BASE 0x400 - #include "cpu/x86/bist.h" - #include "northbridge/amd/amdk8/debug.c" - -#include "cpu/amd/mtrr/amd_earlymtrr.c" - +#include <cpu/amd/mtrr.h> +#include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" - #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1) static void memreset_setup(void) @@ -54,15 +45,14 @@ { } -static void sio_gpio_setup(void){ - +static void sio_gpio_setup(void) +{ unsigned value; /*Enable onboard scsi*/ lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c); lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1))); - } static inline void activate_spd_rom(const struct mem_controller *ctrl) @@ -111,10 +101,9 @@ static void sio_setup(void) { - unsigned value; - uint32_t dword; - uint8_t byte; + u32 dword; + u8 byte; pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400); @@ -134,18 +123,15 @@ value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); value &= 0xbf; lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); - } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr [] = { + static const u16 spd_addr [] = { (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 (0xa<<3)|4, (0xa<<3)|6, 0, 0, (0xa<<3)|5, (0xa<<3)|7, 0, 0, -#endif }; int needs_reset; @@ -170,8 +156,6 @@ bsp_apicid = init_cpus(cpu_init_detectedx); } -// post_code(0x32); - lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -186,11 +170,10 @@ needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); -#endif needs_reset |= ht_setup_chains_x(); Modified: trunk/src/northbridge/amd/amdk8/debug.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/debug.c Fri Apr 9 15:49:48 2010 (r5395) +++ trunk/src/northbridge/amd/amdk8/debug.c Fri Apr 9 16:46:51 2010 (r5396) @@ -84,7 +84,7 @@ } #endif -static void dump_pci_devices(void) +static inline void dump_pci_devices(void) { device_t dev; for(dev = PCI_DEV(0, 0, 0); Modified: trunk/src/northbridge/amd/amdk8/incoherent_ht.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/incoherent_ht.c Fri Apr 9 15:49:48 2010 (r5395) +++ trunk/src/northbridge/amd/amdk8/incoherent_ht.c Fri Apr 9 16:46:51 2010 (r5396) @@ -476,6 +476,7 @@ } +#if 0 #if RAMINIT_SYSINFO == 1 static void ht_setup_chain(device_t udev, unsigned upos, struct sys_info *sysinfo) #else @@ -506,6 +507,8 @@ return ht_setup_chainx(udev, upos, 0, offset_unitid); #endif } +#endif + static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt, uint8_t val) { uint32_t dword, dword_old; Modified: trunk/src/northbridge/amd/amdk8/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/northbridge.c Fri Apr 9 15:49:48 2010 (r5395) +++ trunk/src/northbridge/amd/amdk8/northbridge.c Fri Apr 9 16:46:51 2010 (r5396) @@ -925,7 +925,7 @@ #if 1 #warning "FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M MMIO hole" - /* Round the mmio hold to 64M */ + /* Round the mmio hole to 64M */ mmio_basek &= ~((64*1024) - 1); #endif Modified: trunk/src/northbridge/amd/amdk8/raminit.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit.c Fri Apr 9 15:49:48 2010 (r5395) +++ trunk/src/northbridge/amd/amdk8/raminit.c Fri Apr 9 16:46:51 2010 (r5396) @@ -7,6 +7,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> #include <stdlib.h> +#include <reset.h> #include "raminit.h" #include "amdk8.h" @@ -564,11 +565,13 @@ static int is_opteron(const struct mem_controller *ctrl) { - /* Test to see if I am an Opteron. - * FIXME Socket 939 based Athlon64 have dual channel capability, - * too, so we need a better test for Opterons + /* Test to see if I am an Opteron. Socket 939 based Athlon64 + * have dual channel capability, too, so we need a better test + * for Opterons. + * However, all code uses is_opteron() to find out whether to + * use dual channel, so if we really check for opteron here, we + * need to fix up all code using this function, too. */ -#warning "FIXME: Implement a better test for Opterons" uint32_t nbcap; nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); return !!(nbcap & NBCAP_128Bit); Modified: trunk/src/northbridge/amd/amdk8/raminit.h ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit.h Fri Apr 9 15:49:48 2010 (r5395) +++ trunk/src/northbridge/amd/amdk8/raminit.h Fri Apr 9 16:46:51 2010 (r5396) @@ -11,4 +11,10 @@ uint16_t channel1[DIMM_SOCKETS]; }; +#if defined(__PRE_RAM__) && defined(RAMINIT_SYSINFO) && RAMINIT_SYSINFO == 1 +void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo); +#else +void sdram_initialize(int controllers, const struct mem_controller *ctrl); +#endif + #endif /* RAMINIT_H */ Modified: trunk/src/northbridge/amd/amdk8/setup_resource_map.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/setup_resource_map.c Fri Apr 9 15:49:48 2010 (r5395) +++ trunk/src/northbridge/amd/amdk8/setup_resource_map.c Fri Apr 9 16:46:51 2010 (r5396) @@ -3,15 +3,14 @@ static void setup_resource_map_offset(const unsigned int *register_values, int max, unsigned offset_pci_dev, unsigned offset_io_base) { int i; -// print_debug("setting up resource map offset...."); -#if 0 - print_debug("\n"); +#if RES_DEBUG + printk(BIOS_DEBUG, "setting up resource map offset....\n"); #endif for(i = 0; i < max; i += 3) { device_t dev; unsigned where; unsigned long reg; -#if 0 +#if RES_DEBUG prink_debug("%08x <- %08x\n", register_values[i] + offset_pci_dev, register_values[i+2]); #endif dev = (register_values[i] & ~0xfff) + offset_pci_dev; @@ -27,7 +26,9 @@ pci_write_config32(register_values[i], reg); #endif } -// print_debug("done.\n"); +#if RES_DEBUG + printk(BIOS_DEBUG, "done.\n"); +#endif } #define RES_PCI_IO 0x10 @@ -40,12 +41,7 @@ int i; #if RES_DEBUG - print_debug("setting up resource map ex offset...."); - -#endif - -#if RES_DEBUG - print_debug("\n"); + printk(BIOS_DEBUG, "setting up resource map ex offset....\n"); #endif for(i = 0; i < max; i += 4) { #if RES_DEBUG @@ -112,21 +108,19 @@ } #if RES_DEBUG - print_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); #endif } + +#if defined(SOUTHBRIDGE_NVIDIA_MCP55) || defined(SOUTHBRIDGE_NVIDIA_CK804) static void setup_resource_map_x(const unsigned int *register_values, int max) { int i; #if RES_DEBUG - print_debug("setting up resource map ex offset...."); - + printk(BIOS_DEBUG, "setting up resource map ex....\n"); #endif -#if RES_DEBUG - print_debug("\n"); -#endif for(i = 0; i < max; i += 4) { #if RES_DEBUG printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n", @@ -188,47 +182,12 @@ } #if RES_DEBUG - print_debug("done.\n"); + printk(BIOS_DEBUG, "done.\n"); #endif } - -#if 0 -static void setup_iob_resource_map(const unsigned int *register_values, int max) -{ - int i; - - for(i = 0; i < max; i += 3) { - unsigned where; - unsigned reg; - - where = register_values[i]; -#if 0 - udelay(2000); - print_debug_hex16(where); -#endif - reg = inb(where); -#if 0 - print_debug("="); - print_debug_hex8(reg); #endif - reg &= register_values[i+1]; - reg |= register_values[i+2]; #if 0 - print_debug(" <- "); - print_debug_hex8(reg); -#endif - outb(reg, where); -#if 0 - - print_debug(" -> "); - reg = inb(where); - print_debug_hex8(reg); - print_debug("\n"); -#endif - } -} - static void setup_io_resource_map(const unsigned int *register_values, int max) { int i; @@ -240,30 +199,26 @@ where = register_values[i]; #if 0 udelay(2000); - print_debug_hex16(where); + printk(BIOS_DEBUG, "%04x", where); #endif reg = inl(where); #if 0 udelay(2000); - print_debug("="); - print_debug_hex32(reg); + printk(BIOS_DEBUG, "=%08x", reg); #endif reg &= register_values[i+1]; reg |= register_values[i+2]; #if 0 udelay(2000); - print_debug(" <- "); - print_debug_hex32(reg); + printk(BIOS_DEBUG, " <- %08x", reg); #endif outl(reg, where); #if 0 udelay(2000); - print_debug(" -> "); reg = inl(where); - print_debug_hex32(reg); - print_debug("\n"); + printk(BIOS_DEBUG, " -> %08x\n", reg); #endif } } @@ -276,9 +231,8 @@ unsigned where; unsigned long reg; #if 0 - print_debug_hex32(register_values[i]); - print_debug(" <-"); - print_debug_hex32(register_values[i+2]); + prink(BIOS_DEBUG, "%08x <- %08x\n", + register_values[i], register_values[i+2]); #endif where = register_values[i]; reg = read32(where); @@ -286,10 +240,8 @@ reg |= register_values[i+2]; write32( where, reg); #if 0 - print_debug(" RB "); reg = read32(where); - print_debug_hex32(reg); - print_debug("\n"); + prink(BIOS_DEBUG, " RB %08x\n", reg); #endif } } Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c Fri Apr 9 15:49:48 2010 (r5395) +++ trunk/src/southbridge/nvidia/ck804/ck804_early_smbus.c Fri Apr 9 16:46:51 2010 (r5396) @@ -31,7 +31,7 @@ return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -static int smbus_write_byte(unsigned device, unsigned address, +static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val) { return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); Modified: trunk/src/southbridge/nvidia/ck804/ck804_smbus.h ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_smbus.h Fri Apr 9 15:49:48 2010 (r5395) +++ trunk/src/southbridge/nvidia/ck804/ck804_smbus.h Fri Apr 9 16:46:51 2010 (r5396) @@ -23,6 +23,8 @@ outb(0x80, 0x80); } +#if 0 +/* Not needed, upon write to PRTCL, the status will be auto-cleared. */ static int smbus_wait_until_ready(unsigned smbus_io_base) { unsigned long loops; @@ -38,6 +40,7 @@ } while (--loops); return -2; } +#endif static int smbus_wait_until_done(unsigned smbus_io_base) { @@ -53,6 +56,7 @@ return -3; } +#ifndef __PRE_RAM__ static int do_smbus_recv_byte(unsigned smbus_io_base, unsigned device) { unsigned char global_status_register, byte; @@ -129,6 +133,7 @@ return 0; } +#endif static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) Modified: trunk/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c ============================================================================== --- trunk/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c Fri Apr 9 15:49:48 2010 (r5395) +++ trunk/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c Fri Apr 9 16:46:51 2010 (r5396) @@ -30,6 +30,7 @@ return inb(iobase+offset); } +#if 0 /* for GP60-GP64, GP66-GP85 */ #define LPC47B397_GPIO_CNTL_INDEX 0x70 #define LPC47B397_GPIO_CNTL_DATA 0x71 @@ -45,3 +46,4 @@ outb(index,iobase+LPC47B397_GPIO_CNTL_INDEX); return inb(iobase+LPC47B397_GPIO_CNTL_DATA); } +#endif

1 0

password
by ron minnich 09 Apr '10

09 Apr '10

I have a lenovo x300 somebody set the password on and ... as you guess, forgot. So, question: anyone have any idea how deep into the machine the password is kept no new machines? Deep in TPM? in other words, were flashrom to work on this box, can the password be reset? ron

7 8

[commit] r5388 - in trunk/src: arch/i386 arch/i386/include/arch arch/i386/lib cpu/intel cpu/intel/model_6bx cpu/intel/model_6ex cpu/intel/socket_mFCBGA479 include mainboard/rca/rm4100 mainboard/tho...
by repository service 09 Apr '10

09 Apr '10

Author: stepan Date: Fri Apr 9 13:10:25 2010 New Revision: 5388 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5388 Log: 1. This patch adds CAR for Intel P6 series processors. 2. Add support for Micro-FCBGA 479 Celeron and PIII's 3. Add support for model_6bx and microcode updates 4. Add support for CAR and Tinybootblock on RCA RM4100 and Thomson IP1000 Build and boot tested. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> The change to CAR reveiled a few more warnings in the ICH4 and i830 code, I fixed them on the fly. Checking this in because my last two commits broke Joseph's CAR patch. This version fixes the issues. Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/src/arch/i386/include/arch/stages.h trunk/src/cpu/intel/model_6bx/ trunk/src/cpu/intel/model_6bx/Kconfig trunk/src/cpu/intel/model_6bx/Makefile.inc trunk/src/cpu/intel/model_6bx/cache_as_ram_disable.c trunk/src/cpu/intel/model_6bx/microcode-737-MU16b11c.h trunk/src/cpu/intel/model_6bx/microcode-738-MU16b11d.h trunk/src/cpu/intel/model_6bx/microcode-875-MU16b401.h trunk/src/cpu/intel/model_6bx/microcode-885-MU16b402.h trunk/src/cpu/intel/model_6bx/model_6bx_init.c trunk/src/cpu/intel/socket_mFCBGA479/ trunk/src/cpu/intel/socket_mFCBGA479/Kconfig trunk/src/cpu/intel/socket_mFCBGA479/Makefile.inc trunk/src/cpu/intel/socket_mFCBGA479/chip.h trunk/src/cpu/intel/socket_mFCBGA479/socket_mFCBGA479.c Modified: trunk/src/arch/i386/Makefile.inc trunk/src/arch/i386/lib/cbfs_and_run.c trunk/src/cpu/intel/Kconfig trunk/src/cpu/intel/Makefile.inc trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c trunk/src/include/cbfs.h trunk/src/mainboard/rca/rm4100/Kconfig trunk/src/mainboard/rca/rm4100/Makefile.inc trunk/src/mainboard/rca/rm4100/devicetree.cb trunk/src/mainboard/rca/rm4100/romstage.c trunk/src/mainboard/thomson/ip1000/Kconfig trunk/src/mainboard/thomson/ip1000/Makefile.inc trunk/src/mainboard/thomson/ip1000/devicetree.cb trunk/src/mainboard/thomson/ip1000/romstage.c trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c trunk/src/northbridge/intel/i82830/raminit.c trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c trunk/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c Modified: trunk/src/arch/i386/Makefile.inc ============================================================================== --- trunk/src/arch/i386/Makefile.inc Fri Apr 9 12:43:49 2010 (r5387) +++ trunk/src/arch/i386/Makefile.inc Fri Apr 9 13:10:25 2010 (r5388) @@ -165,6 +165,9 @@ ifeq ($(CONFIG_CPU_INTEL_SOCKET_BGA956),y) crt0s += $(src)/cpu/intel/model_6ex/cache_as_ram.inc endif +ifeq ($(CONFIG_CPU_INTEL_SOCKET_MFCBGA479),y) +crt0s += $(src)/cpu/x86/car/cache_as_ram.inc +endif # should be CONFIG_CPU_VIA_C7, but bcom/winnetp680, jetway/j7f24, via/epia-cn, via/pc2500e don't use CAR yet ifeq ($(CONFIG_BOARD_VIA_VT8454C),y) crt0s += $(src)/cpu/via/car/cache_as_ram.inc Added: trunk/src/arch/i386/include/arch/stages.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/arch/i386/include/arch/stages.h Fri Apr 9 13:10:25 2010 (r5388) @@ -0,0 +1,5 @@ +void cbfs_and_run_core(const char *filename, unsigned int ebp); +void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset); +void __attribute__((regparm(0))) copy_and_run_ap_code_in_car(unsigned ret_addr); + + Modified: trunk/src/arch/i386/lib/cbfs_and_run.c ============================================================================== --- trunk/src/arch/i386/lib/cbfs_and_run.c Fri Apr 9 12:43:49 2010 (r5387) +++ trunk/src/arch/i386/lib/cbfs_and_run.c Fri Apr 9 13:10:25 2010 (r5388) @@ -19,6 +19,7 @@ #include <console/console.h> #include <cbfs.h> +#include <arch/stages.h> void cbfs_and_run_core(const char *filename, unsigned ebp) { @@ -41,8 +42,6 @@ ); } -void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset); - void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset) { // FIXME fix input parameters instead normalizing them here. @@ -53,7 +52,7 @@ } #if CONFIG_AP_CODE_IN_CAR == 1 -static void __attribute__((regparm(0))) copy_and_run_ap_code_in_car(unsigned ret_addr) +void __attribute__((regparm(0))) copy_and_run_ap_code_in_car(unsigned ret_addr) { cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ap", ret_addr); } Modified: trunk/src/cpu/intel/Kconfig ============================================================================== --- trunk/src/cpu/intel/Kconfig Fri Apr 9 12:43:49 2010 (r5387) +++ trunk/src/cpu/intel/Kconfig Fri Apr 9 13:10:25 2010 (r5388) @@ -1,6 +1,7 @@ # CPU models source src/cpu/intel/model_6xx/Kconfig source src/cpu/intel/model_69x/Kconfig +source src/cpu/intel/model_6bx/Kconfig source src/cpu/intel/model_6dx/Kconfig source src/cpu/intel/model_6ex/Kconfig source src/cpu/intel/model_6fx/Kconfig @@ -16,6 +17,7 @@ source src/cpu/intel/bga956/Kconfig source src/cpu/intel/slot_2/Kconfig source src/cpu/intel/slot_1/Kconfig +source src/cpu/intel/socket_mFCBGA479/Kconfig source src/cpu/intel/socket_mFCPGA478/Kconfig source src/cpu/intel/socket_mPGA478/Kconfig source src/cpu/intel/socket_mPGA479M/Kconfig Modified: trunk/src/cpu/intel/Makefile.inc ============================================================================== --- trunk/src/cpu/intel/Makefile.inc Fri Apr 9 12:43:49 2010 (r5387) +++ trunk/src/cpu/intel/Makefile.inc Fri Apr 9 13:10:25 2010 (r5388) @@ -6,6 +6,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441 subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += bga956 subdirs-$(CONFIG_CPU_INTEL_EP80579) += ep80579 +subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCBGA479) += socket_mFCBGA479 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA478) += socket_mPGA478 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA479M) += socket_mPGA479M Added: trunk/src/cpu/intel/model_6bx/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/intel/model_6bx/Kconfig Fri Apr 9 13:10:25 2010 (r5388) @@ -0,0 +1,3 @@ +config CPU_INTEL_MODEL_6BX + bool + select SMP Added: trunk/src/cpu/intel/model_6bx/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/intel/model_6bx/Makefile.inc Fri Apr 9 13:10:25 2010 (r5388) @@ -0,0 +1 @@ +driver-y += model_6bx_init.o Added: trunk/src/cpu/intel/model_6bx/cache_as_ram_disable.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/intel/model_6bx/cache_as_ram_disable.c Fri Apr 9 13:10:25 2010 (r5388) @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/stages.h> + +/* called from assembler code */ +void stage1_main(unsigned long bist); + +/* from romstage.c */ +void real_main(unsigned long bist); + +void stage1_main(unsigned long bist) +{ + unsigned int cpu_reset = 0; + + real_main(bist); + + /* No servicable parts below this line .. */ +#ifdef CAR_DEBUG + /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ + unsigned v_esp; + __asm__ volatile ( + "movl %%esp, %0\n" + : "=a" (v_esp) + ); + printk(BIOS_SPEW, "v_esp=%08x\n", v_esp); +#endif + + printk(BIOS_SPEW, "cpu_reset = %08x\n", cpu_reset); + printk(BIOS_SPEW, "No cache as ram now - "); + + /* store cpu_reset to ebx */ + __asm__ volatile ( + "movl %0, %%ebx\n\t" + ::"a" (cpu_reset) + ); + +#undef CLEAR_FIRST_1M_RAM +#include "cpu/x86/car/cache_as_ram_post.c" + + /* For now: use rambase + 1MB - 64K (counting downwards) as stack. This + * makes sure that we stay completely within the 1M of memory we + * preserve with the memcpy above. + */ + +#ifndef HIGH_MEMORY_SAVE +#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) +#endif + + __asm__ volatile ( + "movl %0, %%ebp\n" + "movl %0, %%esp\n" + :: "a" (CONFIG_RAMBASE + HIGH_MEMORY_SAVE) + ); + + { + unsigned new_cpu_reset; + + /* get back cpu_reset from ebx */ + __asm__ volatile ( + "movl %%ebx, %0\n" + :"=a" (new_cpu_reset) + ); + + /* Copy and execute coreboot_ram */ + copy_and_run(new_cpu_reset); + } + + /* We will not return */ + printk(BIOS_DEBUG, "sorry. parachute did not open.\n"); +} Added: trunk/src/cpu/intel/model_6bx/microcode-737-MU16b11c.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/intel/model_6bx/microcode-737-MU16b11c.h Fri Apr 9 13:10:25 2010 (r5388) @@ -0,0 +1,163 @@ +//+++ +// Copyright (c) <1995-2009>, Intel Corporation. +// All rights reserved. +// +// Redistribution. Redistribution and use in binary form, without modification, are +// permitted provided that the following conditions are met: +// .Redistributions must reproduce the above copyright notice and the following +// disclaimer in the documentation and/or other materials provided with the +// distribution. +// .Neither the name of Intel Corporation nor the names of its suppliers may be used +// to endorse or promote products derived from this software without specific prior +// written permission. +// .No reverse engineering, decompilation, or disassembly of this software is +// permitted. +// ."Binary form" includes any format commonly used for electronic conveyance +// which is a reversible, bit-exact translation of binary representation to ASCII or +// ISO text, for example, "uuencode." +// +// DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +// HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER +// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +// NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//--- +/* Sun Sep 27 10:52:54 CST 2009 */ +/* 737-MU16b11c.inc */ +0x00000001, 0x0000001c, 0x02152001, 0x000006b1, +0x6506e1cf, 0x00000001, 0x00000010, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x3ff8d1ac, 0x6ad5a5d7, 0x41bc1a2f, 0xc0cfcf98, +0xae80b685, 0x4e7fdba5, 0xee70aae6, 0x857f82df, +0x4c12ad1c, 0xc6eab058, 0x849e97b8, 0x4b425e5a, +0xe6819908, 0x8134a945, 0x601aea2a, 0xc633b991, +0x8f9e395f, 0x4699cb55, 0xcbc3795e, 0x85561846, +0x6f4f5e1f, 0xcf0cf38f, 0xac133e0c, 0x4bbe51fc, +0xc340f285, 0x8c63f67d, 0x45160027, 0xc85a74bb, +0xaeb95e32, 0x4f4fc61d, 0xe5033858, 0x8e4e090f, +0x4b5acb2a, 0xc75bc00c, 0x880daabb, 0x43d6f6af, +0xefd1d4e8, 0x87575a65, 0x6ef3afc2, 0xc8062d96, +0x8945ca80, 0x41c583c3, 0xcbb2f0a7, 0x8661bdce, +0x6d21f128, 0xc24acdc4, 0xaeaf43d5, 0x46dcbcd3, +0xcf544779, 0x82ea3983, 0x4b1656e2, 0xc3a0de21, +0xa14ded06, 0x4e779174, 0xe01de86d, 0x80c33ba8, +0x44762085, 0xc74f0d93, 0x85ca1cfa, 0x4dc7752f, +0xe0c2bfd0, 0x853e48b1, 0x67f42503, 0xcfed157c, +0x8d33cb2f, 0x43eb149b, 0xc71e279a, 0x82561424, +0x60cc4578, 0xce0d779d, 0xa6254192, 0x43e5a2cf, +0xcaee4715, 0x857afd44, 0x45ad93fa, 0xc6043ebf, +0xa98f3eee, 0x4f8e481c, 0xee5d3fe4, 0x84e30c80, +0x464de23b, 0xc76af7c3, 0x8155a3cb, 0x4a425a2f, +0xe3fd06a4, 0x8b51c2ec, 0x61bda6b9, 0xc71d76c2, +0x8bd436d3, 0x4e4a5c77, 0xc2cffcfd, 0x833c6a3c, +0x65d4f768, 0xcbfe0635, 0xa9bd7c0a, 0x49d3018a, +0xca646403, 0x8776d3d2, 0x426a93f7, 0xc03b8393, +0xa8e7690c, 0x46d7b40c, 0xe6a47d18, 0x8b927811, +0x4febdfe3, 0xc38a9d51, 0x8f76a603, 0x49d5cc1c, +0xe79861ed, 0x8d4c5baa, 0x6c7da6df, 0xc157063a, +0x87dbd994, 0x472dff09, 0xcc1742f2, 0x8de8e9c7, +0x641ab500, 0xc437013a, 0xaeaedc04, 0x492e9f4e, +0xc3de047e, 0x8dbd801d, 0x4cfd2f32, 0xcc34102c, +0xac06dbb4, 0x4ac3f30b, 0xe83b3458, 0x8634b95b, +0x444079d2, 0xc807d487, 0x8da4cd9e, 0x4760f318, +0xec62523f, 0x816240b9, 0x6cba09ce, 0xca86a264, +0x863f14ca, 0x49b9d4a1, 0xc6bd9715, 0x87edeb98, +0x6fa1a092, 0xcb36670f, 0xa2edb3a7, 0x43545378, +0xc3c35ad7, 0x8e2d1255, 0x4a06377c, 0xcd1b61d4, +0xa83a9bc7, 0x4c48d28d, 0xe8a27b8a, 0x8a47665c, +0x49a35371, 0xc8a8fb0a, 0x830dc900, 0x4c01d1bc, +0xee2ffff4, 0x83243d8d, 0x61ead599, 0xc82c0451, +0x8c19b0ec, 0x465ee1d4, 0xc52df943, 0x8490687c, +0x68474c0d, 0xcc495773, 0xa04396d5, 0x4824c02c, +0xceb15f4d, 0x80a78140, 0x4de85a0b, 0x8945e8c5, +0xc981ea75, 0x7ff89629, 0x4e4ce4e2, 0x6e9ceb88, +0x7f0b4dff, 0x165e46c8, 0xcf59bf6c, 0x9c430db4, +0xb55a941c, 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0x1ee0661f, +0x9b6c2030, 0x8e8dc989, 0xcd4bc9fc, 0x4454675b, +0x8d583c9c, 0xe3400094, 0x116ebb83, 0xe847bc9a, +0x2a4622dd, 0x2a901e6f, 0xd789b1c0, 0x094e2bbb, +0x056e563f, 0x9f17e606, 0x8bc79b8d, 0xd2c535c1, +0x06a45a27, 0x9dc56771, 0xa06649e2, 0x5ff25ac8, +0x6554961e, 0x98e583d9, 0x38ba93da, 0xdee1de18, +0x037cb9d5, 0x6b17f195, 0x3431faaf, 0x13860a0d, +0x28bca10d, 0x0a54c011, 0x9957cdb6, 0x3aa1f429, +0x9d41b7b3, 0x9aea5be2, 0x60c7ce6b, 0x4cd1c10b, +0x24ddddcd, 0xe28412ba, 0xa03a5466, 0xa1896879, +0x59edcb87, 0x1b241765, 0x157bf161, 0xf219f950, +0xe86ff526, 0x262005d9, 0x11769531, 0xbca15d95, +0x28f5ef17, 0x1f27e725, 0xc32631d2, 0x07249e61, +0x1ba851e3, 0x4f49b577, 0xe2a1df5e, 0x826fa7ff, +0xc34e1e2e, 0x7fe26024, 0xbc19800f, 0x0d368dc9, +0xe03da0c6, 0xadaa4f9c, 0x9ad1e43c, 0x96f84e44, +0x0b6cd695, 0x1bb46971, 0x942d6e5b, 0x6316170d, +0x3164509f, 0xc6659450, 0xb2a0370a, 0xabc208e8, +0x6d479811, 0x3684bc0e, 0x80b7b101, 0xa50b7bb5, +0x43d21233, 0xb423559d, 0xf41dcd16, 0xdfd3c276, +0x3e586469, 0xd9b7630a, 0xb88f9e44, 0x0cda6f4d, +0xe5bf5844, 0x8709f788, 0xdae37da6, 0x1fb41777, +0x1d903f69, 0x34383b69, 0xd409ae70, 0xd1c99758, +0xdedfd7a4, 0xa4bdf018, 0xf4058202, 0x8565d66f, +0x5365aed9, 0xfa69742e, 0x2cfbfbcf, 0x88a00b60, +0x506c0713, 0x2866475b, 0x3e1df573, 0xb86f7feb, +0x31d23a7f, 0xc6320e6a, 0x3ebbc2a5, 0x83a1d4ef, +0x15169f5f, 0x42a61753, 0x893e553e, 0x4ddbc66d, +0x7449ec1f, 0x76f65d22, 0x0622e13b, 0x32986f89, +0x21181b4b, 0x99a80c0a, 0xd6fe00b0, 0x282c0e81, +0x9fc1cf88, 0x919b855d, 0x618257d8, 0x82c448b8, +0xe22537a1, 0xa90de388, 0xba73b90c, 0xd765eeb0, +0x62b2727e, 0xa08dfe20, 0x70b3c8c5, 0x3ef04007, +0x9f73732b, 0x2201edd7, 0xb836219c, 0xf913af7c, +0xf50f64ca, 0x93ac107a, 0xf509f84a, 0x6f6026f6, +0xd9bb8eac, 0x4b268cfa, 0xa65a3fa6, 0x9837cb75, +0x784fb835, 0x2060576d, 0xb1604cae, 0xb9da4116, +0xab320cf2, 0x60a1b501, 0x0c73fa79, 0x8d5a6f1e, +0x57688086, 0x218e4005, 0xca054e3d, 0xc1a3c3ec, Added: trunk/src/cpu/intel/model_6bx/microcode-738-MU16b11d.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/intel/model_6bx/microcode-738-MU16b11d.h Fri Apr 9 13:10:25 2010 (r5388) @@ -0,0 +1,163 @@ +//+++ +// Copyright (c) <1995-2009>, Intel Corporation. +// All rights reserved. +// +// Redistribution. Redistribution and use in binary form, without modification, are +// permitted provided that the following conditions are met: +// .Redistributions must reproduce the above copyright notice and the following +// disclaimer in the documentation and/or other materials provided with the +// distribution. +// .Neither the name of Intel Corporation nor the names of its suppliers may be used +// to endorse or promote products derived from this software without specific prior +// written permission. +// .No reverse engineering, decompilation, or disassembly of this software is +// permitted. +// ."Binary form" includes any format commonly used for electronic conveyance +// which is a reversible, bit-exact translation of binary representation to ASCII or +// ISO text, for example, "uuencode." +// +// DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +// HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER +// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +// NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//--- +/* Sun Sep 27 10:52:54 CST 2009 */ +/* 738-MU16b11d.inc */ +0x00000001, 0x0000001d, 0x02202001, 0x000006b1, +0x6d9b5661, 0x00000001, 0x00000020, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x965e94ce, 0xea6ba8df, 0xbfae08d4, 0x3ec50299, +0xbf2b31ed, 0xbd80d71d, 0x19bfb06d, 0x95e56995, +0xa52265a7, 0x247242bb, 0x90900442, 0xa4d69328, +0x15fb69e8, 0x940daeb6, 0x8d930183, 0x2ad6a75d, +0x970bcd0c, 0xbfc335a6, 0x382df453, 0x8dfa472a, +0x95f0eda4, 0x2feaf1e8, 0xb6e292dc, 0xb7c32497, +0x2daa2a09, 0x83b58903, 0xaf122f90, 0x3730c2af, +0xa8f684d3, 0xa7f33a97, 0x11b46600, 0x8f8af52b, +0xab23714a, 0x2a87cf3b, 0x9ae73e3e, 0xa032cf57, +0x0adc600d, 0x96117940, 0x9ac65c28, 0x3a23596e, +0x94800c0f, 0xbf793392, 0x2c503bb1, 0x8dc252ce, +0x9b7de53f, 0x2af3d7b4, 0xb7bd4575, 0xbc71e798, +0x23d62362, 0x8393e39e, 0xafb59604, 0x290633b6, +0xac09d0f8, 0xbaced873, 0x1fbd177c, 0x9b51acfe, +0xa4d82134, 0x2dff3e84, 0x86d59af1, 0xa4789758, +0x0469ae88, 0x9a3f986b, 0x8f18edcb, 0x3a200e44, +0x8138b3f9, 0xb9aaf81c, 0x25af1d92, 0x8313e883, +0x9a7ff75e, 0x20a6b69d, 0xa1bb0bbb, 0xbb78f982, +0x27c1974a, 0x8dafbb13, 0xbc2ac530, 0x2c84f9a8, +0xa1d686a1, 0xbd6b3d97, 0x07419bad, 0x99535e65, +0xa1ee3deb, 0x3aca5a6d, 0x9c60ad82, 0xa9ac0d86, +0x14ba77c2, 0x80b20413, 0x93be9f5f, 0x34c56863, +0x87e25909, 0xbaaf9373, 0x2e9396d7, 0x836c3f99, +0x8c81e59b, 0x24c4123f, 0xbc3b2921, 0xa2744f80, +0x37dec6c6, 0x9e6b0ec7, 0xa6d652e6, 0x349f2dec, +0xafcf34e5, 0xa81bf9cf, 0x046ce7f0, 0x973ce507, +0xbd2386a9, 0x336dbfa6, 0x8de954fe, 0xb823c3bd, +0x13088720, 0x86bec81c, 0x9265d562, 0x24574333, +0x92f871dc, 0xa34ef2fd, 0x366b59f0, 0x84a9a050, +0x81e55751, 0x3f326f2a, 0xbbf66ec3, 0xa784062a, +0x2c9bc339, 0x889b495a, 0xa44822fe, 0x2e9b5fbd, +0xa69f6830, 0xa446b369, 0x1da26dbb, 0x820f296a, +0xbe2c600f, 0x27b90904, 0x88f003c9, 0xa9191c49, +0x024286cb, 0x9fe1354e, 0x91a7670e, 0x38236d32, +0x9c70820d, 0xbad8c44e, 0x2f9b35eb, 0x8fb157de, +0x82ea988a, 0x32f204c5, 0xb6a7fd19, 0xbe64276b, +0x2ad2ea1d, 0x95449132, 0xa7e07868, 0x3ae7a323, +0xbd4b67ba, 0xa1a1914f, 0x1f964ad2, 0x85f986d7, +0xa84bc3cc, 0x2739696c, 0x81196fea, 0xa90cd44b, +0x05728610, 0x8873057c, 0x83035ccc, 0x24e56003, +0x863ee7bf, 0xb4b92f27, 0x328f2941, 0x8ace163b, +0x94f39234, 0x39f2eb7f, 0xa10f03e2, 0xbd9ae083, +0x325e4950, 0x99241d8d, 0xa07f585f, 0xf2ed61ff, +0x3341f541, 0x68372f11, 0xa01b5b7f, 0xcc5d571c, +0x7ac343af, 0xa4a1568a, 0x142d7f47, 0x8f0b9477, +0x720e7fff, 0xf9214071, 0x84fa4a07, 0x5463cfab, +0xffa780fc, 0xb8fbd2fb, 0x84a2fdb4, 0xef1c1b2e, +0x7e4ce78b, 0x8a5e9464, 0x60bbad48, 0x463ffc56, +0x0d9ac7e7, 0x545e8378, 0x595db59f, 0x04edbae3, +0x5e4540e3, 0x489aaeb4, 0x94b5b57c, 0xbe693e7a, +0xcc870854, 0x7f6caa27, 0x0a85aa9d, 0xf678f31c, +0xc0a00529, 0x350ee2b8, 0x163fd3f5, 0x13fc2e76, +0xd92bb224, 0xdf829dcb, 0x07db061e, 0x2c99066b, +0xcb0327e8, 0xe3d4e5e8, 0xd7d7da31, 0x643aed9f, +0x1994a531, 0x73f84914, 0x5f296334, 0x874490b7, +0x517b63f6, 0xc04b51ef, 0x34d7de4d, 0x478cb112, +0x66642af0, 0x2f392ef9, 0x1811ec70, 0x943bc492, +0x70c61209, 0xeec40884, 0x47bb5b01, 0x255afce3, +0x393fcd34, 0x1cca4e00, 0x3d2ac97e, 0x314450fa, +0x838ba96f, 0x4f0239d3, 0xf295395e, 0xb3c38631, +0x7ea7a143, 0x157a4e43, 0x46f8173f, 0xfbc18d4a, +0xc401e17a, 0xc4620358, 0xd2ab5437, 0xa01db06f, +0x58ce91fc, 0x850de1a3, 0x9b542dba, 0xee77f038, +0xddd3ced6, 0xc225d2ce, 0x63a3f765, 0x3342a06c, +0x6a780c2f, 0xfaa925b2, 0x366ebeec, 0xbcc9abea, +0xc7b3fa4e, 0xf4f1123d, 0x5198702c, 0x3e3458b7, +0x0b1ce9a1, 0x51b1bd7f, 0x711e791e, 0x927d8bed, +0x91dbaea9, 0x7eefbda9, 0x7a19edd9, 0xdf7b8dce, +0x5bb40613, 0x0b0c1e0f, 0x85b82c98, 0x18da4dc1, +0xc5fd78ac, 0x57c1e31d, 0x4c4001b5, 0xe31d2643, +0xa6afbf58, 0xad200e68, 0xf0114ba4, 0xd6a620f2, +0xc753a720, 0xac9022a0, 0x28a41f01, 0x22a4ba95, +0xc00b7531, 0x23d42795, 0xcd836a86, 0x90262708, +0x3292cad0, 0x40022e39, 0xc1581b0a, 0xe5101550, +0x6538096b, 0x208c549d, 0x3ce2bf88, 0xa71df38e, +0x3dec3685, 0xca3949f1, 0x79f3ad1b, 0x3ee8b300, +0x9d305fc6, 0x7a2e5288, 0xbe81a2f2, 0x7ada0c06, +0x191c7f01, 0x58dfcbd1, 0xc78dee72, 0x72364226, +0x1866de12, 0x8d22305c, 0x943a0f0e, 0xc81967ff, +0x4d55fb0f, 0xaf199be1, 0x90bbda61, 0x4e7c234f, +0x90cfec16, 0x9b4bcf26, 0x21622023, 0x0926f0fa, +0x1d504377, 0xa58db427, 0x8d93ce2b, 0x90bfe900, +0x29e67397, 0x2c1261ed, 0x4ace9474, 0xd5c60282, +0xe53fb300, 0x8a61a0ab, 0xa7aa0918, 0x4389d7c5, +0xd09d605c, 0x6c5bedb5, 0xd6d54c51, 0x433dea21, +0x7ad9e677, 0x813bff76, 0x5a162c75, 0x1ee0661f, +0x9b6c2030, 0x8e8dc989, 0xcd4bc9fc, 0x4454675b, +0x8d583c9c, 0xe3400094, 0x116ebb83, 0xe847bc9a, +0x2a4622dd, 0x2a901e6f, 0xd789b1c0, 0x094e2bbb, +0x056e563f, 0x9f17e606, 0x8bc79b8d, 0xd2c535c1, +0x06a45a27, 0x9dc56771, 0xa06649e2, 0x5ff25ac8, +0x6554961e, 0x98e583d9, 0x38ba93da, 0xdee1de18, +0x037cb9d5, 0x6b17f195, 0x3431faaf, 0x13860a0d, +0x28bca10d, 0x0a54c011, 0x9957cdb6, 0x3aa1f429, +0x9d41b7b3, 0x9aea5be2, 0x60c7ce6b, 0x4cd1c10b, +0x24ddddcd, 0xe28412ba, 0xa03a5466, 0xa1896879, +0x59edcb87, 0x1b241765, 0x157bf161, 0xf219f950, +0xe86ff526, 0x262005d9, 0x11769531, 0xbca15d95, +0x28f5ef17, 0x1f27e725, 0xc32631d2, 0x07249e61, +0x1ba851e3, 0x4f49b577, 0xe2a1df5e, 0x826fa7ff, +0xc34e1e2e, 0x7fe26024, 0xbc19800f, 0x0d368dc9, +0xe03da0c6, 0xadaa4f9c, 0x9ad1e43c, 0x96f84e44, +0x0b6cd695, 0x1bb46971, 0x942d6e5b, 0x6316170d, +0x3164509f, 0xc6659450, 0xb2a0370a, 0xabc208e8, +0x6d479811, 0x3684bc0e, 0x80b7b101, 0xa50b7bb5, +0x43d21233, 0xb423559d, 0xf41dcd16, 0xdfd3c276, +0x3e586469, 0xd9b7630a, 0xb88f9e44, 0x0cda6f4d, +0xe5bf5844, 0x8709f788, 0xdae37da6, 0x1fb41777, +0x1d903f69, 0x34383b69, 0xd409ae70, 0xd1c99758, +0xdedfd7a4, 0xa4bdf018, 0xf4058202, 0x8565d66f, +0x5365aed9, 0xfa69742e, 0x2cfbfbcf, 0x88a00b60, +0x506c0713, 0x2866475b, 0x3e1df573, 0xb86f7feb, +0x31d23a7f, 0xc6320e6a, 0x3ebbc2a5, 0x83a1d4ef, +0x15169f5f, 0x42a61753, 0x893e553e, 0x4ddbc66d, +0x7449ec1f, 0x76f65d22, 0x0622e13b, 0x32986f89, +0x21181b4b, 0x99a80c0a, 0xd6fe00b0, 0x282c0e81, +0x9fc1cf88, 0x919b855d, 0x618257d8, 0x82c448b8, +0xe22537a1, 0xa90de388, 0xba73b90c, 0xd765eeb0, +0x62b2727e, 0xa08dfe20, 0x70b3c8c5, 0x3ef04007, +0x9f73732b, 0x2201edd7, 0xb836219c, 0xf913af7c, +0xf50f64ca, 0x93ac107a, 0xf509f84a, 0x6f6026f6, +0xd9bb8eac, 0x4b268cfa, 0xa65a3fa6, 0x9837cb75, +0x784fb835, 0x2060576d, 0xb1604cae, 0xb9da4116, +0xab320cf2, 0x60a1b501, 0x0c73fa79, 0x8d5a6f1e, +0x57688086, 0x218e4005, 0xca054e3d, 0xc1a3c3ec, Added: trunk/src/cpu/intel/model_6bx/microcode-875-MU16b401.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/intel/model_6bx/microcode-875-MU16b401.h Fri Apr 9 13:10:25 2010 (r5388) @@ -0,0 +1,163 @@ +//+++ +// Copyright (c) <1995-2009>, Intel Corporation. +// All rights reserved. +// +// Redistribution. Redistribution and use in binary form, without modification, are +// permitted provided that the following conditions are met: +// .Redistributions must reproduce the above copyright notice and the following +// disclaimer in the documentation and/or other materials provided with the +// distribution. +// .Neither the name of Intel Corporation nor the names of its suppliers may be used +// to endorse or promote products derived from this software without specific prior +// written permission. +// .No reverse engineering, decompilation, or disassembly of this software is +// permitted. +// ."Binary form" includes any format commonly used for electronic conveyance +// which is a reversible, bit-exact translation of binary representation to ASCII or +// ISO text, for example, "uuencode." +// +// DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +// HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER +// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +// NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//--- +/* Sun Sep 27 10:52:54 CST 2009 */ +/* 875-MU16b401.inc */ +0x00000001, 0x00000001, 0x01102002, 0x000006b4, +0x58213e6a, 0x00000001, 0x00000010, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x1016aa4c, 0xba6d2007, 0x139b094a, 0x8d5cd4f5, +0xece206e4, 0xfac0aa68, 0x26674533, 0x9464601b, +0x4b3f7f76, 0x64133194, 0x37c151ed, 0x3ee0e278, +0x7cffc9c4, 0x562be2dc, 0xd1067021, 0xaf8f1728, +0xbad0534c, 0xf7a67cca, 0xdd34e969, 0x774bb723, +0x5635256e, 0xd23cce15, 0x3c7c50ce, 0xa5faaecc, +0x1c717607, 0xcc1e6f3e, 0x16a4c6a7, 0x58bd5816, +0x0a2e73b3, 0xd65104e4, 0xb873ec1a, 0xe6cdd62e, +0xcd278f3c, 0x2e081c41, 0xf43f4439, 0xbcdfa892, +0xbb20c46f, 0xe0c8f8e1, 0xa619c4cc, 0x48eea22e, +0xcfdf4bc4, 0xefaf4494, 0xa7cac511, 0x783c367e, +0x6fc43ebc, 0x67e32786, 0xf0c1fbb1, 0xf93d5b0d, +0x36e9b7e8, 0xc3b4dc36, 0x4beec4fb, 0x88382c9d, +0x735dd739, 0xc5e23b67, 0x0d325dd4, 0xfe8bd98b, +0xa0f294f9, 0x1916bcd9, 0x7b73f066, 0x26758acb, +0xf10be125, 0x5aee77d0, 0xa005f65a, 0xd4d88c84, +0x02340625, 0x687da1c4, 0x29906f8c, 0x20ca4e9c, +0xcad37ebf, 0x15ae02ef, 0x06ac0241, 0x60c210b8, +0x07bb359b, 0x970ada27, 0xd15463c5, 0xb1df482a, +0x32c0386e, 0x72719013, 0xbe45b1da, 0xda807e08, +0xe1340a36, 0x9bbc789b, 0x71ae0eb2, 0xa7b0e639, +0x12948517, 0x8bd37587, 0x083273be, 0x1a73a3be, +0x2e0cf9a6, 0x3c401aa6, 0xc74c77f8, 0xe6ee9da6, +0x3188f408, 0xcdfe98ff, 0x71369d02, 0x032e20b7, +0xb9083418, 0xe5ef65a8, 0x3a9317d2, 0x23117ad6, +0x6c303cfc, 0xe6aed513, 0x97b7af1e, 0xe277f5aa, +0xd1f788a7, 0x72305569, 0x2a241259, 0x7f786fa4, +0xeba79f99, 0x740b14fa, 0x2a8e8a3c, 0x7824a0f2, +0xb1b4588e, 0xc775677d, 0xbc2372a6, 0xd485e398, +0x8a989d5d, 0x960199ba, 0xe5dca6a2, 0x818b5c9c, +0x655f760d, 0x8a75081a, 0x86a6d67a, 0x05e74583, +0x160d2e9b, 0xecf3f2b6, 0xb0e5f342, 0x162dcc4b, +0x95d05b92, 0xec736eb1, 0xad367c81, 0x6b98845e, +0xaea10969, 0x32a923cc, 0x0e20e511, 0x11f1d80d, +0xa80bff0c, 0xdee5c142, 0x5618820b, 0x9ab1530f, +0xeb2e5aad, 0x71986a78, 0x4b9f79ab, 0xdcb38492, +0x5d1df5ee, 0xa6947ea5, 0x4b81b7aa, 0x4fd1194a, +0x809256af, 0x2d7d2c85, 0xc3a3d15b, 0x4e4dde55, +0xa275c268, 0xe584005b, 0xe7975491, 0xed9d3d06, +0x6aaf4acf, 0xf4e3f967, 0x7c04ded2, 0x9fefbb0c, +0xff806dc8, 0xbe36d1ce, 0xdc9e4a45, 0xe54a5b71, +0xea53d6aa, 0xf0e13f21, 0x250f7e77, 0x09429ec2, +0xb34360be, 0xdf249256, 0x4b6b8d57, 0x6f3b9f7d, +0x1dd4d988, 0x6a68c719, 0x82d171e5, 0x04de6517, +0xd2628f0d, 0xfe6fd4e1, 0x8f3cbd0b, 0xd8517c88, +0x7993bb4f, 0x9487f25f, 0x493ad1f1, 0x781b2745, +0xd25de9ed, 0x63fe8ffa, 0x83be8468, 0x5955efd3, +0xd07886cb, 0x3cbbf313, 0x10255dcf, 0x4fe6e5df, +0x2afbe5ce, 0x2731cea5, 0x3ca3a0b4, 0x9a73e5b3, +0x7022f776, 0x43f0062b, 0xac060c7c, 0x89c88761, +0xdf86c5be, 0x0f705bcc, 0x811d31cd, 0x56e72be7, +0x473becc1, 0x74d511a7, 0x7f44e656, 0xc04d3763, +0x487e15a7, 0x851f93bd, 0xc0cfdff8, 0x11b62ba1, +0x45ebf606, 0x5ae10f89, 0xcfd063cf, 0x25b52d80, +0x03b35a1a, 0x7e5be251, 0x643e69b1, 0xe50e0a26, +0x73a3be25, 0x7bd17fb9, 0x72ac0b0e, 0x2f04ee8b, +0x8e614214, 0x73fbbb40, 0x6c87f572, 0xc2cca0b1, +0x3a575557, 0xe38b025c, 0x57d61954, 0x5a77769b, +0x123d2893, 0xd21f163e, 0xef617597, 0xbfd67b8c, +0x838ba96f, 0x4f0239d3, 0xf295395e, 0xb3c38631, +0x7ea7a143, 0x157a4e43, 0x46f8173f, 0xfbc18d4a, +0xc401e17a, 0xc4620358, 0xd2ab5437, 0xa01db06f, +0x58ce91fc, 0x850de1a3, 0x9b542dba, 0xee77f038, +0xddd3ced6, 0xc225d2ce, 0x63a3f765, 0x3342a06c, +0x6a780c2f, 0xfaa925b2, 0x366ebeec, 0xbcc9abea, +0xc7b3fa4e, 0xf4f1123d, 0x5198702c, 0x3e3458b7, +0x0b1ce9a1, 0x51b1bd7f, 0x711e791e, 0x927d8bed, +0x91dbaea9, 0x7eefbda9, 0x7a19edd9, 0xdf7b8dce, +0x5bb40613, 0x0b0c1e0f, 0x85b82c98, 0x18da4dc1, +0xc5fd78ac, 0x57c1e31d, 0x4c4001b5, 0xe31d2643, +0xa6afbf58, 0xad200e68, 0xf0114ba4, 0xd6a620f2, +0xc753a720, 0xac9022a0, 0x28a41f01, 0x22a4ba95, +0xc00b7531, 0x23d42795, 0xcd836a86, 0x90262708, +0x3292cad0, 0x40022e39, 0xc1581b0a, 0xe5101550, +0x6538096b, 0x208c549d, 0x3ce2bf88, 0xa71df38e, +0x3dec3685, 0xca3949f1, 0x79f3ad1b, 0x3ee8b300, +0x9d305fc6, 0x7a2e5288, 0xbe81a2f2, 0x7ada0c06, +0x191c7f01, 0x58dfcbd1, 0xc78dee72, 0x72364226, +0x1866de12, 0x8d22305c, 0x943a0f0e, 0xc81967ff, +0x4d55fb0f, 0xaf199be1, 0x90bbda61, 0x4e7c234f, +0x90cfec16, 0x9b4bcf26, 0x21622023, 0x0926f0fa, +0x1d504377, 0xa58db427, 0x8d93ce2b, 0x90bfe900, +0x29e67397, 0x2c1261ed, 0x4ace9474, 0xd5c60282, +0xe53fb300, 0x8a61a0ab, 0xa7aa0918, 0x4389d7c5, +0xd09d605c, 0x6c5bedb5, 0xd6d54c51, 0x433dea21, +0x7ad9e677, 0x813bff76, 0x5a162c75, 0x1ee0661f, +0x9b6c2030, 0x8e8dc989, 0xcd4bc9fc, 0x4454675b, +0x8d583c9c, 0xe3400094, 0x116ebb83, 0xe847bc9a, +0x2a4622dd, 0x2a901e6f, 0xd789b1c0, 0x094e2bbb, +0x056e563f, 0x9f17e606, 0x8bc79b8d, 0xd2c535c1, +0x06a45a27, 0x9dc56771, 0xa06649e2, 0x5ff25ac8, +0x6554961e, 0x98e583d9, 0x38ba93da, 0xdee1de18, +0x037cb9d5, 0x6b17f195, 0x3431faaf, 0x13860a0d, +0x28bca10d, 0x0a54c011, 0x9957cdb6, 0x3aa1f429, +0x9d41b7b3, 0x9aea5be2, 0x60c7ce6b, 0x4cd1c10b, +0x24ddddcd, 0xe28412ba, 0xa03a5466, 0xa1896879, +0x59edcb87, 0x1b241765, 0x157bf161, 0xf219f950, +0xe86ff526, 0x262005d9, 0x11769531, 0xbca15d95, +0x28f5ef17, 0x1f27e725, 0xc32631d2, 0x07249e61, +0x1ba851e3, 0x4f49b577, 0xe2a1df5e, 0x826fa7ff, +0xc34e1e2e, 0x7fe26024, 0xbc19800f, 0x0d368dc9, +0xe03da0c6, 0xadaa4f9c, 0x9ad1e43c, 0x96f84e44, +0x0b6cd695, 0x1bb46971, 0x942d6e5b, 0x6316170d, +0x3164509f, 0xc6659450, 0xb2a0370a, 0xabc208e8, +0x6d479811, 0x3684bc0e, 0x80b7b101, 0xa50b7bb5, +0x43d21233, 0xb423559d, 0xf41dcd16, 0xdfd3c276, +0x3e586469, 0xd9b7630a, 0xb88f9e44, 0x0cda6f4d, +0xe5bf5844, 0x8709f788, 0xdae37da6, 0x1fb41777, +0x1d903f69, 0x34383b69, 0xd409ae70, 0xd1c99758, +0xdedfd7a4, 0xa4bdf018, 0xf4058202, 0x8565d66f, +0x5365aed9, 0xfa69742e, 0x2cfbfbcf, 0x88a00b60, +0x506c0713, 0x2866475b, 0x3e1df573, 0xb86f7feb, +0x31d23a7f, 0xc6320e6a, 0x3ebbc2a5, 0x83a1d4ef, +0x15169f5f, 0x42a61753, 0x893e553e, 0x4ddbc66d, +0x7449ec1f, 0x76f65d22, 0x0622e13b, 0x32986f89, +0x21181b4b, 0x99a80c0a, 0xd6fe00b0, 0x282c0e81, +0x9fc1cf88, 0x919b855d, 0x618257d8, 0x82c448b8, +0xe22537a1, 0xa90de388, 0xba73b90c, 0xd765eeb0, +0x62b2727e, 0xa08dfe20, 0x70b3c8c5, 0x3ef04007, +0x9f73732b, 0x2201edd7, 0xb836219c, 0xf913af7c, +0xf50f64ca, 0x93ac107a, 0xf509f84a, 0x6f6026f6, +0xd9bb8eac, 0x4b268cfa, 0xa65a3fa6, 0x9837cb75, +0x784fb835, 0x2060576d, 0xb1604cae, 0xb9da4116, +0xab320cf2, 0x60a1b501, 0x0c73fa79, 0x8d5a6f1e, +0x57688086, 0x218e4005, 0xca054e3d, 0xc1a3c3ec, Added: trunk/src/cpu/intel/model_6bx/microcode-885-MU16b402.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/intel/model_6bx/microcode-885-MU16b402.h Fri Apr 9 13:10:25 2010 (r5388) @@ -0,0 +1,163 @@ +//+++ +// Copyright (c) <1995-2009>, Intel Corporation. +// All rights reserved. +// +// Redistribution. Redistribution and use in binary form, without modification, are +// permitted provided that the following conditions are met: +// .Redistributions must reproduce the above copyright notice and the following +// disclaimer in the documentation and/or other materials provided with the +// distribution. +// .Neither the name of Intel Corporation nor the names of its suppliers may be used +// to endorse or promote products derived from this software without specific prior +// written permission. +// .No reverse engineering, decompilation, or disassembly of this software is +// permitted. +// ."Binary form" includes any format commonly used for electronic conveyance +// which is a reversible, bit-exact translation of binary representation to ASCII or +// ISO text, for example, "uuencode." +// +// DISCLAIMER. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT +// HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED +// WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER +// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT +// NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF +// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// +//--- +/* Sun Sep 27 10:52:54 CST 2009 */ +/* 885-MU16b402.inc */ +0x00000001, 0x00000002, 0x01112002, 0x000006b4, +0xf512ec8f, 0x00000001, 0x00000020, 0x00000000, +0x00000000, 0x00000000, 0x00000000, 0x00000000, +0x8d14e438, 0x725bfb67, 0x2d37e08c, 0xe7b19dfb, +0x4c8d3c95, 0xffc6f57a, 0xfccb06b2, 0xc6e24fdf, +0x1a3c7f2b, 0xa4b0a3ca, 0x09db4042, 0x61f7da54, +0xf3aa8795, 0x7b8f1487, 0xecd5a1b8, 0xdc8c213d, +0xcca7e859, 0xea53a869, 0x6029671d, 0xa2aa975e, +0x5ad10a3c, 0x61dcc9e8, 0x6949a4d4, 0x114d569b, +0xf3373941, 0x1c1838fd, 0xb175a480, 0x4f01d669, +0xe91ced35, 0xe1d0c798, 0xc51cb3ea, 0xb1ca685f, +0xa6d307d8, 0x4abbe7b0, 0xd37e4089, 0x43f218ca, +0x2c775ea9, 0x3e312577, 0x948e06b0, 0x09cc6398, +0x0f717e24, 0xac27b46c, 0xbeb41e37, 0xb6f8bcfb, +0xe357533b, 0xe99f4a97, 0xb20b928d, 0xa3239533, +0xd483e1ee, 0xbe688435, 0x11ce1bc2, 0xef04a8b7, +0x10c9a575, 0xd74f47ec, 0x7e1caa09, 0xbdf4f1b4, +0xbf14445b, 0x21b2f2a2, 0x63f32e79, 0x49df792a, +0xd81e7458, 0x8d1996f9, 0x0ccd33e5, 0x907d96dc, +0xd5b4ae37, 0xd743e460, 0x8d1eeb27, 0xbefe322f, +0x84edfa2e, 0x94a23dcb, 0x5519aa65, 0x60fb77a8, +0xfb3b499d, 0x5accc8df, 0x7e4fa2ae, 0xee70a051, +0xa00e5234, 0x7411fac7, 0x9e3bd4ac, 0x8870b19a, +0x0bf8210d, 0xa13413ee, 0xb18ccc76, 0x72217b46, +0xbac79caa, 0x3c196591, 0x975b9d8e, 0x8750facc, +0x4f4ba92a, 0x54a1c0e8, 0x2c30a8bc, 0xcb228a22, +0x8a1a76a9, 0x20f0b73c, 0xcbf6d97d, 0x2c3d632f, +0x487e9718, 0xdb39229d, 0x9dec941c, 0x857c67ac, +0x3fcb6bed, 0x24b8a438, 0x19802922, 0x6e2ef495, +0x2363800c, 0x8ed26f96, 0xe833a8b4, 0xf0f90321, +0xeee74569, 0x6fe1b339, 0xb571118c, 0x96faaa1f, +0xc0a5b115, 0xe0103aa4, 0x09679bc9, 0xe6c7ecc3, +0xddd7fab7, 0x169d9eab, 0x46de7a6b, 0x8e62dc8d, +0x0352127f, 0x9bbec1b4, 0xb4a22510, 0x06f94e5f, +0xd7cc03d6, 0xb2e2c178, 0x8d8a48ea, 0xa089e856, +0x6f2e29a3, 0xa6de73c0, 0x099bb823, 0xd642a2b6, +0xd222edee, 0x4d618164, 0x8028d02a, 0xe7462bd9, +0x993d5b65, 0x0d76b5b0, 0x20166d1b, 0x5000520b, +0x2d1b6fc8, 0x417d7251, 0x7c13ac74, 0x1aac7da6, +0xe3843e3d, 0xb76299a0, 0x9fb249c1, 0x4864d56e, +0xe12eab25, 0x38ce3d26, 0xc0d5b8a5, 0xd4910b5c, +0xbd428d74, 0x58ff0ae3, 0x78669ee4, 0x10471ff9, +0x534e002a, 0xe1d8feeb, 0xf4feee35, 0x76f222b0, +0x68c0270c, 0x0030d599, 0xd4241546, 0x8cfda1d1, +0x3852f115, 0xd7fb3466, 0x58fe4578, 0x57038162, +0xdb6dc364, 0x88baec17, 0xaf062790, 0xb70f6e83, +0x73fd4542, 0x010debbc, 0xdd02bcda, 0xd7b44398, +0xb2856418, 0x76aa8ecb, 0x72043c88, 0x00ba511e, +0x58df48d2, 0x8a10f33c, 0x684fd7a5, 0x47f15765, +0xe38065bf, 0x584d4eed, 0xa434b261, 0xc9254576, +0xe10ff696, 0x9882bde6, 0xb0967eda, 0x8b12dd5b, +0x1155b6a9, 0x679e8f2d, 0xe522ca3c, 0xff4432e0, +0xf1172213, 0x540032ff, 0xeaa78315, 0x003217dc, +0x96a5e987, 0x02d92ea1, 0x176db865, 0xbff26fc8, +0xa1ed85cc, 0x8d1e3673, 0xaf598c4d, 0xbb472150, +0xa522b7dc, 0x755194c6, 0x2cdafab3, 0x8ebd657c, +0x6197fa59, 0x2ef39c18, 0x8f63f7e8, 0xf1cf5923, +0x55e21350, 0xd44e22d0, 0xe134e739, 0xbd670fe0, +0xe2685063, 0x6dae2e19, 0xfbce6e8d, 0x3d4fdea6, +0xa7f23d9c, 0x1c7fe950, 0x2a23ef65, 0xf3f3a2f6, +0xa3c1fa25, 0xc5b98bc7, 0xc2f482b2, 0xc7745101, +0xfcf64472, 0x3f22aecb, 0x92018d3c, 0x24818346, +0x838ba96f, 0x4f0239d3, 0xf295395e, 0xb3c38631, +0x7ea7a143, 0x157a4e43, 0x46f8173f, 0xfbc18d4a, +0xc401e17a, 0xc4620358, 0xd2ab5437, 0xa01db06f, +0x58ce91fc, 0x850de1a3, 0x9b542dba, 0xee77f038, +0xddd3ced6, 0xc225d2ce, 0x63a3f765, 0x3342a06c, +0x6a780c2f, 0xfaa925b2, 0x366ebeec, 0xbcc9abea, +0xc7b3fa4e, 0xf4f1123d, 0x5198702c, 0x3e3458b7, +0x0b1ce9a1, 0x51b1bd7f, 0x711e791e, 0x927d8bed, +0x91dbaea9, 0x7eefbda9, 0x7a19edd9, 0xdf7b8dce, +0x5bb40613, 0x0b0c1e0f, 0x85b82c98, 0x18da4dc1, +0xc5fd78ac, 0x57c1e31d, 0x4c4001b5, 0xe31d2643, +0xa6afbf58, 0xad200e68, 0xf0114ba4, 0xd6a620f2, +0xc753a720, 0xac9022a0, 0x28a41f01, 0x22a4ba95, +0xc00b7531, 0x23d42795, 0xcd836a86, 0x90262708, +0x3292cad0, 0x40022e39, 0xc1581b0a, 0xe5101550, +0x6538096b, 0x208c549d, 0x3ce2bf88, 0xa71df38e, +0x3dec3685, 0xca3949f1, 0x79f3ad1b, 0x3ee8b300, +0x9d305fc6, 0x7a2e5288, 0xbe81a2f2, 0x7ada0c06, +0x191c7f01, 0x58dfcbd1, 0xc78dee72, 0x72364226, +0x1866de12, 0x8d22305c, 0x943a0f0e, 0xc81967ff, +0x4d55fb0f, 0xaf199be1, 0x90bbda61, 0x4e7c234f, +0x90cfec16, 0x9b4bcf26, 0x21622023, 0x0926f0fa, +0x1d504377, 0xa58db427, 0x8d93ce2b, 0x90bfe900, +0x29e67397, 0x2c1261ed, 0x4ace9474, 0xd5c60282, +0xe53fb300, 0x8a61a0ab, 0xa7aa0918, 0x4389d7c5, +0xd09d605c, 0x6c5bedb5, 0xd6d54c51, 0x433dea21, +0x7ad9e677, 0x813bff76, 0x5a162c75, 0x1ee0661f, +0x9b6c2030, 0x8e8dc989, 0xcd4bc9fc, 0x4454675b, +0x8d583c9c, 0xe3400094, 0x116ebb83, 0xe847bc9a, +0x2a4622dd, 0x2a901e6f, 0xd789b1c0, 0x094e2bbb, +0x056e563f, 0x9f17e606, 0x8bc79b8d, 0xd2c535c1, +0x06a45a27, 0x9dc56771, 0xa06649e2, 0x5ff25ac8, +0x6554961e, 0x98e583d9, 0x38ba93da, 0xdee1de18, +0x037cb9d5, 0x6b17f195, 0x3431faaf, 0x13860a0d, +0x28bca10d, 0x0a54c011, 0x9957cdb6, 0x3aa1f429, +0x9d41b7b3, 0x9aea5be2, 0x60c7ce6b, 0x4cd1c10b, +0x24ddddcd, 0xe28412ba, 0xa03a5466, 0xa1896879, +0x59edcb87, 0x1b241765, 0x157bf161, 0xf219f950, +0xe86ff526, 0x262005d9, 0x11769531, 0xbca15d95, +0x28f5ef17, 0x1f27e725, 0xc32631d2, 0x07249e61, +0x1ba851e3, 0x4f49b577, 0xe2a1df5e, 0x826fa7ff, +0xc34e1e2e, 0x7fe26024, 0xbc19800f, 0x0d368dc9, +0xe03da0c6, 0xadaa4f9c, 0x9ad1e43c, 0x96f84e44, +0x0b6cd695, 0x1bb46971, 0x942d6e5b, 0x6316170d, +0x3164509f, 0xc6659450, 0xb2a0370a, 0xabc208e8, +0x6d479811, 0x3684bc0e, 0x80b7b101, 0xa50b7bb5, +0x43d21233, 0xb423559d, 0xf41dcd16, 0xdfd3c276, +0x3e586469, 0xd9b7630a, 0xb88f9e44, 0x0cda6f4d, +0xe5bf5844, 0x8709f788, 0xdae37da6, 0x1fb41777, +0x1d903f69, 0x34383b69, 0xd409ae70, 0xd1c99758, +0xdedfd7a4, 0xa4bdf018, 0xf4058202, 0x8565d66f, +0x5365aed9, 0xfa69742e, 0x2cfbfbcf, 0x88a00b60, +0x506c0713, 0x2866475b, 0x3e1df573, 0xb86f7feb, +0x31d23a7f, 0xc6320e6a, 0x3ebbc2a5, 0x83a1d4ef, +0x15169f5f, 0x42a61753, 0x893e553e, 0x4ddbc66d, +0x7449ec1f, 0x76f65d22, 0x0622e13b, 0x32986f89, +0x21181b4b, 0x99a80c0a, 0xd6fe00b0, 0x282c0e81, +0x9fc1cf88, 0x919b855d, 0x618257d8, 0x82c448b8, +0xe22537a1, 0xa90de388, 0xba73b90c, 0xd765eeb0, +0x62b2727e, 0xa08dfe20, 0x70b3c8c5, 0x3ef04007, +0x9f73732b, 0x2201edd7, 0xb836219c, 0xf913af7c, +0xf50f64ca, 0x93ac107a, 0xf509f84a, 0x6f6026f6, +0xd9bb8eac, 0x4b268cfa, 0xa65a3fa6, 0x9837cb75, +0x784fb835, 0x2060576d, 0xb1604cae, 0xb9da4116, +0xab320cf2, 0x60a1b501, 0x0c73fa79, 0x8d5a6f1e, +0x57688086, 0x218e4005, 0xca054e3d, 0xc1a3c3ec, Added: trunk/src/cpu/intel/model_6bx/model_6bx_init.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/intel/model_6bx/model_6bx_init.c Fri Apr 9 13:10:25 2010 (r5388) @@ -0,0 +1,130 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2010 Joseph Smith <joe(a)settoplinux.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <string.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/lapic.h> +#include <cpu/intel/microcode.h> +#include <cpu/x86/cache.h> +#include <usbdebug_direct.h> + +static const uint32_t microcode_updates[] = { + #include "microcode-737-MU16b11c.h" + #include "microcode-738-MU16b11d.h" + #include "microcode-875-MU16b401.h" + #include "microcode-885-MU16b402.h" + /* Dummy terminator */ + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, + 0x0, 0x0, 0x0, 0x0, +}; + +static inline void strcpy(char *dst, char *src) +{ + while (*src) *dst++ = *src++; +} + +static void fill_processor_name(char *processor_name) +{ + struct cpuid_result regs; + char temp_processor_name[49]; + char *processor_name_start; + unsigned int *name_as_ints = (unsigned int *)temp_processor_name; + int i; + + for (i=0; i<3; i++) { + regs = cpuid(0x80000002 + i); + name_as_ints[i*4 + 0] = regs.eax; + name_as_ints[i*4 + 1] = regs.ebx; + name_as_ints[i*4 + 2] = regs.ecx; + name_as_ints[i*4 + 3] = regs.edx; + } + + temp_processor_name[48] = 0; + + /* Skip leading spaces */ + processor_name_start = temp_processor_name; + while (*processor_name_start == ' ') + processor_name_start++; + + memset(processor_name, 0, 49); + strcpy(processor_name, processor_name_start); +} + +#if CONFIG_USBDEBUG_DIRECT +static unsigned ehci_debug_addr; +#endif + +static void model_6bx_init(device_t cpu) +{ + char processor_name[49]; + + /* Turn on caching if we haven't already */ + x86_enable_cache(); + + /* Update the microcode */ + intel_update_microcode(microcode_updates); + + /* Print processor name */ + fill_processor_name(processor_name); + printk(BIOS_INFO, "CPU: %s.\n", processor_name); + +#if CONFIG_USBDEBUG_DIRECT + // Is this caution really needed? + if(!ehci_debug_addr) + ehci_debug_addr = get_ehci_debug(); + set_ehci_debug(0); +#endif + + /* Setup MTRRs */ + x86_setup_mtrrs(36); + x86_mtrr_check(); + +#if CONFIG_USBDEBUG_DIRECT + set_ehci_debug(ehci_debug_addr); +#endif + + /* Enable the local cpu apics */ + setup_lapic(); +} + +static struct device_operations cpu_dev_ops = { + .init = model_6bx_init, +}; + +static struct cpu_device_id cpu_table[] = { + { X86_VENDOR_INTEL, 0x06B1 }, + { X86_VENDOR_INTEL, 0x06B4 }, /* Low Voltage PIII Micro-FCBGA Socket 479 */ + { 0, 0 }, +}; + +static const struct cpu_driver driver __cpu_driver = { + .ops = &cpu_dev_ops, + .id_table = cpu_table, +}; + Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c Fri Apr 9 12:43:49 2010 (r5387) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c Fri Apr 9 13:10:25 2010 (r5388) @@ -19,7 +19,7 @@ * MA 02110-1301 USA */ - +#include <arch/stages.h> /* called from assembler code */ void stage1_main(unsigned long bist); Added: trunk/src/cpu/intel/socket_mFCBGA479/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/intel/socket_mFCBGA479/Kconfig Fri Apr 9 13:10:25 2010 (r5388) @@ -0,0 +1,5 @@ +config CPU_INTEL_SOCKET_MFCBGA479 + bool + select CPU_INTEL_MODEL_6BX + select MMX + select SSE Added: trunk/src/cpu/intel/socket_mFCBGA479/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/intel/socket_mFCBGA479/Makefile.inc Fri Apr 9 13:10:25 2010 (r5388) @@ -0,0 +1,8 @@ +obj-y += socket_mFCBGA479.o +subdirs-y += ../model_6bx +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/smm +subdirs-y += ../microcode Added: trunk/src/cpu/intel/socket_mFCBGA479/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/intel/socket_mFCBGA479/chip.h Fri Apr 9 13:10:25 2010 (r5388) @@ -0,0 +1,4 @@ +extern struct chip_operations cpu_intel_socket_mFCBGA479_ops; + +struct cpu_intel_socket_mFCBGA479_config { +}; Added: trunk/src/cpu/intel/socket_mFCBGA479/socket_mFCBGA479.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/cpu/intel/socket_mFCBGA479/socket_mFCBGA479.c Fri Apr 9 13:10:25 2010 (r5388) @@ -0,0 +1,6 @@ +#include <device/device.h> +#include "chip.h" + +struct chip_operations cpu_intel_socket_mFCBGA479_ops = { + CHIP_NAME("Micro-FCBGA 479 CPU") +}; Modified: trunk/src/include/cbfs.h ============================================================================== --- trunk/src/include/cbfs.h Fri Apr 9 12:43:49 2010 (r5387) +++ trunk/src/include/cbfs.h Fri Apr 9 13:10:25 2010 (r5388) @@ -171,7 +171,5 @@ int run_address(void *f); struct cbfs_file *cbfs_find(const char *name); void *cbfs_find_file(const char *name, int type); -void cbfs_and_run_core(const char *filename, unsigned int ebp); - #endif Modified: trunk/src/mainboard/rca/rm4100/Kconfig ============================================================================== --- trunk/src/mainboard/rca/rm4100/Kconfig Fri Apr 9 12:43:49 2010 (r5387) +++ trunk/src/mainboard/rca/rm4100/Kconfig Fri Apr 9 13:10:25 2010 (r5388) @@ -1,18 +1,20 @@ config BOARD_RCA_RM4100 bool "RM4100" select ARCH_X86 - select CPU_INTEL_SOCKET_PGA370 + select CPU_INTEL_SOCKET_MFCBGA479 select NORTHBRIDGE_INTEL_I82830 select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_SMSCSUPERIO - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC - select BOARD_ROMSIZE_KB_1024 - select HAVE_MAINBOARD_RESOURCES + select BOARD_ROMSIZE_KB_1024 select HAVE_HARD_RESET + select HAVE_MAINBOARD_RESOURCES + select USE_PRINTK_IN_CAR select HAVE_SMI_HANDLER - select GFXUMA + select GFXUMA + select USE_DCACHE_RAM + select TINY_BOOTBLOCK config MAINBOARD_DIR string @@ -29,6 +31,16 @@ default n depends on BOARD_RCA_RM4100 +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + depends on BOARD_RCA_RM4100 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_RCA_RM4100 + config IRQ_SLOT_COUNT int default 7 Modified: trunk/src/mainboard/rca/rm4100/Makefile.inc ============================================================================== --- trunk/src/mainboard/rca/rm4100/Makefile.inc Fri Apr 9 12:43:49 2010 (r5387) +++ trunk/src/mainboard/rca/rm4100/Makefile.inc Fri Apr 9 13:10:25 2010 (r5388) @@ -1,4 +1,2 @@ -ROMCCFLAGS=-mcpu=p3 -O - smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o Modified: trunk/src/mainboard/rca/rm4100/devicetree.cb ============================================================================== --- trunk/src/mainboard/rca/rm4100/devicetree.cb Fri Apr 9 12:43:49 2010 (r5387) +++ trunk/src/mainboard/rca/rm4100/devicetree.cb Fri Apr 9 13:10:25 2010 (r5388) @@ -1,6 +1,6 @@ chip northbridge/intel/i82830 # Northbridge device apic_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # Mobile Celeron Micro-FCBGA Socket 479 + chip cpu/intel/socket_mFCBGA479 # Mobile Celeron Micro-FCBGA Socket 479 device apic 0 on end # APIC end end Modified: trunk/src/mainboard/rca/rm4100/romstage.c ============================================================================== --- trunk/src/mainboard/rca/rm4100/romstage.c Fri Apr 9 12:43:49 2010 (r5387) +++ trunk/src/mainboard/rca/rm4100/romstage.c Fri Apr 9 13:10:25 2010 (r5388) @@ -34,7 +34,6 @@ #include "northbridge/intel/i82830/memory_initialized.c" #include "southbridge/intel/i82801dx/i82801dx.h" #include "southbridge/intel/i82801dx/i82801dx_reset.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "spd_table.h" #include "gpio.c" @@ -98,10 +97,11 @@ pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10); } -static void main(unsigned long bist) +#include "cpu/intel/model_6bx/cache_as_ram_disable.c" + +void real_main(unsigned long bist) { if (bist == 0) { - early_mtrr_init(); if (memory_initialized()) { hard_reset(); } Modified: trunk/src/mainboard/thomson/ip1000/Kconfig ============================================================================== --- trunk/src/mainboard/thomson/ip1000/Kconfig Fri Apr 9 12:43:49 2010 (r5387) +++ trunk/src/mainboard/thomson/ip1000/Kconfig Fri Apr 9 13:10:25 2010 (r5388) @@ -1,18 +1,20 @@ config BOARD_THOMSON_IP1000 bool "IP1000" select ARCH_X86 - select CPU_INTEL_SOCKET_PGA370 + select CPU_INTEL_SOCKET_MFCBGA479 select NORTHBRIDGE_INTEL_I82830 select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_SMSCSUPERIO - select ROMCC select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_512 select HAVE_HARD_RESET select HAVE_MAINBOARD_RESOURCES + select USE_PRINTK_IN_CAR select HAVE_SMI_HANDLER select GFXUMA + select USE_DCACHE_RAM + select TINY_BOOTBLOCK config MAINBOARD_DIR string @@ -29,6 +31,16 @@ default n depends on BOARD_THOMSON_IP1000 +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + depends on BOARD_THOMSON_IP1000 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_THOMSON_IP1000 + config IRQ_SLOT_COUNT int default 7 Modified: trunk/src/mainboard/thomson/ip1000/Makefile.inc ============================================================================== --- trunk/src/mainboard/thomson/ip1000/Makefile.inc Fri Apr 9 12:43:49 2010 (r5387) +++ trunk/src/mainboard/thomson/ip1000/Makefile.inc Fri Apr 9 13:10:25 2010 (r5388) @@ -1,4 +1,2 @@ -ROMCCFLAGS=-mcpu=p3 -O - smmobj-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.o Modified: trunk/src/mainboard/thomson/ip1000/devicetree.cb ============================================================================== --- trunk/src/mainboard/thomson/ip1000/devicetree.cb Fri Apr 9 12:43:49 2010 (r5387) +++ trunk/src/mainboard/thomson/ip1000/devicetree.cb Fri Apr 9 13:10:25 2010 (r5388) @@ -1,6 +1,6 @@ chip northbridge/intel/i82830 # Northbridge device apic_cluster 0 on # APIC cluster - chip cpu/intel/socket_PGA370 # Low Voltage PIII Micro-FCBGA Socket 479 + chip cpu/intel/socket_mFCBGA479 # Low Voltage PIII Micro-FCBGA Socket 479 device apic 0 on end # APIC end end Modified: trunk/src/mainboard/thomson/ip1000/romstage.c ============================================================================== --- trunk/src/mainboard/thomson/ip1000/romstage.c Fri Apr 9 12:43:49 2010 (r5387) +++ trunk/src/mainboard/thomson/ip1000/romstage.c Fri Apr 9 13:10:25 2010 (r5388) @@ -35,7 +35,6 @@ #include "northbridge/intel/i82830/memory_initialized.c" #include "southbridge/intel/i82801dx/i82801dx.h" #include "southbridge/intel/i82801dx/i82801dx_reset.c" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "spd_table.h" #include "gpio.c" @@ -97,10 +96,11 @@ pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10); } -static void main(unsigned long bist) +#include "cpu/intel/model_6bx/cache_as_ram_disable.c" + +void real_main(unsigned long bist) { if (bist == 0) { - early_mtrr_init(); if (memory_initialized()) { hard_reset(); } Modified: trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Fri Apr 9 12:43:49 2010 (r5387) +++ trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Fri Apr 9 13:10:25 2010 (r5388) @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <arch/stages.h> + //0: mean no debug info #define DQS_TRAIN_DEBUG 0 @@ -2091,7 +2093,7 @@ sysinfox->mem_trained[nodeid] = sysinfo->mem_trained[nodeid]; } -static void copy_and_run_ap_code_in_car(unsigned ret_addr); + static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) { if(coreid) return; // only do it on core0 Modified: trunk/src/northbridge/intel/i82830/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i82830/raminit.c Fri Apr 9 12:43:49 2010 (r5387) +++ trunk/src/northbridge/intel/i82830/raminit.c Fri Apr 9 13:10:25 2010 (r5388) @@ -191,8 +191,8 @@ -----------------------------------------------------------------------------*/ struct dimm_size { - unsigned long side1; - unsigned long side2; + unsigned int side1; + unsigned int side2; }; static struct dimm_size spd_get_dimm_size(unsigned device) @@ -541,7 +541,6 @@ static void sdram_initialize(void) { - int i; u32 reg32; /* Setup Initial SDRAM Registers */ Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c Fri Apr 9 12:43:49 2010 (r5387) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c Fri Apr 9 13:10:25 2010 (r5388) @@ -115,7 +115,6 @@ static int smbus_read_byte(unsigned device, unsigned address) { - unsigned char global_control_register; unsigned char global_status_register; unsigned char byte; Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c Fri Apr 9 12:43:49 2010 (r5387) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_tco_timer.c Fri Apr 9 13:10:25 2010 (r5388) @@ -21,11 +21,8 @@ static void i82801dx_halt_tco_timer(void) { - device_t dev; - uint16_t halt_tco_timer; - /* Set the LPC device statically. */ - dev = PCI_DEV(0x0, 0x1f, 0x0); + device_t dev = PCI_DEV(0x0, 0x1f, 0x0); /* Temporarily set ACPI base address (I/O space). */ pci_write_config32(dev, PMBASE, (PMBASE_ADDR | 1));

3 2

[commit] r5395 - in trunk/src/arch/i386: . lib
by repository service 09 Apr '10

09 Apr '10

Author: stepan Date: Fri Apr 9 15:49:48 2010 New Revision: 5395 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5395 Log: drop now unussed cpu_reset.inc make it more clear if coreboot is building without payload. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Deleted: trunk/src/arch/i386/lib/cpu_reset.inc Modified: trunk/src/arch/i386/Makefile.inc Modified: trunk/src/arch/i386/Makefile.inc ============================================================================== --- trunk/src/arch/i386/Makefile.inc Fri Apr 9 15:35:03 2010 (r5394) +++ trunk/src/arch/i386/Makefile.inc Fri Apr 9 15:49:48 2010 (r5395) @@ -35,7 +35,7 @@ fi $(CBFSTOOL) $@.tmp add-stage $(obj)/coreboot_ram $(CONFIG_CBFS_PREFIX)/coreboot_ram $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) - printf " PAYLOAD none (as specified by user)\n" + printf " PAYLOAD \e[1;31mnone (as specified by user)\e[0m\n" else printf " PAYLOAD $(CONFIG_FALLBACK_PAYLOAD_FILE) $(CBFS_PAYLOAD_COMPRESS_FLAG)\n" $(CBFSTOOL) $@.tmp add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE) $(CONFIG_CBFS_PREFIX)/payload $(CBFS_PAYLOAD_COMPRESS_FLAG) @@ -112,9 +112,6 @@ ifeq ($(CONFIG_BIG_BOOTBLOCK),y) crt0s += $(src)/cpu/x86/16bit/reset16.inc ldscripts += $(src)/cpu/x86/16bit/reset16.lds -ifeq ($(CONFIG_ROMCC),y) -crt0s += $(src)/arch/i386/lib/cpu_reset.inc -endif crt0s += $(src)/arch/i386/lib/id.inc ldscripts += $(src)/arch/i386/lib/id.lds endif

1 0

[commit] r5394 - in trunk/src: northbridge/amd/amdfam10 northbridge/amd/amdht northbridge/amd/amdmct/mct southbridge/amd/amd8111 southbridge/amd/sb700
by repository service 09 Apr '10

09 Apr '10

Author: stepan Date: Fri Apr 9 15:35:03 2010 New Revision: 5394 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5394 Log: zero warnings days. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/amd/amdfam10/northbridge.h trunk/src/northbridge/amd/amdht/h3ncmn.c trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c trunk/src/northbridge/amd/amdmct/mct/mctsrc1p.c trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c trunk/src/southbridge/amd/sb700/sb700_reset.c Modified: trunk/src/northbridge/amd/amdfam10/northbridge.h ============================================================================== --- trunk/src/northbridge/amd/amdfam10/northbridge.h Fri Apr 9 15:33:59 2010 (r5393) +++ trunk/src/northbridge/amd/amdfam10/northbridge.h Fri Apr 9 15:35:03 2010 (r5394) @@ -20,6 +20,6 @@ #ifndef NORTHBRIDGE_AMD_AMDFAM10_H #define NORTHBRIDGE_AMD_AMDFAM10_H -extern u32 amdfam10_scan_root_bus(device_t root, u32 max); +u32 amdfam10_scan_root_bus(device_t root, u32 max); #endif /* NORTHBRIDGE_AMD_AMDFAM10_H */ Modified: trunk/src/northbridge/amd/amdht/h3ncmn.c ============================================================================== --- trunk/src/northbridge/amd/amdht/h3ncmn.c Fri Apr 9 15:33:59 2010 (r5393) +++ trunk/src/northbridge/amd/amdht/h3ncmn.c Fri Apr 9 15:35:03 2010 (r5394) @@ -166,7 +166,7 @@ /**---------------------------------------------------------------------------------------- * - * void + * static void * writeRoutingTable(u8 node, u8 target, u8 Link, cNorthBridge *nb) * * Description: @@ -188,7 +188,7 @@ * --------------------------------------------------------------------------------------- */ -void writeRoutingTable(u8 node, u8 target, u8 link, cNorthBridge *nb) +static void writeRoutingTable(u8 node, u8 target, u8 link, cNorthBridge *nb) { #ifndef HT_BUILD_NC_ONLY u32 temp = (nb->selfRouteResponseMask | nb->selfRouteRequestMask) << (link + 1); @@ -206,7 +206,7 @@ /**---------------------------------------------------------------------------------------- * - * void + * static void * writeNodeID(u8 node, u8 nodeID, cNorthBridge *nb) * * Description: @@ -220,7 +220,7 @@ * --------------------------------------------------------------------------------------- */ -void writeNodeID(u8 node, u8 nodeID, cNorthBridge *nb) +static void writeNodeID(u8 node, u8 nodeID, cNorthBridge *nb) { u32 temp = nodeID; ASSERT((node < nb->maxNodes) && (nodeID < nb->maxNodes)); @@ -234,7 +234,7 @@ /**---------------------------------------------------------------------------------------- * - * void + * static void * readDefLnk(u8 node, cNorthBridge *nb) * * Description: @@ -252,7 +252,7 @@ * --------------------------------------------------------------------------------------- */ -u8 readDefLnk(u8 node, cNorthBridge *nb) +static u8 readDefLnk(u8 node, cNorthBridge *nb) { u32 deflink = 0; SBDFO licr; @@ -273,7 +273,7 @@ /**---------------------------------------------------------------------------------------- * - * void + * static void * enableRoutingTables(u8 node, cNorthBridge *nb) * * Description: @@ -286,7 +286,7 @@ * --------------------------------------------------------------------------------------- */ -void enableRoutingTables(u8 node, cNorthBridge *nb) +static void enableRoutingTables(u8 node, cNorthBridge *nb) { u32 temp = 0; ASSERT((node < nb->maxNodes)); @@ -301,7 +301,7 @@ /**---------------------------------------------------------------------------------------- * - * void + * static BOOL * verifyLinkIsCoherent(u8 node, u8 Link, cNorthBridge *nbk) * * Description: @@ -322,7 +322,7 @@ * --------------------------------------------------------------------------------------- */ -BOOL verifyLinkIsCoherent(u8 node, u8 link, cNorthBridge *nb) +static BOOL verifyLinkIsCoherent(u8 node, u8 link, cNorthBridge *nb) { #ifndef HT_BUILD_NC_ONLY @@ -345,7 +345,7 @@ /**---------------------------------------------------------------------------------------- * - * bool + * static bool * readTrueLinkFailStatus(u8 node, u8 link, sMainData *pDat, cNorthBridge *nb) * * Description: @@ -371,7 +371,7 @@ * * --------------------------------------------------------------------------------------- */ -BOOL readTrueLinkFailStatus(u8 node, u8 link, sMainData *pDat, cNorthBridge *nb) +static BOOL readTrueLinkFailStatus(u8 node, u8 link, sMainData *pDat, cNorthBridge *nb) { u32 before, after, unconnected, crc; SBDFO linkBase; @@ -436,7 +436,7 @@ /**---------------------------------------------------------------------------------------- * - * u8 + * static u8 * readToken(u8 node, cNorthBridge *nb) * * Description: @@ -452,7 +452,7 @@ * * --------------------------------------------------------------------------------------- */ -u8 readToken(u8 node, cNorthBridge *nb) +static u8 readToken(u8 node, cNorthBridge *nb) { u32 temp; @@ -472,7 +472,7 @@ /**---------------------------------------------------------------------------------------- * - * void + * static void * writeToken(u8 node, u8 Value, cNorthBridge *nb) * * Description: @@ -488,7 +488,7 @@ * * --------------------------------------------------------------------------------------- */ -void writeToken(u8 node, u8 value, cNorthBridge *nb) +static void writeToken(u8 node, u8 value, cNorthBridge *nb) { u32 temp = value; ASSERT((node < nb->maxNodes)); @@ -504,7 +504,7 @@ /**---------------------------------------------------------------------------------------- * - * u8 + * static u8 * fam0FGetNumCoresOnNode(u8 node, cNorthBridge *nb) * * Description: @@ -517,7 +517,7 @@ * * --------------------------------------------------------------------------------------- */ -u8 fam0FGetNumCoresOnNode(u8 node, cNorthBridge *nb) +static u8 fam0FGetNumCoresOnNode(u8 node, cNorthBridge *nb) { u32 temp; @@ -536,7 +536,7 @@ /**---------------------------------------------------------------------------------------- * - * u8 + * static u8 * fam10GetNumCoresOnNode(u8 node, cNorthBridge *nb) * * Description: @@ -549,7 +549,7 @@ * * --------------------------------------------------------------------------------------- */ -u8 fam10GetNumCoresOnNode(u8 node, cNorthBridge *nb) +static u8 fam10GetNumCoresOnNode(u8 node, cNorthBridge *nb) { u32 temp, leveling, cores; u8 i; @@ -583,7 +583,7 @@ /**---------------------------------------------------------------------------------------- * - * void + * static void * setTotalNodesAndCores(u8 node, u8 totalNodes, u8 totalCores, cNorthBridge *nb) * * Description: @@ -597,7 +597,7 @@ * * --------------------------------------------------------------------------------------- */ -void setTotalNodesAndCores(u8 node, u8 totalNodes, u8 totalCores, cNorthBridge *nb) +static void setTotalNodesAndCores(u8 node, u8 totalNodes, u8 totalCores, cNorthBridge *nb) { SBDFO nodeIDReg; u32 temp; @@ -621,7 +621,7 @@ /**---------------------------------------------------------------------------------------- * - * void + * static void * limitNodes(u8 node, cNorthBridge *nb) * * Description: @@ -633,7 +633,7 @@ * * --------------------------------------------------------------------------------------- */ -void limitNodes(u8 node, cNorthBridge *nb) +static void limitNodes(u8 node, cNorthBridge *nb) { u32 temp = 1; ASSERT((node < nb->maxNodes)); @@ -647,7 +647,7 @@ /**---------------------------------------------------------------------------------------- * - * void + * static void * writeFullRoutingTable(u8 node, u8 target, u8 reqLink, u8 rspLink, u32 BClinks, cNorthBridge *nb) * * Description: @@ -664,7 +664,7 @@ * * --------------------------------------------------------------------------------------- */ -void writeFullRoutingTable(u8 node, u8 target, u8 reqLink, u8 rspLink, u32 bClinks, cNorthBridge *nb) +static void writeFullRoutingTable(u8 node, u8 target, u8 reqLink, u8 rspLink, u32 bClinks, cNorthBridge *nb) { #ifndef HT_BUILD_NC_ONLY u32 value = 0; @@ -732,7 +732,7 @@ /**---------------------------------------------------------------------------------------- * - * BOOL + * static BOOL * isCompatible(u8 currentNode, cNorthBridge *nb) * * Description: @@ -747,14 +747,14 @@ * * --------------------------------------------------------------------------------------- */ -BOOL isCompatible(u8 node, cNorthBridge *nb) +static BOOL isCompatible(u8 node, cNorthBridge *nb) { return (makeKey(node) == nb->compatibleKey); } /**---------------------------------------------------------------------------------------- * - * BOOL + * static BOOL * fam0fIsCapable(u8 node, sMainData *pDat, cNorthBridge *nb) * * Description: @@ -770,7 +770,7 @@ * * --------------------------------------------------------------------------------------- */ -BOOL fam0fIsCapable(u8 node, sMainData *pDat, cNorthBridge *nb) +static BOOL fam0fIsCapable(u8 node, sMainData *pDat, cNorthBridge *nb) { #ifndef HT_BUILD_NC_ONLY u32 temp; @@ -808,7 +808,7 @@ /**---------------------------------------------------------------------------------------- * - * BOOL + * static BOOL * fam10IsCapable(u8 node, sMainData *pDat, cNorthBridge *nb) * * Description: @@ -824,7 +824,7 @@ * * --------------------------------------------------------------------------------------- */ -BOOL fam10IsCapable(u8 node, sMainData *pDat, cNorthBridge *nb) +static BOOL fam10IsCapable(u8 node, sMainData *pDat, cNorthBridge *nb) { #ifndef HT_BUILD_NC_ONLY u32 temp; @@ -861,7 +861,7 @@ /**---------------------------------------------------------------------------------------- * - * void + * static void * fam0fStopLink(u8 currentNode, u8 currentLink, cNorthBridge *nb) * * Description: @@ -874,7 +874,7 @@ * * --------------------------------------------------------------------------------------- */ -void fam0fStopLink(u8 node, u8 link, cNorthBridge *nb) +static void fam0fStopLink(u8 node, u8 link, cNorthBridge *nb) { #ifndef HT_BUILD_NC_ONLY u32 temp; @@ -892,7 +892,7 @@ /**---------------------------------------------------------------------------------------- * - * void + * static void * commonVoid() * * Description: @@ -903,13 +903,13 @@ * * --------------------------------------------------------------------------------------- */ -void commonVoid() +static void commonVoid(void) { } /**---------------------------------------------------------------------------------------- * - * BOOL + * static BOOL * commonReturnFalse() * * Description: @@ -919,7 +919,7 @@ * @param[out] BOOL result = false * --------------------------------------------------------------------------------------- */ -BOOL commonReturnFalse() +static BOOL commonReturnFalse(void) { return 0; } @@ -931,7 +931,7 @@ /**---------------------------------------------------------------------------------------- * - * u8 + * static u8 * readSbLink(cNorthBridge *nb) * * Description: @@ -943,7 +943,7 @@ * * --------------------------------------------------------------------------------------- */ -u8 readSbLink(cNorthBridge *nb) +static u8 readSbLink(cNorthBridge *nb) { u32 temp; AmdPCIReadBits(MAKE_SBDFO(makePCISegmentFromNode(0), @@ -957,7 +957,7 @@ /**---------------------------------------------------------------------------------------- * - * BOOL + * static BOOL * verifyLinkIsNonCoherent(u8 node, u8 link, cNorthBridge *nb) * * Description: @@ -977,7 +977,7 @@ * * --------------------------------------------------------------------------------------- */ -BOOL verifyLinkIsNonCoherent(u8 node, u8 link, cNorthBridge *nb) +static BOOL verifyLinkIsNonCoherent(u8 node, u8 link, cNorthBridge *nb) { u32 linkType; SBDFO linkBase; @@ -995,7 +995,7 @@ /**---------------------------------------------------------------------------------------- * - * void + * static void * ht3SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb) * * Description: @@ -1012,7 +1012,7 @@ * * --------------------------------------------------------------------------------------- */ -void ht3SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb) +static void ht3SetCFGAddrMap(u8 cfgMapIndex, u8 secBus, u8 subBus, u8 targetNode, u8 targetLink, sMainData *pDat, cNorthBridge *nb) { u8 curNode; SBDFO linkBase; @@ -1094,7 +1094,7 @@ /**---------------------------------------------------------------------------------------- * - * u8 + * static u8 * convertBitsToWidth(u8 value, cNorthBridge *nb) * * Description: @@ -1107,7 +1107,7 @@ * * --------------------------------------------------------------------------------------- */ -u8 convertBitsToWidth(u8 value, cNorthBridge *nb) +static u8 convertBitsToWidth(u8 value, cNorthBridge *nb) { switch(value) { case 1: return 16; @@ -1121,7 +1121,7 @@ /**---------------------------------------------------------------------------------------- * - * u8 + * static u8 * convertWidthToBits(u8 value, cNorthBridge *nb) * * Description: @@ -1134,7 +1134,7 @@ * * --------------------------------------------------------------------------------------- */ -u8 convertWidthToBits(u8 value, cNorthBridge *nb) +static u8 convertWidthToBits(u8 value, cNorthBridge *nb) { switch (value) { case 16: return 1; @@ -1148,7 +1148,7 @@ /**---------------------------------------------------------------------------------------- * - * u16 + * static u16 * ht1NorthBridgeFreqMask(u8 NodeID, cNorthBridge *nb) * * Description: @@ -1162,7 +1162,7 @@ * * --------------------------------------------------------------------------------------- */ -u16 ht1NorthBridgeFreqMask(u8 node, cNorthBridge *nb) +static u16 ht1NorthBridgeFreqMask(u8 node, cNorthBridge *nb) { /* only up to HT1 speeds */ return (HT_FREQUENCY_LIMIT_HT1_ONLY); @@ -1170,7 +1170,7 @@ /**---------------------------------------------------------------------------------------- * - * u16 + * static u16 * fam10NorthBridgeFreqMask(u8 NodeID, cNorthBridge *nb) * * Description: @@ -1184,7 +1184,7 @@ * * --------------------------------------------------------------------------------------- */ -u16 fam10NorthBridgeFreqMask(u8 node, cNorthBridge *nb) +static u16 fam10NorthBridgeFreqMask(u8 node, cNorthBridge *nb) { u8 nbCOF; u16 supported; @@ -1225,7 +1225,7 @@ /**---------------------------------------------------------------------------------------- * - * void + * static void * gatherLinkData(sMainData *pDat, cNorthBridge *nb) * * Description: @@ -1238,7 +1238,7 @@ * * --------------------------------------------------------------------------------------- */ -void gatherLinkData(sMainData *pDat, cNorthBridge *nb) +static void gatherLinkData(sMainData *pDat, cNorthBridge *nb) { u8 i; SBDFO linkBase; @@ -1301,7 +1301,7 @@ /**---------------------------------------------------------------------------------------- * - * void + * static void * setLinkData(sMainData *pDat, cNorthBridge *nb) * * Description: @@ -1314,7 +1314,7 @@ * * --------------------------------------------------------------------------------------- */ -void setLinkData(sMainData *pDat, cNorthBridge *nb) +static void setLinkData(sMainData *pDat, cNorthBridge *nb) { u8 i; SBDFO linkBase; @@ -1614,7 +1614,7 @@ /**---------------------------------------------------------------------------------------- * - * void + * static void * ht3WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge *nb) * * Description: @@ -1627,7 +1627,7 @@ * * --------------------------------------------------------------------------------------- */ -void ht3WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge *nb) +static void ht3WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge *nb) { #ifndef HT_BUILD_NC_ONLY u32 temp; @@ -1670,7 +1670,7 @@ /**---------------------------------------------------------------------------------------- * - * void + * static void * ht1WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge *nb) * * Description: @@ -1685,7 +1685,7 @@ * * --------------------------------------------------------------------------------------- */ -void ht1WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge *nb) +static void ht1WriteTrafficDistribution(u32 links01, u32 links10, cNorthBridge *nb) { #ifndef HT_BUILD_NC_ONLY u32 route01, route10; @@ -1779,7 +1779,7 @@ /**---------------------------------------------------------------------------------------- * - * void + * static void * fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) * * Description: @@ -1793,7 +1793,7 @@ * * --------------------------------------------------------------------------------------- */ -void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) +static void fam0fBufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) { #ifndef HT_BUILD_NC_ONLY u8 i; @@ -1976,7 +1976,7 @@ /**---------------------------------------------------------------------------------------- * - * void + * static void * fam10BufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) * * Description: @@ -1990,7 +1990,7 @@ * * --------------------------------------------------------------------------------------- */ -void fam10BufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) +static void fam10BufferOptimizations(u8 node, sMainData *pDat, cNorthBridge *nb) { u32 temp; SBDFO currentPtr; Modified: trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c Fri Apr 9 15:33:59 2010 (r5393) +++ trunk/src/northbridge/amd/amdmct/mct/mctdqs_d.c Fri Apr 9 15:35:03 2010 (r5394) @@ -1183,7 +1183,7 @@ } -void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, +static void mct_Write1LTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u32 TestAddr, u8 pattern) { Modified: trunk/src/northbridge/amd/amdmct/mct/mctsrc1p.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctsrc1p.c Fri Apr 9 15:33:59 2010 (r5393) +++ trunk/src/northbridge/amd/amdmct/mct/mctsrc1p.c Fri Apr 9 15:35:03 2010 (r5394) @@ -44,7 +44,7 @@ return 0; } -u8 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel, u8 Receiver, +static u8 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel, u8 Receiver, u8 Pass) { u8 i, MaxValue; @@ -72,7 +72,7 @@ -u8 mct_AdjustFinalDQSRcvValue_1Pass(u8 val_1p, u8 val_2p) +static u8 mct_AdjustFinalDQSRcvValue_1Pass(u8 val_1p, u8 val_2p) { return (val_1p & 0xff) + ((val_2p & 0xff)<<8); } Modified: trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c ============================================================================== --- trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c Fri Apr 9 15:33:59 2010 (r5393) +++ trunk/src/southbridge/amd/amd8111/amd8111_early_ctrl.c Fri Apr 9 15:35:03 2010 (r5394) @@ -1,3 +1,5 @@ +#include <reset.h> + /* by yhlu 2005.10 */ static unsigned get_sbdn(unsigned bus) { Modified: trunk/src/southbridge/amd/sb700/sb700_reset.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_reset.c Fri Apr 9 15:33:59 2010 (r5393) +++ trunk/src/southbridge/amd/sb700/sb700_reset.c Fri Apr 9 15:35:03 2010 (r5394) @@ -17,38 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <reset.h> #include <arch/io.h> - -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) - -typedef u32 device_t; - -static void pci_write_config8(device_t dev, unsigned where, unsigned char value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); -} - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(device_t dev, unsigned where) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} +#include <arch/romcc_io.h> #include "../../../northbridge/amd/amdk8/reset_test.c"

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coreboot April 2010