coreboot April 2010

coreboot@coreboot.org

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402 discussions

[FILO] r124 - trunk/filo
by repository service 11 Apr '10

11 Apr '10

Author: stepan Date: Sun Apr 11 13:37:06 2010 New Revision: 124 URL: http://tracker.coreboot.org/trac/filo/changeset/124 Log: - drop duplicate .config - print an explicit message instead of bailing out with 2 pages of errors if there is no libpayload installed. The check could be better but it's a start. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/filo/Makefile Modified: trunk/filo/Makefile ============================================================================== --- trunk/filo/Makefile Sun Apr 11 13:34:44 2010 (r123) +++ trunk/filo/Makefile Sun Apr 11 13:37:06 2010 (r124) @@ -99,9 +99,13 @@ TARGET = $(obj)/filo.elf -include $(src)/.config - +HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD)) +ifeq ($(strip $(HAVE_LIBPAYLOAD)),) +all: + @printf "\nError: libpayload is not installed!\nexpected: $(LIBPAYLOAD).\n" +else all: prepare $(obj)/version.h $(TARGET) +endif $(obj)/filo: $(src)/.config $(OBJS) $(Q)printf " LD $(subst $(shell pwd)/,,$(@))\n"

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filo-squash build patch
by baiyin cai 11 Apr '10

11 Apr '10

hi, it seem there is no "shared.h" under filo/fs/ which included in squashfs_zilb.c which would caused build error while open FSYS_SQUASHFS. it seems also useless. just remove the declaration. signed-off-by Cai Bai Yin <caibaiyin.pku(a)gmail.com>

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[FILO] r123 - trunk/filo/fs
by repository service 11 Apr '10

11 Apr '10

Author: stepan Date: Sun Apr 11 13:34:44 2010 New Revision: 123 URL: http://tracker.coreboot.org/trac/filo/changeset/123 Log: squashfs_zilb.c included shared.h which was not there (anymore?) it seems also useless. just remove the include. Signed-off-by: Cai Bai Yin <caibaiyin.pku(a)gmail.com> Modified: trunk/filo/fs/squashfs_zlib.c Modified: trunk/filo/fs/squashfs_zlib.c ============================================================================== --- trunk/filo/fs/squashfs_zlib.c Fri Apr 2 18:18:59 2010 (r122) +++ trunk/filo/fs/squashfs_zlib.c Sun Apr 11 13:34:44 2010 (r123) @@ -18,7 +18,6 @@ #include <lib.h> -#include "shared.h" #include "squashfs_zlib.h"

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Re: [coreboot] Nokia IP530 (firewall) motherbord wih PIII, i440BX, 4nic's and PCMCIA
by Stefan Reinauer 10 Apr '10

10 Apr '10

On 4/10/10 1:06 PM, Marc Bertens wrote: > Op zaterdag 10-04-2010 om 12:55 uur [tijdzone +0200], schreef Stefan > Reinauer: > >> dumping mptable + pirq with the originally installed bios? >> > yes, but running the mptable tool give an error like that i should try > the -grope option, but i was already using this :-( > > the pirq tables where extracted and are already in my coreboot build. > What about dumping the ACPI tables? Does that work? Your pirq table is probably wrong. Check the boot log and lspci -vvv for differences. Stefan

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Nokia IP530 (firewall) motherbord wih PIII, i440BX, 4nic's and PCMCIA
by Marc Bertens 10 Apr '10

10 Apr '10

Hi all, currently i have coreboot, seabios and sgabios running on Nokia IP530 (firewall) motherbord wih PIII, i440BX. and that works great, with alot of help already from the #coreboot and #flashrom irc rooms and all the people there, for that thanks. But here is the problem, the NICs and PCMCIA are not working. I attached a logging with the startup sequence of coreboot, seabios, sgabios and debian linux 5.0.4. a output lppci -vv and dmesg. i hope that someone can help me with this to get it working. Kind regards, Marc Bertens

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[commit] r5401 - trunk/src/mainboard/asrock/939a785gmh
by repository service 10 Apr '10

10 Apr '10

Author: oxygene Date: Sat Apr 10 00:25:27 2010 New Revision: 5401 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5401 Log: We don't define LB_CKS_* per board anymore: build_opt_tbl figures them out for us. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/mainboard/asrock/939a785gmh/Kconfig Modified: trunk/src/mainboard/asrock/939a785gmh/Kconfig ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/Kconfig Fri Apr 9 23:05:36 2010 (r5400) +++ trunk/src/mainboard/asrock/939a785gmh/Kconfig Sat Apr 10 00:25:27 2010 (r5401) @@ -52,16 +52,6 @@ default 0x0 depends on BOARD_ASROCK_939A785GMH -config LB_CKS_RANGE_END - int - default 122 - depends on BOARD_ASROCK_939A785GMH - -config LB_CKS_LOC - int - default 123 - depends on BOARD_ASROCK_939A785GMH - config MAINBOARD_PART_NUMBER string default "939A785GMH"

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Infrastructure Projects
by Stefan Reinauer 09 Apr '10

09 Apr '10

Hi, I just updated our central upcoming infrastructure changes list. http://www.coreboot.org/Infrastructure_Projects If you can / want to work on any of these issues, step up now :-) It's essential that we drop as many special cases from the code as possible and only let new ones in if there is no better way. Also, please help completing the list. Stefan

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[commit] r5400 - trunk/src/cpu/amd/model_lx
by repository service 09 Apr '10

09 Apr '10

Author: stepan Date: Fri Apr 9 23:05:36 2010 New Revision: 5400 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5400 Log: Drop ASM_CONSOLE_LOGLEVEL from LX car code. We do output in C in copy_and_run / later. Call copy_and_run instead of cbfs_and_run_core because we can choose the coreboot_ram filename in C instead of Assembler. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/cpu/amd/model_lx/cache_as_ram.inc Modified: trunk/src/cpu/amd/model_lx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/amd/model_lx/cache_as_ram.inc Fri Apr 9 22:36:29 2010 (r5399) +++ trunk/src/cpu/amd/model_lx/cache_as_ram.inc Fri Apr 9 23:05:36 2010 (r5400) @@ -17,10 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef ASM_CONSOLE_LOGLEVEL -#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -#endif - #define LX_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */ #define LX_STACK_END LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1) @@ -204,13 +200,11 @@ /* clear boot_complete flag */ xorl %ebp, %ebp __main: + post_code(0x11) /* post 11 */ - /* - * Copy data into RAM and clear the BSS. Since these segments - * isn\'t really that big we just copy/clear using bytes, not - * double words. + /* TODO For suspend/resume the cache will have to live between + * CONFIG_RAMBASE and CONFIG_RAMTOP */ - post_code(0x11) /* post 11 */ cld /* clear direction flag */ @@ -220,67 +214,10 @@ */ movl %ebp, %esi pushl %esi - pushl $str_coreboot_ram_name - call cbfs_and_run_core + call copy_and_run .Lhlt: post_code(0xee) /* post fail ee */ hlt jmp .Lhlt -#ifdef __CRT_CONSOLE_TX_STRING - /* Uses esp, ebx, ax, dx */ -crt_console_tx_string: - mov (%ebx), %al - inc %ebx - cmp $0, %al - jne 9f - RETSP -9: -/* Base Address */ -#ifndef CONFIG_TTYS0_BASE -#define CONFIG_TTYS0_BASE 0x3f8 -#endif -/* Data */ -#define TTYS0_RBR (CONFIG_TTYS0_BASE+0x00) - -/* Control */ -#define TTYS0_TBR TTYS0_RBR -#define TTYS0_IER (CONFIG_TTYS0_BASE+0x01) -#define TTYS0_IIR (CONFIG_TTYS0_BASE+0x02) -#define TTYS0_FCR TTYS0_IIR -#define TTYS0_LCR (CONFIG_TTYS0_BASE+0x03) -#define TTYS0_MCR (CONFIG_TTYS0_BASE+0x04) -#define TTYS0_DLL TTYS0_RBR -#define TTYS0_DLM TTYS0_IER - -/* Status */ -#define TTYS0_LSR (CONFIG_TTYS0_BASE+0x05) -#define TTYS0_MSR (CONFIG_TTYS0_BASE+0x06) -#define TTYS0_SCR (CONFIG_TTYS0_BASE+0x07) - - mov %al, %ah -10: mov $TTYS0_LSR, %dx - inb %dx, %al - test $0x20, %al - je 10b - mov $TTYS0_TBR, %dx - mov %ah, %al - outb %al, %dx - - jmp crt_console_tx_string -#endif /* __CRT_CONSOLE_TX_STRING */ - -#if defined(CONSOLE_DEBUG_TX_STRING) && (ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG) -.section ".rom.data" -#if CONFIG_COMPRESS -str_copying_to_ram: .string "Uncompressing coreboot to ram.\r\n" -#else -str_copying_to_ram: .string "Copying coreboot to ram.\r\n" -#endif -str_pre_main: .string "Jumping to coreboot.\r\n" -.previous - -#endif /* ASM_CONSOLE_LOGLEVEL > BIOS_DEBUG */ -str_coreboot_ram_name: .ascii CONFIG_CBFS_PREFIX - .string "/coreboot_ram"

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[PATCH] clean up AMD Geode LX CAR code
by Stefan Reinauer 09 Apr '10

09 Apr '10

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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[commit] r5399 - in trunk: . src/arch/i386 src/cpu src/cpu/via/car src/cpu/via/model_c7 src/mainboard/bcom/winnetp680 src/mainboard/jetway/j7f24 src/mainboard/via/epia-cn src/mainboard/via/epia-m70...
by repository service 09 Apr '10

09 Apr '10

Author: stepan Date: Fri Apr 9 22:36:29 2010 New Revision: 5399 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5399 Log: This patch changes C7 CAR code to be a single assembler file instead of the ugly mixture it was before. It also enables CAR for all C7 boards Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Deleted: trunk/src/cpu/via/car/cache_as_ram.lds trunk/src/cpu/via/car/cache_as_ram_post.c Modified: trunk/Makefile trunk/src/arch/i386/Makefile.inc trunk/src/cpu/Kconfig trunk/src/cpu/via/car/cache_as_ram.inc trunk/src/cpu/via/model_c7/Kconfig trunk/src/mainboard/bcom/winnetp680/romstage.c trunk/src/mainboard/jetway/j7f24/Kconfig trunk/src/mainboard/jetway/j7f24/romstage.c trunk/src/mainboard/via/epia-cn/Kconfig trunk/src/mainboard/via/epia-cn/romstage.c trunk/src/mainboard/via/epia-m700/Kconfig trunk/src/mainboard/via/epia-m700/romstage.c trunk/src/mainboard/via/pc2500e/Kconfig trunk/src/mainboard/via/pc2500e/romstage.c trunk/src/mainboard/via/vt8454c/Kconfig trunk/src/mainboard/via/vt8454c/romstage.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Fri Apr 9 17:39:21 2010 (r5398) +++ trunk/Makefile Fri Apr 9 22:36:29 2010 (r5399) @@ -274,8 +274,10 @@ CBFS_COMPRESS_FLAG:=l CBFS_PAYLOAD_COMPRESS_FLAG:= +CBFS_PAYLOAD_COMPRESS_NAME:=none ifeq ($(CONFIG_COMPRESSED_PAYLOAD_LZMA),y) CBFS_PAYLOAD_COMPRESS_FLAG:=l +CBFS_PAYLOAD_COMPRESS_NAME:=LZMA endif coreboot: prepare $(obj)/coreboot.rom Modified: trunk/src/arch/i386/Makefile.inc ============================================================================== --- trunk/src/arch/i386/Makefile.inc Fri Apr 9 17:39:21 2010 (r5398) +++ trunk/src/arch/i386/Makefile.inc Fri Apr 9 22:36:29 2010 (r5399) @@ -37,7 +37,7 @@ ifeq ($(CONFIG_PAYLOAD_NONE),y) printf " PAYLOAD \e[1;31mnone (as specified by user)\e[0m\n" else - printf " PAYLOAD $(CONFIG_FALLBACK_PAYLOAD_FILE) $(CBFS_PAYLOAD_COMPRESS_FLAG)\n" + printf " PAYLOAD $(CONFIG_FALLBACK_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_NAME))\n" $(CBFSTOOL) $@.tmp add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE) $(CONFIG_CBFS_PREFIX)/payload $(CBFS_PAYLOAD_COMPRESS_FLAG) endif ifeq ($(CONFIG_VGA_BIOS),y) @@ -165,11 +165,7 @@ ifeq ($(CONFIG_CPU_INTEL_SOCKET_MFCBGA479),y) crt0s += $(src)/cpu/x86/car/cache_as_ram.inc endif -# should be CONFIG_CPU_VIA_C7, but bcom/winnetp680, jetway/j7f24, via/epia-cn, via/pc2500e don't use CAR yet -ifeq ($(CONFIG_BOARD_VIA_VT8454C),y) -crt0s += $(src)/cpu/via/car/cache_as_ram.inc -endif -ifeq ($(CONFIG_BOARD_VIA_EPIA_M700),y) +ifeq ($(CONFIG_CPU_VIA_C7),y) crt0s += $(src)/cpu/via/car/cache_as_ram.inc endif # who else could use this? @@ -208,7 +204,7 @@ ifeq ($(CONFIG_ROMCC),y) ROMCCFLAGS ?= -mcpu=p2 -O2 -$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/romcc $(OPTION_TABLE_H) $(obj)/build.h +$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(obj)/romcc $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h printf " ROMCC romstage.inc\n" $(ROMCC) -c -S $(ROMCCFLAGS) -D__PRE_RAM__ -I. $(INCLUDES) $< -o $@ else Modified: trunk/src/cpu/Kconfig ============================================================================== --- trunk/src/cpu/Kconfig Fri Apr 9 17:39:21 2010 (r5398) +++ trunk/src/cpu/Kconfig Fri Apr 9 22:36:29 2010 (r5399) @@ -5,7 +5,7 @@ config USE_DCACHE_RAM bool - default n + default !ROMCC config DCACHE_RAM_BASE hex Modified: trunk/src/cpu/via/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.inc Fri Apr 9 17:39:21 2010 (r5398) +++ trunk/src/cpu/via/car/cache_as_ram.inc Fri Apr 9 22:36:29 2010 (r5399) @@ -63,6 +63,20 @@ wrmsr jmp clear_fixed_var_mtrr + +fixed_mtrr_msr: + .long 0x250, 0x258, 0x259 + .long 0x268, 0x269, 0x26A + .long 0x26B, 0x26C, 0x26D + .long 0x26E, 0x26F + +var_mtrr_msr: + .long 0x200, 0x201, 0x202, 0x203 + .long 0x204, 0x205, 0x206, 0x207 + .long 0x208, 0x209, 0x20A, 0x20B + .long 0x20C, 0x20D, 0x20E, 0x20F + .long 0x000 /* NULL, end of table */ + clear_fixed_var_mtrr_out: /* MTRRPhysBase */ movl $0x200, %ecx @@ -163,17 +177,113 @@ /* We need to set ebp ? No need */ movl %esp, %ebp pushl %eax /* bist */ - call stage1_main - /* We will not go back */ + call main + + /* + * TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we + * get STACK up, we restore that. It is only needed if we + * want to go back. + */ + + /* We don't need cache as ram for now on */ + /* disable cache */ + movl %cr0, %eax + orl $(0x1<<30),%eax + movl %eax, %cr0 + + + /* Set the default memory type and disable fixed and enable variable MTRRs */ + movl $0x2ff, %ecx + //movl $MTRRdefType_MSR, %ecx + xorl %edx, %edx + + /* Enable Variable and Disable Fixed MTRRs */ + movl $0x00000800, %eax + wrmsr + + /* enable caching for first 1M using variable mtrr */ + movl $0x200, %ecx + xorl %edx, %edx + movl $(0 | 6), %eax + //movl $(0 | MTRR_TYPE_WRBACK), %eax + wrmsr + + /* enable cache for 0-7ffff, 80000-9ffff, e0000-fffff; + * If 1M cacheable, then when S3 resume, there is stange color on + * screen for 2 sec. suppose problem of a0000-dfffff and cache. + * And in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable. + */ + + movl $0x201, %ecx + movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ + movl $((~(( 0 + 0x80000) - 1)) | 0x800), %eax + wrmsr + + movl $0x202, %ecx + xorl %edx, %edx + movl $(0x80000 | 6), %eax + orl $(0 | 6), %eax + wrmsr + + movl $0x203, %ecx + movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ + movl $((~(( 0 + 0x20000) - 1)) | 0x800), %eax + wrmsr + + movl $0x204, %ecx + xorl %edx, %edx + movl $(0xc0000 | 6), %eax + orl $(0 | 6), %eax + wrmsr + + movl $0x205, %ecx + movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ + movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax + wrmsr + + /* cache CONFIG_XIP_ROM_BASE-SIZE to speedup coreboot code */ + movl $0x206, %ecx + xorl %edx, %edx + movl $CONFIG_XIP_ROM_BASE,%eax + orl $(0 | 6), %eax + wrmsr + + movl $0x207, %ecx + xorl %edx, %edx + movl $CONFIG_XIP_ROM_SIZE,%eax + decl %eax + notl %eax + orl $(0 | 0x800), %eax + wrmsr + + /* enable cache */ + movl %cr0, %eax + andl $0x9fffffff,%eax + movl %eax, %cr0 + invd + + /* clear boot_complete flag */ + xorl %ebp, %ebp +__main: + post_code(0x11) + cld /* clear direction flag */ + + movl %ebp, %esi + + /* FIXME: These values might have to change for suspend-to-ram. + * the 0x00400000 was chosen as this is a place in memory that + * should exist in all contemporary configurations (ie. large + * enough RAM), but doesn't collide with anything coreboot does. + * Other than that, it's arbitrary. + */ + + movl $0x4000000, %esp + movl %esp, %ebp + pushl %esi + call copy_and_run + +.Lhlt: + post_code(0xee) + hlt + jmp .Lhlt -fixed_mtrr_msr: - .long 0x250, 0x258, 0x259 - .long 0x268, 0x269, 0x26A - .long 0x26B, 0x26C, 0x26D - .long 0x26E, 0x26F -var_mtrr_msr: - .long 0x200, 0x201, 0x202, 0x203 - .long 0x204, 0x205, 0x206, 0x207 - .long 0x208, 0x209, 0x20A, 0x20B - .long 0x20C, 0x20D, 0x20E, 0x20F - .long 0x000 /* NULL, end of table */ Modified: trunk/src/cpu/via/model_c7/Kconfig ============================================================================== --- trunk/src/cpu/via/model_c7/Kconfig Fri Apr 9 17:39:21 2010 (r5398) +++ trunk/src/cpu/via/model_c7/Kconfig Fri Apr 9 22:36:29 2010 (r5399) @@ -3,3 +3,16 @@ select UDELAY_TSC select MMX select SSE2 + select USE_PRINTK_IN_CAR + +config DCACHE_RAM_BASE + hex + default 0xffef0000 + depends on CPU_VIA_C7 + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on CPU_VIA_C7 + + Modified: trunk/src/mainboard/bcom/winnetp680/romstage.c ============================================================================== --- trunk/src/mainboard/bcom/winnetp680/romstage.c Fri Apr 9 17:39:21 2010 (r5398) +++ trunk/src/mainboard/bcom/winnetp680/romstage.c Fri Apr 9 22:36:29 2010 (r5399) @@ -87,7 +87,7 @@ .channel0 = { 0x50 }, }; -static void main(unsigned long bist) +void main(unsigned long bist) { unsigned long x; device_t dev; Modified: trunk/src/mainboard/jetway/j7f24/Kconfig ============================================================================== --- trunk/src/mainboard/jetway/j7f24/Kconfig Fri Apr 9 17:39:21 2010 (r5398) +++ trunk/src/mainboard/jetway/j7f24/Kconfig Fri Apr 9 22:36:29 2010 (r5399) @@ -14,16 +14,6 @@ default jetway/j7f24 depends on BOARD_JETWAY_J7F24 -#config DCACHE_RAM_BASE -# hex -# default 0xffef0000 -# depends on BOARD_JETWAY_J7F24 -# -#config DCACHE_RAM_SIZE -# hex -# default 0x8000 -# depends on BOARD_JETWAY_J7F24 - config MAINBOARD_PART_NUMBER string default "J7f24" Modified: trunk/src/mainboard/jetway/j7f24/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/j7f24/romstage.c Fri Apr 9 17:39:21 2010 (r5398) +++ trunk/src/mainboard/jetway/j7f24/romstage.c Fri Apr 9 22:36:29 2010 (r5399) @@ -87,7 +87,7 @@ .channel0 = { 0x50 }, }; -static void main(unsigned long bist) +void main(unsigned long bist) { /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); Modified: trunk/src/mainboard/via/epia-cn/Kconfig ============================================================================== --- trunk/src/mainboard/via/epia-cn/Kconfig Fri Apr 9 17:39:21 2010 (r5398) +++ trunk/src/mainboard/via/epia-cn/Kconfig Fri Apr 9 22:36:29 2010 (r5399) @@ -5,7 +5,6 @@ select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237R select SUPERIO_VIA_VT1211 - select ROMCC select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_512 @@ -14,16 +13,6 @@ default via/epia-cn depends on BOARD_VIA_EPIA_CN -#config DCACHE_RAM_BASE -# hex -# default 0xffef0000 -# depends on BOARD_VIA_EPIA_CN -# -#config DCACHE_RAM_SIZE -# hex -# default 0x8000 -# depends on BOARD_VIA_EPIA_CN - config MAINBOARD_PART_NUMBER string default "EPIA-CN" Modified: trunk/src/mainboard/via/epia-cn/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-cn/romstage.c Fri Apr 9 17:39:21 2010 (r5398) +++ trunk/src/mainboard/via/epia-cn/romstage.c Fri Apr 9 22:36:29 2010 (r5399) @@ -86,7 +86,7 @@ .channel0 = { 0x50 }, }; -static void main(unsigned long bist) +void main(unsigned long bist) { unsigned long x; device_t dev; Modified: trunk/src/mainboard/via/epia-m700/Kconfig ============================================================================== --- trunk/src/mainboard/via/epia-m700/Kconfig Fri Apr 9 17:39:21 2010 (r5398) +++ trunk/src/mainboard/via/epia-m700/Kconfig Fri Apr 9 22:36:29 2010 (r5399) @@ -7,23 +7,12 @@ select BOARD_HAS_FADT select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 - select USE_PRINTK_IN_CAR config MAINBOARD_DIR string default via/epia-m700 depends on BOARD_VIA_EPIA_M700 -config DCACHE_RAM_BASE - hex - default 0xffef0000 - depends on BOARD_VIA_EPIA_M700 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - depends on BOARD_VIA_EPIA_M700 - config MAINBOARD_PART_NUMBER string default "EPIA-M700" Modified: trunk/src/mainboard/via/epia-m700/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/romstage.c Fri Apr 9 17:39:21 2010 (r5398) +++ trunk/src/mainboard/via/epia-m700/romstage.c Fri Apr 9 22:36:29 2010 (r5399) @@ -381,7 +381,7 @@ } /* cache_as_ram.inc jumps to here. */ -void stage1_main(unsigned long bist) +void main(unsigned long bist) { unsigned cpu_reset = 0; u16 boot_mode; @@ -686,108 +686,5 @@ #endif -/* - * The following code is copied from tyan\s2735\romstage.c. - * Only the code around CLEAR_FIRST_1M_RAM is changed. Removed all the code - * around CLEAR_FIRST_1M_RAM and #include "cpu/x86/car/cache_as_ram_post.c". - * The CLEAR_FIRST_1M_RAM seems to make cpu/x86/car/cache_as_ram_post.c stop - * at somewhere, and cpu/x86/car/cache_as_ram_post.c do not cache my - * $CONFIG_XIP_ROM_BASE+SIZE area. - * - * Use #include "cpu/via/car/cache_as_ram_post.c". This version post.c have - * some diff with x86-version. - */ -#if 1 - { - /* - * Check value of esp to verify if we have enough ROM for - * stack in Cache as RAM. - */ - unsigned v_esp; - __asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp)); -#if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp); -#else - print_debug("v_esp="); - print_debug_hex32(v_esp); - print_debug("\n"); -#endif - } -#endif - -#if 1 -cpu_reset_x: - - /* It seems that cpu_reset is not used before this, so I just reset - * it, (this is because the s3 resume, setting in MTRR and copy data - * may destroy stack. - */ - cpu_reset = 0; - -#if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "cpu_reset = %08x\n", cpu_reset); -#else - print_debug("cpu_reset = "); - print_debug_hex32(cpu_reset); - print_debug("\n"); -#endif - - if (cpu_reset == 0) - print_debug("Clearing initial memory region: "); - print_debug("No cache as ram now - "); - - /* Store cpu_reset to ebx. */ - __asm__ volatile ("movl %0, %%ebx\n\t"::"a" (cpu_reset)); - - /* - * Cancel these lines, CLEAR_FIRST_1M_RAM cause the - * cpu/x86/car/cache_as_ram_post.c stop at somewhere. - */ -#if 0 - if (cpu_reset == 0) { -#define CLEAR_FIRST_1M_RAM 1 -#include "cpu/via/car/cache_as_ram_post.c" - } else { -#undef CLEAR_FIRST_1M_RAM -#include "cpu/via/car/cache_as_ram_post.c" - } -#endif - -#include "cpu/via/car/cache_as_ram_post.c" -/* #include "cpu/x86/car/cache_as_ram_post.c" */ - __asm__ volatile ( - /* Set new esp *//* before CONFIG_RAMBASE */ - "subl %0, %%ebp\n\t" - "subl %0, %%esp\n\t":: - "a" ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - CONFIG_RAMBASE) - ); - - { - unsigned new_cpu_reset; - - /* Get back cpu_reset from ebx. */ - __asm__ volatile ("movl %%ebx, %0\n\t":"=a" (new_cpu_reset)); - - /* We can't go back anymore, we lost old stack data in CAR. */ - if (new_cpu_reset == 0) - print_debug("Use Ram as Stack now - done\n"); - else - print_debug("Use Ram as Stack now - \n"); - -#if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset); -#else - print_debug("new_cpu_reset = "); - print_debug_hex32(new_cpu_reset); - print_debug("\n"); -#endif - - /* Copy and execute coreboot_ram. */ - copy_and_run(new_cpu_reset); - /* We will not return. */ - } -#endif - - print_debug("should not be here -\n"); } Modified: trunk/src/mainboard/via/pc2500e/Kconfig ============================================================================== --- trunk/src/mainboard/via/pc2500e/Kconfig Fri Apr 9 17:39:21 2010 (r5398) +++ trunk/src/mainboard/via/pc2500e/Kconfig Fri Apr 9 22:36:29 2010 (r5399) @@ -5,7 +5,6 @@ select NORTHBRIDGE_VIA_CN700 select SOUTHBRIDGE_VIA_VT8237R select SUPERIO_ITE_IT8716F - select ROMCC select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select SMP @@ -22,16 +21,6 @@ default "pc2500e" depends on BOARD_VIA_PC2500E -config DCACHE_RAM_BASE - hex - default 0xc0000 - depends on BOARD_VIA_PC2500E - -config DCACHE_RAM_SIZE - hex - default 0x1000 - depends on BOARD_VIA_PC2500E - config RAMBASE hex default 0x4000 Modified: trunk/src/mainboard/via/pc2500e/romstage.c ============================================================================== --- trunk/src/mainboard/via/pc2500e/romstage.c Fri Apr 9 17:39:21 2010 (r5398) +++ trunk/src/mainboard/via/pc2500e/romstage.c Fri Apr 9 22:36:29 2010 (r5399) @@ -58,7 +58,7 @@ .channel0 = { 0x50 }, /* TODO: CN700 currently only supports 1 DIMM. */ }; -static void main(unsigned long bist) +void main(unsigned long bist) { /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); Modified: trunk/src/mainboard/via/vt8454c/Kconfig ============================================================================== --- trunk/src/mainboard/via/vt8454c/Kconfig Fri Apr 9 17:39:21 2010 (r5398) +++ trunk/src/mainboard/via/vt8454c/Kconfig Fri Apr 9 22:36:29 2010 (r5399) @@ -8,7 +8,6 @@ select HAVE_PIRQ_TABLE select HAVE_MP_TABLE # select MMCONF_SUPPORT - select USE_PRINTK_IN_CAR select HAVE_HARD_RESET select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 @@ -19,16 +18,6 @@ default via/vt8454c depends on BOARD_VIA_VT8454C -config DCACHE_RAM_BASE - hex - default 0xffef0000 - depends on BOARD_VIA_VT8454C - -config DCACHE_RAM_SIZE - hex - default 0x8000 - depends on BOARD_VIA_VT8454C - config MAINBOARD_PART_NUMBER string default "VT8454c" Modified: trunk/src/mainboard/via/vt8454c/romstage.c ============================================================================== --- trunk/src/mainboard/via/vt8454c/romstage.c Fri Apr 9 17:39:21 2010 (r5398) +++ trunk/src/mainboard/via/vt8454c/romstage.c Fri Apr 9 22:36:29 2010 (r5399) @@ -32,8 +32,6 @@ #include "northbridge/via/cx700/raminit.h" #include "cpu/x86/bist.h" -#define DEACTIVATE_CAR 1 -#define DEACTIVATE_CAR_FILE "cpu/via/car/cache_as_ram_post.c" #include "pc80/udelay_io.c" #include "lib/delay.c" @@ -89,7 +87,7 @@ pci_write_config8(PCI_DEV(0, 0, 3), 0x83, shadowreg); } -static void main(unsigned long bist) +void main(unsigned long bist) { /* Set statically so it should work with cx700 as well */ static const struct mem_controller cx700[] = { @@ -115,17 +113,5 @@ sdram_set_registers(cx700); enable_shadow_ram(cx700); sdram_enable(cx700); - -#ifdef DEACTIVATE_CAR - print_debug("Deactivating CAR"); -#include DEACTIVATE_CAR_FILE - print_debug(" - Done.\n"); -#endif - copy_and_run(0); -} - -void stage1_main(unsigned long bist) -{ - main(bist); }

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coreboot April 2010