coreboot April 2010

coreboot@coreboot.org

64 participants
402 discussions

[commit] r5415 - in trunk/src: cpu/intel/model_106cx mainboard/intel/d945gclf
by repository service 12 Apr '10

12 Apr '10

Author: stepan Date: Tue Apr 13 02:11:59 2010 New Revision: 5415 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5415 Log: update atom car code in the same way that 6ex/6fx was updated. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Deleted: trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c trunk/src/cpu/intel/model_106cx/cache_as_ram_post.c Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc trunk/src/mainboard/intel/d945gclf/romstage.c Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Tue Apr 13 02:02:20 2010 (r5414) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Tue Apr 13 02:11:59 2010 (r5415) @@ -35,8 +35,6 @@ movl $0xFEE00300, %esi movl %eax, (%esi) - post_code(0x21) - /* Zero out all Fixed Range and Variable Range MTRRs */ movl $mtrr_table, %esi movl $( (mtrr_table_end - mtrr_table) / 2), %edi @@ -49,7 +47,6 @@ add $2, %esi dec %edi jnz clear_mtrrs - post_code(0x22) /* Configure the default memory type to uncacheable */ movl $MTRRdefType_MSR, %ecx @@ -57,42 +54,36 @@ andl $(~0x00000cff), %eax wrmsr - post_code(0x23) /* Set cache as ram base address */ movl $(MTRRphysBase_MSR(0)), %ecx movl $(CACHE_AS_RAM_BASE | MTRR_TYPE_WRBACK), %eax xorl %edx, %edx wrmsr - post_code(0x24) /* Set cache as ram mask */ movl $(MTRRphysMask_MSR(0)), %ecx movl $(~((CACHE_AS_RAM_SIZE-1)) | (1 << 11)), %eax xorl %edx, %edx wrmsr - post_code(0x25) /* Enable MTRR */ movl $MTRRdefType_MSR, %ecx rdmsr orl $(1 << 11), %eax wrmsr - post_code(0x26) /* Enable L2 Cache */ movl $0x11e, %ecx rdmsr orl $(1 << 8), %eax wrmsr - post_code(0x27) /* CR0.CD = 0, CR0.NW = 0 */ movl %cr0, %eax andl $( ~( (1 << 30) | (1 << 29) ) ), %eax invd movl %eax, %cr0 - post_code(0x28) /* Clear the cache memory reagion */ movl $CACHE_AS_RAM_BASE, %esi movl %esi, %edi @@ -101,7 +92,6 @@ xorl %eax, %eax rep stosl - post_code(0x29) /* Enable Cache As RAM mode by disabling cache */ movl %cr0, %eax orl $(1 << 30), %eax @@ -110,7 +100,7 @@ #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE) /* Enable cache for our code in Flash because we do XIP here */ movl $MTRRphysBase_MSR(1), %ecx - xorl %edx, %edx + xorl %edx, %edx #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE #else @@ -126,7 +116,6 @@ wrmsr #endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */ - post_code(0x2a) /* enable cache */ movl %cr0, %eax andl $( ~( (1 << 30) | (1 << 29) ) ), %eax @@ -148,12 +137,143 @@ post_code(0x23) - call stage1_main + /* Call romstage.c main function */ + call main post_code(0x2f) -error: + + post_code(0x30) + + /* Disable Cache */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x31) + + /* Disable MTRR */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~(1 << 11)), %eax + wrmsr + + post_code(0x31) + + invd +#if 0 + xorl %eax, %eax + xorl %edx, %edx + movl $MTRRphysBase_MSR(0), %ecx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + wrmsr + movl $MTRRphysBase_MSR(1), %ecx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + wrmsr +#endif + + post_code(0x33) + +#undef CLEAR_FIRST_1M_RAM +#ifdef CLEAR_FIRST_1M_RAM + post_code(0x34) + /* Enable Write Combining and Speculative Reads for the first 1MB */ + movl $MTRRphysBase_MSR(0), %ecx + movl $(0x00000000 | MTRR_TYPE_WRCOMB), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + movl $(~(1024*1024 -1) | (1 << 11)), %eax + xorl %edx, %edx + wrmsr + post_code(0x35) +#endif + + /* Enable Cache */ + movl %cr0, %eax + andl $~( (1 << 30) | (1 << 29) ), %eax + movl %eax, %cr0 + + + post_code(0x36) +#ifdef CLEAR_FIRST_1M_RAM + + /* Clear first 1MB of RAM */ + movl $0x00000000, %edi + cld + xorl %eax, %eax + movl $((1024*1024) / 4), %ecx + rep stosl + + post_code(0x37) +#endif + + /* Disable Cache */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x38) + + /* Enable Write Back and Speculative Reads for the first 1MB */ + movl $MTRRphysBase_MSR(0), %ecx + movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + movl $(~(1024*1024 -1) | (1 << 11)), %eax + xorl %edx, %edx + wrmsr + + post_code(0x39) + + /* And Enable Cache again after setting MTRRs */ + movl %cr0, %eax + andl $~( (1 << 30) | (1 << 29) ), %eax + movl %eax, %cr0 + + post_code(0x3a) + + /* Enable MTRR */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $(1 << 11), %eax + wrmsr + + post_code(0x3b) + + /* Invalidate the cache again */ + invd + + post_code(0x3c) + + /* clear boot_complete flag */ + xorl %ebp, %ebp +__main: + post_code(0x11) + cld /* clear direction flag */ + + movl %ebp, %esi + + /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This + * makes sure that we stay completely within the 1M-64K of memory that we + * preserve for suspend/resume. + */ + +#ifndef HIGH_MEMORY_SAVE +#warning Need a central place for HIGH_MEMORY_SAVE +#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) +#endif + movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp + movl %esp, %ebp + pushl %esi + call copy_and_run + +.Lhlt: + post_code(0xee) hlt - jmp error + jmp .Lhlt mtrr_table: /* Fixed MTRRs */ Modified: trunk/src/mainboard/intel/d945gclf/romstage.c ============================================================================== --- trunk/src/mainboard/intel/d945gclf/romstage.c Tue Apr 13 02:02:20 2010 (r5414) +++ trunk/src/mainboard/intel/d945gclf/romstage.c Tue Apr 13 02:11:59 2010 (r5415) @@ -223,9 +223,7 @@ // #include "lib/cbmem.c" -#include "cpu/intel/model_106cx/cache_as_ram_disable.c" - -void real_main(unsigned long bist) +void main(unsigned long bist) { u32 reg32; int boot_mode = 0;

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Console ports and Coreboot versions
by Gregg Levine 12 Apr '10

12 Apr '10

Hello! Here's the issue: Dating over a period of about two to three weeks, and averaging about three messages per time period about two years ago September to October, happen to be a serial about just that. The group was discussing the issue concerning the impending (by that time) disappearance of the serial port from the selected boards. And they were looking into a series of interesting hacks, one was applying the technology behind the PS/2 port, one other concerned a floppy drive connector. And even the parallel port was considered. Even the SMBUS was looked at. As of this past week the links in the messages have died so there isn't a reference for the gizmo described that enables a PS/2 keyboard style connector to be connected to a USB style port. Or perhaps the reverse is true. Using it someone could plug a USB key or flash drive into a PS/2 keyboard connector. As I understand it, it looks something like the USB Debug device described sometime ago, except for the fact that one end contained the PS/2 connection. This concerned the V3 port or build or release of Coreboot. Since the reasons why I initially got involved with the entire product from its early days as LinuxBIOS to right now with everyone working with different ideas for Coreboot moving towards a reality are summed up in that serial I decided to label it. Basically folks I have an interest in strange things like that, and of course regular computer electronics as such I decided today to ask about it. ----- Gregg C Levine gregg.drwho8(a)gmail.com "This signature fought the Time Wars, time and again."

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[commit] r5414 - trunk/src/mainboard/intel/eagleheights
by repository service 12 Apr '10

12 Apr '10

Author: stepan Date: Tue Apr 13 02:02:20 2010 New Revision: 5414 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5414 Log: Fix eagleheights not a 6ex board, but using the same CAR code. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/intel/eagleheights/romstage.c Modified: trunk/src/mainboard/intel/eagleheights/romstage.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/romstage.c Tue Apr 13 01:12:15 2010 (r5413) +++ trunk/src/mainboard/intel/eagleheights/romstage.c Tue Apr 13 02:02:20 2010 (r5414) @@ -163,7 +163,7 @@ pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0)); } -void real_main(unsigned long bist) +void main(unsigned long bist) { /* int boot_mode = 0; */ @@ -232,6 +232,3 @@ sdram_initialize(ARRAY_SIZE(mch), mch); } -/* Use Intel Core (not Core 2) code for CAR init, any CPU might be used. */ -#include "cpu/intel/model_6ex/cache_as_ram_disable.c" -

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build service results for r5413
by coreboot information 12 Apr '10

12 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5413 to the coreboot repository. This caused the following changes: Change Log: port latest model 6ex car changes to 6fx car, which is almost identical and currently unused. Just keep it in sync, we might need it some day. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of intel:eagleheights is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5413&device=eagleheights&v… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r5412
by coreboot information 12 Apr '10

12 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5412 to the coreboot repository. This caused the following changes: Change Log: move model_6ex car to a single file. No more .c files that only consist of a single several pages long asm statement Could use some renumbering of post codes, but that's good for another time. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Build Log: Compilation of intel:eagleheights has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5412&device=eagleheights&v… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5413 - in trunk/src/cpu/intel: model_6ex model_6fx
by repository service 12 Apr '10

12 Apr '10

Author: stepan Date: Tue Apr 13 01:12:15 2010 New Revision: 5413 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5413 Log: port latest model 6ex car changes to 6fx car, which is almost identical and currently unused. Just keep it in sync, we might need it some day. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Deleted: trunk/src/cpu/intel/model_6fx/cache_as_ram_disable.c trunk/src/cpu/intel/model_6fx/cache_as_ram_post.c Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Tue Apr 13 01:04:29 2010 (r5412) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Tue Apr 13 01:12:15 2010 (r5413) @@ -246,6 +246,7 @@ /* Invalidate the cache again */ invd + post_code(0x3c) /* clear boot_complete flag */ xorl %ebp, %ebp Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Tue Apr 13 01:04:29 2010 (r5412) +++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Tue Apr 13 01:12:15 2010 (r5413) @@ -144,12 +144,150 @@ post_code(0x23) - call stage1_main + /* Call romstage.c main function */ + call main post_code(0x2f) -error: + + post_code(0x30) + + /* Disable Cache */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x31) + + /* Disable MTRR */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~(1 << 11)), %eax + wrmsr + + post_code(0x31) + + invd +#if 0 + xorl %eax, %eax + xorl %edx, %edx + movl $MTRRphysBase_MSR(0), %ecx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + wrmsr + movl $MTRRphysBase_MSR(1), %ecx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + wrmsr +#endif + + post_code(0x33) + +#undef CLEAR_FIRST_1M_RAM +#ifdef CLEAR_FIRST_1M_RAM + post_code(0x34) + /* Enable Write Combining and Speculative Reads for the first 1MB */ + movl $MTRRphysBase_MSR(0), %ecx + movl $(0x00000000 | MTRR_TYPE_WRCOMB), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + movl $(~(1024*1024 -1) | (1 << 11)), %eax + movl $0x0000000f, %edx // 36bit address space + wrmsr + post_code(0x35) +#endif + + /* Enable Cache */ + movl %cr0, %eax + andl $~( (1 << 30) | (1 << 29) ), %eax + movl %eax, %cr0 + + + post_code(0x36) +#ifdef CLEAR_FIRST_1M_RAM + + /* Clear first 1MB of RAM */ + movl $0x00000000, %edi + cld + xorl %eax, %eax + movl $((1024*1024) / 4), %ecx + rep stosl + + post_code(0x37) +#endif + + /* Disable Cache */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x38) + + /* Enable Write Back and Speculative Reads for the first 1MB */ + movl $MTRRphysBase_MSR(0), %ecx + movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + movl $(~(1024*1024 -1) | (1 << 11)), %eax + movl $0x0000000f, %edx // 36bit address space + wrmsr + + post_code(0x39) + + /* And Enable Cache again after setting MTRRs */ + movl %cr0, %eax + andl $~( (1 << 30) | (1 << 29) ), %eax + movl %eax, %cr0 + + post_code(0x3a) + + /* Enable MTRR */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $(1 << 11), %eax + wrmsr + + post_code(0x3b) + + /* Enable prefetchers */ + movl $0x01a0, %ecx + rdmsr + andl $~((1 << 9) | (1 << 19)), %eax + andl $~((1 << 5) | (1 << 7)), %edx + wrmsr + + /* Invalidate the cache again */ + invd + + post_code(0x3c) + + /* clear boot_complete flag */ + xorl %ebp, %ebp +__main: + post_code(0x11) + cld /* clear direction flag */ + + movl %ebp, %esi + + /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This + * makes sure that we stay completely within the 1M-64K of memory that we + * preserve for suspend/resume. + */ + +#ifndef HIGH_MEMORY_SAVE +#warning Need a central place for HIGH_MEMORY_SAVE +#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) +#endif + movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp + movl %esp, %ebp + pushl %esi + call copy_and_run + +.Lhlt: + post_code(0xee) hlt - jmp error + jmp .Lhlt mtrr_table: /* Fixed MTRRs */

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[commit] r5412 - in trunk/src: cpu/intel/model_6ex mainboard/kontron/986lcd-m mainboard/roda/rk886ex
by repository service 12 Apr '10

12 Apr '10

Author: stepan Date: Tue Apr 13 01:04:29 2010 New Revision: 5412 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5412 Log: move model_6ex car to a single file. No more .c files that only consist of a single several pages long asm statement Could use some renumbering of post codes, but that's good for another time. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Deleted: trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c trunk/src/cpu/intel/model_6ex/cache_as_ram_post.c Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/src/mainboard/kontron/986lcd-m/romstage.c trunk/src/mainboard/roda/rk886ex/romstage.c Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Mon Apr 12 17:28:34 2010 (r5411) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Tue Apr 13 01:04:29 2010 (r5412) @@ -137,12 +137,142 @@ post_code(0x23) - call stage1_main + /* Call romstage.c main function */ + call main post_code(0x2f) -error: + + post_code(0x30) + + /* Disable Cache */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x31) + + /* Disable MTRR */ + movl $MTRRdefType_MSR, %ecx + rdmsr + andl $(~(1 << 11)), %eax + wrmsr + + post_code(0x31) + + invd +#if 0 + xorl %eax, %eax + xorl %edx, %edx + movl $MTRRphysBase_MSR(0), %ecx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + wrmsr + movl $MTRRphysBase_MSR(1), %ecx + wrmsr + movl $MTRRphysMask_MSR(1), %ecx + wrmsr +#endif + + post_code(0x33) + +#undef CLEAR_FIRST_1M_RAM +#ifdef CLEAR_FIRST_1M_RAM + post_code(0x34) + /* Enable Write Combining and Speculative Reads for the first 1MB */ + movl $MTRRphysBase_MSR(0), %ecx + movl $(0x00000000 | MTRR_TYPE_WRCOMB), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + movl $(~(1024*1024 -1) | (1 << 11)), %eax + movl $0x0000000f, %edx // 36bit address space + wrmsr + post_code(0x35) +#endif + + /* Enable Cache */ + movl %cr0, %eax + andl $~( (1 << 30) | (1 << 29) ), %eax + movl %eax, %cr0 + + + post_code(0x36) +#ifdef CLEAR_FIRST_1M_RAM + + /* Clear first 1MB of RAM */ + movl $0x00000000, %edi + cld + xorl %eax, %eax + movl $((1024*1024) / 4), %ecx + rep stosl + + post_code(0x37) +#endif + + /* Disable Cache */ + movl %cr0, %eax + orl $(1 << 30), %eax + movl %eax, %cr0 + + post_code(0x38) + + /* Enable Write Back and Speculative Reads for the first 1MB */ + movl $MTRRphysBase_MSR(0), %ecx + movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax + xorl %edx, %edx + wrmsr + movl $MTRRphysMask_MSR(0), %ecx + movl $(~(1024*1024 -1) | (1 << 11)), %eax + movl $0x0000000f, %edx // 36bit address space + wrmsr + + post_code(0x39) + + /* And Enable Cache again after setting MTRRs */ + movl %cr0, %eax + andl $~( (1 << 30) | (1 << 29) ), %eax + movl %eax, %cr0 + + post_code(0x3a) + + /* Enable MTRR */ + movl $MTRRdefType_MSR, %ecx + rdmsr + orl $(1 << 11), %eax + wrmsr + + post_code(0x3b) + + /* Invalidate the cache again */ + invd + + + /* clear boot_complete flag */ + xorl %ebp, %ebp +__main: + post_code(0x11) + cld /* clear direction flag */ + + movl %ebp, %esi + + /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This + * makes sure that we stay completely within the 1M-64K of memory that we + * preserve for suspend/resume. + */ + +#ifndef HIGH_MEMORY_SAVE +#warning Need a central place for HIGH_MEMORY_SAVE +#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) +#endif + movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp + movl %esp, %ebp + pushl %esi + call copy_and_run + +.Lhlt: + post_code(0xee) hlt - jmp error + jmp .Lhlt mtrr_table: /* Fixed MTRRs */ Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/romstage.c Mon Apr 12 17:28:34 2010 (r5411) +++ trunk/src/mainboard/kontron/986lcd-m/romstage.c Tue Apr 13 01:04:29 2010 (r5412) @@ -359,9 +359,7 @@ // #include "lib/cbmem.c" -#include "cpu/intel/model_6ex/cache_as_ram_disable.c" - -void real_main(unsigned long bist) +void main(unsigned long bist) { u32 reg32; int boot_mode = 0; Modified: trunk/src/mainboard/roda/rk886ex/romstage.c ============================================================================== --- trunk/src/mainboard/roda/rk886ex/romstage.c Mon Apr 12 17:28:34 2010 (r5411) +++ trunk/src/mainboard/roda/rk886ex/romstage.c Tue Apr 13 01:04:29 2010 (r5412) @@ -272,9 +272,8 @@ // __PRE_RAM__ to determine whether we're in ram init stage (stage 1) // #include "lib/cbmem.c" -#include "cpu/intel/model_6ex/cache_as_ram_disable.c" -void real_main(unsigned long bist) +void main(unsigned long bist) { u32 reg32; int boot_mode = 0;

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#103: flashrom: Don't exit() after successful erase operation
by coreboot 12 Apr '10

12 Apr '10

#103: flashrom: Don't exit() after successful erase operation ---------------------------------+------------------------------------------ Reporter: stuge | Owner: somebody Type: defect | Status: new Priority: major | Milestone: flashrom v1.0 Component: flashrom | Version: Keywords: erase exit | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/103> coreboot <http://www.coreboot.org/>

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#119: Winbond W39V040FBPZ is not written correctly by flashrom
by coreboot 12 Apr '10

12 Apr '10

#119: Winbond W39V040FBPZ is not written correctly by flashrom -----------------------------------------+---------------------------------- Reporter: charles.herndon@… | Owner: somebody Type: enhancement | Status: new Priority: minor | Milestone: Component: flashrom | Version: v2 Keywords: W39V040FBPZ | Dependencies: Patchstatus: there is no patch | -----------------------------------------+---------------------------------- Flash device is detected as a Winbond W39V040B device. Flashrom attempts to flash device, but verification fails. No actual writing to the chip appears to be done. Tried changing write and erase in flashchips.c to: jedec, winbond_fwhub and 49lfxxxc. ./flashrom -wv xxxx.bin Calibrating delay loop... OK. No coreboot table found. Found chipset "Intel ICH7/ICH7R", enabling flash write... OK. Found chip "Winbond W39V040B" (512 KB) at physical address 0xfff80000. Flash image seems to be a legacy BIOS. Disabling checks. Programming page: 0007 at address: 0x00070000 Verifying flash... FAILED! Expected=0xc7, Read=0x49 -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/119> coreboot <http://www.coreboot.org/>

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[PATCH] clean up some ld files.
by Stefan Reinauer 12 Apr '10

12 Apr '10

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

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coreboot April 2010