coreboot April 2010

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build service results for r5423
by coreboot information 14 Apr '10

14 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5423 to the coreboot repository. This caused the following changes: Change Log: move cpu/x86/car to cpu/intel/car as previously discussed on the mailing list. this patch also slightly changes it so we have a single cache_as_ram.inc which requires no "help" from cache_as_ram_post.c and cache_as_ram_disable.c (or worse, a lot of cruft hacked right into romstage.c like on tyan s2735) Now all CAR code except the AMD Opteron/Athlon64 CAR code follows the new simpler scheme. I'll gladly leave src/cpu/amd/car to someone else ;-) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of digitallogic:adl855pc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5423&device=adl855pc&vendo… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5423 - in trunk/src: arch/i386 cpu/intel/car cpu/intel/model_6bx cpu/intel/socket_mFCBGA479 cpu/x86/car mainboard/rca/rm4100 mainboard/thomson/ip1000 mainboard/tyan/s2735 northbridge/via/...
by repository service 14 Apr '10

14 Apr '10

Author: stepan Date: Wed Apr 14 09:47:07 2010 New Revision: 5423 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5423 Log: move cpu/x86/car to cpu/intel/car as previously discussed on the mailing list. this patch also slightly changes it so we have a single cache_as_ram.inc which requires no "help" from cache_as_ram_post.c and cache_as_ram_disable.c (or worse, a lot of cruft hacked right into romstage.c like on tyan s2735) Now all CAR code except the AMD Opteron/Athlon64 CAR code follows the new simpler scheme. I'll gladly leave src/cpu/amd/car to someone else ;-) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/src/cpu/intel/car/ - copied from r5413, trunk/src/cpu/x86/car/ Deleted: trunk/src/cpu/intel/car/cache_as_ram_post.c trunk/src/cpu/intel/model_6bx/cache_as_ram_disable.c trunk/src/cpu/x86/car/ Modified: trunk/src/arch/i386/Makefile.inc trunk/src/cpu/intel/car/cache_as_ram.inc trunk/src/cpu/intel/socket_mFCBGA479/Makefile.inc trunk/src/mainboard/rca/rm4100/romstage.c trunk/src/mainboard/thomson/ip1000/romstage.c trunk/src/mainboard/tyan/s2735/romstage.c trunk/src/northbridge/via/vx800/examples/romstage.c Modified: trunk/src/arch/i386/Makefile.inc ============================================================================== --- trunk/src/arch/i386/Makefile.inc Tue Apr 13 23:31:42 2010 (r5422) +++ trunk/src/arch/i386/Makefile.inc Wed Apr 14 09:47:07 2010 (r5423) @@ -127,7 +127,7 @@ # FIXME move to CPU_INTEL_SOCKET_MPGA604 # ifeq ($(CONFIG_BOARD_TYAN_S2735),y) -crt0s += $(src)/cpu/x86/car/cache_as_ram.inc +crt0s += $(src)/cpu/intel/car/cache_as_ram.inc endif ifeq ($(CONFIG_LLSHELL),y) Modified: trunk/src/cpu/intel/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/x86/car/cache_as_ram.inc Tue Apr 13 01:12:15 2010 (r5413) +++ trunk/src/cpu/intel/car/cache_as_ram.inc Wed Apr 14 09:47:07 2010 (r5423) @@ -126,6 +126,19 @@ wrmsr jmp clear_fixed_var_mtrr + +fixed_mtrr_msr: + .long 0x250, 0x258, 0x259 + .long 0x268, 0x269, 0x26A + .long 0x26B, 0x26C, 0x26D + .long 0x26E, 0x26F +var_mtrr_msr: + .long 0x200, 0x201, 0x202, 0x203 + .long 0x204, 0x205, 0x206, 0x207 + .long 0x208, 0x209, 0x20A, 0x20B + .long 0x20C, 0x20D, 0x20E, 0x20F + .long 0x000 /* NULL, end of table */ + clear_fixed_var_mtrr_out: /* 0x06 is the WB IO type for a given 4k segment. @@ -289,48 +302,118 @@ /* We need to set ebp ? No need */ movl %esp, %ebp pushl %eax /* bist */ - call stage1_main - /* We will not go back */ + call main -fixed_mtrr_msr: - .long 0x250, 0x258, 0x259 - .long 0x268, 0x269, 0x26A - .long 0x26B, 0x26C, 0x26D - .long 0x26E, 0x26F -var_mtrr_msr: - .long 0x200, 0x201, 0x202, 0x203 - .long 0x204, 0x205, 0x206, 0x207 - .long 0x208, 0x209, 0x20A, 0x20B - .long 0x20C, 0x20D, 0x20E, 0x20F - .long 0x000 /* NULL, end of table */ + /* + FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that. + It is only needed if we want to go back + */ + + /* We don't need cache as ram for now on */ + /* disable cache */ + movl %cr0, %eax + orl $(0x1<<30),%eax + movl %eax, %cr0 + + /* clear sth */ + movl $0x269, %ecx /* fix4k_c8000*/ + xorl %edx, %edx + xorl %eax, %eax + wrmsr - .align 0x1000 - .code16 -.global LogicalAP_SIPI -LogicalAP_SIPI: - // cr0 register is shared among the logical processors; - // so clear CD & NW bits so that the BSP's cr0 register - // controls the cache behavior - // Note: The cache behavior is determined by "OR" result - // of the cr0 registers of the logical processors +#if CONFIG_DCACHE_RAM_SIZE > 0x8000 + movl $0x268, %ecx /* fix4k_c0000*/ + wrmsr +#endif - movl %cr0, %eax - andl $0x9FFFFFFF, %eax - movl %eax, %cr0 + /* Set the default memory type and disable fixed and enable variable MTRRs */ + movl $0x2ff, %ecx +// movl $MTRRdefType_MSR, %ecx + xorl %edx, %edx + /* Enable Variable and Disable Fixed MTRRs */ + movl $0x00000800, %eax + wrmsr - finit +#if defined(CLEAR_FIRST_1M_RAM) + /* enable caching for first 1M using variable mtrr */ + movl $0x200, %ecx + xorl %edx, %edx + movl $(0 | 1), %eax +// movl $(0 | MTRR_TYPE_WRCOMB), %eax + wrmsr - // Set the semaphore to indicate the Logical AP is done - // with CAR specific initialization - movl $0x250, %ecx - movl $0x06, %eax - xorl %edx, %edx + movl $0x201, %ecx + movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ + movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax + wrmsr +#endif + + /* enable cache */ + movl %cr0, %eax + andl $0x9fffffff,%eax + movl %eax, %cr0 + +#if defined(CLEAR_FIRST_1M_RAM) + /* clear the first 1M */ + movl $0x0, %edi + cld + movl $(0x100000>>2), %ecx + xorl %eax, %eax + rep stosl + + /* disable cache */ + movl %cr0, %eax + orl $(0x1<<30),%eax + movl %eax, %cr0 + + /* enable caching for first 1M using variable mtrr */ + movl $0x200, %ecx + xorl %edx, %edx + movl $(0 | 6), %eax +// movl $(0 | MTRR_TYPE_WRBACK), %eax wrmsr - // Halt this AP - cli -Halt_LogicalAP: + movl $0x201, %ecx + movl $0x0000000f, %edx /* AMD 40 bit 0xff*/ + movl $((~(( 0 + 0x100000) - 1)) | 0x800), %eax + wrmsr + + /* enable cache */ + movl %cr0, %eax + andl $0x9fffffff,%eax + movl %eax, %cr0 + invd + + /* FIXME: I hope we don't need to change esp and ebp value here, so we + * can restore value from mmx sse back But the problem is the range is + * some io related, So don't go back + */ +#endif + + /* clear boot_complete flag */ + xorl %ebp, %ebp +__main: + post_code(0x11) + cld /* clear direction flag */ + + movl %ebp, %esi + + /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This + * makes sure that we stay completely within the 1M-64K of memory that we + * preserve for suspend/resume. + */ + +#ifndef HIGH_MEMORY_SAVE +#warning Need a central place for HIGH_MEMORY_SAVE +#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) +#endif + movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp + movl %esp, %ebp + pushl %esi + call copy_and_run + +.Lhlt: + post_code(0xee) hlt - jmp Halt_LogicalAP - .code32 -.CacheAsRam_out: + jmp .Lhlt + Modified: trunk/src/cpu/intel/socket_mFCBGA479/Makefile.inc ============================================================================== --- trunk/src/cpu/intel/socket_mFCBGA479/Makefile.inc Tue Apr 13 23:31:42 2010 (r5422) +++ trunk/src/cpu/intel/socket_mFCBGA479/Makefile.inc Wed Apr 14 09:47:07 2010 (r5423) @@ -7,4 +7,4 @@ subdirs-y += ../../x86/smm subdirs-y += ../microcode -cpu_incs += $(src)/cpu/x86/car/cache_as_ram.inc +cpu_incs += $(src)/cpu/intel/car/cache_as_ram.inc Modified: trunk/src/mainboard/rca/rm4100/romstage.c ============================================================================== --- trunk/src/mainboard/rca/rm4100/romstage.c Tue Apr 13 23:31:42 2010 (r5422) +++ trunk/src/mainboard/rca/rm4100/romstage.c Wed Apr 14 09:47:07 2010 (r5423) @@ -97,9 +97,7 @@ pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10); } -#include "cpu/intel/model_6bx/cache_as_ram_disable.c" - -void real_main(unsigned long bist) +void main(unsigned long bist) { if (bist == 0) { if (memory_initialized()) { Modified: trunk/src/mainboard/thomson/ip1000/romstage.c ============================================================================== --- trunk/src/mainboard/thomson/ip1000/romstage.c Tue Apr 13 23:31:42 2010 (r5422) +++ trunk/src/mainboard/thomson/ip1000/romstage.c Wed Apr 14 09:47:07 2010 (r5423) @@ -96,9 +96,7 @@ pci_write_config8(PCI_DEV(0, 0x1f, 0), ACPI_CNTL, 0x10); } -#include "cpu/intel/model_6bx/cache_as_ram_disable.c" - -void real_main(unsigned long bist) +void main(unsigned long bist) { if (bist == 0) { if (memory_initialized()) { Modified: trunk/src/mainboard/tyan/s2735/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/romstage.c Tue Apr 13 23:31:42 2010 (r5422) +++ trunk/src/mainboard/tyan/s2735/romstage.c Wed Apr 14 09:47:07 2010 (r5423) @@ -63,9 +63,7 @@ #include "northbridge/intel/e7501/reset_test.c" #include "lib/generic_sdram.c" - - -void stage1_main(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller memctrl[] = { { @@ -97,8 +95,7 @@ // setup_s2735_resource_map(); if(bios_reset_detected()) { - cpu_reset = 1; - goto cpu_reset_x; + hard_reset(); } enable_smbus(); @@ -119,94 +116,5 @@ #if 1 dump_pci_device(PCI_DEV(0, 0, 0)); #endif - -#if 1 - { - /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ - unsigned v_esp; - __asm__ volatile ( - "movl %%esp, %0\n\t" - : "=a" (v_esp) - ); -#if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp); -#else - print_debug("v_esp="); print_debug_hex32(v_esp); print_debug("\n"); -#endif - } - -#endif -#if 1 - -cpu_reset_x: - -#if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "cpu_reset = %08x\n",cpu_reset); -#else - print_debug("cpu_reset = "); print_debug_hex32(cpu_reset); print_debug("\n"); -#endif - - if(cpu_reset == 0) { - print_debug("Clearing initial memory region: "); - } - print_debug("No cache as ram now - "); - - /* store cpu_reset to ebx */ - __asm__ volatile ( - "movl %0, %%ebx\n\t" - ::"a" (cpu_reset) - ); - - if(cpu_reset==0) { -#define CLEAR_FIRST_1M_RAM 1 -#include "cpu/x86/car/cache_as_ram_post.c" - } - else { -#undef CLEAR_FIRST_1M_RAM -#include "cpu/x86/car/cache_as_ram_post.c" - } - - __asm__ volatile ( - /* set new esp */ /* before CONFIG_RAMBASE */ - "subl %0, %%ebp\n\t" - "subl %0, %%esp\n\t" - ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE ) - ); - - { - unsigned new_cpu_reset; - - /* get back cpu_reset from ebx */ - __asm__ volatile ( - "movl %%ebx, %0\n\t" - :"=a" (new_cpu_reset) - ); - - /* We can not go back any more, we lost old stack data in cache as ram*/ - if(new_cpu_reset==0) { - print_debug("Use Ram as Stack now - done\n"); - } else - { - print_debug("Use Ram as Stack now - \n"); - } -#if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset); -#else - print_debug("new_cpu_reset = "); print_debug_hex32(new_cpu_reset); print_debug("\n"); -#endif - -#ifdef DEACTIVATE_CAR - print_debug("Deactivating CAR"); -#include DEACTIVATE_CAR_FILE - print_debug(" - Done.\n"); -#endif - /*copy and execute coreboot_ram */ - copy_and_run(new_cpu_reset); - /* We will not return */ - } -#endif - - print_debug("should not be here -\n"); - } Modified: trunk/src/northbridge/via/vx800/examples/romstage.c ============================================================================== --- trunk/src/northbridge/via/vx800/examples/romstage.c Tue Apr 13 23:31:42 2010 (r5422) +++ trunk/src/northbridge/via/vx800/examples/romstage.c Wed Apr 14 09:47:07 2010 (r5423) @@ -300,7 +300,7 @@ /* cache_as_ram.inc jump to here */ -void stage1_main(unsigned long bist) +void main(unsigned long bist) { unsigned cpu_reset = 0; u16 boot_mode; @@ -556,103 +556,4 @@ );*/ } #endif -/* -the following code is copied from src/mainboard/tyan/s2735/romstage.c -Only the code around CLEAR_FIRST_1M_RAM is changed. -I remove all the code around CLEAR_FIRST_1M_RAM and #include "cpu/x86/car/cache_as_ram_post.c" -the CLEAR_FIRST_1M_RAM seems to make cpu/x86/car/cache_as_ram_post.c stop at somewhere, -and cpu/x86/car/cache_as_ram_post.c do not cache my $CONFIG_XIP_ROM_BASE+SIZE area. - -So, I use: #include "cpu/via/car/cache_as_ram_post.c". my via-version post.c have some diff with x86-version -*/ -#if 1 - { - /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ - unsigned v_esp; - __asm__ volatile ("movl %%esp, %0\n\t":"=a" (v_esp) - ); -#if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "v_esp=%08x\n", v_esp); -#else - print_debug("v_esp="); - print_debug_hex32(v_esp); - print_debug("\n"); -#endif - } - -#endif -#if 1 - - cpu_reset_x: -// it seems that cpu_reset is not used before this, so I just reset it, (this is because the s3 resume, setting in mtrr and copy data may destroy -//stack - cpu_reset = 0; -#if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "cpu_reset = %08x\n", cpu_reset); -#else - print_debug("cpu_reset = "); - print_debug_hex32(cpu_reset); - print_debug("\n"); -#endif - - if (cpu_reset == 0) { - print_debug("Clearing initial memory region: "); - } - print_debug("No cache as ram now - "); - - /* store cpu_reset to ebx */ - __asm__ volatile ("movl %0, %%ebx\n\t"::"a" (cpu_reset) - ); - - -/* cancel these lines, CLEAR_FIRST_1M_RAM cause the cpu/x86/car/cache_as_ram_post.c stop at somewhere - - if(cpu_reset==0) { -#define CLEAR_FIRST_1M_RAM 1 -#include "cpu/via/car/cache_as_ram_post.c" - } - else { -#undef CLEAR_FIRST_1M_RAM -#include "cpu/via/car/cache_as_ram_post.c" - } -*/ -#include "cpu/via/car/cache_as_ram_post.c" -//#include "cpu/x86/car/cache_as_ram_post.c" - __asm__ volatile ( - /* set new esp *//* before CONFIG_RAMBASE */ - "subl %0, %%ebp\n\t" - "subl %0, %%esp\n\t":: - "a" ((CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE) - - CONFIG_RAMBASE) - ); - - { - unsigned new_cpu_reset; - - /* get back cpu_reset from ebx */ - __asm__ volatile ("movl %%ebx, %0\n\t":"=a" (new_cpu_reset) - ); - - /* We can not go back any more, we lost old stack data in cache as ram */ - if (new_cpu_reset == 0) { - print_debug("Use Ram as Stack now - done\n"); - } else { - print_debug("Use Ram as Stack now - \n"); - } -#if CONFIG_USE_PRINTK_IN_CAR - printk(BIOS_DEBUG, "new_cpu_reset = %08x\n", new_cpu_reset); -#else - print_debug("new_cpu_reset = "); - print_debug_hex32(new_cpu_reset); - print_debug("\n"); -#endif - /*copy and execute coreboot_ram */ - copy_and_run(new_cpu_reset); - /* We will not return */ - } -#endif - - - print_debug("should not be here -\n"); - }

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[commit] r5422 - in trunk/src: mainboard/thomson/ip1000 northbridge/intel/i82830
by repository service 13 Apr '10

13 Apr '10

Author: stepan Date: Tue Apr 13 23:31:42 2010 New Revision: 5422 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5422 Log: ip1000: fix seabios start, fix flash gpio detection simplify i82830 code. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/thomson/ip1000/mainboard.c trunk/src/northbridge/intel/i82830/northbridge.c Modified: trunk/src/mainboard/thomson/ip1000/mainboard.c ============================================================================== --- trunk/src/mainboard/thomson/ip1000/mainboard.c Tue Apr 13 23:29:43 2010 (r5421) +++ trunk/src/mainboard/thomson/ip1000/mainboard.c Tue Apr 13 23:31:42 2010 (r5422) @@ -74,27 +74,15 @@ static void flash_gpios(void) { - u32 flash_base = 0xfff80000; - u8 manufacturer_id, device_id; - - // reset mode - write8(flash_base, 0xff); - udelay(10); - // read id - write8(flash_base, 0x90); - udelay(10); - manufacturer_id = read8(flash_base); - device_id = read8(flash_base + 1); - // reset mode - write8(flash_base, 0xff); - udelay(10); + u8 manufacturer_id = read8(0xffbc0000); + u8 device_id = read8(0xffbc0001); if ((manufacturer_id == 0x20) && ((device_id == 0x2c) || (device_id == 0x2d))) { printk(BIOS_DEBUG, "Detected ST M50FW0%c0 flash:\n", (device_id==0x2c)?'4':'8'); u8 fgpi = read8(0xffbc0100); - printk(BIOS_DEBUG, " FGPI0 [%c] FGPI1 [%c] FGPI2 [%c] FGPI3 [%c] FGPI4 [%c]", + printk(BIOS_DEBUG, " FGPI0 [%c] FGPI1 [%c] FGPI2 [%c] FGPI3 [%c] FGPI4 [%c]\n", (fgpi & (1 << 0)) ? 'X' : ' ', (fgpi & (1 << 1)) ? 'X' : ' ', (fgpi & (1 << 2)) ? 'X' : ' ', @@ -109,7 +97,6 @@ #if CONFIG_PCI_OPTION_ROM_RUN_YABEL static int int15_handler(void) { - u8 display_id; #define BOOT_DISPLAY_DEFAULT 0 #define BOOT_DISPLAY_CRT (1 << 0) #define BOOT_DISPLAY_TV (1 << 1) @@ -126,8 +113,8 @@ switch (M.x86.R_AX) { case 0x5f35: /* Boot Display */ M.x86.R_AX = 0x005f; // Success - // M.x86.R_CL = BOOT_DISPLAY_TV; - M.x86.R_CL = BOOT_DISPLAY_DEFAULT; + M.x86.R_CL = BOOT_DISPLAY_TV2; + //M.x86.R_CL = BOOT_DISPLAY_DEFAULT; break; case 0x5f36: /* Boot TV Format Hook */ printk(BIOS_DEBUG, "Boot TV Format Hook. TODO\n"); Modified: trunk/src/northbridge/intel/i82830/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i82830/northbridge.c Tue Apr 13 23:29:43 2010 (r5421) +++ trunk/src/northbridge/intel/i82830/northbridge.c Tue Apr 13 23:31:42 2010 (r5422) @@ -114,49 +114,52 @@ pci_tolm = find_pci_tolm(&dev->link[0]); mc_dev = dev->link[0].children; - if (mc_dev) { - unsigned long tomk, tolmk; - int idx; - - if (CONFIG_VIDEO_MB == 512) { - igd_memory = (CONFIG_VIDEO_MB); - printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory >> 10); - } else { - igd_memory = (CONFIG_VIDEO_MB * 1024); - printk(BIOS_DEBUG, "%dMB IGD UMA\n", igd_memory >> 10); - } - - /* Get the value of the highest DRB. This tells the end of - * the physical memory. The units are ticks of 32MB - * i.e. 1 means 32MB. - */ - tomk = ((unsigned long)pci_read_config8(mc_dev, DRB + 3)) << 15; - tomk -= igd_memory; - - /* For reserving UMA memory in the memory map */ - uma_memory_base = tomk * 1024ULL; - uma_memory_size = igd_memory * 1024ULL; - printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk); - - /* Compute the top of low memory. */ - tolmk = pci_tolm >> 10; - if (tolmk >= tomk) { - /* The PCI hole does does not overlap the memory. */ - tolmk = tomk; - } - - /* Report the memory regions. */ - idx = 10; - ram_resource(dev, idx++, 0, 640); - ram_resource(dev, idx++, 1024, tolmk - 1024); + if (!mc_dev) + return; -#if CONFIG_WRITE_HIGH_TABLES==1 - /* Leave some space for ACPI, PIRQ and MP tables */ - high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; - high_tables_size = HIGH_TABLES_SIZE * 1024; -#endif + unsigned long tomk, tolmk; + int idx; + + if (CONFIG_VIDEO_MB == 512) { + igd_memory = (CONFIG_VIDEO_MB); + printk(BIOS_DEBUG, "%dKB IGD UMA\n", igd_memory >> 10); + } else { + igd_memory = (CONFIG_VIDEO_MB * 1024); + printk(BIOS_DEBUG, "%dMB IGD UMA\n", igd_memory >> 10); + } + + /* Get the value of the highest DRB. This tells the end of + * the physical memory. The units are ticks of 32MB + * i.e. 1 means 32MB. + */ + tomk = ((unsigned long)pci_read_config8(mc_dev, DRB + 3)) << 15; + tomk -= igd_memory; + + /* For reserving UMA memory in the memory map */ + uma_memory_base = tomk * 1024ULL; + uma_memory_size = igd_memory * 1024ULL; + printk(BIOS_DEBUG, "Available memory: %ldKB\n", tomk); + + /* Compute the top of low memory. */ + tolmk = pci_tolm >> 10; + if (tolmk >= tomk) { + /* The PCI hole does does not overlap the memory. */ + tolmk = tomk; } + + /* Report the memory regions. */ + idx = 10; + ram_resource(dev, idx++, 0, 640); + ram_resource(dev, idx++, 768, 256); + ram_resource(dev, idx++, 1024, tolmk - 1024); + assign_resources(&dev->link[0]); + +#if CONFIG_WRITE_HIGH_TABLES==1 + /* Leave some space for ACPI, PIRQ and MP tables */ + high_tables_base = (tomk - HIGH_TABLES_SIZE) * 1024; + high_tables_size = HIGH_TABLES_SIZE * 1024; +#endif } static struct device_operations pci_domain_ops = {

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[commit] r5421 - trunk/src/devices/oprom/yabel
by repository service 13 Apr '10

13 Apr '10

Author: stepan Date: Tue Apr 13 23:29:43 2010 New Revision: 5421 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5421 Log: fix a trivial warning when yabel with direct hw access is enabled. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/devices/oprom/yabel/io.c Modified: trunk/src/devices/oprom/yabel/io.c ============================================================================== --- trunk/src/devices/oprom/yabel/io.c Tue Apr 13 15:48:20 2010 (r5420) +++ trunk/src/devices/oprom/yabel/io.c Tue Apr 13 23:29:43 2010 (r5421) @@ -24,52 +24,6 @@ #include <device/pci_ops.h> #endif -static unsigned int -read_io(void *addr, size_t sz) -{ - unsigned int ret; - /* since we are using inb instructions, we need the port number as 16bit value */ - u16 port = (u16)(u32) addr; - - switch (sz) { - case 1: - asm volatile ("inb %1, %b0" : "=a"(ret) : "d" (port)); - break; - case 2: - asm volatile ("inw %1, %w0" : "=a"(ret) : "d" (port)); - break; - case 4: - asm volatile ("inl %1, %0" : "=a"(ret) : "d" (port)); - break; - default: - ret = 0; - } - - return ret; -} - -static int -write_io(void *addr, unsigned int value, size_t sz) -{ - u16 port = (u16)(u32) addr; - switch (sz) { - /* since we are using inb instructions, we need the port number as 16bit value */ - case 1: - asm volatile ("outb %b0, %1" : : "a"(value), "d" (port)); - break; - case 2: - asm volatile ("outw %w0, %1" : : "a"(value), "d" (port)); - break; - case 4: - asm volatile ("outl %0, %1" : : "a"(value), "d" (port)); - break; - default: - return -1; - } - - return 0; -} - #ifdef CONFIG_ARCH_X86 #include <arch/io.h> #else @@ -172,6 +126,52 @@ #else +static unsigned int +read_io(void *addr, size_t sz) +{ + unsigned int ret; + /* since we are using inb instructions, we need the port number as 16bit value */ + u16 port = (u16)(u32) addr; + + switch (sz) { + case 1: + asm volatile ("inb %1, %b0" : "=a"(ret) : "d" (port)); + break; + case 2: + asm volatile ("inw %1, %w0" : "=a"(ret) : "d" (port)); + break; + case 4: + asm volatile ("inl %1, %0" : "=a"(ret) : "d" (port)); + break; + default: + ret = 0; + } + + return ret; +} + +static int +write_io(void *addr, unsigned int value, size_t sz) +{ + u16 port = (u16)(u32) addr; + switch (sz) { + /* since we are using inb instructions, we need the port number as 16bit value */ + case 1: + asm volatile ("outb %b0, %1" : : "a"(value), "d" (port)); + break; + case 2: + asm volatile ("outw %w0, %1" : : "a"(value), "d" (port)); + break; + case 4: + asm volatile ("outl %0, %1" : : "a"(value), "d" (port)); + break; + default: + return -1; + } + + return 0; +} + u32 pci_cfg_read(X86EMU_pioAddr addr, u8 size); void pci_cfg_write(X86EMU_pioAddr addr, u32 val, u8 size); u8 handle_port_61h(void);

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another patch for FILO building error
by baiyin cai 13 Apr '10

13 Apr '10

Hi, attached patch does: - add extern declaration of UNIQUE_BUF Signed-off-by: Cai Bai Yin <caibaiyin.pku(a)gmail.com>

2 1

[FILO] r125 - trunk/filo/include/grub
by repository service 13 Apr '10

13 Apr '10

Author: stepan Date: Tue Apr 13 22:34:58 2010 New Revision: 125 URL: http://tracker.coreboot.org/trac/filo/changeset/125 Log: add extern declaration of UNIQUE_BUF (fixes CONFIG_EXPERIMENTAL compilation) Signed-off-by: Cai Bai Yin <caibaiyin.pku(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/filo/include/grub/shared.h Modified: trunk/filo/include/grub/shared.h ============================================================================== --- trunk/filo/include/grub/shared.h Sun Apr 11 13:37:06 2010 (r124) +++ trunk/filo/include/grub/shared.h Tue Apr 13 22:34:58 2010 (r125) @@ -55,6 +55,7 @@ #define COMPLETION_BUFLEN MAX_CMDLINE /* The buffer for the unique string. */ +extern char UNIQUE_BUF[]; #define UNIQUE_BUFLEN MAX_CMDLINE /* The buffer for the menu entries. */

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Jetway PA78VM5-H support?
by Scott Olsen 13 Apr '10

13 Apr '10

Hello, I noticed that AMD RS780/SB700 support has recently gotten initial support. I was wondering if the Jetway PA78VM5-H board is suitable for support? I've attached the lspci/superiotool/flashrom outputs. Thanks! Scott -- JetWay JPA78VM5-H-LF AM2+/AM2 AMD 780V HDMI Micro ATX AMD Motherboard - Retail<http://www.newegg.com/Product/Product.aspx?Item=N82E16813153138&cm_re=jetwa…> Model Brand JetWay Model JPA78VM5-H-LF Supported CPU CPU Socket Type AM2+/AM2 CPU Type Phenom / Athlon 64 X2 / Athlon 64 / Sempron FSB 2600MHz Hyper Transport (5200 MT/s) Chipsets North Bridge AMD 780V South Bridge AMD SB700

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build service results for r5420
by coreboot information 13 Apr '10

13 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5420 to the coreboot repository. This caused the following changes: Change Log: fix timer choice in Kconfig. HAVE_INIT_TIMER is selected correctly, no need to mention it explicitly. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of digitallogic:msm586seg has been fixed Compilation of technologic:ts5300 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r5419
by coreboot information 13 Apr '10

13 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5419 to the coreboot repository. This caused the following changes: Change Log: clean up LD scripts and add some comments and proper license headers where applicable. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of digitallogic:msm586seg is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5419&device=msm586seg&vend… Compilation of technologic:ts5300 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5419&device=ts5300&vendor=… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5420 - in trunk/src: cpu/amd/model_10xxx cpu/amd/model_fxx cpu/amd/sc520 cpu/intel/model_106cx cpu/intel/model_6ex cpu/intel/model_6fx mainboard/intel/d945gclf mainboard/kontron/986lcd-m ...
by repository service 13 Apr '10

13 Apr '10

Author: stepan Date: Tue Apr 13 15:48:20 2010 New Revision: 5420 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5420 Log: fix timer choice in Kconfig. HAVE_INIT_TIMER is selected correctly, no need to mention it explicitly. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/amd/model_10xxx/Kconfig trunk/src/cpu/amd/model_fxx/Kconfig trunk/src/cpu/amd/sc520/Kconfig trunk/src/cpu/intel/model_106cx/Kconfig trunk/src/cpu/intel/model_6ex/Kconfig trunk/src/cpu/intel/model_6fx/Kconfig trunk/src/mainboard/intel/d945gclf/Kconfig trunk/src/mainboard/kontron/986lcd-m/Kconfig trunk/src/mainboard/roda/rk886ex/Kconfig Modified: trunk/src/cpu/amd/model_10xxx/Kconfig ============================================================================== --- trunk/src/cpu/amd/model_10xxx/Kconfig Tue Apr 13 15:43:35 2010 (r5419) +++ trunk/src/cpu/amd/model_10xxx/Kconfig Tue Apr 13 15:48:20 2010 (r5420) @@ -4,7 +4,6 @@ select USE_DCACHE_RAM select SSE select SSE2 - select HAVE_INIT_TIMER config CPU_ADDR_BITS int Modified: trunk/src/cpu/amd/model_fxx/Kconfig ============================================================================== --- trunk/src/cpu/amd/model_fxx/Kconfig Tue Apr 13 15:43:35 2010 (r5419) +++ trunk/src/cpu/amd/model_fxx/Kconfig Tue Apr 13 15:48:20 2010 (r5420) @@ -5,7 +5,6 @@ select MMX select SSE select SSE2 - select HAVE_INIT_TIMER config CPU_ADDR_BITS int Modified: trunk/src/cpu/amd/sc520/Kconfig ============================================================================== --- trunk/src/cpu/amd/sc520/Kconfig Tue Apr 13 15:43:35 2010 (r5419) +++ trunk/src/cpu/amd/sc520/Kconfig Tue Apr 13 15:48:20 2010 (r5420) @@ -1,12 +1,2 @@ config CPU_AMD_SC520 bool - -config UDELAY_IO - bool - default n - depends on CPU_AMD_SC520 - -config HAVE_INIT_TIMER - bool - default n - depends on CPU_AMD_SC520 Modified: trunk/src/cpu/intel/model_106cx/Kconfig ============================================================================== --- trunk/src/cpu/intel/model_106cx/Kconfig Tue Apr 13 15:43:35 2010 (r5419) +++ trunk/src/cpu/intel/model_106cx/Kconfig Tue Apr 13 15:48:20 2010 (r5420) @@ -2,3 +2,5 @@ bool select SMP select SSE2 + select UDELAY_LAPIC + select AP_IN_SIPI_WAIT Modified: trunk/src/cpu/intel/model_6ex/Kconfig ============================================================================== --- trunk/src/cpu/intel/model_6ex/Kconfig Tue Apr 13 15:43:35 2010 (r5419) +++ trunk/src/cpu/intel/model_6ex/Kconfig Tue Apr 13 15:48:20 2010 (r5420) @@ -2,3 +2,5 @@ bool select SMP select SSE2 + select UDELAY_LAPIC + select AP_IN_SIPI_WAIT Modified: trunk/src/cpu/intel/model_6fx/Kconfig ============================================================================== --- trunk/src/cpu/intel/model_6fx/Kconfig Tue Apr 13 15:43:35 2010 (r5419) +++ trunk/src/cpu/intel/model_6fx/Kconfig Tue Apr 13 15:48:20 2010 (r5420) @@ -2,3 +2,5 @@ bool select SMP select SSE2 + select UDELAY_LAPIC + select AP_IN_SIPI_WAIT Modified: trunk/src/mainboard/intel/d945gclf/Kconfig ============================================================================== --- trunk/src/mainboard/intel/d945gclf/Kconfig Tue Apr 13 15:43:35 2010 (r5419) +++ trunk/src/mainboard/intel/d945gclf/Kconfig Tue Apr 13 15:48:20 2010 (r5420) @@ -37,8 +37,6 @@ select HAVE_MAINBOARD_RESOURCES select MMCONF_SUPPORT select USE_PRINTK_IN_CAR - select AP_IN_SIPI_WAIT - select UDELAY_LAPIC select HAVE_ACPI_TABLES select HAVE_SMI_HANDLER select BOARD_ROMSIZE_KB_512 Modified: trunk/src/mainboard/kontron/986lcd-m/Kconfig ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/Kconfig Tue Apr 13 15:43:35 2010 (r5419) +++ trunk/src/mainboard/kontron/986lcd-m/Kconfig Tue Apr 13 15:48:20 2010 (r5420) @@ -15,8 +15,6 @@ select HAVE_MAINBOARD_RESOURCES select MMCONF_SUPPORT select USE_PRINTK_IN_CAR - select AP_IN_SIPI_WAIT - select UDELAY_LAPIC select HAVE_SMI_HANDLER select BOARD_ROMSIZE_KB_1024 select USE_DCACHE_RAM Modified: trunk/src/mainboard/roda/rk886ex/Kconfig ============================================================================== --- trunk/src/mainboard/roda/rk886ex/Kconfig Tue Apr 13 15:43:35 2010 (r5419) +++ trunk/src/mainboard/roda/rk886ex/Kconfig Tue Apr 13 15:48:20 2010 (r5420) @@ -13,8 +13,6 @@ select HAVE_MP_TABLE select MMCONF_SUPPORT select USE_PRINTK_IN_CAR - select AP_IN_SIPI_WAIT - select UDELAY_LAPIC select HAVE_SMI_HANDLER select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME

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coreboot April 2010