coreboot April 2010

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[commit] r5442 - in trunk/src: drivers/ati/ragexl include/boot mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/serengeti_cheetah main...
by repository service 15 Apr '10

15 Apr '10

Author: stepan Date: Thu Apr 15 14:39:29 2010 New Revision: 5442 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5442 Log: zero warnings days... Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/drivers/ati/ragexl/mach64_ct.c trunk/src/drivers/ati/ragexl/xlinit.c trunk/src/include/boot/tables.h trunk/src/mainboard/amd/dbm690t/mainboard.c trunk/src/mainboard/amd/mahogany/mainboard.c trunk/src/mainboard/amd/mahogany_fam10/mainboard.c trunk/src/mainboard/amd/pistachio/mainboard.c trunk/src/mainboard/amd/serengeti_cheetah/romstage.c trunk/src/mainboard/asrock/939a785gmh/get_bus_conf.c trunk/src/mainboard/asrock/939a785gmh/mainboard.c trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/asus/m2v-mx_se/mainboard.c trunk/src/mainboard/asus/m2v-mx_se/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/intel/eagleheights/debug.c trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/kontron/kt690/mainboard.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/olpc/btest/mainboard.c trunk/src/mainboard/sunw/ultra40/get_bus_conf.c trunk/src/mainboard/sunw/ultra40/irq_tables.c trunk/src/mainboard/sunw/ultra40/mptable.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/technexion/tim5690/mainboard.c trunk/src/mainboard/technexion/tim5690/vgabios.c trunk/src/mainboard/technexion/tim8690/mainboard.c trunk/src/mainboard/tyan/s2735/romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/via/epia-m700/Makefile.inc trunk/src/mainboard/via/epia-m700/wakeup.c trunk/src/mainboard/via/epia-n/mainboard.c trunk/src/northbridge/amd/amdk8/raminit_f.c trunk/src/northbridge/intel/e7501/debug.c trunk/src/northbridge/intel/e7501/raminit.c trunk/src/northbridge/intel/e7501/raminit.h trunk/src/northbridge/intel/i82830/northbridge.c trunk/src/northbridge/intel/i945/northbridge.c trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c trunk/src/southbridge/via/vt8235/vt8235.c Modified: trunk/src/drivers/ati/ragexl/mach64_ct.c ============================================================================== --- trunk/src/drivers/ati/ragexl/mach64_ct.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/drivers/ati/ragexl/mach64_ct.c Thu Apr 15 14:39:29 2010 (r5442) @@ -1,4 +1,5 @@ #define DEBUG_PLL 0 +#define PLL_CRTC_DECODE 0 /* FIXME: remove the FAIL definition */ #if 0 @@ -123,9 +124,7 @@ #if DEBUG_PLL==1 int pllmclk, pllsclk; #endif - - u32 q, x; /* x is a workaround for sparc64-linux-gcc */ - x = x; /* x is a workaround for sparc64-linux-gcc */ + u32 q; pll->pll_ref_div = info->pll_per*2*255/info->ref_clk_per; Modified: trunk/src/drivers/ati/ragexl/xlinit.c ============================================================================== --- trunk/src/drivers/ati/ragexl/xlinit.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/drivers/ati/ragexl/xlinit.c Thu Apr 15 14:39:29 2010 (r5442) @@ -485,12 +485,12 @@ static void ati_ragexl_init(device_t dev) { u32 chip_id; - u32 i; int j; u16 type; u8 rev; const char *chipname = NULL; #if CONFIG_CONSOLE_BTEXT + u32 i; const char *xtal; #endif int pll, mclk, xclk; Modified: trunk/src/include/boot/tables.h ============================================================================== --- trunk/src/include/boot/tables.h Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/include/boot/tables.h Thu Apr 15 14:39:29 2010 (r5442) @@ -2,6 +2,7 @@ #define BOOT_TABLES_H #include <boot/coreboot_tables.h> +#include <arch/coreboot_tables.h> void lb_add_memory_range(struct lb_memory *mem, uint32_t type, uint64_t start, uint64_t size); Modified: trunk/src/mainboard/amd/dbm690t/mainboard.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/mainboard.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/amd/dbm690t/mainboard.c Thu Apr 15 14:39:29 2010 (r5442) @@ -21,12 +21,11 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> +#include <boot/tables.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include <../southbridge/amd/sb600/sb600.h> +#include <southbridge/amd/sb600/sb600.h> #include "chip.h" #define ADT7461_ADDRESS 0x4C @@ -36,8 +35,6 @@ extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, - uint64_t start, uint64_t size); #define ADT7461_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) #define ARA_read_byte(address) \ Modified: trunk/src/mainboard/amd/mahogany/mainboard.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/mainboard.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/amd/mahogany/mainboard.c Thu Apr 15 14:39:29 2010 (r5442) @@ -21,19 +21,15 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <boot/coreboot_tables.h> +#include <boot/tables.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include <arch/coreboot_tables.h> -#include <../southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/sb700.h> #include "chip.h" #define SMBUS_IO_BASE 0x6000 -extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, - uint64_t start, uint64_t size); - uint64_t uma_memory_base, uma_memory_size; void set_pcie_dereset(void); Modified: trunk/src/mainboard/amd/mahogany_fam10/mainboard.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/mainboard.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/amd/mahogany_fam10/mainboard.c Thu Apr 15 14:39:29 2010 (r5442) @@ -21,19 +21,15 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <boot/coreboot_tables.h> +#include <boot/tables.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include <arch/coreboot_tables.h> -#include <../southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/sb700.h> #include "chip.h" #define SMBUS_IO_BASE 0x6000 -extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, - uint64_t start, uint64_t size); - uint64_t uma_memory_base, uma_memory_size; void set_pcie_dereset(void); Modified: trunk/src/mainboard/amd/pistachio/mainboard.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/mainboard.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/amd/pistachio/mainboard.c Thu Apr 15 14:39:29 2010 (r5442) @@ -21,12 +21,11 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> +#include <boot/tables.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include <../southbridge/amd/sb600/sb600.h> +#include <southbridge/amd/sb600/sb600.h> #include "chip.h" #define ADT7475_ADDRESS 0x2E @@ -35,9 +34,6 @@ extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, - uint64_t start, uint64_t size); - #define ADT7475_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7475_ADDRESS, address) #define ADT7475_write_byte(address, val) \ Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Thu Apr 15 14:39:29 2010 (r5442) @@ -101,12 +101,9 @@ } #include "northbridge/amd/amdk8/amdk8.h" -#include "northbridge/amd/amdk8/coherent_ht.c" - #include "northbridge/amd/amdk8/incoherent_ht.c" - +#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" - #include "lib/generic_sdram.c" /* tyan does not want the default */ Modified: trunk/src/mainboard/asrock/939a785gmh/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/get_bus_conf.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/asrock/939a785gmh/get_bus_conf.c Thu Apr 15 14:39:29 2010 (r5442) @@ -63,8 +63,6 @@ static u32 get_bus_conf_done = 0; -void get_bus_conf(void); - void get_bus_conf(void) { u32 apicid_base; Modified: trunk/src/mainboard/asrock/939a785gmh/mainboard.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/mainboard.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/asrock/939a785gmh/mainboard.c Thu Apr 15 14:39:29 2010 (r5442) @@ -21,19 +21,15 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <boot/coreboot_tables.h> +#include <boot/tables.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include <arch/coreboot_tables.h> -#include <../southbridge/amd/sb700/sb700.h> +#include <southbridge/amd/sb700/sb700.h> #include "chip.h" #define SMBUS_IO_BASE 0x6000 -extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, - uint64_t start, uint64_t size); - uint64_t uma_memory_base, uma_memory_size; void set_pcie_dereset(void); Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Thu Apr 15 14:39:29 2010 (r5442) @@ -105,10 +105,11 @@ #define K8_4RANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/amdk8.h" -#include "northbridge/amd/amdk8/raminit.c" -#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit.c" #include "lib/generic_sdram.c" + #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/via/k8t890/k8t890_early_car.c" @@ -126,7 +127,7 @@ return (dev >> 15) & 0x1f; } -void sio_init(void) +static void sio_init(void) { u8 reg; @@ -171,17 +172,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { + // Node 0 (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 + // Node 1 (0xa << 3) | 4, (0xa << 3) | 6, 0, 0, (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, -#endif }; unsigned bsp_apicid = 0; int needs_reset = 0; - struct sys_info *sysinfo = - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); sio_init(); w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); Modified: trunk/src/mainboard/asus/m2v-mx_se/mainboard.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/mainboard.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/asus/m2v-mx_se/mainboard.c Thu Apr 15 14:39:29 2010 (r5442) @@ -21,9 +21,8 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <boot/tables.h> -#include <arch/coreboot_tables.h> -#include "chip.h" #include <southbridge/via/k8t890/k8t890.h> +#include "chip.h" int add_mainboard_resources(struct lb_memory *mem) { Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Thu Apr 15 14:39:29 2010 (r5442) @@ -70,10 +70,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO) -static void memreset_setup(void) -{ -} - static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -83,18 +79,20 @@ return smbus_read_byte(device, address); } -void activate_spd_rom(const struct mem_controller *ctrl) +static void activate_spd_rom(const struct mem_controller *ctrl) { } #define K8_4RANK_DIMM_SUPPORT 1 #include "southbridge/via/k8t890/k8t890_early_car.c" + #include "northbridge/amd/amdk8/amdk8.h" -#include "northbridge/amd/amdk8/raminit_f.c" -#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" + #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" @@ -144,34 +142,21 @@ return (dev >> 15) & 0x1f; } -void sio_init(void) -{ - -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx); - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - real_main(bist, cpu_init_detectedx); -} - -void real_main(unsigned long bist, unsigned long cpu_init_detectedx) -{ static const uint16_t spd_addr[] = { + // Node 0 (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 + // Node 1 (0xa << 3) | 4, (0xa << 3) | 6, 0, 0, (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, -#endif }; unsigned bsp_apicid = 0; int needs_reset = 0; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - sio_init(); it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); it8712f_kill_watchdog(); it8712f_enable_3vsbsw(); @@ -234,7 +219,6 @@ /* It's the time to set ctrl now. */ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); - memreset_setup(); sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); } Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Thu Apr 15 14:39:29 2010 (r5442) @@ -86,10 +86,6 @@ #include "southbridge/sis/sis966/sis966_early_ctrl.c" -static void memreset_setup(void) -{ -} - static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -105,12 +101,9 @@ } #include "northbridge/amd/amdk8/amdk8_f.h" -#include "northbridge/amd/amdk8/coherent_ht.c" - #include "northbridge/amd/amdk8/incoherent_ht.c" - +#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" - #include "lib/generic_sdram.c" #include "resourcemap.c" @@ -165,12 +158,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { + // Node 0 (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 + // Node 1 (0xa<<3)|4, (0xa<<3)|6, 0, 0, (0xa<<3)|5, (0xa<<3)|7, 0, 0, -#endif }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + @@ -275,8 +268,6 @@ sis_init_stage1(); enable_smbus(); - memreset_setup(); - //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ // init_timer(); // Need to use TMICT to synconize FID/VID Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Thu Apr 15 14:39:29 2010 (r5442) @@ -84,10 +84,6 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" -static void memreset_setup(void) -{ -} - static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -103,12 +99,9 @@ } #include "northbridge/amd/amdk8/amdk8_f.h" -#include "northbridge/amd/amdk8/coherent_ht.c" - #include "northbridge/amd/amdk8/incoherent_ht.c" - +#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" - #include "lib/generic_sdram.c" #include "resourcemap.c" @@ -132,8 +125,6 @@ #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" - - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" @@ -145,8 +136,6 @@ static void sio_setup(void) { - - unsigned value; uint32_t dword; uint8_t byte; @@ -166,15 +155,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { + // Node 0 (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 + // Node 1 (0xa<<3)|4, (0xa<<3)|6, 0, 0, (0xa<<3)|5, (0xa<<3)|7, 0, 0, -#endif }; - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; @@ -289,8 +279,6 @@ enable_smbus(); - memreset_setup(); - //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ // init_timer(); // Need to use TMICT to synconize FID/VID Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Thu Apr 15 14:39:29 2010 (r5442) @@ -107,16 +107,11 @@ } #include "northbridge/amd/amdk8/amdk8_f.h" -#include "northbridge/amd/amdk8/coherent_ht.c" - #include "northbridge/amd/amdk8/incoherent_ht.c" - +#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" - #include "lib/generic_sdram.c" -//#include "resourcemap.c" - #include "cpu/amd/dualcore/dualcore.c" //first node @@ -212,8 +207,6 @@ pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - //setup_mp_resource_map(); - uart_init(); /* Halt if there was a built in self test failure */ Modified: trunk/src/mainboard/intel/eagleheights/debug.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/debug.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/intel/eagleheights/debug.c Thu Apr 15 14:39:29 2010 (r5442) @@ -38,7 +38,7 @@ return; } -static void xbus_en(void) +static inline void xbus_en(void) { /* select the XBUS function in the SIO */ outb(0x07, 0x2e); @@ -66,7 +66,7 @@ return; } -static void siodump(void) +static inline void siodump(void) { int i; unsigned char data; @@ -143,7 +143,7 @@ print_debug_hex8((dev >> 8) & 7); } -static void print_pci_devices(void) +static inline void print_pci_devices(void) { device_t dev; for(dev = PCI_DEV(0, 0, 0); @@ -161,7 +161,7 @@ } } -static void dump_pci_device(unsigned dev) +static inline void dump_pci_device(unsigned dev) { int i; print_debug_pci_dev(dev); @@ -182,7 +182,7 @@ } } -static void dump_bar14(unsigned dev) +static inline void dump_bar14(unsigned dev) { int i; unsigned long bar; @@ -227,70 +227,7 @@ } } -#if 0 -static void dump_spd_registers(const struct mem_controller *ctrl) -{ - int i; - print_debug("\n"); - for(i = 0; i < 4; i++) { - unsigned device; - device = ctrl->channel0[i]; - if (device) { - int j; - print_debug("dimm: "); - print_debug_hex8(i); - print_debug(".0: "); - print_debug_hex8(device); - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) { - print_debug("\n"); - print_debug_hex8(j); - print_debug(": "); - } - status = smbus_read_byte(device, j); - if (status < 0) { - print_debug("bad device\n"); - break; - } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); - } - print_debug("\n"); - } - device = ctrl->channel1[i]; - if (device) { - int j; - print_debug("dimm: "); - print_debug_hex8(i); - print_debug(".1: "); - print_debug_hex8(device); - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) { - print_debug("\n"); - print_debug_hex8(j); - print_debug(": "); - } - status = smbus_read_byte(device, j); - if (status < 0) { - print_debug("bad device\n"); - break; - } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); - } - print_debug("\n"); - } - } -} -#endif - -void dump_spd_registers(void) +static inline void dump_spd_registers(void) { unsigned device; device = SMBUS_MEM_DEVICE_START; @@ -322,7 +259,7 @@ } } -void dump_ipmi_registers(void) +static inline void dump_ipmi_registers(void) { unsigned device; device = 0x42; Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Thu Apr 15 14:39:29 2010 (r5442) @@ -90,12 +90,9 @@ } #include "northbridge/amd/amdk8/amdk8.h" -#include "northbridge/amd/amdk8/coherent_ht.c" - #include "northbridge/amd/amdk8/incoherent_ht.c" - +#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" - #include "lib/generic_sdram.c" #include "lib/ramtest.c" @@ -113,7 +110,6 @@ #define DIMM6 0x56 #define DIMM7 0x57 - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Thu Apr 15 14:39:29 2010 (r5442) @@ -90,12 +90,9 @@ } #include "northbridge/amd/amdk8/amdk8.h" -#include "northbridge/amd/amdk8/coherent_ht.c" - #include "northbridge/amd/amdk8/incoherent_ht.c" - +#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" - #include "lib/generic_sdram.c" #include "lib/ramtest.c" @@ -113,7 +110,6 @@ #define DIMM6 0x56 #define DIMM7 0x57 - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Thu Apr 15 14:39:29 2010 (r5442) @@ -90,12 +90,9 @@ } #include "northbridge/amd/amdk8/amdk8.h" -#include "northbridge/amd/amdk8/coherent_ht.c" - #include "northbridge/amd/amdk8/incoherent_ht.c" - +#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" - #include "lib/generic_sdram.c" #include "lib/ramtest.c" @@ -113,7 +110,6 @@ #define DIMM6 0x56 #define DIMM7 0x57 - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/kontron/kt690/mainboard.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/mainboard.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/kontron/kt690/mainboard.c Thu Apr 15 14:39:29 2010 (r5442) @@ -21,8 +21,7 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> +#include <boot/tables.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> @@ -36,8 +35,6 @@ extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, - uint64_t start, uint64_t size); #define ADT7461_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) #define ARA_read_byte(address) \ Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/msi/ms7260/romstage.c Thu Apr 15 14:39:29 2010 (r5442) @@ -83,7 +83,6 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" -static void memreset_setup(void) {} static void memreset(int controllers, const struct mem_controller *ctrl) {} static inline void activate_spd_rom(const struct mem_controller *ctrl) {} @@ -93,10 +92,11 @@ } #include "northbridge/amd/amdk8/amdk8_f.h" -#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" + #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -144,16 +144,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { + // Node 0 (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 + // Node 1 (0xa << 3) | 4, (0xa << 3) | 6, 0, 0, (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, -#endif }; - struct sys_info *sysinfo = - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + int needs_reset = 0; unsigned bsp_apicid = 0; @@ -252,8 +253,6 @@ enable_smbus(); - memreset_setup(); - /* Do we need apci timer, tsc...., only debug need it for better output */ /* All AP stopped? */ // init_timer(); /* Need to use TMICT to synconize FID/VID. */ Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/msi/ms9185/romstage.c Thu Apr 15 14:39:29 2010 (r5442) @@ -71,9 +71,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1) #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC) #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" -static void memreset_setup(void) -{ -} static void memreset(int controllers, const struct mem_controller *ctrl) { @@ -104,12 +101,9 @@ } #include "northbridge/amd/amdk8/amdk8_f.h" -#include "northbridge/amd/amdk8/coherent_ht.c" - #include "northbridge/amd/amdk8/incoherent_ht.c" - +#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" - #include "lib/generic_sdram.c" /* msi does not want the default */ @@ -129,7 +123,6 @@ #define DIMM6 0x56 #define DIMM7 0x57 - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" @@ -144,12 +137,9 @@ //first node RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 //second node RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, -#endif - }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + @@ -278,8 +268,6 @@ } #endif - memreset_setup(); - //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ // init_timer(); // Need to use TMICT to synconize FID/VID Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/msi/ms9282/romstage.c Thu Apr 15 14:39:29 2010 (r5442) @@ -68,9 +68,6 @@ #include <device/pci_ids.h> #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" -static void memreset_setup(void) -{ -} static void memreset(int controllers, const struct mem_controller *ctrl) { @@ -103,9 +100,9 @@ //#define K8_4RANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/amdk8_f.h" -#include "northbridge/amd/amdk8/raminit_f.c" -#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" /* msi does not want the default */ @@ -228,8 +225,6 @@ } #endif - memreset_setup(); - sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); Modified: trunk/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c Thu Apr 15 14:39:29 2010 (r5442) @@ -92,11 +92,9 @@ void get_bus_conf(void) { - unsigned apicid_base; struct mb_sysconf_t *m; - device_t dev; int i, j; if (get_bus_conf_done) @@ -160,5 +158,4 @@ #endif m->apicid_mcp55 = apicid_base+0; m->apicid_mcp55b = apicid_base+1; - } Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Thu Apr 15 14:39:29 2010 (r5442) @@ -83,10 +83,6 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" -static void memreset_setup(void) -{ -} - static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -102,12 +98,9 @@ } #include "northbridge/amd/amdk8/amdk8_f.h" -#include "northbridge/amd/amdk8/coherent_ht.c" - #include "northbridge/amd/amdk8/incoherent_ht.c" - +#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" - #include "lib/generic_sdram.c" #include "resourcemap.c" @@ -274,8 +267,6 @@ enable_smbus(); - memreset_setup(); - //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ // init_timer(); // Need to use TMICT to synconize FID/VID Modified: trunk/src/mainboard/olpc/btest/mainboard.c ============================================================================== --- trunk/src/mainboard/olpc/btest/mainboard.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/olpc/btest/mainboard.c Thu Apr 15 14:39:29 2010 (r5442) @@ -69,7 +69,7 @@ write_bit(rev > 0 ? 1 : 0); } -void +static void init_cafe_irq(void){ const unsigned char slots_cafe[4] = {11, 0, 0, 0}; Modified: trunk/src/mainboard/sunw/ultra40/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/get_bus_conf.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/sunw/ultra40/get_bus_conf.c Thu Apr 15 14:39:29 2010 (r5442) @@ -7,6 +7,7 @@ #include <cpu/amd/multicore.h> #endif #include <stdlib.h> +#include <cpu/amd/amdk8_sysconf.h> // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables Modified: trunk/src/mainboard/sunw/ultra40/irq_tables.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/irq_tables.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/sunw/ultra40/irq_tables.c Thu Apr 15 14:39:29 2010 (r5442) @@ -9,6 +9,7 @@ #include <string.h> #include <stdint.h> #include <arch/pirq_routing.h> +#include <cpu/amd/amdk8_sysconf.h> static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0, uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3, Modified: trunk/src/mainboard/sunw/ultra40/mptable.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/mptable.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/sunw/ultra40/mptable.c Thu Apr 15 14:39:29 2010 (r5442) @@ -3,6 +3,7 @@ #include <device/pci.h> #include <string.h> #include <stdint.h> +#include <cpu/amd/amdk8_sysconf.h> extern unsigned char bus_isa; extern unsigned char bus_ck804_0; //1 @@ -32,8 +33,6 @@ extern unsigned sbdn3; extern unsigned sbdnb; - - static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Thu Apr 15 14:39:29 2010 (r5442) @@ -77,10 +77,6 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" -static void memreset_setup(void) -{ -} - static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -154,12 +150,9 @@ } #include "northbridge/amd/amdk8/amdk8_f.h" -#include "northbridge/amd/amdk8/coherent_ht.c" - #include "northbridge/amd/amdk8/incoherent_ht.c" - +#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" - #include "lib/generic_sdram.c" #include "resourcemap.c" @@ -175,8 +168,6 @@ #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" - - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" @@ -340,8 +331,6 @@ enable_smbus(); /* enable in sio_setup */ - memreset_setup(); - //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ // init_timer(); // Need to use TMICT to synconize FID/VID Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Thu Apr 15 14:39:29 2010 (r5442) @@ -80,10 +80,6 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" -static void memreset_setup(void) -{ -} - static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -99,12 +95,9 @@ } #include "northbridge/amd/amdk8/amdk8_f.h" -#include "northbridge/amd/amdk8/coherent_ht.c" - #include "northbridge/amd/amdk8/incoherent_ht.c" - +#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" - #include "lib/generic_sdram.c" #include "resourcemap.c" @@ -120,8 +113,6 @@ #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" - - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" @@ -263,8 +254,6 @@ // enable_smbus(); /* enable in sio_setup */ - memreset_setup(); - //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ // init_timer(); // Need to use TMICT to synconize FID/VID @@ -272,6 +261,4 @@ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now - } - Modified: trunk/src/mainboard/technexion/tim5690/mainboard.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/mainboard.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/technexion/tim5690/mainboard.c Thu Apr 15 14:39:29 2010 (r5442) @@ -21,8 +21,7 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> +#include <boot/tables.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> @@ -179,7 +178,7 @@ } /* Mainboard specific GPIO setup. */ -void mb_gpio_init(u16 *iobase) +static void mb_gpio_init(u16 *iobase) { /* Init Super I/O GPIOs. */ it8712f_enter_conf(); @@ -193,7 +192,7 @@ } /* The LCD's panel id seletion. */ -void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id) +static void lcd_panel_id(rs690_vbios_regs *vbios_regs, u8 num_id) { switch (num_id) { case 0x1: @@ -226,9 +225,6 @@ *************************************************/ static void tim5690_enable(device_t dev) { - struct mainboard_config *mainboard = - (struct mainboard_config *)dev->chip_info; - rs690_vbios_regs vbios_regs; u16 gpio_base = IT8712F_SIMPLE_IO_BASE; u8 port2; @@ -240,6 +236,7 @@ /* The LCD's panel id seletion by switch. */ port2 = inb(gpio_base+1); lcd_panel_id(&vbios_regs, ((~port2) & 0xf)); + /* No support TV */ vbios_regs.int15_regs.fun05_tv_standard = TV_MODE_NO; vgabios_init(&vbios_regs); Modified: trunk/src/mainboard/technexion/tim5690/vgabios.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/vgabios.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/technexion/tim5690/vgabios.c Thu Apr 15 14:39:29 2010 (r5442) @@ -36,6 +36,7 @@ vbios_regs_local.int15_regs.fun00_panel_id = vbios_regs->int15_regs.fun00_panel_id; vbios_regs_local.int15_regs.fun05_tv_standard = vbios_regs->int15_regs.fun05_tv_standard; } + /* BIOS int15 function */ int tim5690_int15_handler(struct eregs *regs) { Modified: trunk/src/mainboard/technexion/tim8690/mainboard.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/mainboard.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/technexion/tim8690/mainboard.c Thu Apr 15 14:39:29 2010 (r5442) @@ -21,12 +21,11 @@ #include <device/device.h> #include <device/pci.h> #include <arch/io.h> -#include <boot/coreboot_tables.h> -#include <arch/coreboot_tables.h> +#include <boot/tables.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include <../southbridge/amd/sb600/sb600.h> +#include <southbridge/amd/sb600/sb600.h> #include "chip.h" #define ADT7461_ADDRESS 0x4C @@ -36,8 +35,6 @@ extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); -extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, - uint64_t start, uint64_t size); #define ADT7461_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) #define ARA_read_byte(address) \ Modified: trunk/src/mainboard/tyan/s2735/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/romstage.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/tyan/s2735/romstage.c Thu Apr 15 14:39:29 2010 (r5442) @@ -15,7 +15,6 @@ #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7501/raminit.h" -#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/intel/e7501/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/tyan/s2912/romstage.c Thu Apr 15 14:39:29 2010 (r5442) @@ -83,10 +83,6 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" -static void memreset_setup(void) -{ -} - static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -102,12 +98,9 @@ } #include "northbridge/amd/amdk8/amdk8_f.h" -#include "northbridge/amd/amdk8/coherent_ht.c" - #include "northbridge/amd/amdk8/incoherent_ht.c" - +#include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" - #include "lib/generic_sdram.c" #include "resourcemap.c" @@ -130,8 +123,6 @@ #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" - - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" @@ -271,8 +262,6 @@ enable_smbus(); - memreset_setup(); - //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ // init_timer(); // Need to use TMICT to synconize FID/VID @@ -280,6 +269,4 @@ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now - } - Modified: trunk/src/mainboard/via/epia-m700/Makefile.inc ============================================================================== --- trunk/src/mainboard/via/epia-m700/Makefile.inc Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/via/epia-m700/Makefile.inc Thu Apr 15 14:39:29 2010 (r5442) @@ -19,5 +19,8 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -obj-y += wakeup.o +# This code is unused and should be replaced by the generic resume code +# completely. If anyone works on wakeup for this chipset/board, delete +# wakeup.c when you are done. +# obj-y += wakeup.o Modified: trunk/src/mainboard/via/epia-m700/wakeup.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/wakeup.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/via/epia-m700/wakeup.c Thu Apr 15 14:39:29 2010 (r5442) @@ -19,6 +19,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* FIXME This code should be dropped and instead the generic resume code + * should be used. + */ + /* Parts of this code is taken from reboot.c from Linux. */ /* @@ -96,19 +100,6 @@ 0xea, 0x00, 0x00, 0x00, 0xe0 /* ljmp $0xffff, $0x0000 */ }; -/* - * Switch to real mode and then execute the code - * specified by the code and length parameters. - * We assume that length will aways be less that 100! - */ -static unsigned char show31[6] = { - 0xb0, 0x31, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff, $0x0000 */ -}; - -static unsigned char show32[6] = { - 0xb0, 0x32, 0xe6, 0x80, 0xeb, 0xFA /* ljmp $0xffff, $0x0000 */ -}; - void acpi_jump_wake(u32 vector) { u32 dwEip; @@ -337,8 +328,6 @@ * Enable A20 gate (return -1 on failure) */ -// #include "boot.h" - #define MAX_8042_LOOPS 100000 static int empty_8042(void) @@ -375,13 +364,9 @@ int ok = 0; int saved, ctr; -// set_fs(0x0000); -// set_gs(0xffff); - saved = ctr = *((u32 *) A20_TEST_ADDR); while (loops--) { - //wrfs32(++ctr, A20_TEST_ADDR); *((u32 *) A20_TEST_ADDR) = ++ctr; Modified: trunk/src/mainboard/via/epia-n/mainboard.c ============================================================================== --- trunk/src/mainboard/via/epia-n/mainboard.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/mainboard/via/epia-n/mainboard.c Thu Apr 15 14:39:29 2010 (r5442) @@ -23,8 +23,8 @@ #include <device/pci.h> #include <device/pci_ids.h> #include <boot/tables.h> +#include <southbridge/via/vt8237r/vt8237r.h> #include "chip.h" -#include "../../../southbridge/via/vt8237r/vt8237r.h" int add_mainboard_resources(struct lb_memory *mem) { Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/northbridge/amd/amdk8/raminit_f.c Thu Apr 15 14:39:29 2010 (r5442) @@ -718,12 +718,14 @@ static int is_opteron(const struct mem_controller *ctrl) { - /* Test to see if I am an Opteron. - * FIXME Testing dual channel capability is correct for now - * but a better test is probably required. - * m2 and s1g1 support dual channel too. but only support unbuffered dimm + /* Test to see if I am an Opteron. M2 and S1G1 support dual + * channel, too, but only support unbuffered DIMMs so we need a + * better test for Opterons. + * However, all code uses is_opteron() to find out whether to + * use dual channel, so if we really check for opteron here, we + * need to fix up all code using this function, too. */ -#warning "FIXME implement a better test for opterons" + uint32_t nbcap; nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP); return !!(nbcap & NBCAP_128Bit); Modified: trunk/src/northbridge/intel/e7501/debug.c ============================================================================== --- trunk/src/northbridge/intel/e7501/debug.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/northbridge/intel/e7501/debug.c Thu Apr 15 14:39:29 2010 (r5442) @@ -13,7 +13,7 @@ print_debug_hex8((dev >> 8) & 7); } -static void print_pci_devices(void) +static inline void print_pci_devices(void) { device_t dev; for(dev = PCI_DEV(0, 0, 0); @@ -58,7 +58,7 @@ print_debug("\n"); } -static void dump_pci_devices(void) +static inline void dump_pci_devices(void) { device_t dev; for(dev = PCI_DEV(0, 0, 0); @@ -75,7 +75,7 @@ } } -static void dump_pci_devices_on_bus(unsigned busn) +static inline void dump_pci_devices_on_bus(unsigned busn) { device_t dev; for(dev = PCI_DEV(busn, 0, 0); @@ -92,7 +92,7 @@ } } -static void dump_spd_registers(const struct mem_controller *ctrl) +static inline void dump_spd_registers(const struct mem_controller *ctrl) { int i; print_debug("\n"); @@ -174,7 +174,7 @@ } } } -static void dump_smbus_registers(void) +static inline void dump_smbus_registers(void) { unsigned device; print_debug("\n"); @@ -215,7 +215,7 @@ } } -static void dump_io_resources(unsigned port) +static inline void dump_io_resources(unsigned port) { int i; @@ -249,7 +249,7 @@ } } -static void dump_mem(unsigned start, unsigned end) +static inline void dump_mem(unsigned start, unsigned end) { unsigned i; print_debug("dump_mem:"); Modified: trunk/src/northbridge/intel/e7501/raminit.c ============================================================================== --- trunk/src/northbridge/intel/e7501/raminit.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/northbridge/intel/e7501/raminit.c Thu Apr 15 14:39:29 2010 (r5442) @@ -24,9 +24,9 @@ #if CONFIG_DEBUG_RAM_SETUP #define RAM_DEBUG_MESSAGE(x) print_debug(x) -#define RAM_DEBUG_HEX32(x) print_debug_hex32(x) -#define RAM_DEBUG_HEX8(x) print_debug_hex8(x) -#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) +#define RAM_DEBUG_HEX32(x) print_debug_hex32(x) +#define RAM_DEBUG_HEX8(x) print_debug_hex8(x) +#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) #else #define RAM_DEBUG_MESSAGE(x) #define RAM_DEBUG_HEX32(x) @@ -35,23 +35,23 @@ #endif #define E7501_SDRAM_MODE (SDRAM_BURST_INTERLEAVED | SDRAM_BURST_4) -#define SPD_ERROR "Error reading SPD info\n" +#define SPD_ERROR "Error reading SPD info\n" // NOTE: This used to be 0x100000. -// That doesn't work on systems where A20M# is asserted, because -// attempts to access 0x1000NN end up accessing 0x0000NN. +// That doesn't work on systems where A20M# is asserted, because +// attempts to access 0x1000NN end up accessing 0x0000NN. #define RCOMP_MMIO 0x200000 struct dimm_size { - unsigned long side1; - unsigned long side2; + unsigned long side1; + unsigned long side2; }; /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/ -/* DEFINITIONS */ +/* DEFINITIONS */ /**********************************************************************************/ -static const uint32_t refresh_frequency[]= { +static const uint32_t refresh_frequency[] = { /* Relative frequency (array value) of each E7501 Refresh Mode Select * (RMS) value (array index) * 0 == least frequent refresh (longest interval between refreshes) @@ -64,7 +64,8 @@ * [6] reserved -> 0 * [7] 64 clocks -> 4 */ - 0, 2, 3, 1, 0, 0, 0, 4 }; + 0, 2, 3, 1, 0, 0, 0, 4 +}; static const uint32_t refresh_rate_map[] = { /* Map the JEDEC spd refresh rates (array index) to E7501 Refresh Mode @@ -73,7 +74,7 @@ * The E7501 supports only 15.6 us (1), 7.8 us (2), 64 us (3), and * 64 clock (481 ns) (7) refresh. * [0] == 15.625 us -> 15.6 us - * [1] == 3.9 us -> 481 ns + * [1] == 3.9 us -> 481 ns * [2] == 7.8 us -> 7.8 us * [3] == 31.3 us -> 15.6 us * [4] == 62.5 us -> 15.6 us @@ -81,22 +82,22 @@ */ 1, 7, 2, 1, 1, 3 }; -#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1) +#define MAX_SPD_REFRESH_RATE ((sizeof(refresh_rate_map) / sizeof(uint32_t)) - 1) // SPD parameters that must match for dual-channel operation static const uint8_t dual_channel_parameters[] = { - SPD_MEMORY_TYPE, - SPD_MODULE_VOLTAGE, - SPD_NUM_COLUMNS, - SPD_NUM_ROWS, - SPD_NUM_DIMM_BANKS, - SPD_PRIMARY_SDRAM_WIDTH, + SPD_MEMORY_TYPE, + SPD_MODULE_VOLTAGE, + SPD_NUM_COLUMNS, + SPD_NUM_ROWS, + SPD_NUM_DIMM_BANKS, + SPD_PRIMARY_SDRAM_WIDTH, SPD_NUM_BANKS_PER_SDRAM }; /* - * Table: constant_register_values + * Table: constant_register_values */ static const long constant_register_values[] = { /* SVID - Subsystem Vendor Identification Register @@ -107,9 +108,9 @@ * 0x2e - 0x2f * [15:00] Subsystem ID */ - // Not everyone wants to be Super Micro Computer, Inc. - // The mainboard should set this if desired. - // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16), + // Not everyone wants to be Super Micro Computer, Inc. + // The mainboard should set this if desired. + // 0x2c, 0, (0x15d9 << 0) | (0x3580 << 16), /* Undocumented * (DRAM Read Timing Control, if similar to 855PM?) @@ -128,7 +129,7 @@ * work at all. * Steven James 02/06/2003 */ - /* NOTE: values now configured in configure_e7501_cas_latency() based + /* NOTE: values now configured in configure_e7501_cas_latency() based * on SPD info and total number of DIMMs (per Intel) */ @@ -172,15 +173,15 @@ */ // Conservatively say each row has 64MB of ram, we will fix this up later // NOTE: These defaults allow us to prime all of the DIMMs on the board - // without jumping through 36-bit adddressing hoops, even if the - // total memory is > 4 GB. Changing these values may break do_ram_command()! + // without jumping through 36-bit adddressing hoops, even if the + // total memory is > 4 GB. Changing these values may break do_ram_command()! 0x60, 0x00000000, (0x01 << 0) | (0x02 << 8) | (0x03 << 16) | (0x04 << 24), 0x64, 0x00000000, (0x05 << 0) | (0x06 << 8) | (0x07 << 16) | (0x08 << 24), /* DRA - DRAM Row Attribute Register * 0x70 Row 0,1 * 0x71 Row 2,3 - * 0x72 Row 4,5 + * 0x72 Row 4,5 * 0x73 Row 6,7 * [7:7] Device width for Odd numbered rows * 0 == 8 bits wide x8 @@ -201,7 +202,7 @@ * 101 == 64KB (This page size appears broken) * Others == Reserved */ - // NOTE: overridden by configure_e7501_row_attributes(), later + // NOTE: overridden by configure_e7501_row_attributes(), later 0x70, 0x00000000, 0, /* DRT - DRAM Timing Register @@ -223,9 +224,9 @@ * Others == Reserved * [23:19] Reserved * [18:16] DRAM idle timer - * 000 == infinite - * 011 == 16 dram clocks - * 001 == 0 clocks + * 000 == infinite + * 011 == 16 dram clocks + * 001 == 0 clocks * [15:11] Reserved * [10:09] Active to Precharge (tRAS) * 00 == 7 clocks @@ -241,9 +242,9 @@ * [03:03] Write Ras# to Cas# Delay (tRCD) * 0 == 3 DRAM Clocks * 1 == 2 DRAM Clocks - * [02:01] Read RAS# to CAS# Delay (tRCD) - * 00 == reserved - * 01 == reserved + * [02:01] Read RAS# to CAS# Delay (tRCD) + * 00 == reserved + * 01 == reserved * 10 == 3 DRAM Clocks * 11 == 2 DRAM Clocks * [00:00] DRAM RAS# to Precharge (tRP) @@ -251,15 +252,15 @@ * 1 == 2 DRAM Clocks */ - // Some earlier settings: + // Some earlier settings: /* Most aggressive settings possible */ -// 0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|CAS_LATENCY|(1<<3)|(1<<1)|(1<<0), -// 0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0), -// 0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0), +// 0x78, 0xc0fff8c4, (1<<29)|(1<<28)|(1<<27)|(2<<24)|(2<<9)|CAS_LATENCY|(1<<3)|(1<<1)|(1<<0), +// 0x78, 0xc0f8f8c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0), +// 0x78, 0xc0f8f9c0, (1<<29)|(1<<28)|(1<<27)|(1<<24)|(1<<16)|(2<<9)|CAS_LATENCY|(1<<3)|(3<<1)|(1<<0), // The only things we need to set here are DRAM idle timer, Back-to-Back Read Turnaround, and // Back-to-Back Write-Read Turnaround. All others are configured based on SPD. - 0x78, 0xD7F8FFFF, (1<<29)|(1<<27)|(1<<16), + 0x78, 0xD7F8FFFF, (1 << 29) | (1 << 27) | (1 << 16), /* FIXME why was I attempting to set a reserved bit? */ /* 0x0100040f */ @@ -271,9 +272,9 @@ * 0 == Not Complete * 1 == Complete * [28:23] Reserved - * [22:22] Channels - * 0 == Single channel - * 1 == Dual Channel + * [22:22] Channels + * 0 == Single channel + * 1 == Dual Channel * [21:20] DRAM Data Integrity Mode * 00 == Disabled, no ECC * 01 == Reserved @@ -281,10 +282,10 @@ * 11 == Reserved * [19:18] DRB Granularity (Read-Only) * 00 == 32 MB quantities (single channel mode) - * 01 == 64 MB quantities (dual-channel mode) - * 10 == Reserved - * 11 == Reserved - * [17:17] (Intel Undocumented) should always be set to 1 (SJM: comment inconsistent with current setting, below) + * 01 == 64 MB quantities (dual-channel mode) + * 10 == Reserved + * 11 == Reserved + * [17:17] (Intel Undocumented) should always be set to 1 (SJM: comment inconsistent with current setting, below) * [16:16] Command Per Clock - Address/Control Assertion Rule (CPC) * 0 == 2n Rule * 1 == 1n rule @@ -301,42 +302,42 @@ * 001 == NOP Command * 010 == All Banks Precharge * 011 == Mode Register Set - * 100 == Extended Mode Register Set + * 100 == Extended Mode Register Set * 101 == Reserved * 110 == CBR Refresh * 111 == Normal Operation * [03:00] Reserved */ -// .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8), -// .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8), -// .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8), +// .long 0x7c, 0xffcefcff, (1<<22)|(2 << 20)|(1 << 16)| (0 << 8), +// .long 0x7c, 0xff8cfcff, (1<<22)|(2 << 20)|(1 << 17)|(1 << 16)| (0 << 8), +// .long 0x7c, 0xff80fcff, (1<<22)|(2 << 20)|(1 << 18)|(1 << 17)|(1 << 16)| (0 << 8), // Default to dual-channel mode, ECC, 1-clock address/cmd hold // NOTE: configure_e7501_dram_controller_mode() configures further - 0x7c, 0xff8ef8ff, (1<<22)|(2<<20)|(1<<16)|(0<<8), + 0x7c, 0xff8ef8ff, (1 << 22) | (2 << 20) | (1 << 16) | (0 << 8), /* Another Intel undocumented register * 0x88 - 0x8B - * [31:31] Purpose unknown - * [26:26] Master DLL Reset? - * 0 == Normal operation? - * 1 == Reset? - * [07:07] Periodic memory recalibration? - * 0 == Disabled? - * 1 == Enabled? - * [04:04] Receive FIFO RE-Sync? - * 0 == Normal operation? - * 1 == Reset? + * [31:31] Purpose unknown + * [26:26] Master DLL Reset? + * 0 == Normal operation? + * 1 == Reset? + * [07:07] Periodic memory recalibration? + * 0 == Disabled? + * 1 == Enabled? + * [04:04] Receive FIFO RE-Sync? + * 0 == Normal operation? + * 1 == Reset? */ - // NOTE: Some factory BIOSs don't do this. - // Doesn't seem to matter either way. + // NOTE: Some factory BIOSs don't do this. + // Doesn't seem to matter either way. 0x88, 0xffffff00, 0x80, /* CLOCK_DIS - CK/CK# Disable Register * 0x8C * [7:7] DDR Frequency - * 0 == 100 MHz (200 MHz data rate) - * 1 == 133 MHz (266 MHz data rate) + * 0 == 100 MHz (200 MHz data rate) + * 1 == 133 MHz (266 MHz data rate) * [6:4] Reserved * [3:3] CK3 * 0 == Enable @@ -352,7 +353,7 @@ * 1 == Disable */ // NOTE: Disable all clocks initially; turn ones we need back on - // in enable_e7501_clocks() + // in enable_e7501_clocks() 0x8C, 0xfffffff0, 0xf, /* TOLM - Top of Low Memory Register @@ -383,23 +384,23 @@ /* DVNP - Device Not Present Register * 0xE0 - 0xE1 * [15:05] Reserved - * [04:04] Device 4 Function 1 Present + * [04:04] Device 4 Function 1 Present * 0 == Present * 1 == Absent - * [03:03] Device 3 Function 1 Present + * [03:03] Device 3 Function 1 Present * 0 == Present * 1 == Absent - * [02:02] Device 2 Function 1 Present + * [02:02] Device 2 Function 1 Present * 0 == Present * 1 == Absent - * [01:01] Reserved - * [00:00] Device 0 Function 1 Present + * [01:01] Reserved + * [00:00] Device 0 Function 1 Present * 0 == Present * 1 == Absent */ // Enable D0:D1, disable D2:F1, D3:F1, D4:F1 - 0xe0, 0xffffffe2, (1<<4)|(1<<3)|(1<<2)|(0<<0), + 0xe0, 0xffffffe2, (1 << 4) | (1 << 3) | (1 << 2) | (0 << 0), // Undocumented 0xd8, 0xffff9fff, 0x00000000, @@ -410,22 +411,22 @@ * [31:31] Purpose unknown * [30:30] Purpose unknown * [29:23] Unknown - not used? - * [22:22] System Memory MMR Enable + * [22:22] System Memory MMR Enable * 0 == Disable: mem space and BAR at 0x14 are not accessible * 1 == Enable: mem space and BAR at 0x14 are accessible * [21:20] Purpose unknown - * [19:02] Unknown - not used? - * [01:01] D6EN (Device #6 enable) + * [19:02] Unknown - not used? + * [01:01] D6EN (Device #6 enable) * 0 == Disable * 1 == Enable - * [00:00] Unknown - not used? + * [00:00] Unknown - not used? */ 0xf4, 0x3f8ffffd, 0x40300002, #ifdef SUSPICIOUS_LOOKING_CODE // SJM: Undocumented. - // This will access D2:F0:0x50, is this correct?? + // This will access D2:F0:0x50, is this correct?? 0x1050, 0xffffffcf, 0x00000030, #endif }; @@ -453,29 +454,31 @@ /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/ /* TABLES */ /**********************************************************************************/ -#define SLOW_DOWN_IO inb(0x80); +#define SLOW_DOWN_IO inb(0x80) //#define SLOW_DOWN_IO udelay(40); - /* Estimate that SLOW_DOWN_IO takes about 50&76us*/ + /* Estimate that SLOW_DOWN_IO takes about 50&76us */ /* delay for 200us */ #if 1 static void do_delay(void) { int i; - for(i = 0; i < 16; i++) { SLOW_DOWN_IO } + for (i = 0; i < 16; i++) { + SLOW_DOWN_IO; + } } -#define DO_DELAY do_delay(); + +#define DO_DELAY do_delay() #else #define DO_DELAY \ - udelay(200); -#endif + udelay(200) +#endif #define EXTRA_DELAY DO_DELAY - /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/ -/* DELAY FUNCTIONS */ +/* DELAY FUNCTIONS */ /**********************************************************************************/ static void die_on_spd_error(int spd_return_value) @@ -485,90 +488,100 @@ } //---------------------------------------------------------------------------------- -// Function: sdram_spd_get_page_size -// Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate -// Return Value: struct dimm_size - log2(page size) for each side of the DIMM. -// Description: Calculate the page size for each physical bank of the DIMM: -// log2(page size) = (# columns) + log2(data width) +// Function: sdram_spd_get_page_size +// Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate +// Return Value: struct dimm_size - log2(page size) for each side of the DIMM. +// Description: Calculate the page size for each physical bank of the DIMM: +// log2(page size) = (# columns) + log2(data width) // -// NOTE: page size is the total number of data bits in a row. +// NOTE: page size is the total number of data bits in a row. // -static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address) +static struct dimm_size sdram_spd_get_page_size(uint16_t + dimm_socket_address) { uint16_t module_data_width; int value; struct dimm_size pgsz; pgsz.side1 = 0; - pgsz.side2 = 0; - + pgsz.side2 = 0; + // Side 1 - value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); - if (value < 0) goto hw_err; - pgsz.side1 = value & 0xf; // # columns in bank 1 - + value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); + if (value < 0) + goto hw_err; + pgsz.side1 = value & 0xf; // # columns in bank 1 + /* Get the module data width and convert it to a power of two */ - value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB); - if (value < 0) goto hw_err; + value = + spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_MSB); + if (value < 0) + goto hw_err; module_data_width = (value & 0xff) << 8; - value = spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB); - if (value < 0) goto hw_err; + value = + spd_read_byte(dimm_socket_address, SPD_MODULE_DATA_WIDTH_LSB); + if (value < 0) + goto hw_err; module_data_width |= (value & 0xff); pgsz.side1 += log2(module_data_width); /* side two */ value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); - if (value < 0) goto hw_err; - if (value > 2) + if (value < 0) + goto hw_err; + if (value > 2) die("Bad SPD value\n"); if (value == 2) { - pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently - value = spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); - if (value < 0) goto hw_err; + pgsz.side2 = pgsz.side1; // Assume symmetric banks until we know differently + value = + spd_read_byte(dimm_socket_address, SPD_NUM_COLUMNS); + if (value < 0) + goto hw_err; if ((value & 0xf0) != 0) { // Asymmetric banks - pgsz.side2 -= value & 0xf; /* Subtract out columns on side 1 */ - pgsz.side2 += (value>>4) & 0xf; /* Add in columns on side 2 */ + pgsz.side2 -= value & 0xf; /* Subtract out columns on side 1 */ + pgsz.side2 += (value >> 4) & 0xf; /* Add in columns on side 2 */ } } - return pgsz; + return pgsz; -hw_err: + hw_err: die(SPD_ERROR); - return pgsz; // Never reached + return pgsz; // Never reached } - //---------------------------------------------------------------------------------- -// Function: sdram_spd_get_width -// Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate -// Return Value: dimm_size - width in bits of each DIMM side's DRAMs. -// Description: Read the width in bits of each DIMM side's DRAMs via SPD. -// (i.e. 4, 8, 16) +// Function: sdram_spd_get_width +// Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate +// Return Value: dimm_size - width in bits of each DIMM side's DRAMs. +// Description: Read the width in bits of each DIMM side's DRAMs via SPD. +// (i.e. 4, 8, 16) // -static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address) +static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address) { int value; struct dimm_size width; - + width.side1 = 0; width.side2 = 0; - value = spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH); + value = + spd_read_byte(dimm_socket_address, SPD_PRIMARY_SDRAM_WIDTH); die_on_spd_error(value); - - width.side1 = value & 0x7f; // Mask off bank 2 flag + + width.side1 = value & 0x7f; // Mask off bank 2 flag if (value & 0x80) { width.side2 = width.side1 << 1; // Bank 2 exists and is double-width } else { // If bank 2 exists, it's the same width as bank 1 - value = spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); - die_on_spd_error(value); + value = + spd_read_byte(dimm_socket_address, SPD_NUM_DIMM_BANKS); + die_on_spd_error(value); #ifdef ROMCC_IF_BUG_FIXED if (value == 2) @@ -587,94 +600,100 @@ return width; } - + //---------------------------------------------------------------------------------- -// Function: spd_get_dimm_size -// Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate -// Return Value: dimm_size - log2(number of bits) for each side of the DIMM -// Description: Calculate the log base 2 size in bits of both DIMM sides. -// log2(# bits) = (# columns) + log2(data width) + -// (# rows) + log2(banks per SDRAM) -// -// Note that it might be easier to use SPD byte 31 here, it has the -// DIMM size as a multiple of 4MB. The way we do it now we can size -// both sides of an asymmetric dimm. +// Function: spd_get_dimm_size +// Parameters: dimm_socket_address - SMBus address of DIMM socket to interrogate +// Return Value: dimm_size - log2(number of bits) for each side of the DIMM +// Description: Calculate the log base 2 size in bits of both DIMM sides. +// log2(# bits) = (# columns) + log2(data width) + +// (# rows) + log2(banks per SDRAM) +// +// Note that it might be easier to use SPD byte 31 here, it has the +// DIMM size as a multiple of 4MB. The way we do it now we can size +// both sides of an asymmetric dimm. // static struct dimm_size spd_get_dimm_size(unsigned dimm_socket_address) { - int value; + int value; // Start with log2(page size) - struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address); + struct dimm_size sz = sdram_spd_get_page_size(dimm_socket_address); if (sz.side1 > 0) { value = spd_read_byte(dimm_socket_address, SPD_NUM_ROWS); die_on_spd_error(value); - sz.side1 += value & 0xf; + sz.side1 += value & 0xf; if (sz.side2 > 0) { // Double-sided DIMM if (value & 0xF0) - sz.side2 += value >> 4; // Asymmetric + sz.side2 += value >> 4; // Asymmetric else - sz.side2 += value; // Symmetric + sz.side2 += value; // Symmetric } - value = spd_read_byte(dimm_socket_address, SPD_NUM_BANKS_PER_SDRAM); - die_on_spd_error(value); + value = + spd_read_byte(dimm_socket_address, + SPD_NUM_BANKS_PER_SDRAM); + die_on_spd_error(value); value = log2(value); - sz.side1 += value; + sz.side1 += value; if (sz.side2 > 0) - sz.side2 += value; + sz.side2 += value; } return sz; } +#ifdef VALIDATE_DIMM_COMPATIBILITY //---------------------------------------------------------------------------------- -// Function: are_spd_values_equal -// Parameters: spd_byte_number - -// dimmN_address - SMBus addresses of DIMM sockets to interrogate -// Return Value: 1 if both DIMM sockets report the same value for the specified -// SPD parameter; 0 if the values differed or an error occurred. -// Description: Determine whether two DIMMs have the same value for a SPD parameter. -// -static uint8_t are_spd_values_equal(uint8_t spd_byte_number, uint16_t dimm0_address, - uint16_t dimm1_address) +// Function: are_spd_values_equal +// Parameters: spd_byte_number - +// dimmN_address - SMBus addresses of DIMM sockets to interrogate +// Return Value: 1 if both DIMM sockets report the same value for the specified +// SPD parameter; 0 if the values differed or an error occurred. +// Description: Determine whether two DIMMs have the same value for a SPD parameter. +// +static uint8_t are_spd_values_equal(uint8_t spd_byte_number, + uint16_t dimm0_address, + uint16_t dimm1_address) { uint8_t bEqual = 0; int dimm0_value = spd_read_byte(dimm0_address, spd_byte_number); int dimm1_value = spd_read_byte(dimm1_address, spd_byte_number); - if ((dimm0_value >= 0) && (dimm1_value >= 0) && (dimm0_value == dimm1_value)) + if ((dimm0_value >= 0) && (dimm1_value >= 0) + && (dimm0_value == dimm1_value)) bEqual = 1; return bEqual; } +#endif //---------------------------------------------------------------------------------- -// Function: spd_get_supported_dimms -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// Return Value: uint8_t - a bitmask indicating which of the possible sockets -// for each channel was found to contain a compatible DIMM. -// Bit 0 corresponds to the closest socket for channel 0, -// Bit 1 to the next socket for channel 0, -// ... -// Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0, -// Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1, -// ... -// Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1 -// Description: Scan for compatible DIMMs. -// The code in this module only supports dual-channel operation, -// so we test that compatible DIMMs are paired. +// Function: spd_get_supported_dimms +// Parameters: ctrl - PCI addresses of memory controller functions, and +// SMBus addresses of DIMM slots on the mainboard +// Return Value: uint8_t - a bitmask indicating which of the possible sockets +// for each channel was found to contain a compatible DIMM. +// Bit 0 corresponds to the closest socket for channel 0, +// Bit 1 to the next socket for channel 0, +// ... +// Bit MAX_DIMM_SOCKETS_PER_CHANNEL-1 to the last socket for channel 0, +// Bit MAX_DIMM_SOCKETS_PER_CHANNEL is the closest socket for channel 1, +// ... +// Bit 2*MAX_DIMM_SOCKETS_PER_CHANNEL-1 is the last socket for channel 1 +// Description: Scan for compatible DIMMs. +// The code in this module only supports dual-channel operation, +// so we test that compatible DIMMs are paired. // -static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) +static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) { int i; uint8_t dimm_mask = 0; @@ -686,54 +705,60 @@ // Then see if the corresponding channel 1 DIMM has the same parameters, // since we only support dual-channel. - for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { + for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { - uint16_t channel0_dimm = ctrl->channel0[i]; + uint16_t channel0_dimm = ctrl->channel0[i]; uint16_t channel1_dimm = ctrl->channel1[i]; uint8_t bDualChannel = 1; - struct dimm_size page_size; - struct dimm_size sdram_width; +#ifdef VALIDATE_DIMM_COMPATIBILITY + struct dimm_size page_size; + struct dimm_size sdram_width; +#endif int spd_value; - int j; if (channel0_dimm == 0) - continue; // No such socket on this mainboard + continue; // No such socket on this mainboard - if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR) + if (spd_read_byte(channel0_dimm, SPD_MEMORY_TYPE) != + SPD_MEMORY_TYPE_SDRAM_DDR) continue; #ifdef VALIDATE_DIMM_COMPATIBILITY - if (spd_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) != SPD_VOLTAGE_SSTL2) - continue; // Unsupported voltage + if (spd_read_byte(channel0_dimm, SPD_MODULE_VOLTAGE) != + SPD_VOLTAGE_SSTL2) + continue; // Unsupported voltage // E7501 does not support unregistered DIMMs - spd_value = spd_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES); + spd_value = + spd_read_byte(channel0_dimm, SPD_MODULE_ATTRIBUTES); if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) continue; - - // Must support burst = 4 for dual-channel operation on E7501 + + // Must support burst = 4 for dual-channel operation on E7501 // NOTE: for single-channel, burst = 8 is required - spd_value = spd_read_byte(channel0_dimm, SPD_SUPPORTED_BURST_LENGTHS); + spd_value = + spd_read_byte(channel0_dimm, + SPD_SUPPORTED_BURST_LENGTHS); if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0)) continue; - page_size = sdram_spd_get_page_size(channel0_dimm); + page_size = sdram_spd_get_page_size(channel0_dimm); sdram_width = sdram_spd_get_width(channel0_dimm); // Validate DIMM page size // The E7501 only supports page sizes of 4, 8, 16, or 32 KB per channel // NOTE: 4 KB = 32 Kb = 2^15 - // 32 KB = 262 Kb = 2^18 + // 32 KB = 262 Kb = 2^18 if ((page_size.side1 < 15) || (page_size.side1 > 18)) continue; // If DIMM is double-sided, verify side2 page size - if (page_size.side2 != 0) { - if ((page_size.side2 < 15) || (page_size.side2 > 18)) + if (page_size.side2 != 0) { + if ((page_size.side2 < 15) + || (page_size.side2 > 18)) continue; } - // Validate SDRAM width // The E7501 only supports x4 and x8 devices @@ -741,31 +766,37 @@ continue; // If DIMM is double-sided, verify side2 width - if (sdram_width.side2 != 0) { - if ((sdram_width.side2 != 4) && (sdram_width.side2 != 8)) + if (sdram_width.side2 != 0) { + if ((sdram_width.side2 != 4) + && (sdram_width.side2 != 8)) continue; } -#endif +#endif // Channel 0 DIMM looks compatible. // Now see if it is paired with the proper DIMM on channel 1. - ASSERT(channel1_dimm != 0); // No such socket on this mainboard?? + ASSERT(channel1_dimm != 0); // No such socket on this mainboard?? // NOTE: unpopulated DIMMs cause read to fail - spd_value = spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES); + spd_value = + spd_read_byte(channel1_dimm, SPD_MODULE_ATTRIBUTES); if (!(spd_value & MODULE_REGISTERED) || (spd_value < 0)) { - + print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n"); continue; } - #ifdef VALIDATE_DIMM_COMPATIBILITY - spd_value = spd_read_byte(channel1_dimm, SPD_SUPPORTED_BURST_LENGTHS); + spd_value = + spd_read_byte(channel1_dimm, + SPD_SUPPORTED_BURST_LENGTHS); if (!(spd_value & SPD_BURST_LENGTH_4) || (spd_value < 0)) continue; - for (j=0; j<sizeof(dual_channel_parameters); ++j) { - if (!are_spd_values_equal(dual_channel_parameters[j], channel0_dimm, channel1_dimm)) { + int j; + for (j = 0; j < sizeof(dual_channel_parameters); ++j) { + if (!are_spd_values_equal + (dual_channel_parameters[j], channel0_dimm, + channel1_dimm)) { bDualChannel = 0; break; @@ -777,22 +808,21 @@ #ifdef ROMCC_IF_BUG_FIXED if (bDualChannel) { // Made it through all the checks, this DIMM pair is usable - dimm_mask |= ((1<<i) | (1<<(MAX_DIMM_SOCKETS_PER_CHANNEL + i))); - } - else + dimm_mask |= ((1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i))); + } else print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n"); #else switch (bDualChannel) { case 0: print_debug("Skipping un-matched DIMMs - only dual-channel operation supported\n"); break; - + default: // Made it through all the checks, this DIMM pair is usable - dimm_mask |= (1<<i) | (1<<(MAX_DIMM_SOCKETS_PER_CHANNEL + i)); + dimm_mask |= (1 << i) | (1 << (MAX_DIMM_SOCKETS_PER_CHANNEL + i)); break; } -#endif +#endif } return dimm_mask; @@ -803,32 +833,32 @@ /**********************************************************************************/ //---------------------------------------------------------------------------------- -// Function: do_ram_command -// Parameters: -// command - specifies the command to be sent to the DIMMs: -// RAM_COMMAND_NOP - No Operation -// RAM_COMMAND_PRECHARGE - Precharge all banks -// RAM_COMMAND_MRS - Load Mode Register -// RAM_COMMAND_EMRS - Load Extended Mode Register -// RAM_COMMAND_CBR - Auto Refresh ("CAS-before-RAS") -// RAM_COMMAND_NORMAL - Normal operation -// jedec_mode_bits - for mode register set & extended mode register set -// commands, bits 0-12 contain the register value in JEDEC format. -// Return Value: None -// Description: Send the specified command to all DIMMs. +// Function: do_ram_command +// Parameters: +// command - specifies the command to be sent to the DIMMs: +// RAM_COMMAND_NOP - No Operation +// RAM_COMMAND_PRECHARGE - Precharge all banks +// RAM_COMMAND_MRS - Load Mode Register +// RAM_COMMAND_EMRS - Load Extended Mode Register +// RAM_COMMAND_CBR - Auto Refresh ("CAS-before-RAS") +// RAM_COMMAND_NORMAL - Normal operation +// jedec_mode_bits - for mode register set & extended mode register set +// commands, bits 0-12 contain the register value in JEDEC format. +// Return Value: None +// Description: Send the specified command to all DIMMs. // -static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) +static void do_ram_command(uint8_t command, uint16_t jedec_mode_bits) { - int i; + int i; uint32_t dram_controller_mode; uint8_t dimm_start_64M_multiple = 0; uint16_t e7501_mode_bits = jedec_mode_bits; // Configure the RAM command - dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); - dram_controller_mode &= 0xFFFFFF8F; - dram_controller_mode |= command; - pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); + dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); + dram_controller_mode &= 0xFFFFFF8F; + dram_controller_mode |= command; + pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); // RAM_COMMAND_NORMAL is an exception. // It affects only the memory controller and does not need to be "sent" to the DIMMs. @@ -837,7 +867,7 @@ // Send the command to all DIMMs by accessing a memory location within each // NOTE: for mode select commands, some of the location address bits - // are part of the command + // are part of the command // Map JEDEC mode bits to E7501 if (command == RAM_COMMAND_MRS) { @@ -846,8 +876,8 @@ ASSERT(!(jedec_mode_bits & 0x0401)); - e7501_mode_bits = ((jedec_mode_bits & 0x1800) << (15-12)) | // JEDEC bits 11-12 move to bits 14-15 - ((jedec_mode_bits & 0x03FE) << (13-9)); // JEDEC bits 1-9 move to bits 5-13 + e7501_mode_bits = ((jedec_mode_bits & 0x1800) << (15 - 12)) | // JEDEC bits 11-12 move to bits 14-15 + ((jedec_mode_bits & 0x03FE) << (13 - 9)); // JEDEC bits 1-9 move to bits 5-13 } else if (command == RAM_COMMAND_EMRS) { // Host address lines [15:3] map to DIMM address lines [12:0] @@ -855,12 +885,12 @@ } else ASSERT(jedec_mode_bits == 0); - dimm_start_64M_multiple = 0; for (i = 0; i < (MAX_NUM_CHANNELS * MAX_DIMM_SOCKETS_PER_CHANNEL); ++i) { - uint8_t dimm_end_64M_multiple = pci_read_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + i); + uint8_t dimm_end_64M_multiple = + pci_read_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + i); if (dimm_end_64M_multiple > dimm_start_64M_multiple) { // This code assumes DRAM row boundaries are all set below 4 GB @@ -869,34 +899,38 @@ // NOTE: 2^26 == 64 MB - uint32_t dimm_start_address = dimm_start_64M_multiple << 26; + uint32_t dimm_start_address = + dimm_start_64M_multiple << 26; RAM_DEBUG_MESSAGE(" Sending RAM command to 0x"); RAM_DEBUG_HEX32(dimm_start_address + e7501_mode_bits); RAM_DEBUG_MESSAGE("\n"); + read32(dimm_start_address + e7501_mode_bits); // Set the start of the next DIMM - dimm_start_64M_multiple = dimm_end_64M_multiple; + dimm_start_64M_multiple = + dimm_end_64M_multiple; } } } } //---------------------------------------------------------------------------------- -// Function: set_ram_mode -// Parameters: jedec_mode_bits - for mode register set & extended mode register set -// commands, bits 0-12 contain the register value in JEDEC format. -// Return Value: None -// Description: Set the mode register of all DIMMs. The proper CAS# latency -// setting is added to the mode bits specified by the caller. +// Function: set_ram_mode +// Parameters: jedec_mode_bits - for mode register set & extended mode register set +// commands, bits 0-12 contain the register value in JEDEC format. +// Return Value: None +// Description: Set the mode register of all DIMMs. The proper CAS# latency +// setting is added to the mode bits specified by the caller. // static void set_ram_mode(uint16_t jedec_mode_bits) { ASSERT(!(jedec_mode_bits & SDRAM_CAS_MASK)); - uint32_t dram_cas_latency = pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK; - + uint32_t dram_cas_latency = + pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK; + switch (dram_cas_latency) { case DRT_CAS_2_5: jedec_mode_bits |= SDRAM_CAS_2_5; @@ -915,25 +949,22 @@ } /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/ -/* SDRAM CONFIGURATION FUNCTIONS */ +/* SDRAM CONFIGURATION FUNCTIONS */ /**********************************************************************************/ //---------------------------------------------------------------------------------- -// Function: configure_dimm_row_boundaries -// Parameters: -// dimm_log2_num_bits - log2(number of bits) for each side of the DIMM -// total_dram_64M_multiple - total DRAM in the system (as a -// multiple of 64 MB) for DIMMs < dimm_index -// dimm_index - which DIMM pair is being processed -// (0..MAX_DIMM_SOCKETS_PER_CHANNEL) -// Return Value: New multiple of 64 MB total DRAM in the system -// Description: Configure the E7501's DRAM Row Boundary registers for the memory -// present in the specified DIMM. -// -static uint8_t configure_dimm_row_boundaries( - struct dimm_size dimm_log2_num_bits, - uint8_t total_dram_64M_multiple, - unsigned dimm_index) +// Function: configure_dimm_row_boundaries +// Parameters: +// dimm_log2_num_bits - log2(number of bits) for each side of the DIMM +// total_dram_64M_multiple - total DRAM in the system (as a +// multiple of 64 MB) for DIMMs < dimm_index +// dimm_index - which DIMM pair is being processed +// (0..MAX_DIMM_SOCKETS_PER_CHANNEL) +// Return Value: New multiple of 64 MB total DRAM in the system +// Description: Configure the E7501's DRAM Row Boundary registers for the memory +// present in the specified DIMM. +// +static uint8_t configure_dimm_row_boundaries(struct dimm_size dimm_log2_num_bits, uint8_t total_dram_64M_multiple, unsigned dimm_index) { int i; @@ -941,7 +972,8 @@ // DIMM sides must be at least 32 MB ASSERT(dimm_log2_num_bits.side1 >= 28); - ASSERT((dimm_log2_num_bits.side2 == 0) || (dimm_log2_num_bits.side2 >= 28)); + ASSERT((dimm_log2_num_bits.side2 == 0) + || (dimm_log2_num_bits.side2 >= 28)); // In dual-channel mode, we are called only once for each pair of DIMMs. // Each time we process twice the capacity of a single DIMM. @@ -951,7 +983,7 @@ dimm_log2_num_bits.side1++; if (dimm_log2_num_bits.side2 > 0) dimm_log2_num_bits.side2++; - + // Add the capacity of side 1 this DIMM pair (as a multiple of 64 MB) // to the total capacity of the system // NOTE: 64 MB == 512 Mb, and log2(512 Mb) == 29 @@ -959,76 +991,82 @@ total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side1 - 29)); // Configure the boundary address for the row on side 1 - pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0+(dimm_index<<1), total_dram_64M_multiple); + pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (dimm_index << 1), + total_dram_64M_multiple); // If the DIMMs are double-sided, add the capacity of side 2 this DIMM pair // (as a multiple of 64 MB) to the total capacity of the system - if (dimm_log2_num_bits.side2 >= 29) - total_dram_64M_multiple += (1 << (dimm_log2_num_bits.side2 - 29)); - + if (dimm_log2_num_bits.side2 >= 29) + total_dram_64M_multiple += + (1 << (dimm_log2_num_bits.side2 - 29)); + // Configure the boundary address for the row (if any) on side 2 - pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1+(dimm_index<<1), total_dram_64M_multiple); + pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1 + (dimm_index << 1), + total_dram_64M_multiple); // Update boundaries for rows subsequent to these. // These settings will be overridden by a subsequent call if a populated physical slot exists - - for(i=dimm_index+1; i<MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { - pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0+(i<<1), total_dram_64M_multiple); - pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1+(i<<1), total_dram_64M_multiple); + + for (i = dimm_index + 1; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { + pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_0 + (i << 1), + total_dram_64M_multiple); + pci_write_config8(PCI_DEV(0, 0, 0), DRB_ROW_1 + (i << 1), + total_dram_64M_multiple); } - - return total_dram_64M_multiple; + + return total_dram_64M_multiple; } //---------------------------------------------------------------------------------- -// Function: configure_e7501_ram_addresses -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see -// spd_get_supported_dimms() -// Return Value: None -// Description: Program the E7501's DRAM row boundary addresses and its Top Of -// Low Memory (TOLM). If necessary, set up a remap window so we -// don't waste DRAM that ordinarily would lie behind addresses -// reserved for memory-mapped I/O. +// Function: configure_e7501_ram_addresses +// Parameters: ctrl - PCI addresses of memory controller functions, and +// SMBus addresses of DIMM slots on the mainboard +// dimm_mask - bitmask of populated DIMMs on the board - see +// spd_get_supported_dimms() +// Return Value: None +// Description: Program the E7501's DRAM row boundary addresses and its Top Of +// Low Memory (TOLM). If necessary, set up a remap window so we +// don't waste DRAM that ordinarily would lie behind addresses +// reserved for memory-mapped I/O. // -static void configure_e7501_ram_addresses(const struct mem_controller *ctrl, - uint8_t dimm_mask) +static void configure_e7501_ram_addresses(const struct mem_controller + *ctrl, uint8_t dimm_mask) { int i; - uint8_t total_dram_64M_multiple = 0; + uint8_t total_dram_64M_multiple = 0; // Configure the E7501's DRAM row boundaries // Start by zeroing out the temporary initial configuration pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_0, 0); pci_write_config32(PCI_DEV(0, 0, 0), DRB_ROW_4, 0); - for(i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { + for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { - uint16_t dimm_socket_address = ctrl->channel0[i]; + uint16_t dimm_socket_address = ctrl->channel0[i]; struct dimm_size sz; - if (!(dimm_mask & (1 << i))) - continue; // This DIMM not present + if (!(dimm_mask & (1 << i))) + continue; // This DIMM not present - sz = spd_get_dimm_size(dimm_socket_address); + sz = spd_get_dimm_size(dimm_socket_address); - RAM_DEBUG_MESSAGE("dimm size ="); - RAM_DEBUG_HEX32(sz.side1); - RAM_DEBUG_MESSAGE(" "); - RAM_DEBUG_HEX32(sz.side2); - RAM_DEBUG_MESSAGE("\n"); + RAM_DEBUG_MESSAGE("dimm size ="); + RAM_DEBUG_HEX32(sz.side1); + RAM_DEBUG_MESSAGE(" "); + RAM_DEBUG_HEX32(sz.side2); + RAM_DEBUG_MESSAGE("\n"); if (sz.side1 == 0) die("Bad SPD value\n"); - total_dram_64M_multiple = configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i); + total_dram_64M_multiple = + configure_dimm_row_boundaries(sz, total_dram_64M_multiple, i); } // Configure the Top Of Low Memory (TOLM) in the E7501 // This address must be a multiple of 128 MB that is less than 4 GB. // NOTE: 16-bit wide TOLM register stores only the highest 5 bits of a 32-bit address - // in the highest 5 bits. + // in the highest 5 bits. // We set TOLM to the smaller of 0xC0000000 (3 GB) or the total DRAM in the system. // This reserves addresses from 0xC0000000 - 0xFFFFFFFF for non-DRAM purposes @@ -1040,30 +1078,33 @@ // NOTE: 0xC0000000 / (64 MB) == 0x30 - if (total_dram_64M_multiple <= 0x30) { + if (total_dram_64M_multiple <= 0x30) { // <= 3 GB total RAM /* I should really adjust all of this in C after I have resources - * to all of the pci devices. - */ + * to all of the pci devices. + */ // Round up to 128MB granularity // SJM: Is "missing" 64 MB of memory a potential issue? Should this round down? - uint8_t total_dram_128M_multiple = (total_dram_64M_multiple + 1) >> 1; + uint8_t total_dram_128M_multiple = + (total_dram_64M_multiple + 1) >> 1; // Convert to high 16 bits of address - uint16_t top_of_low_memory = total_dram_128M_multiple << 11; + uint16_t top_of_low_memory = + total_dram_128M_multiple << 11; - pci_write_config16(PCI_DEV(0, 0, 0), TOLM, top_of_low_memory); + pci_write_config16(PCI_DEV(0, 0, 0), TOLM, + top_of_low_memory); } else { // > 3 GB total RAM // Set defaults for > 4 GB DRAM, i.e. remap a 1 GB (= 0x10 * 64 MB) range of memory - uint16_t remap_base = total_dram_64M_multiple; // A[25:0] == 0 + uint16_t remap_base = total_dram_64M_multiple; // A[25:0] == 0 uint16_t remap_limit = total_dram_64M_multiple + 0x10 - 1; // A[25:0] == 0xF // Put TOLM at 3 GB @@ -1073,25 +1114,28 @@ // Define a remap window to make the RAM that would appear from 3 GB - 4 GB // visible just beyond 4 GB or the end of physical memory, whichever is larger // NOTE: 16-bit wide REMAP registers store only the highest 10 bits of a 36-bit address, - // (i.e. a multiple of 64 MB) in the lowest 10 bits. + // (i.e. a multiple of 64 MB) in the lowest 10 bits. // NOTE: 0x100000000 / (64 MB) == 0x40 - if (total_dram_64M_multiple < 0x40) { - remap_base = 0x40; // 0x100000000 - remap_limit = 0x40 + (total_dram_64M_multiple - 0x30) - 1; + if (total_dram_64M_multiple < 0x40) { + remap_base = 0x40; // 0x100000000 + remap_limit = + 0x40 + (total_dram_64M_multiple - 0x30) - 1; } - pci_write_config16(PCI_DEV(0, 0, 0), REMAPBASE, remap_base); - pci_write_config16(PCI_DEV(0, 0, 0), REMAPLIMIT, remap_limit); + pci_write_config16(PCI_DEV(0, 0, 0), REMAPBASE, + remap_base); + pci_write_config16(PCI_DEV(0, 0, 0), REMAPLIMIT, + remap_limit); } } //---------------------------------------------------------------------------------- -// Function: initialize_ecc -// Parameters: None -// Return Value: None -// Description: If we're configured to use ECC, initialize the SDRAM and -// clear the E7501's ECC error flags. +// Function: initialize_ecc +// Parameters: None +// Return Value: None +// Description: If we're configured to use ECC, initialize the SDRAM and +// clear the E7501's ECC error flags. // static void initialize_ecc(void) { @@ -1101,145 +1145,156 @@ dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); dram_controller_mode >>= 20; dram_controller_mode &= 3; - if (dram_controller_mode == 2) { - + if (dram_controller_mode == 2) { + uint8_t byte; RAM_DEBUG_MESSAGE("Initializing ECC state...\n"); - /* Initialize ECC bits , use ECC zero mode (new to 7501)*/ + /* Initialize ECC bits , use ECC zero mode (new to 7501) */ pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x06); pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 0x07); // Wait for scrub cycle to complete do { - byte = pci_read_config8(PCI_DEV(0, 0, 0), MCHCFGNS); - - } while ( (byte & 0x08 ) == 0); + byte = + pci_read_config8(PCI_DEV(0, 0, 0), MCHCFGNS); + } while ((byte & 0x08) == 0); pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, byte & 0xfc); - RAM_DEBUG_MESSAGE("ECC state initialized.\n"); + RAM_DEBUG_MESSAGE("ECC state initialized.\n"); /* Clear the ECC error bits */ pci_write_config8(PCI_DEV(0, 0, 1), DRAM_FERR, 0x03); pci_write_config8(PCI_DEV(0, 0, 1), DRAM_NERR, 0x03); // Clear DRAM Interface error bits (write-one-clear) - pci_write_config32(PCI_DEV(0, 0, 1), FERR_GLOBAL, 1<<18); - pci_write_config32(PCI_DEV(0, 0, 1), NERR_GLOBAL, 1<<18); + pci_write_config32(PCI_DEV(0, 0, 1), FERR_GLOBAL, 1 << 18); + pci_write_config32(PCI_DEV(0, 0, 1), NERR_GLOBAL, 1 << 18); // Start normal ECC scrub pci_write_config8(PCI_DEV(0, 0, 0), MCHCFGNS, 5); } - + } //---------------------------------------------------------------------------------- -// Function: configure_e7501_dram_timing -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see -// spd_get_supported_dimms() -// Return Value: None -// Description: Program the DRAM Timing register of the E7501 (except for CAS# -// latency, which is assumed to have been programmed already), based -// on the parameters of the various installed DIMMs. +// Function: configure_e7501_dram_timing +// Parameters: ctrl - PCI addresses of memory controller functions, and +// SMBus addresses of DIMM slots on the mainboard +// dimm_mask - bitmask of populated DIMMs on the board - see +// spd_get_supported_dimms() +// Return Value: None +// Description: Program the DRAM Timing register of the E7501 (except for CAS# +// latency, which is assumed to have been programmed already), based +// on the parameters of the various installed DIMMs. // -static void configure_e7501_dram_timing(const struct mem_controller *ctrl, uint8_t dimm_mask) +static void configure_e7501_dram_timing(const struct mem_controller *ctrl, + uint8_t dimm_mask) { int i; - uint32_t dram_timing; - int value; + uint32_t dram_timing; + int value; uint8_t slowest_row_precharge = 0; uint8_t slowest_ras_cas_delay = 0; uint8_t slowest_active_to_precharge_delay = 0; - uint32_t current_cas_latency = pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK; + uint32_t current_cas_latency = + pci_read_config32(PCI_DEV(0, 0, 0), DRT) & DRT_CAS_MASK; // CAS# latency must be programmed beforehand - ASSERT((current_cas_latency == DRT_CAS_2_0) || (current_cas_latency == DRT_CAS_2_5)); + ASSERT((current_cas_latency == DRT_CAS_2_0) + || (current_cas_latency == DRT_CAS_2_5)); // Each timing parameter is determined by the slowest DIMM for (i = 0; i < MAX_DIMM_SOCKETS; i++) { + uint16_t dimm_socket_address; - uint16_t dimm_socket_address; - if (!(dimm_mask & (1 << i))) - continue; // This DIMM not present + continue; // This DIMM not present if (i < MAX_DIMM_SOCKETS_PER_CHANNEL) dimm_socket_address = ctrl->channel0[i]; else - dimm_socket_address = ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL]; + dimm_socket_address = + ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL]; - value = spd_read_byte(dimm_socket_address, SPD_MIN_ROW_PRECHARGE_TIME); - if (value < 0) goto hw_err; + value = + spd_read_byte(dimm_socket_address, + SPD_MIN_ROW_PRECHARGE_TIME); + if (value < 0) + goto hw_err; if (value > slowest_row_precharge) slowest_row_precharge = value; - value = spd_read_byte(dimm_socket_address, SPD_MIN_RAS_TO_CAS_DELAY); - if(value < 0 ) goto hw_err; + value = + spd_read_byte(dimm_socket_address, + SPD_MIN_RAS_TO_CAS_DELAY); + if (value < 0) + goto hw_err; if (value > slowest_ras_cas_delay) slowest_ras_cas_delay = value; - value = spd_read_byte(dimm_socket_address, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); - if(value < 0 ) goto hw_err; + value = + spd_read_byte(dimm_socket_address, + SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); + if (value < 0) + goto hw_err; if (value > slowest_active_to_precharge_delay) slowest_active_to_precharge_delay = value; } // NOTE for timing parameters: - // At 133 MHz, 1 clock == 7.52 ns + // At 133 MHz, 1 clock == 7.52 ns - /* Read the initial state */ - dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT); + /* Read the initial state */ + dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT); /* Trp */ // E7501 supports only 2 or 3 clocks for tRP - if (slowest_row_precharge > ((22<<2) | (2<<0))) - die("unsupported DIMM tRP"); // > 22.5 ns: 4 or more clocks - else if (slowest_row_precharge > (15<<2)) - dram_timing &= ~(1<<0); // > 15.0 ns: 3 clocks + if (slowest_row_precharge > ((22 << 2) | (2 << 0))) + die("unsupported DIMM tRP"); // > 22.5 ns: 4 or more clocks + else if (slowest_row_precharge > (15 << 2)) + dram_timing &= ~(1 << 0); // > 15.0 ns: 3 clocks else - dram_timing |= (1<<0); // <= 15.0 ns: 2 clocks + dram_timing |= (1 << 0); // <= 15.0 ns: 2 clocks /* Trcd */ // E7501 supports only 2 or 3 clocks for tRCD // Use the same value for both read & write - dram_timing &= ~((1<<3)|(3<<1)); - if (slowest_ras_cas_delay > ((22<<2) | (2<<0))) - die("unsupported DIMM tRCD"); // > 22.5 ns: 4 or more clocks - else if (slowest_ras_cas_delay > (15<<2)) - dram_timing |= (2<<1); // > 15.0 ns: 3 clocks + dram_timing &= ~((1 << 3) | (3 << 1)); + if (slowest_ras_cas_delay > ((22 << 2) | (2 << 0))) + die("unsupported DIMM tRCD"); // > 22.5 ns: 4 or more clocks + else if (slowest_ras_cas_delay > (15 << 2)) + dram_timing |= (2 << 1); // > 15.0 ns: 3 clocks else - dram_timing |= ((1<<3) | (3<<1)); // <= 15.0 ns: 2 clocks + dram_timing |= ((1 << 3) | (3 << 1)); // <= 15.0 ns: 2 clocks /* Tras */ // E7501 supports only 5, 6, or 7 clocks for tRAS // 5 clocks ~= 37.6 ns, 6 clocks ~= 45.1 ns, 7 clocks ~= 52.6 ns - dram_timing &= ~(3<<9); + dram_timing &= ~(3 << 9); if (slowest_active_to_precharge_delay > 52) - die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks + die("unsupported DIMM tRAS"); // > 52 ns: 8 or more clocks else if (slowest_active_to_precharge_delay > 45) - dram_timing |= (0<<9); // 46-52 ns: 7 clocks + dram_timing |= (0 << 9); // 46-52 ns: 7 clocks else if (slowest_active_to_precharge_delay > 37) - dram_timing |= (1<<9); // 38-45 ns: 6 clocks + dram_timing |= (1 << 9); // 38-45 ns: 6 clocks else - dram_timing |= (2<<9); // < 38 ns: 5 clocks - + dram_timing |= (2 << 9); // < 38 ns: 5 clocks - /* Trd */ + /* Trd */ /* Set to a 7 clock read delay. This is for 133Mhz - * with a CAS latency of 2.5 if 2.0 a 6 clock - * delay is good */ + * with a CAS latency of 2.5 if 2.0 a 6 clock + * delay is good */ - dram_timing &= ~(7<<24); // 7 clocks + dram_timing &= ~(7 << 24); // 7 clocks if (current_cas_latency == DRT_CAS_2_0) - dram_timing |= (1<<24); // 6 clocks + dram_timing |= (1 << 24); // 6 clocks /* * Back to Back Read-Write Turn Around @@ -1247,29 +1302,30 @@ /* Set to a 5 clock back to back read to write turn around. * 4 is a good delay if the CAS latency is 2.0 */ - dram_timing &= ~(1<<28); // 5 clocks + dram_timing &= ~(1 << 28); // 5 clocks if (current_cas_latency == DRT_CAS_2_0) - dram_timing |= (1<<28); // 4 clocks + dram_timing |= (1 << 28); // 4 clocks pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing); return; -hw_err: + hw_err: die(SPD_ERROR); } //---------------------------------------------------------------------------------- -// Function: configure_e7501_cas_latency -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see -// spd_get_supported_dimms() -// Return Value: None -// Description: Determine the shortest CAS# latency that the E7501 and all DIMMs -// have in common, and program the E7501 to use it. +// Function: configure_e7501_cas_latency +// Parameters: ctrl - PCI addresses of memory controller functions, and +// SMBus addresses of DIMM slots on the mainboard +// dimm_mask - bitmask of populated DIMMs on the board - see +// spd_get_supported_dimms() +// Return Value: None +// Description: Determine the shortest CAS# latency that the E7501 and all DIMMs +// have in common, and program the E7501 to use it. // -static void configure_e7501_cas_latency(const struct mem_controller *ctrl, uint8_t dimm_mask) +static void configure_e7501_cas_latency(const struct mem_controller *ctrl, + uint8_t dimm_mask) { int i; int value; @@ -1279,32 +1335,40 @@ // CAS# latency bitmasks in SPD_ACCEPTABLE_CAS_LATENCIES format // NOTE: E7501 supports only 2.0 and 2.5 - uint32_t system_compatible_cas_latencies = SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5; + uint32_t system_compatible_cas_latencies = + SPD_CAS_LATENCY_2_0 | SPD_CAS_LATENCY_2_5; uint32_t current_cas_latency; uint32_t dimm_compatible_cas_latencies; - + for (i = 0; i < MAX_DIMM_SOCKETS; i++) { - uint16_t dimm_socket_address; + uint16_t dimm_socket_address; if (!(dimm_mask & (1 << i))) - continue; // This DIMM not usable + continue; // This DIMM not usable if (i < MAX_DIMM_SOCKETS_PER_CHANNEL) dimm_socket_address = ctrl->channel0[i]; else - dimm_socket_address = ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL]; + dimm_socket_address = + ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL]; - value = spd_read_byte(dimm_socket_address, SPD_ACCEPTABLE_CAS_LATENCIES); - if (value < 0) goto hw_err; + value = + spd_read_byte(dimm_socket_address, + SPD_ACCEPTABLE_CAS_LATENCIES); + if (value < 0) + goto hw_err; - dimm_compatible_cas_latencies = value & 0x7f; // Start with all supported by DIMM - current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM + dimm_compatible_cas_latencies = value & 0x7f; // Start with all supported by DIMM + current_cas_latency = 1 << log2(dimm_compatible_cas_latencies); // Max supported by DIMM // Can we support the highest CAS# latency? - value = spd_read_byte(dimm_socket_address, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); - if (value < 0) goto hw_err; + value = + spd_read_byte(dimm_socket_address, + SPD_MIN_CYCLE_TIME_AT_CAS_MAX); + if (value < 0) + goto hw_err; // NOTE: At 133 MHz, 1 clock == 7.52 ns if (value > 0x75) { @@ -1312,30 +1376,36 @@ // Remove it from the bitmask of those supported by the DIMM that are compatible dimm_compatible_cas_latencies &= ~current_cas_latency; } - // Can we support the next-highest CAS# latency (max - 0.5)? current_cas_latency >>= 1; if (current_cas_latency != 0) { - value = spd_read_byte(dimm_socket_address, SPD_SDRAM_CYCLE_TIME_2ND); - if(value < 0 ) goto hw_err; - if(value > 0x75) - dimm_compatible_cas_latencies &= ~current_cas_latency; + value = + spd_read_byte(dimm_socket_address, + SPD_SDRAM_CYCLE_TIME_2ND); + if (value < 0) + goto hw_err; + if (value > 0x75) + dimm_compatible_cas_latencies &= + ~current_cas_latency; } - // Can we support the next-highest CAS# latency (max - 1.0)? current_cas_latency >>= 1; if (current_cas_latency != 0) { - value = spd_read_byte(dimm_socket_address, SPD_SDRAM_CYCLE_TIME_3RD); - if(value < 0 ) goto hw_err; - if(value > 0x75) - dimm_compatible_cas_latencies &= ~current_cas_latency; + value = + spd_read_byte(dimm_socket_address, + SPD_SDRAM_CYCLE_TIME_3RD); + if (value < 0) + goto hw_err; + if (value > 0x75) + dimm_compatible_cas_latencies &= + ~current_cas_latency; } - // Restrict the system to CAS# latencies compatible with this DIMM - system_compatible_cas_latencies &= dimm_compatible_cas_latencies; + system_compatible_cas_latencies &= + dimm_compatible_cas_latencies; - /* go to the next DIMM */ + /* go to the next DIMM */ } /* After all of the arduous calculation setup with the fastest @@ -1345,154 +1415,162 @@ dram_timing = pci_read_config32(PCI_DEV(0, 0, 0), DRT); dram_timing &= ~(DRT_CAS_MASK); - maybe_dram_read_timing = pci_read_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL); + maybe_dram_read_timing = + pci_read_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL); maybe_dram_read_timing &= 0xF00C; if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_0) { dram_timing |= DRT_CAS_2_0; maybe_dram_read_timing |= 0xBB1; - } - else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) { + } else if (system_compatible_cas_latencies & SPD_CAS_LATENCY_2_5) { - uint32_t dram_row_attributes = pci_read_config32(PCI_DEV(0, 0, 0), DRA); + uint32_t dram_row_attributes = + pci_read_config32(PCI_DEV(0, 0, 0), DRA); dram_timing |= DRT_CAS_2_5; // At CAS# 2.5, DRAM Read Timing (if that's what it its) appears to need a slightly // different value if all DIMM slots are populated - if ((dram_row_attributes & 0xff) && (dram_row_attributes & 0xff00) && - (dram_row_attributes & 0xff0000) && (dram_row_attributes & 0xff000000)) { + if ((dram_row_attributes & 0xff) + && (dram_row_attributes & 0xff00) + && (dram_row_attributes & 0xff0000) + && (dram_row_attributes & 0xff000000)) { // All slots populated maybe_dram_read_timing |= 0x0882; - } - else { + } else { // Some unpopulated slots maybe_dram_read_timing |= 0x0662; } - } - else + } else die("No CAS# latencies compatible with all DIMMs!!\n"); pci_write_config32(PCI_DEV(0, 0, 0), DRT, dram_timing); /* set master DLL reset */ dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88); - dword |= (1<<26); + dword |= (1 << 26); pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword); - + dword &= 0x0c0007ff; /* patch try register 88 is undocumented tnz */ dword |= 0xd2109800; pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword); - - pci_write_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL, maybe_dram_read_timing); - + pci_write_config16(PCI_DEV(0, 0, 0), MAYBE_DRDCTL, + maybe_dram_read_timing); + dword = pci_read_config32(PCI_DEV(0, 0, 0), 0x88); /* reset master DLL reset */ - dword &= ~(1<<26); + dword &= ~(1 << 26); pci_write_config32(PCI_DEV(0, 0, 0), 0x88, dword); return; -hw_err: + hw_err: die(SPD_ERROR); } //---------------------------------------------------------------------------------- -// Function: configure_e7501_dram_controller_mode -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see -// spd_get_supported_dimms() -// Return Value: None -// Description: Configure the refresh interval so that we refresh no more often -// than required by the "most needy" DIMM. Also disable ECC if any -// of the DIMMs don't support it. -// -static void configure_e7501_dram_controller_mode(const struct mem_controller *ctrl, - uint8_t dimm_mask) +// Function: configure_e7501_dram_controller_mode +// Parameters: ctrl - PCI addresses of memory controller functions, and +// SMBus addresses of DIMM slots on the mainboard +// dimm_mask - bitmask of populated DIMMs on the board - see +// spd_get_supported_dimms() +// Return Value: None +// Description: Configure the refresh interval so that we refresh no more often +// than required by the "most needy" DIMM. Also disable ECC if any +// of the DIMMs don't support it. +// +static void configure_e7501_dram_controller_mode(const struct + mem_controller *ctrl, + uint8_t dimm_mask) { - int i; + int i; // Initial settings - uint32_t controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); + uint32_t controller_mode = + pci_read_config32(PCI_DEV(0, 0, 0), DRC); uint32_t system_refresh_mode = (controller_mode >> 8) & 7; // Code below assumes that most aggressive settings are in // force when we are called, either via E7501 reset defaults // or by sdram_set_registers(): - // - ECC enabled - // - No refresh + // - ECC enabled + // - No refresh - ASSERT((controller_mode & (3<<20)) == (2<<20)); // ECC - ASSERT(!(controller_mode & (7 << 8))); // Refresh + ASSERT((controller_mode & (3 << 20)) == (2 << 20)); // ECC + ASSERT(!(controller_mode & (7 << 8))); // Refresh - /* Walk through _all_ dimms and find the least-common denominator for: - * - ECC support - * - refresh rates - */ + /* Walk through _all_ dimms and find the least-common denominator for: + * - ECC support + * - refresh rates + */ for (i = 0; i < MAX_DIMM_SOCKETS; i++) { uint32_t dimm_refresh_mode; - int value; - uint16_t dimm_socket_address; + int value; + uint16_t dimm_socket_address; if (!(dimm_mask & (1 << i))) { - continue; // This DIMM not usable - } + continue; // This DIMM not usable + } if (i < MAX_DIMM_SOCKETS_PER_CHANNEL) dimm_socket_address = ctrl->channel0[i]; else - dimm_socket_address = ctrl->channel1[i - MAX_DIMM_SOCKETS_PER_CHANNEL]; + dimm_socket_address = + ctrl->channel1[i - + MAX_DIMM_SOCKETS_PER_CHANNEL]; // Disable ECC mode if any one of the DIMMs does not support ECC // SJM: Should we just die here? E7501 datasheet says non-ECC DIMMs aren't supported. - value = spd_read_byte(dimm_socket_address, SPD_DIMM_CONFIG_TYPE); - die_on_spd_error(value); + value = + spd_read_byte(dimm_socket_address, + SPD_DIMM_CONFIG_TYPE); + die_on_spd_error(value); if (value != ERROR_SCHEME_ECC) { controller_mode &= ~(3 << 20); } value = spd_read_byte(dimm_socket_address, SPD_REFRESH); die_on_spd_error(value); - value &= 0x7f; // Mask off self-refresh bit - if(value > MAX_SPD_REFRESH_RATE) { + value &= 0x7f; // Mask off self-refresh bit + if (value > MAX_SPD_REFRESH_RATE) { print_err("unsupported refresh rate\n"); continue; } - // Get the appropriate E7501 refresh mode for this DIMM dimm_refresh_mode = refresh_rate_map[value]; if (dimm_refresh_mode > 7) { print_err("unsupported refresh rate\n"); continue; } - // If this DIMM requires more frequent refresh than others, // update the system setting - if (refresh_frequency[dimm_refresh_mode] > refresh_frequency[system_refresh_mode]) + if (refresh_frequency[dimm_refresh_mode] > + refresh_frequency[system_refresh_mode]) system_refresh_mode = dimm_refresh_mode; - + #ifdef SUSPICIOUS_LOOKING_CODE // SJM NOTE: This code doesn't look right. SPD values are an order of magnitude smaller -// than the clock period of the memory controller. Also, no other northbridge -// looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME. +// than the clock period of the memory controller. Also, no other northbridge +// looks at SPD_CMD_SIGNAL_INPUT_HOLD_TIME. // Switch to 2 clocks for address/command if required by any one of the DIMMs // NOTE: At 133 MHz, 1 clock == 7.52 ns - value = spd_read_byte(dimm_socket_address, SPD_CMD_SIGNAL_INPUT_HOLD_TIME); + value = + spd_read_byte(dimm_socket_address, + SPD_CMD_SIGNAL_INPUT_HOLD_TIME); die_on_spd_error(value); - if(value >= 0xa0) { /* At 133MHz this constant should be 0x75 */ - controller_mode &= ~(1<<16); /* Use two clock cyles instead of one */ + if (value >= 0xa0) { /* At 133MHz this constant should be 0x75 */ + controller_mode &= ~(1 << 16); /* Use two clock cyles instead of one */ } #endif - - /* go to the next DIMM */ + + /* go to the next DIMM */ } controller_mode |= (system_refresh_mode << 8); @@ -1502,54 +1580,54 @@ } //---------------------------------------------------------------------------------- -// Function: configure_e7501_row_attributes -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// dimm_mask - bitmask of populated DIMMs on the board - see -// spd_get_supported_dimms() -// Return Value: None -// Description: Configure the E7501's DRAM Row Attributes (DRA) registers -// based on DIMM parameters read via SPD. This tells the controller -// the width of the SDRAM chips on each DIMM side (x4 or x8) and -// the page size of each DIMM side (4, 8, 16, or 32 KB). +// Function: configure_e7501_row_attributes +// Parameters: ctrl - PCI addresses of memory controller functions, and +// SMBus addresses of DIMM slots on the mainboard +// dimm_mask - bitmask of populated DIMMs on the board - see +// spd_get_supported_dimms() +// Return Value: None +// Description: Configure the E7501's DRAM Row Attributes (DRA) registers +// based on DIMM parameters read via SPD. This tells the controller +// the width of the SDRAM chips on each DIMM side (x4 or x8) and +// the page size of each DIMM side (4, 8, 16, or 32 KB). // -static void configure_e7501_row_attributes(const struct mem_controller *ctrl, - uint8_t dimm_mask) +static void configure_e7501_row_attributes(const struct mem_controller + *ctrl, uint8_t dimm_mask) { int i; uint32_t row_attributes = 0; - - for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { - uint16_t dimm_socket_address = ctrl->channel0[i]; - struct dimm_size page_size; - struct dimm_size sdram_width; + for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { + + uint16_t dimm_socket_address = ctrl->channel0[i]; + struct dimm_size page_size; + struct dimm_size sdram_width; if (!(dimm_mask & (1 << i))) - continue; // This DIMM not usable + continue; // This DIMM not usable // Get the relevant parameters via SPD - page_size = sdram_spd_get_page_size(dimm_socket_address); + page_size = sdram_spd_get_page_size(dimm_socket_address); sdram_width = sdram_spd_get_width(dimm_socket_address); // Update the DRAM Row Attributes. // Page size is encoded as log2(page size in bits) - log2(8 Kb) // NOTE: 8 Kb = 2^13 - row_attributes |= (page_size.side1 - 13) << (i<<3); // Side 1 of each DIMM is an EVEN row + row_attributes |= (page_size.side1 - 13) << (i << 3); // Side 1 of each DIMM is an EVEN row if (sdram_width.side2 > 0) - row_attributes |= (page_size.side2 - 13) << ((i<<3) + 4); // Side 2 is ODD + row_attributes |= (page_size.side2 - 13) << ((i << 3) + 4); // Side 2 is ODD // Set x4 flags if appropriate if (sdram_width.side1 == 4) { - row_attributes |= 0x08 << (i<<3); + row_attributes |= 0x08 << (i << 3); } if (sdram_width.side2 == 4) { - row_attributes |= 0x08 << ((i<<3) + 4); - } - - /* go to the next DIMM */ + row_attributes |= 0x08 << ((i << 3) + 4); + } + + /* go to the next DIMM */ } /* Write the new row attributes register */ @@ -1557,12 +1635,12 @@ } //---------------------------------------------------------------------------------- -// Function: enable_e7501_clocks -// Parameters: dimm_mask - bitmask of populated DIMMs on the board - see -// spd_get_supported_dimms() -// Return Value: None -// Description: Enable clock signals for populated DIMM sockets and disable them -// for unpopulated sockets (to reduce EMI). +// Function: enable_e7501_clocks +// Parameters: dimm_mask - bitmask of populated DIMMs on the board - see +// spd_get_supported_dimms() +// Return Value: None +// Description: Enable clock signals for populated DIMM sockets and disable them +// for unpopulated sockets (to reduce EMI). // static void enable_e7501_clocks(uint8_t dimm_mask) { @@ -1571,30 +1649,29 @@ for (i = 0; i < MAX_DIMM_SOCKETS_PER_CHANNEL; i++) { - uint8_t socket_mask = 1 << i; + uint8_t socket_mask = 1 << i; if (dimm_mask & socket_mask) clock_disable &= ~socket_mask; // DIMM present, enable clock else clock_disable |= socket_mask; // DIMM absent, disable clock } - + pci_write_config8(PCI_DEV(0, 0, 0), CKDIS, clock_disable); } - /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/ /* DIMM-DEDEPENDENT CONFIGURATION FUNCTIONS */ /**********************************************************************************/ //---------------------------------------------------------------------------------- -// Function: RAM_RESET_DDR_PTR -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// Return Value: None -// Description: DDR Receive FIFO RE-Sync (?) +// Function: RAM_RESET_DDR_PTR +// Parameters: ctrl - PCI addresses of memory controller functions, and +// SMBus addresses of DIMM slots on the mainboard +// Return Value: None +// Description: DDR Receive FIFO RE-Sync (?) // -static void RAM_RESET_DDR_PTR(void) +static void RAM_RESET_DDR_PTR(void) { uint8_t byte; byte = pci_read_config8(PCI_DEV(0, 0, 0), 0x88); @@ -1607,28 +1684,28 @@ } //---------------------------------------------------------------------------------- -// Function: ram_set_d0f0_regs -// Parameters: None -// Return Value: None -// Description: Set E7501 registers that are either independent of DIMM specifics, -// or establish default settings that will be overridden when we -// learn the specifics. -// This sets PCI configuration registers to known good values based -// on the table 'constant_register_values', which are a triple of -// configuration register offset, mask, and bits to set. +// Function: ram_set_d0f0_regs +// Parameters: None +// Return Value: None +// Description: Set E7501 registers that are either independent of DIMM specifics, +// or establish default settings that will be overridden when we +// learn the specifics. +// This sets PCI configuration registers to known good values based +// on the table 'constant_register_values', which are a triple of +// configuration register offset, mask, and bits to set. // -static void ram_set_d0f0_regs(void) +static void ram_set_d0f0_regs(void) { int i; int num_values = ARRAY_SIZE(constant_register_values); - ASSERT((num_values % 3) == 0); // Bad table? + ASSERT((num_values % 3) == 0); // Bad table? - for(i = 0; i < num_values; i += 3) { + for (i = 0; i < num_values; i += 3) { uint32_t register_offset = constant_register_values[i]; - uint32_t bits_to_mask = constant_register_values[i+1]; - uint32_t bits_to_set = constant_register_values[i+2]; + uint32_t bits_to_mask = constant_register_values[i + 1]; + uint32_t bits_to_set = constant_register_values[i + 2]; uint32_t register_value; // It's theoretically possible to set values for something other than D0:F0, @@ -1639,25 +1716,27 @@ // Again, not strictly an error, but flagged as a potential bug ASSERT((bits_to_mask & bits_to_set) == 0); - register_value = pci_read_config32(PCI_DEV(0, 0, 0), register_offset); - register_value &= bits_to_mask; - register_value |= bits_to_set; + register_value = + pci_read_config32(PCI_DEV(0, 0, 0), register_offset); + register_value &= bits_to_mask; + register_value |= bits_to_set; - pci_write_config32(PCI_DEV(0, 0, 0), register_offset, register_value); - } + pci_write_config32(PCI_DEV(0, 0, 0), register_offset, + register_value); + } } //---------------------------------------------------------------------------------- -// Function: write_8dwords -// Parameters: src_addr -// dst_addr -// Return Value: None -// Description: Copy 64 bytes from one location to another. +// Function: write_8dwords +// Parameters: src_addr +// dst_addr +// Return Value: None +// Description: Copy 64 bytes from one location to another. // -static void write_8dwords(uint32_t* src_addr, uint32_t dst_addr) +static void write_8dwords(const uint32_t * src_addr, uint32_t dst_addr) { int i; - for (i=0; i<8; i++) { + for (i = 0; i < 8; i++) { write32(dst_addr, *src_addr); src_addr++; dst_addr += sizeof(uint32_t); @@ -1665,43 +1744,41 @@ } //---------------------------------------------------------------------------------- -// Function: ram_set_rcomp_regs -// Parameters: None -// Return Value: None -// Description: Set the E7501's (undocumented) RCOMP registers. -// Per the 855PM datasheet and IXP2800 HW Initialization Reference -// Manual, RCOMP registers appear to affect drive strength, -// pullup/pulldown offset, and slew rate of various signal groups. -// Comments below are conjecture based on apparent similarity -// between the E7501 and these two chips. +// Function: ram_set_rcomp_regs +// Parameters: None +// Return Value: None +// Description: Set the E7501's (undocumented) RCOMP registers. +// Per the 855PM datasheet and IXP2800 HW Initialization Reference +// Manual, RCOMP registers appear to affect drive strength, +// pullup/pulldown offset, and slew rate of various signal groups. +// Comments below are conjecture based on apparent similarity +// between the E7501 and these two chips. // -static void ram_set_rcomp_regs(void) +static void ram_set_rcomp_regs(void) { uint32_t dword; uint8_t maybe_strength_control; RAM_DEBUG_MESSAGE("Setting RCOMP registers.\n"); - /*enable access to the rcomp bar*/ + /*enable access to the rcomp bar */ dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST); - dword |= (1<<22); - pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword); - + dword |= (1 << 22); + pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword); // Set the RCOMP MMIO base address - pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, RCOMP_MMIO); + pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_SMRBASE, RCOMP_MMIO); // Block RCOMP updates while we configure the registers dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); - dword |= (1<<9); + dword |= (1 << 9); write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); - /* Begin to write the RCOMP registers */ // Set CMD and DQ/DQS strength to 2x (?) maybe_strength_control = read8(RCOMP_MMIO + MAYBE_DQCMDSTR) & 0x88; - maybe_strength_control |= 0x44; + maybe_strength_control |= 0x44; write8(RCOMP_MMIO + MAYBE_DQCMDSTR, maybe_strength_control); write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x80); @@ -1711,19 +1788,18 @@ // NOTE: some factory BIOS set 0x9088 here. Seems to work either way. write16(RCOMP_MMIO + 0x40, 0); - // Set RCVEnOut# strength to 2x (?) maybe_strength_control = read8(RCOMP_MMIO + MAYBE_RCVENSTR) & 0xF8; - maybe_strength_control |= 4; + maybe_strength_control |= 4; write8(RCOMP_MMIO + MAYBE_RCVENSTR, maybe_strength_control); write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x1c0); write16(RCOMP_MMIO + 0x50, 0); - + // Set CS# strength for x4 SDRAM to 2x (?) maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CSBSTR) & 0xF8; - maybe_strength_control |= 4; + maybe_strength_control |= 4; write8(RCOMP_MMIO + MAYBE_CSBSTR, maybe_strength_control); write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0x140); @@ -1731,7 +1807,7 @@ // Set CKE strength for x4 SDRAM to 2x (?) maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKESTR) & 0xF8; - maybe_strength_control |= 4; + maybe_strength_control |= 4; write8(RCOMP_MMIO + MAYBE_CKESTR, maybe_strength_control); write_8dwords(maybe_2x_slew_table, RCOMP_MMIO + 0xa0); @@ -1739,7 +1815,7 @@ // Set CK strength for x4 SDRAM to 1x (?) maybe_strength_control = read8(RCOMP_MMIO + MAYBE_CKSTR) & 0xF8; - maybe_strength_control |= 1; + maybe_strength_control |= 1; write8(RCOMP_MMIO + MAYBE_CKSTR, maybe_strength_control); write_8dwords(maybe_pull_updown_offset_table, RCOMP_MMIO + 0x180); @@ -1747,12 +1823,11 @@ write8(RCOMP_MMIO + 0x2c, 0xff); - // Set the digital filter length to 8 (?) dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); // NOTE: Some factory BIOS don't do this. - // Doesn't seem to matter either way. + // Doesn't seem to matter either way. dword &= ~2; dword |= 1; @@ -1760,25 +1835,25 @@ /* Wait 40 usec */ SLOW_DOWN_IO; - + /* unblock updates */ dword = read32(RCOMP_MMIO + MAYBE_SMRCTL); - dword &= ~(1<<9); + dword &= ~(1 << 9); write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); // Force a RCOMP measurement cycle? - dword |= (1<<8); + dword |= (1 << 8); write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); - dword &= ~(1<<8); + dword &= ~(1 << 8); write32(RCOMP_MMIO + MAYBE_SMRCTL, dword); - + /* Wait 40 usec */ SLOW_DOWN_IO; /*disable access to the rcomp bar */ dword = pci_read_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST); - dword &= ~(1<<22); - pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword); + dword &= ~(1 << 22); + pci_write_config32(PCI_DEV(0, 0, 0), MAYBE_MCHTST, dword); } @@ -1787,16 +1862,17 @@ /**********************************************************************************/ //---------------------------------------------------------------------------------- -// Function: sdram_enable -// Parameters: controllers - not used -// ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// Return Value: None -// Description: Go through the JEDEC initialization sequence for all DIMMs, -// then enable refresh and initialize ECC and memory to zero. -// Upon exit, SDRAM is up and running. +// Function: sdram_enable +// Parameters: controllers - not used +// ctrl - PCI addresses of memory controller functions, and +// SMBus addresses of DIMM slots on the mainboard +// Return Value: None +// Description: Go through the JEDEC initialization sequence for all DIMMs, +// then enable refresh and initialize ECC and memory to zero. +// Upon exit, SDRAM is up and running. // -static void sdram_enable(int controllers, const struct mem_controller *ctrl) +static void sdram_enable(int controllers, + const struct mem_controller *ctrl) { uint8_t dimm_mask = pci_read_config16(PCI_DEV(0, 0, 0), SKPD); uint32_t dram_controller_mode; @@ -1809,111 +1885,107 @@ RAM_DEBUG_MESSAGE("Ram Enable 2\n"); /* A 200us delay is needed */ - - DO_DELAY - EXTRA_DELAY + DO_DELAY; EXTRA_DELAY; /* 3. Apply NOP */ RAM_DEBUG_MESSAGE("Ram Enable 3\n"); do_ram_command(RAM_COMMAND_NOP, 0); - EXTRA_DELAY + EXTRA_DELAY; /* 4 Precharge all */ RAM_DEBUG_MESSAGE("Ram Enable 4\n"); do_ram_command(RAM_COMMAND_PRECHARGE, 0); - EXTRA_DELAY - + EXTRA_DELAY; /* wait until the all banks idle state... */ + /* 5. Issue EMRS to enable DLL */ RAM_DEBUG_MESSAGE("Ram Enable 5\n"); - do_ram_command(RAM_COMMAND_EMRS, SDRAM_EXTMODE_DLL_ENABLE | SDRAM_EXTMODE_DRIVE_NORMAL); - EXTRA_DELAY - + do_ram_command(RAM_COMMAND_EMRS, + SDRAM_EXTMODE_DLL_ENABLE | + SDRAM_EXTMODE_DRIVE_NORMAL); + EXTRA_DELAY; + /* 6. Reset DLL */ RAM_DEBUG_MESSAGE("Ram Enable 6\n"); set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_DLL_RESET); - EXTRA_DELAY - + EXTRA_DELAY; /* Ensure a 200us delay between the DLL reset in step 6 and the final * mode register set in step 9. * Infineon needs this before any other command is sent to the ram. */ - DO_DELAY - EXTRA_DELAY - + DO_DELAY; EXTRA_DELAY; + /* 7 Precharge all */ RAM_DEBUG_MESSAGE("Ram Enable 7\n"); do_ram_command(RAM_COMMAND_PRECHARGE, 0); - EXTRA_DELAY - + EXTRA_DELAY; + /* 8 Now we need 2 AUTO REFRESH / CBR cycles to be performed */ RAM_DEBUG_MESSAGE("Ram Enable 8\n"); do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY + EXTRA_DELAY; do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY + EXTRA_DELAY; + /* And for good luck 6 more CBRs */ do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY + EXTRA_DELAY; do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY + EXTRA_DELAY; do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY + EXTRA_DELAY; do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY + EXTRA_DELAY; do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY + EXTRA_DELAY; do_ram_command(RAM_COMMAND_CBR, 0); - EXTRA_DELAY + EXTRA_DELAY; /* 9 mode register set */ RAM_DEBUG_MESSAGE("Ram Enable 9\n"); set_ram_mode(E7501_SDRAM_MODE | SDRAM_MODE_NORMAL); - EXTRA_DELAY - + EXTRA_DELAY; + /* 10 DDR Receive FIFO RE-Sync */ RAM_DEBUG_MESSAGE("Ram Enable 10\n"); RAM_RESET_DDR_PTR(); - EXTRA_DELAY - + EXTRA_DELAY; + /* 11 normal operation */ RAM_DEBUG_MESSAGE("Ram Enable 11\n"); do_ram_command(RAM_COMMAND_NORMAL, 0); - EXTRA_DELAY + EXTRA_DELAY; // Reconfigure the row boundaries and Top of Low Memory // to match the true size of the DIMMs configure_e7501_ram_addresses(ctrl, dimm_mask); - /* Finally enable refresh */ + /* Finally enable refresh */ dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); dram_controller_mode |= (1 << 29); pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); - EXTRA_DELAY - + EXTRA_DELAY; initialize_ecc(); - dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); /* FCS_EN */ - dram_controller_mode |= (1<<17); // NOTE: undocumented reserved bit + dram_controller_mode = pci_read_config32(PCI_DEV(0, 0, 0), DRC); /* FCS_EN */ + dram_controller_mode |= (1 << 17); // NOTE: undocumented reserved bit pci_write_config32(PCI_DEV(0, 0, 0), DRC, dram_controller_mode); RAM_DEBUG_MESSAGE("Northbridge following SDRAM init:\n"); DUMPNORTH(); - -// verify_ram(); } //---------------------------------------------------------------------------------- -// Function: sdram_set_spd_registers -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// Return Value: None -// Description: Configure SDRAM controller parameters that depend on -// characteristics of the DIMMs installed in the system. These -// characteristics are read from the DIMMs via the standard Serial -// Presence Detect (SPD) interface. +// Function: sdram_set_spd_registers +// Parameters: ctrl - PCI addresses of memory controller functions, and +// SMBus addresses of DIMM slots on the mainboard +// Return Value: None +// Description: Configure SDRAM controller parameters that depend on +// characteristics of the DIMMs installed in the system. These +// characteristics are read from the DIMMs via the standard Serial +// Presence Detect (SPD) interface. // -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(const struct mem_controller *ctrl) { uint8_t dimm_mask; @@ -1934,29 +2006,30 @@ RAM_RESET_DDR_PTR(); configure_e7501_dram_timing(ctrl, dimm_mask); - DO_DELAY + DO_DELAY; RAM_DEBUG_MESSAGE("done\n"); } - // NOTE: configure_e7501_ram_addresses() is NOT called here. - // We want to keep the default 64 MB/row mapping until sdram_enable() is called, - // even though the default mapping is almost certainly incorrect. - // The default mapping makes it easy to initialize all of the DIMMs - // even if the total system memory is > 4 GB. - // - // Save the dimm_mask for when sdram_enable is called, so it can call - // configure_e7501_ram_addresses() without having to regenerate the bitmask - // of usable DIMMs. + /* NOTE: configure_e7501_ram_addresses() is NOT called here. + * We want to keep the default 64 MB/row mapping until sdram_enable() is called, + * even though the default mapping is almost certainly incorrect. + * The default mapping makes it easy to initialize all of the DIMMs + * even if the total system memory is > 4 GB. + * + * Save the dimm_mask for when sdram_enable is called, so it can call + * configure_e7501_ram_addresses() without having to regenerate the bitmask + * of usable DIMMs. + */ pci_write_config16(PCI_DEV(0, 0, 0), SKPD, dimm_mask); } //---------------------------------------------------------------------------------- -// Function: sdram_set_registers -// Parameters: ctrl - PCI addresses of memory controller functions, and -// SMBus addresses of DIMM slots on the mainboard -// Return Value: None -// Description: Do basic ram setup that does NOT depend on serial presence detect -// information (i.e. independent of DIMM specifics). +// Function: sdram_set_registers +// Parameters: ctrl - PCI addresses of memory controller functions, and +// SMBus addresses of DIMM slots on the mainboard +// Return Value: None +// Description: Do basic ram setup that does NOT depend on serial presence detect +// information (i.e. independent of DIMM specifics). // static void sdram_set_registers(const struct mem_controller *ctrl) { @@ -1968,5 +2041,5 @@ } /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/ -/* PUBLIC INTERFACE */ +/* PUBLIC INTERFACE */ /**********************************************************************************/ Modified: trunk/src/northbridge/intel/e7501/raminit.h ============================================================================== --- trunk/src/northbridge/intel/e7501/raminit.h Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/northbridge/intel/e7501/raminit.h Thu Apr 15 14:39:29 2010 (r5442) @@ -15,5 +15,8 @@ uint16_t channel1[MAX_DIMM_SOCKETS_PER_CHANNEL]; }; +#ifndef __ROMCC__ +void sdram_initialize(int controllers, const struct mem_controller *ctrl); +#endif #endif /* RAMINIT_H */ Modified: trunk/src/northbridge/intel/i82830/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i82830/northbridge.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/northbridge/intel/i82830/northbridge.c Thu Apr 15 14:39:29 2010 (r5442) @@ -29,7 +29,6 @@ #include <string.h> #include <bitops.h> #include <boot/tables.h> -#include <arch/coreboot_tables.h> #include "chip.h" #include "i82830.h" Modified: trunk/src/northbridge/intel/i945/northbridge.c ============================================================================== --- trunk/src/northbridge/intel/i945/northbridge.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/northbridge/intel/i945/northbridge.c Thu Apr 15 14:39:29 2010 (r5442) @@ -31,7 +31,6 @@ #include <boot/tables.h> #include "chip.h" #include "i945.h" -#include <arch/coreboot_tables.h> static int get_pcie_bar(u32 *base, u32 *len) { Modified: trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c Thu Apr 15 14:39:29 2010 (r5442) @@ -29,6 +29,7 @@ return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } +#ifdef UNUSED_CODE static void smbus_write_byte(unsigned device, unsigned address, unsigned char val) { if (smbus_wait_until_ready(SMBUS_IO_BASE) < 0) { @@ -126,4 +127,4 @@ print_debug("SMBUS Block complete\n"); return 0; } - +#endif Modified: trunk/src/southbridge/via/vt8235/vt8235.c ============================================================================== --- trunk/src/southbridge/via/vt8235/vt8235.c Thu Apr 15 10:26:30 2010 (r5441) +++ trunk/src/southbridge/via/vt8235/vt8235.c Thu Apr 15 14:39:29 2010 (r5442) @@ -7,18 +7,9 @@ #include <pc80/i8259.h> #include "chip.h" -/* - * Base VT8235. - */ - -void hard_reset(void) -{ - printk(BIOS_ERR, "NO HARD RESET ON VT8235! FIX ME!\n"); -} - static void keyboard_on(struct device *dev) { - unsigned char regval; + u8 regval; regval = pci_read_config8(dev, 0x51); regval |= 0x05; @@ -28,6 +19,7 @@ pc_keyboard_init(0); } +#ifdef UNUSED_CODE void dump_south(device_t dev0) { int i,j; @@ -43,33 +35,37 @@ void set_led(void) { - // set power led to steady now that lxbios has virtually done its job + // set power led to steady now that coreboot has virtually done its job device_t dev; dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, 0); pci_write_config8(dev, 0x94, 0xb0); } - +#endif static void vt8235_enable(struct device *dev) { - unsigned char regval; - unsigned short vendor,model; + u8 regval; + u16 vendor,model; vendor = pci_read_config16(dev,0); model = pci_read_config16(dev,0x2); printk(BIOS_DEBUG, "In vt8235_enable %04x %04x.\n",vendor,model); - /* if this is not the southbridge itself just return */ - /* this is necessary because USB devices are slot 10, whereas this device is slot 11 - therefore usb devices get called first during the bus scan */ + /* If this is not the southbridge itself just return. + * This is necessary because USB devices are slot 10, whereas this + * device is slot 11 therefore usb devices get called first during + * the bus scan. We don't want to wait until we could do dev->init + * because that's too late. + */ if( (vendor != PCI_VENDOR_ID_VIA) || (model != PCI_DEVICE_ID_VIA_8235)) return; printk(BIOS_DEBUG, "Initialising Devices\n"); - setup_i8259(); // make sure interupt controller is configured before keyboard init + /* make sure interupt controller is configured before keyboard init */ + setup_i8259(); /* enable RTC and ethernet */ regval = pci_read_config8(dev, 0x51); @@ -79,7 +75,9 @@ /* turn on keyboard */ keyboard_on(dev); - /* enable USB 1.1 & USB 2.0 -redundant really since we've already been there - see note above*/ + /* enable USB 1.1 & USB 2.0 - redundant really since we've + * already been there - see note above + */ regval = pci_read_config8(dev, 0x50); regval &= ~(0x36); pci_write_config8(dev, 0x50, regval);

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Re: [coreboot] Newbie to coreboot with a 845G chipset
by Joseph Smith 15 Apr '10

15 Apr '10

On 04/15/2010 07:24 AM, A.Haq Abbad wrote: > Ahhh, only if I can help you out. > I can program in C, but looking at coreboot's source code, it makes no > sence to me at all o_O > It is too specialist knowledge I guess. > Sure, two heads are always better than one :-) No not specialist knowledge, like anything it just takes a little time to learn how the code flows. The best way to start would be to find a board as close to yours as possible and adapt it. Unfortunately, I am mid processes on several other projects and won't be able to get to this until I complete them. Which may be a few months from now. But if you want to get started, feel free, I am here to answer any questions you may have :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

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AMD northbridge information on the wiki
by dolphinling 15 Apr '10

15 Apr '10

Hi, I noticed the wiki supported chipsets page has listed under the southbrigde section "AMD RS690" and "AMD RS780/RS785?". But RS690 and RS780 are northbridges, not southbridges, and there is no RS785. Sorted by codename, the chipsets I can find are* Codename Product Name Documentation? RS690 AMD 690G chipset x[2] RS690C AMD 690V chipset x[2] RS690E AMD M690E chipset x[2] RS690M AMD M690 chipset x[2] RS690MC AMD M690V chipset x[2] RS690T AMD M690T chipset x[2] RS740 AMD 740G chipset RX740 AMD 740 chipset RD780 AMD 790X chipset RS780 AMD 780G chipset x[1] RS780C AMD 780V chipset x[1] RS780D AMD 790GX chipset x[1] RS780E AMD 780E chipset x[1] RS780L AMD 760G chipset RS780M AMD M780G chipset x[1] RS780MC AMD M780V chipset x[1] RX780 AMD 770 chipset RX781 AMD M770 chipset x[1] RD790 AMD 790FX chipset RS880 AMD 785G chipset * Cobbled together from wikipedia and amd documentation [1] http://www.coreboot.org/Datasheets#AMD_RS780 [2] http://www.coreboot.org/Datasheets#AMD_RS690 As far as I can tell (though I haven't looked heavily), AMD northbridges are the only ones to use separate code/product names. Since the product names are likely more well-known, I suggest the following: Move "RS690" to northbridges, and rename it to "690G/V, M690/E/V/T" Move "RS780/RS785?" to northbridges, and rename it to "780E/G/V, 790GX, M770, M780G/V" Now, that assumes that support for these actually exists. I only see one motherboard on the supported motherboards page that uses a 690G, and none that uses a 700-series chipset. Does anyone know the actual status? And for all the 700-series without documentation, should they be in the list for clarity, as either WIP or NO with a footnote saying they're similar but documentation hasn't been released? -- dolphinling <http://dolphinling.net/>

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Re: [coreboot] Newbie to coreboot with a 845G chipset
by A.Haq Abbad 15 Apr '10

15 Apr '10

So you advice me to install coreboot on it? the motherboard is not mentioned on the website, but the chipset is! Thanks. On Tue, Apr 13, 2010 at 6:44 PM, Qing Pei Wang <wangqingpei(a)gmail.com>wrote: > if you want to try xp/DOS, Seabios would be the only choice. and it is > unnecessary to use kernel as payload(as a matter of fact, i doubt if it can > be taken as payload). > i think filo will be the easiest payload as the same. > > On Tue, Apr 13, 2010 at 10:52 PM, A.Haq Abbad <haqman(a)gmail.com> wrote: > >> Hi All >> >> Intel® 845G chipset >> Southbridge 82801 >> P4 2.4GHz >> >> From Compaq Evo D310 DT (Custom Mobo, P4B266-VMX) >> >> Any recomemendations? >> >> Which payload to choose? I want to start with a basic one, will be using >> Linux mostly, but I do want to try XP and DOS perhaps. >> SeaBios seems good, but on the Wiki, it only mentions coreboot v3, and not >> 4! I hope it's a typo. >> I don't think I can use a Linux kernel as a payload, as the chip only has >> 512KB. >> >> How risky is it to render the PC useless? Note that the BIOS chip is >> soldered into the Mobo :\ >> and I doubt I'd be bothered to buy a new one and solder it. >> >> Time to complete the whole thing? If too long, I'll do it on the weekend. >> >> Thanks. >> >> -- >> >> coreboot mailing list: coreboot(a)coreboot.org >> http://www.coreboot.org/mailman/listinfo/coreboot >> > > > > -- > Wang Qing Pei > MSN:wangqingpei@hotmail.com <MSN%3Awangqingpei(a)hotmail.com> > Gmail:wangqingpei@gmail.com <Gmail%3Awangqingpei(a)gmail.com> > Phone:86+13426369984 >

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[commit] r5441 - trunk/src/northbridge/intel/i82830
by repository service 15 Apr '10

15 Apr '10

Author: stepan Date: Thu Apr 15 10:26:30 2010 New Revision: 5441 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5441 Log: the dump function assumed that the mbi data comes right after the header. Which is not (always) the case. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/intel/i82830/i82830_smihandler.c Modified: trunk/src/northbridge/intel/i82830/i82830_smihandler.c ============================================================================== --- trunk/src/northbridge/intel/i82830/i82830_smihandler.c Thu Apr 15 07:19:29 2010 (r5440) +++ trunk/src/northbridge/intel/i82830/i82830_smihandler.c Thu Apr 15 10:26:30 2010 (r5441) @@ -262,7 +262,8 @@ getobj->banner.retsts = MSH_OK; #ifdef DEBUG_SMI_I82830 - dump(banner_id, sizeof(getobj) + len); + dump(banner_id, sizeof(getobj)); + dump(getobj->buffer + OBJ_OFFSET, len); #endif break; }

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[commit] r5439 - trunk/src/arch/i386
by repository service 15 Apr '10

15 Apr '10

Author: stepan Date: Thu Apr 15 01:58:07 2010 New Revision: 5439 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5439 Log: get rid of this nerving crt0.d stuff Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/arch/i386/Makefile.bigbootblock.inc trunk/src/arch/i386/Makefile.bootblock.inc Modified: trunk/src/arch/i386/Makefile.bigbootblock.inc ============================================================================== --- trunk/src/arch/i386/Makefile.bigbootblock.inc Wed Apr 14 23:47:24 2010 (r5438) +++ trunk/src/arch/i386/Makefile.bigbootblock.inc Thu Apr 15 01:58:07 2010 (r5439) @@ -26,7 +26,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/crt0.S @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< > $@.new && mv $@.new $@ + $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $< -o $@ $(obj)/coreboot: $$(initobjs) $(obj)/ldscript.ld @printf " LINK $(subst $(obj)/,,$(@))\n" Modified: trunk/src/arch/i386/Makefile.bootblock.inc ============================================================================== --- trunk/src/arch/i386/Makefile.bootblock.inc Wed Apr 14 23:47:24 2010 (r5438) +++ trunk/src/arch/i386/Makefile.bootblock.inc Thu Apr 15 01:58:07 2010 (r5439) @@ -63,7 +63,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.c @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< > $@.new && mv $@.new $@ + $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $< -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/i386/init/$(subst ",,$(CONFIG_BOOTBLOCK_SOURCE)) $(obj)/romcc @printf " ROMCC $(subst $(obj)/,,$(@))\n" @@ -107,5 +107,5 @@ $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S @printf " CC $(subst $(obj)/,,$(@))\n" - $(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $< > $@.new && mv $@.new $@ + $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $< -o $@

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[commit] r5440 - in trunk/src: cpu/amd/microcode cpu/amd/model_10xxx include/cpu/amd mainboard/amd/mahogany_fam10 mainboard/amd/serengeti_cheetah_fam10 mainboard/msi/ms9652_fam10 mainboard/supermic...
by repository service 15 Apr '10

15 Apr '10

Author: myles Date: Thu Apr 15 07:19:29 2010 New Revision: 5440 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5440 Log: Remove a few more warnings from fam10. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/cpu/amd/microcode/microcode.c trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c trunk/src/cpu/amd/model_10xxx/update_microcode.c trunk/src/include/cpu/amd/microcode.h trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/northbridge/amd/amdfam10/amdfam10.h trunk/src/northbridge/amd/amdfam10/debug.c trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c trunk/src/northbridge/amd/amdht/h3finit.c trunk/src/northbridge/amd/amdht/ht_wrapper.c trunk/src/northbridge/amd/amdmct/mct/mct_d.c trunk/src/northbridge/amd/amdmct/mct/mct_d_gcc.h trunk/src/northbridge/amd/amdmct/mct/mct_fd.c trunk/src/northbridge/amd/amdmct/mct/mctardk4.c trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Modified: trunk/src/cpu/amd/microcode/microcode.c ============================================================================== --- trunk/src/cpu/amd/microcode/microcode.c Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/cpu/amd/microcode/microcode.c Thu Apr 15 07:19:29 2010 (r5440) @@ -17,15 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __PRE_RAM__ - +#ifndef __ROMCC__ #include <stdint.h> #include <console/console.h> -#include <cpu/cpu.h> #include <cpu/x86/msr.h> #include <cpu/amd/microcode.h> -#include <cpu/x86/cache.h> +#endif +#ifndef __PRE_RAM__ +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> #endif struct microcode { Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Thu Apr 15 07:19:29 2010 (r5440) @@ -30,7 +30,6 @@ #define SET_FIDVID_CORE0_ONLY 0 #endif -void update_microcode(u32 cpu_deviceid); static void prep_fid_change(void); static void init_fidvid_stage2(u32 apicid, u32 nodeid); void cpuSetAMDMSR(void); Modified: trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c Thu Apr 15 07:19:29 2010 (r5440) @@ -37,8 +37,6 @@ #include <cpu/amd/multicore.h> #include <cpu/amd/model_10xxx_msr.h> -extern device_t get_node_pci(u32 nodeid, u32 fn); - #define MCI_STATUS 0x401 msr_t rdmsr_amd(u32 index) Modified: trunk/src/cpu/amd/model_10xxx/update_microcode.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/update_microcode.c Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/cpu/amd/model_10xxx/update_microcode.c Thu Apr 15 07:19:29 2010 (r5440) @@ -23,7 +23,9 @@ #include <device/device.h> #include <device/pci.h> #include <string.h> +#endif +#ifndef __ROMCC__ #include <cpu/amd/microcode.h> #endif Modified: trunk/src/include/cpu/amd/microcode.h ============================================================================== --- trunk/src/include/cpu/amd/microcode.h Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/include/cpu/amd/microcode.h Thu Apr 15 07:19:29 2010 (r5440) @@ -2,6 +2,7 @@ #define CPU_AMD_MICORCODE_H void amd_update_microcode(void *microcode_updates, unsigned processor_rev_id); +void update_microcode(u32 processor_rev_id); void model_fxx_update_microcode(unsigned cpu_deviceid); #endif /* CPU_AMD_MICROCODE_H */ Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Thu Apr 15 07:19:29 2010 (r5440) @@ -93,6 +93,8 @@ #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" @@ -100,8 +102,6 @@ #include "southbridge/amd/sb700/sb700_early_setup.c" //#include "spd_addr.h" -#include "cpu/amd/microcode/microcode.c" -#include "cpu/amd/model_10xxx/update_microcode.c" #define RC00 0 #define RC01 1 Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Thu Apr 15 07:19:29 2010 (r5440) @@ -115,6 +115,8 @@ #include "cpu/amd/quadcore/quadcore.c" #include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" @@ -122,8 +124,6 @@ #include "northbridge/amd/amdfam10/early_ht.c" #include "spd_addr.h" -#include "cpu/amd/microcode/microcode.c" -#include "cpu/amd/model_10xxx/update_microcode.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Thu Apr 15 07:19:29 2010 (r5440) @@ -118,6 +118,8 @@ #include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" @@ -140,8 +142,6 @@ } #include "spd_addr.h" -#include "cpu/amd/microcode/microcode.c" -#include "cpu/amd/model_10xxx/update_microcode.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Thu Apr 15 07:19:29 2010 (r5440) @@ -107,6 +107,8 @@ #include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" @@ -137,8 +139,6 @@ } #include "spd_addr.h" -#include "cpu/amd/microcode/microcode.c" -#include "cpu/amd/model_10xxx/update_microcode.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Thu Apr 15 07:19:29 2010 (r5440) @@ -111,6 +111,8 @@ #include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" @@ -141,8 +143,6 @@ } #include "spd_addr.h" -#include "cpu/amd/microcode/microcode.c" -#include "cpu/amd/model_10xxx/update_microcode.c" #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1) #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2) Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Thu Apr 15 07:19:29 2010 (r5440) @@ -113,10 +113,10 @@ #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" - - #include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/microcode/microcode.c" +#include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" @@ -144,8 +144,6 @@ } #include "spd_addr.h" -#include "cpu/amd/microcode/microcode.c" -#include "cpu/amd/model_10xxx/update_microcode.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/northbridge/amd/amdfam10/amdfam10.h ============================================================================== --- trunk/src/northbridge/amd/amdfam10/amdfam10.h Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/northbridge/amd/amdfam10/amdfam10.h Thu Apr 15 07:19:29 2010 (r5440) @@ -1084,6 +1084,10 @@ } __attribute__((packed)); +#ifndef __PRE_RAM__ +device_t get_node_pci(u32 nodeid, u32 fn); +#endif + #if CONFIG_AMDMCT == 0 #ifdef __PRE_RAM__ Modified: trunk/src/northbridge/amd/amdfam10/debug.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/debug.c Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/northbridge/amd/amdfam10/debug.c Thu Apr 15 07:19:29 2010 (r5440) @@ -22,6 +22,7 @@ */ #include "amdfam10_pci.c" +#include <delay.h> static inline void print_debug_addr(const char *str, void *val) { @@ -89,8 +90,6 @@ } } - - static void dump_pci_device_range(u32 dev, u32 start_reg, u32 size) { int i; @@ -111,10 +110,12 @@ } print_debug("\n"); } + static void dump_pci_device(u32 dev) { dump_pci_device_range(dev, 0, 4096); } + static void dump_pci_device_index_wait_range(u32 dev, u32 index_reg, u32 start, u32 size) { @@ -136,13 +137,13 @@ } print_debug("\n"); } + static inline void dump_pci_device_index_wait(u32 dev, u32 index_reg) { dump_pci_device_index_wait_range(dev, index_reg, 0, 0x54); dump_pci_device_index_wait_range(dev, index_reg, 0x100, 0x08); //DIMM1 when memclk > 400Hz // dump_pci_device_index_wait_range(dev, index_reg, 0x200, 0x08); //DIMM2 // dump_pci_device_index_wait_range(dev, index_reg, 0x300, 0x08); //DIMM3 - } static inline void dump_pci_device_index(u32 dev, u32 index_reg, u32 type, u32 length) @@ -165,7 +166,6 @@ print_debug("\n"); } - static inline void dump_pci_devices(void) { device_t dev; @@ -191,7 +191,6 @@ } } - static inline void dump_pci_devices_on_bus(u32 busn) { device_t dev; Modified: trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c Thu Apr 15 07:19:29 2010 (r5440) @@ -157,7 +157,7 @@ } -void raminit_amdmct(struct sys_info *sysinfo) +static void raminit_amdmct(struct sys_info *sysinfo) { struct MCTStatStruc *pMCTstat = &(sysinfo->MCTstat); struct DCTStatStruc *pDCTstatA = sysinfo->DCTstatA; Modified: trunk/src/northbridge/amd/amdht/h3finit.c ============================================================================== --- trunk/src/northbridge/amd/amdht/h3finit.c Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/northbridge/amd/amdht/h3finit.c Thu Apr 15 07:19:29 2010 (r5440) @@ -123,7 +123,7 @@ * @param[out] u8 results = the number of nodes in the graph * --------------------------------------------------------------------------------------- */ -u8 graphHowManyNodes(u8 *graph) +static u8 graphHowManyNodes(u8 *graph) { return graph[0]; } @@ -144,7 +144,7 @@ * @param[out] BOOL results = true if nodeA connects to nodeB false if not * --------------------------------------------------------------------------------------- */ -BOOL graphIsAdjacent(u8 *graph, u8 nodeA, u8 nodeB) +static BOOL graphIsAdjacent(u8 *graph, u8 nodeA, u8 nodeB) { u8 size = graph[0]; ASSERT(size <= MAX_NODES); @@ -170,7 +170,7 @@ * @param[out] u8 results = The response route node * --------------------------------------------------------------------------------------- */ -u8 graphGetRsp(u8 *graph, u8 nodeA, u8 nodeB) +static u8 graphGetRsp(u8 *graph, u8 nodeA, u8 nodeB) { u8 size = graph[0]; ASSERT(size <= MAX_NODES); @@ -196,7 +196,7 @@ * @param[out] u8 results = The request route node * --------------------------------------------------------------------------------------- */ -u8 graphGetReq(u8 *graph, u8 nodeA, u8 nodeB) +static u8 graphGetReq(u8 *graph, u8 nodeA, u8 nodeB) { u8 size = graph[0]; ASSERT(size <= MAX_NODES); @@ -219,7 +219,7 @@ * OU u8 results = the broadcast routes for nodeA from nodeB * --------------------------------------------------------------------------------------- */ -u8 graphGetBc(u8 *graph, u8 nodeA, u8 nodeB) +static u8 graphGetBc(u8 *graph, u8 nodeA, u8 nodeB) { u8 size = graph[0]; ASSERT(size <= MAX_NODES); @@ -248,7 +248,7 @@ * @param[in] sMainData* pDat = our global state, port config info * --------------------------------------------------------------------------------------- */ -void routeFromBSP(u8 targetNode, u8 actualTarget, sMainData *pDat) +static void routeFromBSP(u8 targetNode, u8 actualTarget, sMainData *pDat) { u8 predecessorNode, predecessorLink, currentPair; @@ -287,7 +287,7 @@ * @param[out] u8 results = the link on source which connects to target * --------------------------------------------------------------------------------------- */ -u8 convertNodeToLink(u8 srcNode, u8 targetNode, sMainData *pDat) +static u8 convertNodeToLink(u8 srcNode, u8 targetNode, sMainData *pDat) { u8 targetlink = INVALID_LINK; u8 k; @@ -326,7 +326,7 @@ * @param[in] sMainData* pDat = our global state * --------------------------------------------------------------------------------------- */ -void htDiscoveryFloodFill(sMainData *pDat) +static void htDiscoveryFloodFill(sMainData *pDat) { u8 currentNode = 0; u8 currentLink; @@ -595,7 +595,7 @@ * @param[out] BOOL results = the graphs are (or are not) isomorphic * --------------------------------------------------------------------------------------- */ -BOOL isoMorph(u8 i, sMainData *pDat) +static BOOL isoMorph(u8 i, sMainData *pDat) { u8 j, k; u8 nodecnt; @@ -669,7 +669,7 @@ * @param[out] degree matrix, permutation * --------------------------------------------------------------------------------------- */ -void lookupComputeAndLoadRoutingTables(sMainData *pDat) +static void lookupComputeAndLoadRoutingTables(sMainData *pDat) { u8 **pTopologyList; u8 *pSelected; @@ -810,7 +810,7 @@ * @param[in] sMainData* pDat = our global state, number of nodes discovered. * --------------------------------------------------------------------------------------- */ -void finializeCoherentInit(sMainData *pDat) +static void finializeCoherentInit(sMainData *pDat) { u8 curNode; @@ -843,7 +843,7 @@ * @param[in] sMainData* pDat = our global state * --------------------------------------------------------------------------------------- */ -void coherentInit(sMainData *pDat) +static void coherentInit(sMainData *pDat) { u8 i, j; @@ -891,7 +891,7 @@ * @param[in] sMainData* pDat = our global state * --------------------------------------------------------------------------------------- */ -void processLink(u8 node, u8 link, sMainData *pDat) +static void processLink(u8 node, u8 link, sMainData *pDat) { u8 secBus, subBus; u32 currentBUID; @@ -1184,7 +1184,7 @@ * @param[in] sMainData* pDat = our global state * --------------------------------------------------------------------------------------- */ -void ncInit(sMainData *pDat) +static void ncInit(sMainData *pDat) { u8 node, link; u8 compatLink; @@ -1228,7 +1228,7 @@ * @param[in,out] sMainData* pDat = our global state * --------------------------------------------------------------------------------------- */ -void regangLinks(sMainData *pDat) +static void regangLinks(sMainData *pDat) { #ifndef HT_BUILD_NC_ONLY u8 i, j; @@ -1317,7 +1317,7 @@ * @param[in,out] sMainData* pDat = our global state, port list data * --------------------------------------------------------------------------------------- */ -void selectOptimalWidthAndFrequency(sMainData *pDat) +static void selectOptimalWidthAndFrequency(sMainData *pDat) { u8 i, j; u32 temp; @@ -1452,7 +1452,7 @@ * @param[in,out] sMainData* pDat = our global state, link state and port list * --------------------------------------------------------------------------------------- */ -void hammerSublinkFixup(sMainData *pDat) +static void hammerSublinkFixup(sMainData *pDat) { #ifndef HT_BUILD_NC_ONLY u8 i, j, k; @@ -1589,7 +1589,7 @@ * @param[in] sMainData* pDat = our global state * --------------------------------------------------------------------------------------- */ -void linkOptimization(sMainData *pDat) +static void linkOptimization(sMainData *pDat) { pDat->nb->gatherLinkData(pDat, pDat->nb); regangLinks(pDat); @@ -1611,7 +1611,7 @@ * @param[in] sMainData* pDat = our global state, port list data * --------------------------------------------------------------------------------------- */ -void trafficDistribution(sMainData *pDat) +static void trafficDistribution(sMainData *pDat) { #ifndef HT_BUILD_NC_ONLY u32 links01, links10; @@ -1654,7 +1654,7 @@ * @param[in] sMainData* pDat = our global state, port list data * --------------------------------------------------------------------------------------- */ -void tuning(sMainData *pDat) +static void tuning(sMainData *pDat) { u8 i; @@ -1692,7 +1692,7 @@ * @param[out] result BOOL = true if check is ok, false if it failed * --------------------------------------------------------------------------------------- */ -BOOL isSanityCheckOk(void) +static BOOL isSanityCheckOk(void) { uint64 qValue; Modified: trunk/src/northbridge/amd/amdht/ht_wrapper.c ============================================================================== --- trunk/src/northbridge/amd/amdht/ht_wrapper.c Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/northbridge/amd/amdht/ht_wrapper.c Thu Apr 15 07:19:29 2010 (r5440) @@ -80,7 +80,7 @@ /** * void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) */ -void AMD_CB_EventNotify (u8 evtClass, u16 event, u8 *pEventData0) +static void AMD_CB_EventNotify (u8 evtClass, u16 event, const u8 *pEventData0) { u8 i; @@ -114,9 +114,9 @@ * @param[out] BOOL result = true to use a manual list * false to initialize the link automatically */ -BOOL AMD_CB_ManualBUIDSwapList (u8 node, u16 link, u8 **List) +static BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, u8 **List) { - static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; + static u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; /* If the BUID was adjusted in early_ht we need to do the manual override */ if ((CONFIG_HT_CHAIN_UNITID_BASE != 0) && (CONFIG_HT_CHAIN_END_UNITID_BASE != 0)) { printk(BIOS_DEBUG, "AMD_CB_ManualBUIDSwapList()\n"); @@ -148,7 +148,7 @@ * AMD HT init coreboot wrapper * */ -void amd_ht_init(struct sys_info *sysinfo) +static void amd_ht_init(struct sys_info *sysinfo) { AMD_HTBLOCK ht_wrapper = { Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct_d.c Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/northbridge/amd/amdmct/mct/mct_d.c Thu Apr 15 07:19:29 2010 (r5440) @@ -177,7 +177,7 @@ static const u8 Table_Comp_Fall_Slew_20x[] = {7, 5, 3, 2, 0xFF}; static const u8 Table_Comp_Fall_Slew_15x[] = {7, 7, 5, 3, 0xFF}; -void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, +static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { /* @@ -3565,7 +3565,7 @@ u8 Node; u32 i; struct DCTStatStruc *pDCTstat; - u16 start, stop; + u32 start, stop; u8 *p; u16 host_serv1, host_serv2; @@ -3582,12 +3582,12 @@ p = (u8 *) pDCTstat; start = 0; - stop = ((u16) &((struct DCTStatStruc *)0)->CH_MaxRdLat[2]); + stop = (u32)(&((struct DCTStatStruc *)0)->CH_MaxRdLat[2]); for (i = start; i < stop ; i++) { p[i] = 0; } - start = ((u16) &((struct DCTStatStruc *)0)->CH_D_BC_RCVRDLY[2][4]); + start = (u32)(&((struct DCTStatStruc *)0)->CH_D_BC_RCVRDLY[2][4]); stop = sizeof(struct DCTStatStruc); for (i = start; i < stop; i++) { p[i] = 0; @@ -3617,7 +3617,7 @@ } -void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat, +static void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 *dqs_pos) { // FIXME: Skip for Ax Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d_gcc.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct_d_gcc.h Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/northbridge/amd/amdmct/mct/mct_d_gcc.h Thu Apr 15 07:19:29 2010 (r5440) @@ -150,7 +150,7 @@ } -u32 read32_fs(u32 addr_lo) +static u32 read32_fs(u32 addr_lo) { u32 value; __asm__ volatile ( @@ -162,7 +162,7 @@ } -u8 read8_fs(u32 addr_lo) +static u8 read8_fs(u32 addr_lo) { u8 byte; __asm__ volatile ( @@ -312,7 +312,7 @@ } -void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr) +static void WriteMaxRdLat1CLTestPattern_D(u32 buf, u32 addr) { SetUpperFSbase(addr); @@ -351,7 +351,7 @@ } -u32 stream_to_int(u8 *p) +static u32 stream_to_int(u8 const *p) { int i; u32 val; @@ -369,19 +369,19 @@ } -void oemSet_NB32(u32 addr, u32 val, u8 *valid) +static void oemSet_NB32(u32 addr, u32 val, u8 *valid) { } -u32 oemGet_NB32(u32 addr, u8 *valid) +static u32 oemGet_NB32(u32 addr, u8 *valid) { *valid = 0; return 0xffffffff; } -u8 oemNodePresent_D(u8 Node, u8 *ret) +static u8 oemNodePresent_D(u8 Node, u8 *ret) { *ret = 0; return 0; Modified: trunk/src/northbridge/amd/amdmct/mct/mct_fd.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct_fd.c Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/northbridge/amd/amdmct/mct/mct_fd.c Thu Apr 15 07:19:29 2010 (r5440) @@ -19,7 +19,7 @@ -u8 amd_FD_support(void) +static u8 amd_FD_support(void) { return 1; } Modified: trunk/src/northbridge/amd/amdmct/mct/mctardk4.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctardk4.c Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/northbridge/amd/amdmct/mct/mctardk4.c Thu Apr 15 07:19:29 2010 (r5440) @@ -104,7 +104,7 @@ u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, u8 *CMDmode) { - u8 *p; + u8 const *p; *AddrTmgCTL = 0; *ODC_CTL = 0; Modified: trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Thu Apr 15 01:58:07 2010 (r5439) +++ trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Thu Apr 15 07:19:29 2010 (r5440) @@ -19,7 +19,7 @@ /* Call-backs */ #include <delay.h> -u16 mctGet_NVbits(u8 index) +static u16 mctGet_NVbits(u8 index) { u16 val = 0; @@ -223,106 +223,106 @@ } -void mctHookAfterDIMMpre(void) +static void mctHookAfterDIMMpre(void) { } -void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) +static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat) { pDCTstat->PresetmaxFreq = 400; } -void mctAdjustAutoCycTmg(void) +static void mctAdjustAutoCycTmg(void) { } -void mctAdjustAutoCycTmg_D(void) +static void mctAdjustAutoCycTmg_D(void) { } -void mctHookAfterAutoCycTmg(void) +static void mctHookAfterAutoCycTmg(void) { } -void mctGetCS_ExcludeMap(void) +static void mctGetCS_ExcludeMap(void) { } -void mctHookAfterAutoCfg(void) +static void mctHookAfterAutoCfg(void) { } -void mctHookAfterPSCfg(void) +static void mctHookAfterPSCfg(void) { } -void mctHookAfterHTMap(void) +static void mctHookAfterHTMap(void) { } -void mctHookAfterCPU(void) +static void mctHookAfterCPU(void) { } -void mctSaveDQSSigTmg_D(void) +static void mctSaveDQSSigTmg_D(void) { } -void mctGetDQSSigTmg_D(void) +static void mctGetDQSSigTmg_D(void) { } -void mctHookBeforeECC(void) +static void mctHookBeforeECC(void) { } -void mctHookAfterECC(void) +static void mctHookAfterECC(void) { } -void mctInitMemGPIOs_A(void) +static void mctInitMemGPIOs_A(void) { } -void mctInitMemGPIOs_A_D(void) +static void mctInitMemGPIOs_A_D(void) { } -void mctNodeIDDebugPort_D(void) +static void mctNodeIDDebugPort_D(void) { } -void mctWarmReset(void) +static void mctWarmReset(void) { } -void mctWarmReset_D(void) +static void mctWarmReset_D(void) { } -void mctHookBeforeDramInit(void) +static void mctHookBeforeDramInit(void) { } -void mctHookAfterDramInit(void) +static void mctHookAfterDramInit(void) { } @@ -330,7 +330,7 @@ /* Erratum 350 */ -void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) +static void vErrata350(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { u8 u8Channel; u8 u8Receiver; @@ -392,23 +392,23 @@ } -void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) +static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { if (pDCTstatA->LogicalCPUID & (AMD_RB_C2 | AMD_DA_C2)) { vErrata350(pMCTstat, pDCTstatA); } } -void mctHookAfterAnyTraining(void) +static void mctHookAfterAnyTraining(void) { } -u32 mctGetLogicalCPUID_D(u8 node) +static u32 mctGetLogicalCPUID_D(u8 node) { return mctGetLogicalCPUID(node); } -u8 mctSetNodeBoundary_D(void) +static u8 mctSetNodeBoundary_D(void) { return 0; }

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Re: [coreboot] Jetway PA78VM5-H support?
by Qing Pei Wang 15 Apr '10

15 Apr '10

that would be very good, if you can mail me the board. But i would like to try order one first. On Wed, Apr 14, 2010 at 9:06 AM, Scott Olsen <olesen(a)gmail.com> wrote: > Thank you very much. I have an extra board that I could mail to you if > that would help? > > > Scott > > > > On Tue, Apr 13, 2010 at 10:39 AM, Qing Pei Wang <wangqingpei(a)gmail.com>wrote: > >> hi, >> the only AMD 780 mainboard which coreboot support is mahogany. But >> there will be pretty much more, since i am trying to do several 780 >> mainboard >> porting. i think it's pretty find that we can port coreboot to this >> mainboard. I would like to add this mainboard into my GSOC mainboard list. >> I will try to order this mainboard if it can be bought in China. >> >> On Tue, Apr 13, 2010 at 7:23 AM, Scott Olsen <olesen(a)gmail.com> wrote: >> >>> >>> Hello, I noticed that AMD RS780/SB700 support has recently gotten initial >>> support. >>> >>> I was wondering if the Jetway PA78VM5-H board is suitable for support? >>> I've attached the lspci/superiotool/flashrom outputs. >>> >>> >>> Thanks! >>> >>> Scott >>> >>> >>> -- >>> >>> JetWay JPA78VM5-H-LF AM2+/AM2 AMD 780V HDMI Micro ATX AMD Motherboard - >>> Retail<http://www.newegg.com/Product/Product.aspx?Item=N82E16813153138&cm_re=jetwa…> >>> Model Brand JetWay Model JPA78VM5-H-LF Supported CPU CPU Socket Type >>> AM2+/AM2 CPU Type Phenom / Athlon 64 X2 / Athlon 64 / Sempron FSB 2600MHz >>> Hyper Transport (5200 MT/s) Chipsets North Bridge AMD 780V South >>> Bridge AMD SB700 >>> >>> >>> -- >>> >>> coreboot mailing list: coreboot(a)coreboot.org >>> http://www.coreboot.org/mailman/listinfo/coreboot >>> >> >> >> >> -- >> Wang Qing Pei >> MSN:wangqingpei@hotmail.com <MSN%3Awangqingpei(a)hotmail.com> >> Gmail:wangqingpei@gmail.com <Gmail%3Awangqingpei(a)gmail.com> >> Phone:86+13426369984 >> > > -- Wang Qing Pei MSN:wangqingpei@hotmail.com <MSN%3Awangqingpei(a)hotmail.com> Gmail:wangqingpei@gmail.com <Gmail%3Awangqingpei(a)gmail.com> Phone:86+13426369984

1 0

[commit] r5438 - trunk/src/superio/fintek/f71805f
by repository service 14 Apr '10

14 Apr '10

Author: stepan Date: Wed Apr 14 23:47:24 2010 New Revision: 5438 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5438 Log: fix COM2 resource bug in fintek f71805f driver. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/superio/fintek/f71805f/superio.c Modified: trunk/src/superio/fintek/f71805f/superio.c ============================================================================== --- trunk/src/superio/fintek/f71805f/superio.c Wed Apr 14 22:47:45 2010 (r5437) +++ trunk/src/superio/fintek/f71805f/superio.c Wed Apr 14 23:47:24 2010 (r5438) @@ -42,7 +42,7 @@ static void f71805f_init(device_t dev) { struct superio_fintek_f71805f_config *conf = dev->chip_info; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) return; @@ -54,7 +54,7 @@ init_uart8250(res0->base, &conf->com1); break; case F71805F_SP2: - res1 = find_resource(dev, PNP_IDX_IO0); + res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com2); break; }

1 0

[PATCH] warning days - m57sli/mcp55
by Ward Vandewege 14 Apr '10

14 Apr '10

If there are better ways to kill the warnings, please let me know! Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior Systems Administrator

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coreboot April 2010