coreboot April 2010

coreboot@coreboot.org

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402 discussions

[commit] r5428 - trunk/util/sconfig
by repository service 14 Apr '10

14 Apr '10

Author: oxygene Date: Wed Apr 14 16:41:30 2010 New Revision: 5428 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5428 Log: sconfig should return success when it's successful Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/util/sconfig/sconfig.tab.c_shipped trunk/util/sconfig/sconfig.y Modified: trunk/util/sconfig/sconfig.tab.c_shipped ============================================================================== --- trunk/util/sconfig/sconfig.tab.c_shipped Wed Apr 14 16:35:40 2010 (r5427) +++ trunk/util/sconfig/sconfig.tab.c_shipped Wed Apr 14 16:41:30 2010 (r5428) @@ -2057,5 +2057,6 @@ walk_device_tree(staticc, &root, pass1, NULL); fclose(staticc); + return 0; } Modified: trunk/util/sconfig/sconfig.y ============================================================================== --- trunk/util/sconfig/sconfig.y Wed Apr 14 16:35:40 2010 (r5427) +++ trunk/util/sconfig/sconfig.y Wed Apr 14 16:41:30 2010 (r5428) @@ -497,4 +497,5 @@ walk_device_tree(staticc, &root, pass1, NULL); fclose(staticc); + return 0; }

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[commit] r5427 - trunk/util/xcompile
by repository service 14 Apr '10

14 Apr '10

Author: oxygene Date: Wed Apr 14 16:35:40 2010 New Revision: 5427 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5427 Log: Rename variable to not confuse gcc on mingw Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/util/xcompile/xcompile Modified: trunk/util/xcompile/xcompile ============================================================================== --- trunk/util/xcompile/xcompile Wed Apr 14 13:40:34 2010 (r5426) +++ trunk/util/xcompile/xcompile Wed Apr 14 16:35:40 2010 (r5427) @@ -35,8 +35,8 @@ done GCCPREFIX=invalid -TMP=`mktemp /tmp/temp.XXXX 2>/dev/null || echo /tmp/temp.78gOIUGz` -touch $TMP +TMPFILE=`mktemp /tmp/temp.XXXX 2>/dev/null || echo /tmp/temp.78gOIUGz` +touch $TMPFILE # This should be a loop over all supported architectures TARCH=i386 @@ -45,9 +45,9 @@ if ! which ${gccprefixes}as 2>/dev/null >/dev/null; then continue fi - rm -f ${TMP}.o - if ${gccprefixes}as -o ${TMP}.o ${TMP}; then - TYPE=`${gccprefixes}objdump -p ${TMP}.o` + rm -f ${TMPFILE}.o + if ${gccprefixes}as -o ${TMPFILE}.o ${TMPFILE}; then + TYPE=`${gccprefixes}objdump -p ${TMPFILE}.o` if [ ${TYPE##* } == "elf${TWIDTH}-${TARCH}" ]; then GCCPREFIX=$gccprefixes ASFLAGS= @@ -56,8 +56,8 @@ break fi fi - if ${gccprefixes}as --32 -o ${TMP}.o ${TMP}; then - TYPE=`${gccprefixes}objdump -p ${TMP}.o` + if ${gccprefixes}as --32 -o ${TMPFILE}.o ${TMPFILE}; then + TYPE=`${gccprefixes}objdump -p ${TMPFILE}.o` if [ ${TYPE##* } == "elf${TWIDTH}-${TARCH}" ]; then GCCPREFIX=$gccprefixes ASFLAGS=--32 @@ -67,7 +67,7 @@ fi fi done -rm -f $TMP ${TMP}.o +rm -f $TMPFILE ${TMPFILE}.o if [ "$GCCPREFIX" = "invalid" ]; then echo '$(error no suitable gcc found)'

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Re: [coreboot] [commit] r5426 - in trunk/src: cpu/amd/mtrr cpu/x86/mtrr lib mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/serengeti_cheetah_fam10 ...
by Myles Watson 14 Apr '10

14 Apr '10

On Wed, Apr 14, 2010 at 6:50 AM, Stefan Reinauer <stepan(a)coresystems.de>wrote: > On 4/14/10 2:36 PM, Myles Watson wrote: > > Modified: trunk/src/lib/debug.c >> >> ============================================================================== >> --- trunk/src/lib/debug.c Wed Apr 14 12:12:23 2010 (r5425) >> +++ trunk/src/lib/debug.c Wed Apr 14 13:40:34 2010 (r5426) >> @@ -33,7 +33,7 @@ >> { >> device_t dev; >> for (dev = PCI_DEV(0, 0, 0); >> - dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) { >> + dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) { >> > > It looks like this slipped in. I thought it hangs some boards to probe > PCI busses that aren't there. > > Hm,... do you happen to know which ones? > > > http://www.coreboot.org/pipermail/coreboot/2009-October/053330.html I think this is what I was remembering, so it may not be relevant. There are about 15 places where this function is defined. Thanks, Myles

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[commit] r5426 - in trunk/src: cpu/amd/mtrr cpu/x86/mtrr lib mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/serengeti_cheetah_fam10 ...
by repository service 14 Apr '10

14 Apr '10

Author: stepan Date: Wed Apr 14 13:40:34 2010 New Revision: 5426 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5426 Log: drop quite a lot of dead code that did nothing but produce warnings and make the rest of the code unreadable. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Deleted: trunk/src/cpu/amd/mtrr/amd_earlymtrr.c Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c trunk/src/lib/debug.c trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/pistachio/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/arima/hdama/romstage.c trunk/src/mainboard/asrock/939a785gmh/romstage.c trunk/src/mainboard/asus/a8n_e/romstage.c trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/asus/m2v-mx_se/romstage.c trunk/src/mainboard/broadcom/blast/romstage.c trunk/src/mainboard/dell/s1850/romstage.c trunk/src/mainboard/digitallogic/msm586seg/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/ibm/e325/romstage.c trunk/src/mainboard/ibm/e326/romstage.c trunk/src/mainboard/intel/eagleheights/romstage.c trunk/src/mainboard/intel/jarrell/romstage.c trunk/src/mainboard/intel/mtarvon/romstage.c trunk/src/mainboard/intel/truxton/romstage.c trunk/src/mainboard/intel/xe7501devkit/reset.c trunk/src/mainboard/intel/xe7501devkit/romstage.c trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/msi/ms7135/irq_tables.c trunk/src/mainboard/msi/ms7135/romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/newisys/khepri/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/sunw/ultra40/romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/supermicro/x6dai_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/romstage.c trunk/src/mainboard/tyan/s2735/romstage.c trunk/src/mainboard/tyan/s2850/romstage.c trunk/src/mainboard/tyan/s2875/romstage.c trunk/src/mainboard/tyan/s2880/romstage.c trunk/src/mainboard/tyan/s2881/romstage.c trunk/src/mainboard/tyan/s2882/romstage.c trunk/src/mainboard/tyan/s2885/romstage.c trunk/src/mainboard/tyan/s2891/romstage.c trunk/src/mainboard/tyan/s2892/romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/mainboard/tyan/s4880/romstage.c trunk/src/mainboard/tyan/s4882/romstage.c trunk/src/mainboard/via/epia-cn/romstage.c trunk/src/mainboard/via/epia-m/romstage.c trunk/src/mainboard/via/epia-n/romstage.c trunk/src/northbridge/intel/e7501/raminit.c trunk/src/northbridge/intel/i3100/raminit.c trunk/src/northbridge/via/vt8623/northbridge.c Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c ============================================================================== --- trunk/src/cpu/x86/mtrr/earlymtrr.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/cpu/x86/mtrr/earlymtrr.c Wed Apr 14 13:40:34 2010 (r5426) @@ -2,6 +2,7 @@ #define EARLYMTRR_C #include <cpu/x86/cache.h> #include <cpu/x86/mtrr.h> +#include <cpu/amd/mtrr.h> #include <cpu/x86/msr.h> #if 0 Modified: trunk/src/lib/debug.c ============================================================================== --- trunk/src/lib/debug.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/lib/debug.c Wed Apr 14 13:40:34 2010 (r5426) @@ -33,7 +33,7 @@ { device_t dev; for (dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) { + dev <= PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) { u32 id; id = pci_read_config32(dev, PCI_VENDOR_ID); if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -54,7 +54,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/amd/mahogany/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -54,7 +54,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8718f/it8718f_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -71,14 +71,6 @@ #include "southbridge/amd/sb700/sb700_early_setup.c" #include "northbridge/amd/amdfam10/debug.c" -static void memreset_setup(void) -{ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - static void activate_spd_rom(const struct mem_controller *ctrl) { } @@ -245,9 +237,7 @@ /* It's the time to set ctrl in sysinfo now; */ printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); - post_code(0x3D); - memreset_setup(); post_code(0x40); // die("Die Before MCT init."); Modified: trunk/src/mainboard/amd/pistachio/romstage.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/amd/pistachio/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -48,7 +48,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -57,7 +57,7 @@ #include "southbridge/amd/sb600/sb600_early_setup.c" #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ -/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ +/* CAN'T BE REMOVED! memory bus reset hook for some broken amd k8 boards. */ static void memreset(int controllers, const struct mem_controller *ctrl) { } Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -68,7 +68,7 @@ #include "northbridge/amd/amdfam10/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -81,10 +81,6 @@ outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); } -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - static void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 Modified: trunk/src/mainboard/arima/hdama/romstage.c ============================================================================== --- trunk/src/mainboard/arima/hdama/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/arima/hdama/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -23,7 +23,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/nsc/pc87360/pc87360_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -55,7 +55,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/asus/a8n_e/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/asus/a8n_e/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -57,7 +57,7 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/coherent_ht.c" Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -58,7 +58,7 @@ #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "northbridge/amd/amdk8/debug.c" /* After vt8237r_early_smbus.c! */ -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -63,7 +63,7 @@ #include "northbridge/amd/amdk8/early_ht.c" #include "superio/ite/it8712f/it8712f_early_serial.c" #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/broadcom/blast/romstage.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/broadcom/blast/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -29,7 +29,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/nsc/pc87417/pc87417_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/dell/s1850/romstage.c ============================================================================== --- trunk/src/mainboard/dell/s1850/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/dell/s1850/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -41,10 +41,6 @@ #define RECVENA_CONFIG 0x0808090a #define RECVENB_CONFIG 0x0808090a -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -339,7 +335,6 @@ disable_watchdogs(); // dump_ipmi_registers(); mainboard_set_e7520_leds(); -// memreset_setup(); sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 Modified: trunk/src/mainboard/digitallogic/msm586seg/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/digitallogic/msm586seg/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -44,19 +44,6 @@ int i; }; -static void memreset_setup(void) -{ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} - static inline int spd_read_byte(unsigned device, unsigned address) { // return smbus_read_byte(device, address); Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -78,7 +78,7 @@ #include "northbridge/amd/amdk8/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -75,7 +75,7 @@ #include "northbridge/amd/amdk8/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -79,7 +79,7 @@ #include "northbridge/amd/amdk8/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -88,10 +88,6 @@ #include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c" -static void memreset_setup(void) -{ -} - static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -185,36 +181,34 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - //first node + // first node DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + + // second node DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, -#endif - }; struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset; - unsigned bsp_apicid = 0; + int needs_reset; + unsigned bsp_apicid = 0; - if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ - /* Allow the HT devices to be found */ - - enumerate_ht_chain(); - bcm5785_enable_rom(); - bcm5785_enable_lpc(); - //enable RTC + if (!cpu_init_detectedx && boot_cpu()) { + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + + enumerate_ht_chain(); + bcm5785_enable_rom(); + bcm5785_enable_lpc(); + //enable RTC pc87417_enable_dev(RTC_DEV); - } + } - if (bist == 0) { - bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - } + if (bist == 0) { + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + } pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); @@ -284,10 +278,9 @@ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); - memreset_setup(); //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synconize FID/VID + // init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); Modified: trunk/src/mainboard/ibm/e325/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e325/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/ibm/e325/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -25,7 +25,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/nsc/pc87366/pc87366_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/ibm/e326/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e326/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/ibm/e326/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -25,7 +25,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/nsc/pc87366/pc87366_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/intel/eagleheights/romstage.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/intel/eagleheights/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -102,10 +102,6 @@ #define RCBA_FD 0x3418 /* 32 bit */ #define RCBA_PRC 0x341C /* 32 bit */ -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} static inline int spd_read_byte(u16 device, u8 address) { return smbus_read_byte(device, address); @@ -119,8 +115,8 @@ #include "northbridge/intel/i3100/reset_test.c" #include "debug.c" -void early_config(void) { - device_t dev; +static void early_config(void) +{ u32 gcs, rpc, fd; /* Enable RCBA */ Modified: trunk/src/mainboard/intel/jarrell/romstage.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/intel/jarrell/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -38,10 +38,6 @@ #define RECVENB_CONFIG 0x000a090a #define DIMM_MAP_LOGICAL 0x0124 -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); Modified: trunk/src/mainboard/intel/mtarvon/romstage.c ============================================================================== --- trunk/src/mainboard/intel/mtarvon/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/intel/mtarvon/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -46,10 +46,6 @@ #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} static inline int spd_read_byte(u16 device, u8 address) { return smbus_read_byte(device, address); Modified: trunk/src/mainboard/intel/truxton/romstage.c ============================================================================== --- trunk/src/mainboard/intel/truxton/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/intel/truxton/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -46,10 +46,6 @@ #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0) -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} static inline int spd_read_byte(u16 device, u8 address) { return smbus_read_byte(device, address); Modified: trunk/src/mainboard/intel/xe7501devkit/reset.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/reset.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/intel/xe7501devkit/reset.c Wed Apr 14 13:40:34 2010 (r5426) @@ -1,3 +1,5 @@ +#include <reset.h> + void i82801cx_hard_reset(void); void hard_reset(void) Modified: trunk/src/mainboard/intel/xe7501devkit/romstage.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/intel/xe7501devkit/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -27,11 +27,6 @@ outb(0x0e, 0x0cf9); } -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -56,31 +51,28 @@ if (bist == 0) { // Skip this if there was a built in self test failure - early_mtrr_init(); - enable_lapic(); - } + enable_lapic(); + } // Get the serial port running and print a welcome banner - lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - uart_init(); - console_init(); + lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); + console_init(); - // Halt if there was a built in self test failure + // Halt if there was a built in self test failure report_bist_failure(bist); -// print_pci_devices(); + // print_pci_devices(); // If this is a warm boot, some initialization can be skipped if (!bios_reset_detected()) { enable_smbus(); -// dump_spd_registers(&memctrl[0]); -// dump_smbus_registers(); - -// memreset_setup(); No-op for this chipset + // dump_spd_registers(&memctrl[0]); + // dump_smbus_registers(); sdram_initialize(ARRAY_SIZE(memctrl), memctrl); } Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -44,7 +44,7 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -126,20 +126,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - //first node + // first node DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + + // second node DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, -#endif - }; - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset; int i; + int needs_reset; unsigned bsp_apicid = 0; if (!cpu_init_detectedx && boot_cpu()) { Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -44,7 +44,7 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -126,20 +126,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - //first node + // first node DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + + // second node DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, -#endif - }; - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset; int i; + int needs_reset; unsigned bsp_apicid = 0; if (!cpu_init_detectedx && boot_cpu()) { Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -44,7 +44,7 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -126,20 +126,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - //first node + // first node DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node + + // second node DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, -#endif - }; - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset; int i; + int needs_reset; unsigned bsp_apicid = 0; if (!cpu_init_detectedx && boot_cpu()) { Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/kontron/kt690/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -56,7 +56,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627dhg/w83627dhg_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/msi/ms7135/irq_tables.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/irq_tables.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/msi/ms7135/irq_tables.c Wed Apr 14 13:40:34 2010 (r5426) @@ -62,8 +62,6 @@ pirq_info->rfu = rfu; } -void pci_assign_irqs(unsigned, unsigned, const unsigned char *); - /** * Create the IRQ routing table. * Values are derived from getpir generated code. Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/msi/ms7135/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -59,7 +59,7 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/coherent_ht.c" @@ -98,7 +98,6 @@ static void sio_setup(void) { - unsigned value; uint32_t dword; uint8_t byte; Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/msi/ms7260/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -75,7 +75,7 @@ #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" /* Yes, on the MSI K9N Neo (MS-7260) the Super I/O is at 0x4e! */ Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/msi/ms9185/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -63,7 +63,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "superio/nsc/pc87417/pc87417_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/msi/ms9282/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -58,7 +58,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627ehg/w83627ehg_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -67,7 +67,7 @@ #include "northbridge/amd/amdfam10/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -76,14 +76,6 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" -static void memreset_setup(void) -{ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - static inline void activate_spd_rom(const struct mem_controller *ctrl) { /* nothing to do */ @@ -292,9 +284,7 @@ printk(BIOS_DEBUG, "enable_smbus()\n"); enable_smbus(); - post_code(0x3E); - memreset_setup(); post_code(0x40); printk(BIOS_DEBUG, "raminit_amdmct()\n"); Modified: trunk/src/mainboard/newisys/khepri/romstage.c ============================================================================== --- trunk/src/mainboard/newisys/khepri/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/newisys/khepri/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -31,7 +31,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -75,7 +75,7 @@ #include "northbridge/amd/amdk8/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/sunw/ultra40/romstage.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/sunw/ultra40/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -32,7 +32,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c" Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -69,7 +69,7 @@ #include "northbridge/amd/amdk8/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -72,7 +72,7 @@ #include "northbridge/amd/amdk8/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -65,7 +65,7 @@ #include "northbridge/amd/amdfam10/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -73,14 +73,6 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" -static void memreset_setup(void) -{ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - static inline void activate_spd_rom(const struct mem_controller *ctrl) { /* nothing to do */ @@ -281,10 +273,6 @@ //printk(BIOS_DEBUG, "enable_smbus()\n"); // enable_smbus(); /* enable in sio_setup */ -post_code(0x3E); - - memreset_setup(); - post_code(0x40); printk(BIOS_DEBUG, "raminit_amdmct()\n"); Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -66,7 +66,7 @@ #include "northbridge/amd/amdfam10/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -74,14 +74,6 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" -static void memreset_setup(void) -{ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_SWITCH1 0x70 @@ -326,10 +318,6 @@ //printk(BIOS_DEBUG, "enable_smbus()\n"); // enable_smbus(); /* enable in sio_setup */ -post_code(0x3E); - - memreset_setup(); - post_code(0x40); printk(BIOS_DEBUG, "raminit_amdmct()\n"); Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -40,10 +40,6 @@ #define RECVENA_CONFIG 0x0808090a #define RECVENB_CONFIG 0x0808090a -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -41,10 +41,6 @@ #define RECVENA_CONFIG 0x0808090a #define RECVENB_CONFIG 0x0808090a -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -121,7 +117,6 @@ disable_watchdogs(); // dump_ipmi_registers(); // mainboard_set_e7520_leds(); -// memreset_setup(); sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -41,10 +41,6 @@ #define RECVENA_CONFIG 0x0708090a #define RECVENB_CONFIG 0x0708090a -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -122,7 +118,6 @@ disable_watchdogs(); // dump_ipmi_registers(); // mainboard_set_e7520_leds(); -// memreset_setup(); sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -42,10 +42,6 @@ #define RECVENA_CONFIG 0x0808090a #define RECVENB_CONFIG 0x0808090a -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -122,7 +118,6 @@ disable_watchdogs(); // dump_ipmi_registers(); mainboard_set_e7520_leds(); -// memreset_setup(); sdram_initialize(ARRAY_SIZE(mch), mch); #if 1 dump_pci_devices(); Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -42,10 +42,6 @@ #define RECVENA_CONFIG 0x0808090a #define RECVENB_CONFIG 0x0808090a -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -122,7 +118,6 @@ disable_watchdogs(); // dump_ipmi_registers(); mainboard_set_e7520_leds(); -// memreset_setup(); sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -55,7 +55,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/ite/it8712f/it8712f_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -55,7 +55,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/ite/it8712f/it8712f_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/tyan/s2735/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/tyan/s2735/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -41,19 +41,6 @@ #endif } -static void memreset_setup(void) -{ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -76,12 +63,9 @@ unsigned cpu_reset = 0; - if (bist == 0) - { -// early_mtrr_init(); - enable_lapic(); - - } + if (bist == 0) { + enable_lapic(); + } // post_code(0x32); @@ -106,7 +90,6 @@ dump_smbus_registers(); #endif - memreset_setup(); sdram_initialize(1, memctrl); #if 0 Modified: trunk/src/mainboard/tyan/s2850/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2850/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/tyan/s2850/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -25,7 +25,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/tyan/s2875/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2875/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/tyan/s2875/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -25,7 +25,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/tyan/s2880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2880/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/tyan/s2880/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -25,7 +25,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/tyan/s2881/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2881/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/tyan/s2881/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -30,7 +30,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/tyan/s2882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2882/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/tyan/s2882/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -25,7 +25,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/tyan/s2885/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2885/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/tyan/s2885/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -25,7 +25,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/tyan/s2891/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/tyan/s2891/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -30,7 +30,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/tyan/s2892/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/tyan/s2892/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -31,7 +31,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/tyan/s2912/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -75,7 +75,7 @@ #include "northbridge/amd/amdk8/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -68,7 +68,7 @@ #include "northbridge/amd/amdfam10/debug.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdfam10/setup_resource_map.c" @@ -76,14 +76,6 @@ #include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c" -static void memreset_setup(void) -{ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - static inline void activate_spd_rom(const struct mem_controller *ctrl) { /* nothing to do */ @@ -287,9 +279,7 @@ printk(BIOS_DEBUG, "enable_smbus()\n"); enable_smbus(); - post_code(0x3E); - memreset_setup(); post_code(0x40); printk(BIOS_DEBUG, "raminit_amdmct()\n"); Modified: trunk/src/mainboard/tyan/s4880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/tyan/s4880/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -25,7 +25,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/tyan/s4882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4882/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/tyan/s4882/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -24,7 +24,7 @@ #include "northbridge/amd/amdk8/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" -#include "cpu/amd/mtrr/amd_earlymtrr.c" +#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" Modified: trunk/src/mainboard/via/epia-cn/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-cn/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/via/epia-cn/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -38,10 +38,6 @@ #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "southbridge/via/vt8235/vt8235_early_serial.c" -static void memreset_setup(void) -{ -} - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); Modified: trunk/src/mainboard/via/epia-m/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/via/epia-m/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -1,9 +1,6 @@ #include <stdint.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#if 0 -#include <cpu/x86/lapic.h> -#endif #include <arch/io.h> #include <device/pnp_def.h> #include <arch/romcc_io.h> @@ -22,10 +19,6 @@ #include "southbridge/via/vt8235/vt8235_early_smbus.c" #include "southbridge/via/vt8235/vt8235_early_serial.c" -static void memreset_setup(void) -{ -} - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); Modified: trunk/src/mainboard/via/epia-n/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-n/romstage.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/mainboard/via/epia-n/romstage.c Wed Apr 14 13:40:34 2010 (r5426) @@ -54,10 +54,6 @@ .channel0 = { 0x50 }, }; -static void memreset_setup(void) -{ -} - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); Modified: trunk/src/northbridge/intel/e7501/raminit.c ============================================================================== --- trunk/src/northbridge/intel/e7501/raminit.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/northbridge/intel/e7501/raminit.c Wed Apr 14 13:40:34 2010 (r5426) @@ -1919,14 +1919,11 @@ RAM_DEBUG_MESSAGE("Reading SPD data...\n"); - //activate_spd_rom(ctrl); Not necessary for this chipset - - dimm_mask = spd_get_supported_dimms(ctrl); + dimm_mask = spd_get_supported_dimms(ctrl); if (dimm_mask == 0) { print_debug("No usable memory for this controller\n"); - } else { - + } else { enable_e7501_clocks(dimm_mask); RAM_DEBUG_MESSAGE("setting based on SPD data...\n"); @@ -1967,7 +1964,7 @@ DUMPNORTH(); ram_set_rcomp_regs(); - ram_set_d0f0_regs(); + ram_set_d0f0_regs(); } /*^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^*/ Modified: trunk/src/northbridge/intel/i3100/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i3100/raminit.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/northbridge/intel/i3100/raminit.c Wed Apr 14 13:40:34 2010 (r5426) @@ -88,7 +88,7 @@ { /* Calculate the log base 2 size of a DIMM in bits */ struct dimm_size sz; - int value, low, ddr2; + int value, low; sz.side1 = 0; sz.side2 = 0; @@ -594,8 +594,6 @@ goto out; - val_err: - die("Bad SPD value\n"); /* If an hw_error occurs report that I have no memory */ hw_err: drc = 0; @@ -715,7 +713,6 @@ u32 dimm; u32 edge; int32_t data32; - u32 data32_dram; u32 dcal_data32_0; u32 dcal_data32_1; u32 dcal_data32_2; @@ -948,10 +945,6 @@ u32 data32; u32 mode_reg; u32 *iptr; - volatile u32 *iptrv; - msr_t msr; - u32 scratch; - u8 byte; u16 data16; static const struct { u32 clkgr[4]; Modified: trunk/src/northbridge/via/vt8623/northbridge.c ============================================================================== --- trunk/src/northbridge/via/vt8623/northbridge.c Wed Apr 14 12:12:23 2010 (r5425) +++ trunk/src/northbridge/via/vt8623/northbridge.c Wed Apr 14 13:40:34 2010 (r5426) @@ -60,7 +60,7 @@ } } -static void nullfunc(void) +static void nullfunc(device_t dev) { /* Nothing to do */ }

2 1

Newbie to coreboot with a 845G chipset
by A.Haq Abbad 14 Apr '10

14 Apr '10

Hi All Intel® 845G chipset Southbridge 82801 P4 2.4GHz >From Compaq Evo D310 DT (Custom Mobo, P4B266-VMX) Any recomemendations? Which payload to choose? I want to start with a basic one, will be using Linux mostly, but I do want to try XP and DOS perhaps. SeaBios seems good, but on the Wiki, it only mentions coreboot v3, and not 4! I hope it's a typo. I don't think I can use a Linux kernel as a payload, as the chip only has 512KB. How risky is it to render the PC useless? Note that the BIOS chip is soldered into the Mobo :\ and I doubt I'd be bothered to buy a new one and solder it. Time to complete the whole thing? If too long, I'll do it on the weekend. Thanks.

2 1

[commit] r5425 - in trunk/src: cpu/amd/model_lx drivers/ati/ragexl mainboard/bcom/winnetp680 mainboard/digitallogic/msm800sev mainboard/hp/dl145_g3 mainboard/kontron/kt690 mainboard/pcengines/alix1...
by repository service 14 Apr '10

14 Apr '10

Author: stepan Date: Wed Apr 14 12:12:23 2010 New Revision: 5425 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5425 Log: zero warnings days. Down to under 600 different warnings Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/amd/model_lx/vsmsetup.c trunk/src/drivers/ati/ragexl/xlinit.c trunk/src/mainboard/bcom/winnetp680/romstage.c trunk/src/mainboard/digitallogic/msm800sev/romstage.c trunk/src/mainboard/hp/dl145_g3/mptable.c trunk/src/mainboard/kontron/kt690/mainboard.c trunk/src/mainboard/pcengines/alix1c/romstage.c trunk/src/mainboard/technexion/tim8690/mainboard.c trunk/src/northbridge/amd/amdht/h3finit.c trunk/src/northbridge/amd/gx2/northbridge.c trunk/src/northbridge/via/vt8623/northbridge.c trunk/src/northbridge/via/vx800/dev_init.c trunk/src/northbridge/via/vx800/dram_init.c trunk/src/northbridge/via/vx800/dram_init.h trunk/src/northbridge/via/vx800/drdy_bl.c trunk/src/northbridge/via/vx800/freq_setting.c trunk/src/northbridge/via/vx800/raminit.c trunk/src/northbridge/via/vx800/rank_map.c trunk/src/northbridge/via/vx800/uma_ram_setting.c trunk/src/northbridge/via/vx800/vgabios.c trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c trunk/src/southbridge/amd/cs5536/cs5536_smbus2.h trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c trunk/src/southbridge/nvidia/mcp55/mcp55_fadt.c trunk/src/southbridge/via/vt8235/vt8235.c Modified: trunk/src/cpu/amd/model_lx/vsmsetup.c ============================================================================== --- trunk/src/cpu/amd/model_lx/vsmsetup.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/cpu/amd/model_lx/vsmsetup.c Wed Apr 14 12:12:23 2010 (r5425) @@ -268,10 +268,7 @@ void do_vsmbios(void) { - device_t dev; - unsigned long busdevfn; unsigned char *buf; - unsigned int size = SMM_SIZE * 1024; int i; printk(BIOS_ERR, "do_vsmbios\n"); Modified: trunk/src/drivers/ati/ragexl/xlinit.c ============================================================================== --- trunk/src/drivers/ati/ragexl/xlinit.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/drivers/ati/ragexl/xlinit.c Wed Apr 14 12:12:23 2010 (r5425) @@ -489,7 +489,10 @@ int j; u16 type; u8 rev; - const char *chipname = NULL, *xtal; + const char *chipname = NULL; +#if CONFIG_CONSOLE_BTEXT + const char *xtal; +#endif int pll, mclk, xclk; #if CONFIG_CONSOLE_BTEXT==1 Modified: trunk/src/mainboard/bcom/winnetp680/romstage.c ============================================================================== --- trunk/src/mainboard/bcom/winnetp680/romstage.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/mainboard/bcom/winnetp680/romstage.c Wed Apr 14 12:12:23 2010 (r5425) @@ -39,10 +39,6 @@ #include "superio/winbond/w83697hf/w83697hf_early_serial.c" #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) -static void memreset_setup(void) -{ -} - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -53,8 +49,6 @@ static void enable_mainboard_devices(void) { device_t dev; - u8 reg; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev == PCI_DEV_INVALID) die("Southbridge not found!!!\n"); @@ -89,9 +83,6 @@ void main(unsigned long bist) { - unsigned long x; - device_t dev; - /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm800sev/romstage.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c Wed Apr 14 12:12:23 2010 (r5425) @@ -51,7 +51,6 @@ msr.hi = 0x20000000; msr.lo = 0xfff00; wrmsr(MSR_GLIU1 + 0x20, msr); - } static void mb_gpio_init(void) @@ -61,7 +60,6 @@ void cache_as_ram_main(void) { - extern void RestartCAR(); post_code(0x01); static const struct mem_controller memctrl [] = { Modified: trunk/src/mainboard/hp/dl145_g3/mptable.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/mptable.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/mainboard/hp/dl145_g3/mptable.c Wed Apr 14 12:12:23 2010 (r5425) @@ -50,8 +50,6 @@ static const char productid[12] = "TREX "; struct mp_config_table *mc; - unsigned char bus_num; - int i; struct mb_sysconf_t *m; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -78,11 +76,13 @@ /*Bus: Bus ID Type*/ /* define bus and isa numbers */ -/* for(bus_num = 0; bus_num < m->bus_isa; bus_num++) { +#if 0 + unsigned char bus_num; + for(bus_num = 0; bus_num < m->bus_isa; bus_num++) { smp_write_bus(mc, bus_num, "PCI "); printk(BIOS_DEBUG, "writing bus %d as PCI...\n",bus_num); } - */ +#endif smp_write_bus(mc, 0, "PCI "); smp_write_bus(mc, 1, "PCI "); smp_write_bus(mc, 7, "PCI "); Modified: trunk/src/mainboard/kontron/kt690/mainboard.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/mainboard.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/mainboard/kontron/kt690/mainboard.c Wed Apr 14 12:12:23 2010 (r5425) @@ -57,7 +57,7 @@ * RRG4.2.3.1 GPM pins as Input * RRG4.2.3.2 GPM pins as Output ********************************************************/ -static void enable_onboard_nic() +static void enable_onboard_nic(void) { u8 byte; @@ -94,7 +94,7 @@ * IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to * get the cable type, 40 pin or 80 pin? ********************************************************/ -static void get_ide_dma66() +static void get_ide_dma66(void) { u8 byte; struct device *sm_dev; @@ -120,7 +120,7 @@ /* * set thermal config */ -static void set_thermal_config() +static void set_thermal_config(void) { u8 byte; u16 word; Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/romstage.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/mainboard/pcengines/alix1c/romstage.c Wed Apr 14 12:12:23 2010 (r5425) @@ -145,8 +145,6 @@ {.channel0 = {0x50}}, }; - extern void RestartCAR(); - post_code(0x01); SystemPreInit(); Modified: trunk/src/mainboard/technexion/tim8690/mainboard.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/mainboard.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/mainboard/technexion/tim8690/mainboard.c Wed Apr 14 12:12:23 2010 (r5425) @@ -54,7 +54,7 @@ * Both of their pin PERSTn pins are connected to GPIO 5 of the * SB600 southbridge. ****************************************************/ -static void enable_onboard_nic() +static void enable_onboard_nic(void) { u8 byte; @@ -80,7 +80,7 @@ /* set thermal config */ -static void set_thermal_config() +static void set_thermal_config(void) { u8 byte; u16 word; Modified: trunk/src/northbridge/amd/amdht/h3finit.c ============================================================================== --- trunk/src/northbridge/amd/amdht/h3finit.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/northbridge/amd/amdht/h3finit.c Wed Apr 14 12:12:23 2010 (r5425) @@ -1692,7 +1692,7 @@ * @param[out] result BOOL = true if check is ok, false if it failed * --------------------------------------------------------------------------------------- */ -BOOL isSanityCheckOk() +BOOL isSanityCheckOk(void) { uint64 qValue; Modified: trunk/src/northbridge/amd/gx2/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridge.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/northbridge/amd/gx2/northbridge.c Wed Apr 14 12:12:23 2010 (r5425) @@ -123,9 +123,9 @@ }; /* note that dev is NOT used -- yet */ -static void irq_init_steering(struct device *dev, uint16_t irq_map) { +static void irq_init_steering(struct device *dev, u16 irq_map) { /* Set up IRQ steering */ - uint32_t pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; + u32 pciAddr = 0x80000000 | (CHIPSET_DEV_NUM << 11) | 0x5C; printk(BIOS_DEBUG, "%s(%p [%08X], %04X)\n", __func__, dev, pciAddr, irq_map); @@ -298,17 +298,17 @@ /* this is a test -- we are not sure it will work -- but it ought to */ static void set_resources(struct device *dev) { +#if 0 struct resource *resource, *last; - unsigned link; - uint8_t line; -#if 0 last = &dev->resource[dev->resources]; for(resource = &dev->resource[0]; resource < last; resource++) { pci_set_resource(dev, resource); } #endif + unsigned link; + for(link = 0; link < dev->links; link++) { struct bus *bus; bus = &dev->link[link]; @@ -327,7 +327,7 @@ } /* zero the irq settings */ - line = pci_read_config8(dev, PCI_INTERRUPT_PIN); + u8 line = pci_read_config8(dev, PCI_INTERRUPT_PIN); if (line) { pci_write_config8(dev, PCI_INTERRUPT_LINE, 0); } @@ -383,10 +383,10 @@ } #if 0 -static uint32_t find_pci_tolm(struct bus *bus) +static u32 find_pci_tolm(struct bus *bus) { struct resource *min; - uint32_t tolm; + u32 tolm; min = 0; search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min); tolm = 0xffffffffUL; @@ -402,7 +402,7 @@ { #if 0 device_t mc_dev; - uint32_t pci_tolm; + u32 pci_tolm; pci_tolm = find_pci_tolm(&dev->link[0]); mc_dev = dev->link[0].children; Modified: trunk/src/northbridge/via/vt8623/northbridge.c ============================================================================== --- trunk/src/northbridge/via/vt8623/northbridge.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/northbridge/via/vt8623/northbridge.c Wed Apr 14 12:12:23 2010 (r5425) @@ -60,7 +60,10 @@ } } -static void nullfunc(){} +static void nullfunc(void) +{ + /* Nothing to do */ +} static struct device_operations northbridge_operations = { .read_resources = nullfunc, @@ -104,7 +107,7 @@ static void vga_init(device_t dev) { -// unsigned long fb; + //unsigned long fb; //msr_t clocks1,clocks2,instructions,setup; printk(BIOS_DEBUG, "VGA random fixup ...\n"); Modified: trunk/src/northbridge/via/vx800/dev_init.c ============================================================================== --- trunk/src/northbridge/via/vx800/dev_init.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/northbridge/via/vx800/dev_init.c Wed Apr 14 12:12:23 2010 (r5425) @@ -26,7 +26,7 @@ void InitDDR2CHB(DRAM_SYS_ATTR *DramAttr); void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr); -CB_STATUS VerifyChc(); +CB_STATUS VerifyChc(void); /*=================================================================== Function : DRAMRegInitValue() Modified: trunk/src/northbridge/via/vx800/dram_init.c ============================================================================== --- trunk/src/northbridge/via/vx800/dram_init.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/northbridge/via/vx800/dram_init.c Wed Apr 14 12:12:23 2010 (r5425) @@ -17,12 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -CB_STATUS DDR2_DRAM_INIT() +CB_STATUS DDR2_DRAM_INIT(void) { - CB_STATUS Status; u8 i; u32 RamSize; - BOOLEAN bTest; DRAM_SYS_ATTR DramAttr; PRINT_DEBUG_MEM("DRAM_INIT \r"); @@ -76,7 +74,7 @@ PRINT_DEBUG_MEM_HEX32(RamSize); PRINT_DEBUG_MEM("\r"); DumpRegisters(0, 3); - //bTest = DramBaseTest( M1, RamSize - M1 * 2,SPARE, FALSE); + //BOOLEAN bTest = DramBaseTest( M1, RamSize - M1 * 2,SPARE, FALSE); /* the memory can not correct work, this is because the user set the incorrect memory parameter from setup interface.so we must set the boot mode to recovery mode, let the system to reset and use the spd value to initialize the memory */ Modified: trunk/src/northbridge/via/vx800/dram_init.h ============================================================================== --- trunk/src/northbridge/via/vx800/dram_init.h Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/northbridge/via/vx800/dram_init.h Wed Apr 14 12:12:23 2010 (r5425) @@ -253,9 +253,9 @@ void DRAMRegFinalValue(DRAM_SYS_ATTR * DramAttr); /*set UMA*/ -void SetUMARam(); +void SetUMARam(void); CB_STATUS InstallMemory(DRAM_SYS_ATTR * DramAttr, u32 RamSize); -CB_STATUS DDR2_DRAM_INIT(); +CB_STATUS DDR2_DRAM_INIT(void); #endif Modified: trunk/src/northbridge/via/vx800/drdy_bl.c ============================================================================== --- trunk/src/northbridge/via/vx800/drdy_bl.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/northbridge/via/vx800/drdy_bl.c Wed Apr 14 12:12:23 2010 (r5425) @@ -407,9 +407,6 @@ u8 Data, CL, RDRPH; u8 CpuFreq, DramFreq; u8 ProgData[PT894_RDRDY_TBL_Width]; - u8 DelayMode; - u8 DrdyMode; - u8 Index; /* this function has 3 switchs, correspond to 3 level of Drdy setting. @@ -483,16 +480,19 @@ Data = pci_read_config8(MEMCTRL, 0x90); DramFreq = Data & 0x07; + u8 DelayMode; DelayMode = CL + RDRPH; // RDELAYMD = bit0 of (CAS Latency + RDRPH) DelayMode &= 0x01; //In 364, there is no 128 bit if (DelayMode == 1) { // DelayMode 1 + u8 Index; for (Index = 0; Index < PT894_RDRDY_TBL_Width; Index++) ProgData[Index] = PT894_64bit_DELAYMD1_RCONV0[CpuFreq][DramFreq] [Index]; } else { // DelayMode 0 + u8 Index; for (Index = 0; Index < PT894_RDRDY_TBL_Width; Index++) ProgData[Index] = PT894_64bit_DELAYMD0_RCONV0[CpuFreq][DramFreq] Modified: trunk/src/northbridge/via/vx800/freq_setting.c ============================================================================== --- trunk/src/northbridge/via/vx800/freq_setting.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/northbridge/via/vx800/freq_setting.c Wed Apr 14 12:12:23 2010 (r5425) @@ -120,7 +120,7 @@ void CalcCLAndFreq(DRAM_SYS_ATTR * DramAttr) { u8 AllDimmSupportedCL, Tmp; - u8 CLMask, tmpMask, IndexDelta; + u8 CLMask, tmpMask; u8 SckId, BitId, TmpId; u16 CycTime, TmpCycTime; Modified: trunk/src/northbridge/via/vx800/raminit.c ============================================================================== --- trunk/src/northbridge/via/vx800/raminit.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/northbridge/via/vx800/raminit.c Wed Apr 14 12:12:23 2010 (r5425) @@ -55,9 +55,8 @@ * Support one dimm with up to 2 ranks */ -static void ddr2_ram_setup() +static void ddr2_ram_setup(void) { - u8 Data; CB_STATUS Status; PRINT_DEBUG_MEM("In ddr2_ram_setup\r"); Modified: trunk/src/northbridge/via/vx800/rank_map.c ============================================================================== --- trunk/src/northbridge/via/vx800/rank_map.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/northbridge/via/vx800/rank_map.c Wed Apr 14 12:12:23 2010 (r5425) @@ -138,7 +138,6 @@ u32 Size; BOOLEAN HasThreeBitBA; u8 Data; - u32 Address; HasThreeBitBA = FALSE; for (Slot = 0; Slot < 2; Slot++) { Modified: trunk/src/northbridge/via/vx800/uma_ram_setting.c ============================================================================== --- trunk/src/northbridge/via/vx800/uma_ram_setting.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/northbridge/via/vx800/uma_ram_setting.c Wed Apr 14 12:12:23 2010 (r5425) @@ -333,6 +333,7 @@ ByteVal = (ByteVal & 0xE5) | 0x1A; outb(ByteVal, 0x03d5); +#if 0 u8 table3c43c5[0x70] = { 0x03, 0x01, 0x0F, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -395,9 +396,9 @@ 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, }; -#if 0 -//for(i=0;i<0xc0;i++) - for (i = 0; i < 0x40; i++) // + + //for(i=0;i<0xc0;i++) + for (i = 0; i < 0x40; i++) { outb(table3c0space[i], 0x03c0 + i); } @@ -410,6 +411,7 @@ outb(i, 0x03d4); outb(table3d43d5[i], 0x03d5); } + outb(0x92, 0x03d4); outb(0x80, 0x03d5); @@ -419,12 +421,12 @@ outb(0xe8, 0x03d4); outb(0x40, 0x03d5); #endif -//3d4 3d freq -//IO Port / Index: 3X5.3D -//Scratch Pad Register 4 -// outb(0x39,0x03c4);// - //outb(1 << SLD0F3Val ,0x03c5); +// 3d4 3d freq +// IO Port / Index: 3X5.3D +// Scratch Pad Register 4 +// outb(0x39,0x03c4); +// outb(1 << SLD0F3Val ,0x03c5); // #endif Modified: trunk/src/northbridge/via/vx800/vgabios.c ============================================================================== --- trunk/src/northbridge/via/vx800/vgabios.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/northbridge/via/vx800/vgabios.c Wed Apr 14 12:12:23 2010 (r5425) @@ -299,8 +299,6 @@ unsigned char *buf; unsigned int size = 64 * 1024; int i; - u16 tmp; - u8 tmp8; printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); @@ -646,15 +644,7 @@ unsigned long *pesp, unsigned long *pebx, unsigned long *pedx, unsigned long *pecx, unsigned long *peax, unsigned long *pflags) { - unsigned long edi = *pedi; - unsigned long esi = *pesi; - unsigned long ebp = *pebp; - unsigned long esp = *pesp; - unsigned long ebx = *pebx; - unsigned long edx = *pedx; - unsigned long ecx = *pecx; unsigned long eax = *peax; - unsigned long flags = *pflags; unsigned short func = (unsigned short)eax; int retval = 0; unsigned short devid, vendorid, devfn; Modified: trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c Wed Apr 14 12:12:23 2010 (r5425) @@ -23,11 +23,11 @@ /* forward MSR access to CS5535_GLINK_PORT_NUM to CS5535_DEV_NUM */ msr.hi = msr.lo = 0x00000000; - if (CS5535_GLINK_PORT_NUM <= 4) { - msr.lo = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 1) * 8); - } else { - msr.hi = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 5) * 8); - } +#if CS5535_GLINK_PORT_NUM <= 4 + msr.lo = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 1) * 8); +#else + msr.hi = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 5) * 8); +#endif wrmsr(0x5000201e, msr); } Modified: trunk/src/southbridge/amd/cs5536/cs5536_smbus2.h ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536_smbus2.h Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/southbridge/amd/cs5536/cs5536_smbus2.h Wed Apr 14 12:12:23 2010 (r5425) @@ -239,9 +239,9 @@ *data++ = val; if (count > 1) { - int ret = smbus_wait(smbus_io_base); + ret = smbus_wait(smbus_io_base); if (ret) - return ret; + return; } count--; Modified: trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c Wed Apr 14 12:12:23 2010 (r5425) @@ -66,8 +66,6 @@ static int smbus_write_block(unsigned device, unsigned length, unsigned cmd, unsigned data1, unsigned data2) { - unsigned char global_control_register; - unsigned char global_status_register; unsigned char byte; unsigned char stat; int i; Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Wed Apr 14 12:12:23 2010 (r5425) @@ -388,7 +388,7 @@ int mcp55_num = 0; unsigned busnx; unsigned devnx; - int ht_c_index,j; + int ht_c_index; /* FIXME: multi pci segment handling */ Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_fadt.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_fadt.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_fadt.c Wed Apr 14 12:12:23 2010 (r5425) @@ -51,8 +51,8 @@ printk(BIOS_INFO, "ACPI: pm_base: %u...\n", pm_base); - fadt->firmware_ctrl = facs; - fadt->dsdt = dsdt; + fadt->firmware_ctrl = (u32)facs; + fadt->dsdt = (u32)dsdt; fadt->preferred_pm_profile = 1; //check fadt->sci_int = 9; /* disable system management mode by setting to 0 */ @@ -108,9 +108,9 @@ fadt->reset_reg.addrh = 0x0; fadt->reset_value = 0; - fadt->x_firmware_ctl_l = facs; + fadt->x_firmware_ctl_l = (u32)facs; fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = dsdt; + fadt->x_dsdt_l = (u32)dsdt; fadt->x_dsdt_h = 0; fadt->x_pm1a_evt_blk.space_id = 1; Modified: trunk/src/southbridge/via/vt8235/vt8235.c ============================================================================== --- trunk/src/southbridge/via/vt8235/vt8235.c Wed Apr 14 11:04:31 2010 (r5424) +++ trunk/src/southbridge/via/vt8235/vt8235.c Wed Apr 14 12:12:23 2010 (r5425) @@ -41,7 +41,7 @@ } } -void set_led() +void set_led(void) { // set power led to steady now that lxbios has virtually done its job device_t dev;

1 0

[PATCH] epia-en first attempt
by Jasper Mackenzie 14 Apr '10

14 Apr '10

A first attempt at getting epia-en to work irq table will be total crap. Mostly (all) stolen from other epia's Signed-off-by: Jasper Aorangi <jasper.mackenzie_pleasespamemIlovefreegivawaysenlargementsetc_gmail.com>

1 0

Dualbios etc
by Vadim Girlin 14 Apr '10

14 Apr '10

OK, but I sent some disassembled logs - the bios is proprietary, isn't? Anyway all I want is to say that i don't want to violate any rules. Any info that I sent was supposed to help the developers. If some of my posts violates some rules - I'm sorry. So probably you should say on coreboot page that we shouldn't send any disassembled dumps if this could make a problem for you. I hope it's not the case. -- Best regards, Vadim Girlin

2 1

build service results for r5424
by coreboot information 14 Apr '10

14 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5424 to the coreboot repository. This caused the following changes: Change Log: fix digitallogic adl855pc compilation (and clean up the warnings while at it) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of digitallogic:adl855pc has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5424 - in trunk/src: mainboard/digitallogic/adl855pc northbridge/intel/i855
by repository service 14 Apr '10

14 Apr '10

Author: stepan Date: Wed Apr 14 11:04:31 2010 New Revision: 5424 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5424 Log: fix digitallogic adl855pc compilation (and clean up the warnings while at it) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c trunk/src/northbridge/intel/i855/debug.c trunk/src/northbridge/intel/i855/raminit.c trunk/src/northbridge/intel/i855/raminit.h Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/romstage.c Wed Apr 14 09:47:07 2010 (r5423) +++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c Wed Apr 14 11:04:31 2010 (r5424) @@ -3,12 +3,10 @@ #include <arch/io.h> #include <device/pnp_def.h> #include <arch/romcc_io.h> -#if 0 -#include <arch/smp/lapic.h> -#endif #include <arch/hlt.h> //#include "option_table.h" #include <stdlib.h> +#include "pc80/udelay_io.c" #include "pc80/mc146818rtc_early.c" #include "pc80/serial.c" #include "console/console.c" @@ -16,13 +14,6 @@ #include "southbridge/intel/i82801dx/i82801dx.h" #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" #include "northbridge/intel/i855/raminit.h" - -#if 0 -#include "cpu/p6/apic_timer.c" -#include "lib/delay.c" -#endif - -#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/intel/i855/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/mtrr/earlymtrr.c" @@ -30,24 +21,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) -static void hard_reset(void) -{ - outb(0x0e, 0x0cf9); -} - -static void memreset_setup(void) -{ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -57,10 +30,7 @@ #include "northbridge/intel/i855/reset_test.c" #include "lib/generic_sdram.c" - -#include "cpu/intel/model_6bx/cache_as_ram_disable.c" - -void real_main(unsigned long bist) +void main(unsigned long bist) { static const struct mem_controller memctrl[] = { { @@ -93,7 +63,6 @@ dump_spd_registers(&memctrl[0]); dump_smbus_registers(); #endif - memreset_setup(); sdram_initialize(ARRAY_SIZE(memctrl), memctrl); Modified: trunk/src/northbridge/intel/i855/debug.c ============================================================================== --- trunk/src/northbridge/intel/i855/debug.c Wed Apr 14 09:47:07 2010 (r5423) +++ trunk/src/northbridge/intel/i855/debug.c Wed Apr 14 11:04:31 2010 (r5424) @@ -18,24 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* - * generic K8 debug code, used by mainboard specific romstage.c - * - */ -#if 1 -/* -static void print_debug_pci_dev(unsigned dev) -{ - print_debug("PCI: "); - print_debug_hex8((dev >> 16) & 0xff); - print_debug_char(':'); - print_debug_hex8((dev >> 11) & 0x1f); - print_debug_char('.'); - print_debug_hex8((dev >> 8) & 7); -} -*/ - - static void print_debug_pci_dev(unsigned dev) { print_debug("PCI: "); @@ -46,7 +28,7 @@ print_debug_hex8((dev >> 12) & 0x07); } -static void print_pci_devices(void) +static inline void print_pci_devices(void) { device_t dev; for(dev = PCI_DEV(0, 0, 0); @@ -85,7 +67,7 @@ } } -static void dump_pci_devices(void) +static inline void dump_pci_devices(void) { device_t dev; for(dev = PCI_DEV(0, 0, 0); @@ -102,7 +84,7 @@ } } -static void dump_spd_registers(const struct mem_controller *ctrl) +static inline void dump_spd_registers(const struct mem_controller *ctrl) { int i; print_debug("\n"); @@ -134,37 +116,10 @@ } print_debug("\n"); } -#if 0 - device = ctrl->channel1[i]; - if (device) { - int j; - print_debug("dimm: "); - print_debug_hex8(i); - print_debug(".1: "); - print_debug_hex8(device); - for(j = 0; j < 256; j++) { - int status; - unsigned char byte; - if ((j & 0xf) == 0) { - print_debug("\n"); - print_debug_hex8(j); - print_debug(": "); - } - status = smbus_read_byte(device, j); - if (status < 0) { - print_debug("bad device\n"); - break; - } - byte = status & 0xff; - print_debug_hex8(byte); - print_debug_char(' '); - } - print_debug("\n"); - } -#endif } } -static void dump_smbus_registers(void) + +static inline void dump_smbus_registers(void) { int i; print_debug("\n"); @@ -194,4 +149,3 @@ print_debug("\n"); } } -#endif Modified: trunk/src/northbridge/intel/i855/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i855/raminit.c Wed Apr 14 09:47:07 2010 (r5423) +++ trunk/src/northbridge/intel/i855/raminit.c Wed Apr 14 11:04:31 2010 (r5424) @@ -19,6 +19,7 @@ */ #include <sdram_mode.h> +#include <delay.h> #define dumpnorth() dump_pci_device(PCI_DEV(0, 0, 1)) #define VG85X_MODE (SDRAM_BURST_4 | SDRAM_BURST_INTERLEAVED | SDRAM_CAS_2_5) @@ -85,20 +86,11 @@ pci_write_config32(ctrl->d0, 0xa0, dtc_reg); } -void udelay(int usecs) -{ - int i; - for(i = 0; i < usecs; i++) - outb(i & 0xff, 0x80); -} - #define delay() udelay(200) /* if ram still doesn't work do this function */ static void spd_set_undocumented_registers(const struct mem_controller *ctrl) { - uint16_t word; - /* 0:0.0 */ /* pci_write_config32(PCI_DEV(0, 0, 0), 0x10, 0xe0000008); Modified: trunk/src/northbridge/intel/i855/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i855/raminit.h Wed Apr 14 09:47:07 2010 (r5423) +++ trunk/src/northbridge/intel/i855/raminit.h Wed Apr 14 11:04:31 2010 (r5424) @@ -28,5 +28,7 @@ uint16_t channel0[DIMM_SOCKETS]; }; +void sdram_initialize(int controllers, const struct mem_controller *ctrl); + #endif /* RAMINIT_H */

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coreboot April 2010