coreboot April 2010

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[commit] r5419 - in trunk/src/arch/i386: . init
by repository service 13 Apr '10

13 Apr '10

Author: stepan Date: Tue Apr 13 15:43:35 2010 New Revision: 5419 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5419 Log: clean up LD scripts and add some comments and proper license headers where applicable. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/arch/i386/coreboot_ram.ld trunk/src/arch/i386/init/ldscript_apc.lb trunk/src/arch/i386/init/ldscript_failover.lb trunk/src/arch/i386/init/ldscript_fallback_cbfs.lb Modified: trunk/src/arch/i386/coreboot_ram.ld ============================================================================== --- trunk/src/arch/i386/coreboot_ram.ld Tue Apr 13 12:04:35 2010 (r5418) +++ trunk/src/arch/i386/coreboot_ram.ld Tue Apr 13 15:43:35 2010 (r5419) @@ -1,11 +1,12 @@ /* * Memory map: * - * CONFIG_RAMBASE + * CONFIG_RAMBASE : text segment + * : rodata segment * : data segment * : bss segment - * : heap * : stack + * : heap */ /* * Bootstrap code for the STPC Consumer @@ -17,10 +18,8 @@ * Rewritten by Eric Biederman * 2005.12 yhlu add coreboot_ram cross the vga font buffer handling */ -/* - * We use ELF as output format. So that we can - * debug the code in some form. - */ + +/* We use ELF as output format. So that we can debug the code in some form. */ INCLUDE ldoptions ENTRY(_start) @@ -28,9 +27,8 @@ SECTIONS { . = CONFIG_RAMBASE; - /* - * First we place the code and read only data (typically const declared). - * This get placed in rom. + /* First we place the code and read only data (typically const declared). + * This could theoretically be placed in rom. */ .text : { _text = .; @@ -39,6 +37,7 @@ . = ALIGN(16); _etext = .; } + .rodata : { _rodata = .; . = ALIGN(4); @@ -54,17 +53,14 @@ ecpu_drivers = . ; *(.rodata) *(.rodata.*) - /* - * kevinh/Ispiri - Added an align, because the objcopy tool + /* kevinh/Ispiri - Added an align, because the objcopy tool * incorrectly converts sections that are not long word aligned. - * This breaks the coreboot.rom target. */ . = ALIGN(4); _erodata = .; } - /* - * After the code we place initialized data (typically initialized + /* After the code we place initialized data (typically initialized * global variables). This gets copied into ram by startup code. * __data_start and __data_end shows where in ram this should be placed, * whereas __data_loadstart and __data_loadend shows where in rom to @@ -76,18 +72,7 @@ _edata = .; } - .sdata : { - _SDA_BASE_ = .; - *(.sdata) - } - - .sdata2 : { - _SDA2_BASE_ = .; - *(.sdata2) - } - - /* - * bss does not contain data, it is just a space that should be zero + /* bss does not contain data, it is just a space that should be zero * initialized on startup. (typically uninitialized global variables) * crt0.S fills between _bss and _ebss with zeroes. */ @@ -99,6 +84,11 @@ } _ebss = .; _end = .; + + /* coreboot really "ends" here. Only heap and stack are placed after + * this line. + */ + . = ALIGN(CONFIG_STACK_SIZE); _stack = .; @@ -107,6 +97,7 @@ . += CONFIG_MAX_CPUS*CONFIG_STACK_SIZE; } _estack = .; + _heap = .; .heap . : { /* Reserve CONFIG_HEAP_SIZE bytes for the heap */ @@ -115,18 +106,33 @@ } _eheap = .; + /* Some assertions to print human readable errors for certain linker + * error scenarios. + */ + /* Avoid running into 0xa0000-0xfffff */ _bogus = ASSERT(CONFIG_RAMBASE >= 0x100000 || _eheap < 0xa0000, "Please move RAMBASE to 1MB"); - /* The ram segment - * This is all address of the memory resident copy of coreboot. + /* The ram segment. This includes all memory used by the memory + * resident copy of coreboot, except the tables that are produced on + * the fly, but including stack and heap. */ _ram_seg = _text; _eram_seg = _eheap; - _bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "please increase CONFIG_RAMTOP"); + /* CONFIG_RAMTOP is the upper address of cached memory (among other + * things). We must not exceed beyond that address, there be dragons. + */ + _bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP"); + + /* This rule is only good for the few broken targets that still live + * below 1MB per default. Those are the Geode and VIA targets that come + * with their own version of real mode switches that can't live above + * 1MB. Once these are fixed, this rule should go away. + */ + _bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN || CONFIG_HAVE_SMI_HANDLER) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))), "Please increase CONFIG_RAMTOP and if still fail, try to set CONFIG_RAMBASE to 1M"); - _bogus = ASSERT( !((CONFIG_CONSOLE_VGA || CONFIG_PCI_ROM_RUN) && ((_ram_seg<0xa0000) && (_eram_seg>0xa0000))) , "please increase CONFIG_RAMTOP and if still fail, try to set CONFIG_RAMBASE more than 1M"); + /* Discard the sections we don't need/want */ /DISCARD/ : { *(.comment) Modified: trunk/src/arch/i386/init/ldscript_apc.lb ============================================================================== --- trunk/src/arch/i386/init/ldscript_apc.lb Tue Apr 13 12:04:35 2010 (r5418) +++ trunk/src/arch/i386/init/ldscript_apc.lb Tue Apr 13 15:43:35 2010 (r5419) @@ -1,4 +1,23 @@ -/* INPUT(coreboot_ap.rom)*/ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + INCLUDE "ldoptions" SECTIONS { @@ -9,8 +28,4 @@ *(.rodata.*) _eapcrom = .; } - _iseg_apc = CONFIG_DCACHE_RAM_BASE; - _eiseg_apc = _iseg_apc + SIZEOF(.apcrom); - _liseg_apc = _apcrom; - _eliseg_apc = _eapcrom; } Modified: trunk/src/arch/i386/init/ldscript_failover.lb ============================================================================== --- trunk/src/arch/i386/init/ldscript_failover.lb Tue Apr 13 12:04:35 2010 (r5418) +++ trunk/src/arch/i386/init/ldscript_failover.lb Tue Apr 13 15:43:35 2010 (r5419) @@ -1,29 +1,24 @@ /* - * Memory map: + * This file is part of the coreboot project. * - * CONFIG_RAMBASE - * : data segment - * : bss segment - * : heap - * : stack - * CONFIG_ROMBASE - * : coreboot text - * : readonly text - */ -/* - * Bootstrap code for the STPC Consumer - * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. + * Copyright (C) 2006 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* - * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman - */ -/* - * We use ELF as output format. So that we can - * debug the code in some form. - */ +/* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") OUTPUT_ARCH(i386) @@ -34,8 +29,6 @@ TARGET(binary) SECTIONS { - . = 0; - /* This section might be better named .setup */ .rom ROMLOC : { _rom = .; @@ -44,7 +37,7 @@ *(.rom.data.*); *(.rodata.*); _erom = .; - } >rom =0xff + } >rom = 0xff ROMLOC = 0xffffff00 - (_erom - _rom) + 1; Modified: trunk/src/arch/i386/init/ldscript_fallback_cbfs.lb ============================================================================== --- trunk/src/arch/i386/init/ldscript_fallback_cbfs.lb Tue Apr 13 12:04:35 2010 (r5418) +++ trunk/src/arch/i386/init/ldscript_fallback_cbfs.lb Tue Apr 13 15:43:35 2010 (r5419) @@ -1,36 +1,27 @@ /* - * Memory map: + * This file is part of the coreboot project. * - * CONFIG_RAMBASE - * : data segment - * : bss segment - * : heap - * : stack - * CONFIG_ROMBASE - * : coreboot text - * : readonly text - */ -/* - * Bootstrap code for the STPC Consumer - * Copyright (c) 1999 by Net Insight AB. All Rights Reserved. + * Copyright (C) 2006 Advanced Micro Devices, Inc. + * Copyright (C) 2008-2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* - * Written by Johan Rydberg, based on work by Daniel Kahlin. - * Rewritten by Eric Biederman - */ -/* - * We use ELF as output format. So that we can - * debug the code in some form. - */ +/* We use ELF as output format. So that we can debug the code in some form. */ OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") OUTPUT_ARCH(i386) -/* -ENTRY(_start) -*/ - TARGET(binary) SECTIONS { @@ -45,8 +36,6 @@ _rom = .; *(.rom.text); *(.rom.data); - *(.init.rodata.*); - *(.init.text); *(.rodata); *(.rodata.*); *(.rom.data.*);

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build service results for r5418
by coreboot information 13 Apr '10

13 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5418 to the coreboot repository. This caused the following changes: Change Log: use the standard udelay on sc520. Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of digitallogic:msm586seg has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5418&device=msm586seg&vend… Compilation of technologic:ts5300 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5418&device=ts5300&vendor=… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5418 - trunk/src/cpu/amd/sc520
by repository service 13 Apr '10

13 Apr '10

Author: stepan Date: Tue Apr 13 12:04:35 2010 New Revision: 5418 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5418 Log: use the standard udelay on sc520. Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/amd/sc520/raminit.c trunk/src/cpu/amd/sc520/sc520.c Modified: trunk/src/cpu/amd/sc520/raminit.c ============================================================================== --- trunk/src/cpu/amd/sc520/raminit.c Tue Apr 13 12:01:14 2010 (r5417) +++ trunk/src/cpu/amd/sc520/raminit.c Tue Apr 13 12:04:35 2010 (r5418) @@ -234,18 +234,7 @@ *ptr = 0; } -void sc520_udelay(int microseconds) { - volatile int x; - for(x = 0; x < 1000; x++) - ; -} - -/* looks like we define this now */ -void -udelay(int microseconds) { - sc520_udelay(microseconds); -} - +#include "pc80/udelay_io.c" static void dumpram(void){ print_err("ctl "); print_err_hex8(*drcctl); print_err("\n"); @@ -311,7 +300,7 @@ print_err("NOP\n"); /* 100? 200? */ udelay(100); - print_err("after sc520_udelay\n"); + print_err("after udelay\n"); /* issue all banks precharge */ *drcctl=0x02; @@ -385,8 +374,8 @@ dummy_write(); print_err("NOP\n"); /* 100? 200? */ - //sc520_udelay(100); - print_err("after sc520_udelay\n"); + //udelay(100); + print_err("after udelay\n"); /* issue all banks precharge */ *drcctl=0x02; Modified: trunk/src/cpu/amd/sc520/sc520.c ============================================================================== --- trunk/src/cpu/amd/sc520/sc520.c Tue Apr 13 12:01:14 2010 (r5417) +++ trunk/src/cpu/amd/sc520/sc520.c Tue Apr 13 12:04:35 2010 (r5418) @@ -15,19 +15,6 @@ #include <delay.h> #include "chip.h" - -/* hack for now */ -static void sc520_udelay(int microseconds) { - volatile int x; - for(x = 0; x < 1000; x++) - ; -} - -/* looks like we define this now */ -void -udelay(unsigned microseconds) { - sc520_udelay(microseconds); -} /* * set up basic things ... * PAR should NOT go here, as it might change with the mainboard.

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[commit] r5417 - in trunk/src: arch/i386/init cpu/via/car
by repository service 13 Apr '10

13 Apr '10

Author: stepan Date: Tue Apr 13 12:01:14 2010 New Revision: 5417 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5417 Log: Speed up coreboot_ram loading by moving the decompression stack into the cached area. Back to 469ms until coreboot_ram is actually running on epia-cn Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/arch/i386/init/crt0_romcc_epilogue.inc trunk/src/cpu/via/car/cache_as_ram.inc Modified: trunk/src/arch/i386/init/crt0_romcc_epilogue.inc ============================================================================== --- trunk/src/arch/i386/init/crt0_romcc_epilogue.inc Tue Apr 13 03:22:20 2010 (r5416) +++ trunk/src/arch/i386/init/crt0_romcc_epilogue.inc Tue Apr 13 12:01:14 2010 (r5417) @@ -14,8 +14,16 @@ movl %ebp, %esi - /* FIXME: look for a proper place for the stack */ - movl $0x4000000, %esp + /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This + * makes sure that we stay completely within the 1M-64K of memory that we + * preserve for suspend/resume. + */ + +#ifndef HIGH_MEMORY_SAVE +#warning Need a central place for HIGH_MEMORY_SAVE +#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) +#endif + movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp movl %esp, %ebp pushl %esi call copy_and_run Modified: trunk/src/cpu/via/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.inc Tue Apr 13 03:22:20 2010 (r5416) +++ trunk/src/cpu/via/car/cache_as_ram.inc Tue Apr 13 12:01:14 2010 (r5417) @@ -270,14 +270,16 @@ movl %ebp, %esi - /* FIXME: These values might have to change for suspend-to-ram. - * the 0x00400000 was chosen as this is a place in memory that - * should exist in all contemporary configurations (ie. large - * enough RAM), but doesn't collide with anything coreboot does. - * Other than that, it's arbitrary. + /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This + * makes sure that we stay completely within the 1M-64K of memory that we + * preserve for suspend/resume. */ - movl $0x4000000, %esp +#ifndef HIGH_MEMORY_SAVE +#warning Need a central place for HIGH_MEMORY_SAVE +#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) +#endif + movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp movl %esp, %ebp pushl %esi call copy_and_run

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[PATCH] Get rid of unaligned 32-bit config space read in mcd_d.c
by Arne Georg Gleditsch 13 Apr '10

13 Apr '10

Hi, This patch removes a non-32-bit aligned Get_NB32 from src/northbridge/amd/amdmct/mct/mct_d.c. The actual behavior should be unchanged for I/O-based config space reads, but previous behavior was wrong for MMCFG-based config space reads. Perhaps we want pci_mmio_*_config* to enforce natural alignment as well? Signed-off-by: Arne Georg Gleditsch <arne.gleditsch(a)numascale.com> -- Arne.

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superiotool support FDC37C932 for Nokia IP330
by Marc Bertens 12 Apr '10

12 Apr '10

Hi all, I added support for the FDC37C932 (device id 0x02, revision 0x01) chip. This chip is in a Nokia IP330 (firewall hardware). The diff was made using Work Bench version: 1.5.4-0, pysvn version: 1.6.0-0, svn version: 1.5.1-, wxPython 2.6.3.2 , Python 2.5.2 final 0 This is the -deV output of the run on my system. superiotool r5263 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Found SMSC FDC37C932 (id=0x02, rev=0x01) at 0x3f0 Register dump: idx 03 20 21 22 23 24 2d 2e 2f val 03 02 01 39 00 c4 00 00 00 def 03 02 01 00 00 04 NA NA 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val 01 03 f0 06 02 0e 00 ff 00 00 def 00 03 f0 06 02 0e 00 ff 00 00 LDN 0x01 (IDE0 Controller) idx 03 60 61 62 63 70 val 03 00 00 00 00 00 def 00 01 f0 03 f6 0e LDN 0x02 (IDE1 Controller) idx 03 60 61 62 63 70 val 03 00 00 00 00 00 def 00 00 00 00 f0 00 LDN 0x03 (Parallel port) idx 30 60 61 70 74 f0 val 01 03 78 07 03 bb def 00 00 00 00 04 3c LDN 0x04 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 00 def 00 00 00 00 00 LDN 0x05 (COM2) idx 30 60 61 70 f0 f1 val 01 02 f8 03 00 00 def 00 00 00 00 00 00 LDN 0x06 (Real-time clock (RTC)) idx 30 70 f0 f1 f2 f3 f3 f5 f6 val 01 08 00 00 00 00 00 ff 00 def 00 00 00 00 00 NA NA 03 NA LDN 0x07 (Keyboard) idx 30 70 72 val 01 01 00 def 00 00 00 LDN 0x08 (Aux I/O) idx 30 60 61 62 63 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed f0 f1 f2 f3 f4 val 01 00 00 00 00 01 01 01 01 01 01 01 01 08 01 01 01 01 08 00 00 00 00 01 def 00 00 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01 01 01 00 00 00 00 00 No extra registers known for this chip. Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. Regards, Marc

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[commit] r5416 - trunk/util/superiotool
by repository service 12 Apr '10

12 Apr '10

Author: uwe Date: Tue Apr 13 03:22:20 2010 New Revision: 5416 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5416 Log: Add support for the SMSC FDC37C932 Super I/O. This chip is found e.g. in the Nokia IP330 (firewall hardware). Signed-off-by: Marc Bertens <mbertens(a)xs4all.nl> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/superiotool/smsc.c Modified: trunk/util/superiotool/smsc.c ============================================================================== --- trunk/util/superiotool/smsc.c Tue Apr 13 02:11:59 2010 (r5415) +++ trunk/util/superiotool/smsc.c Tue Apr 13 03:22:20 2010 (r5416) @@ -29,6 +29,46 @@ static const struct superio_registers reg_table[] = { /* The following Super I/Os use the 0x20/0x21 ID registers. */ + {0x02, "FDC37C932", { + {NOLDN, NULL, + {0x02,0x03,0x20,0x21,0x22,0x23,0x24,0x2d,0x2e, + 0x2f,EOT}, + {0x00,0x03,0x02,0x01,0x00,0x00,0x04,NANA,NANA, + 0x00,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf1,0xf2,0xf4, + 0xf5,EOT}, + {0x00,0x03,0xf0,0x06,0x02,0x0e,0x00,0xff,0x00, + 0x00,EOT}}, + {0x1, "IDE 1", + {0x30,0x60,0x61,0x62,0x63,0x70,EOT}, + {0x00,0x01,0xf0,0x03,0xf6,0x0e,EOT}}, + {0x2, "IDE 2", + {0x30,0x60,0x61,0x62,0x63,0x70,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x04,0x3c,EOT}}, + {0x4, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x5, "COM2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x00,EOT}}, + {0x6, "Real-time clock (RTC)", + {0x30,0x70,0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,EOT}, + {0x00,0x00,0x00,0x00,0x00,NANA,MISC,NANA,NANA,EOT}}, + {0x7, "Keyboard", + {0x30,0x70,0x72,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x8, "Aux I/O", + {0x30,0x60,0x61,0x62,0x63,0xe0,0xe1,0xe2,0xe3,0xe4, + 0xe5,0xe6,0xe7,0xe8,0xe9,0xea,0xeb,0xec,0xed,0xf0, + 0xf1,0xf2,0xf3,0xf4,EOT}, + {0x00,0x00,0x00,0x00,0x00,0x01,0x01,0x01,0x01,0x01, + 0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x00, + 0x00,0x00,0x00,MISC,EOT}}, + {EOT}}}, {0x03, "FDC37C93xFR", { /* FIXME: There's another 0x03 but found on port 0x0d/0x0e! */ {EOT}}},

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[PATCH] stack location
by Stefan Reinauer 12 Apr '10

12 Apr '10

see patch. Not sure if this area is cached, but I think it should be, none the less. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

2 1

[PATCH] VIA C7 CAR fixes / cleanup
by Stefan Reinauer 12 Apr '10

12 Apr '10

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

4 8

build service results for r5414
by coreboot information 12 Apr '10

12 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5414 to the coreboot repository. This caused the following changes: Change Log: Fix eagleheights not a 6ex board, but using the same CAR code. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of intel:eagleheights has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot April 2010