coreboot April 2010

coreboot@coreboot.org

64 participants
402 discussions

Re: [coreboot] coreboot Digest, Vol 62, Issue 45
by Keith Hui 11 Apr '10

11 Apr '10

Because I smell 440BX, I'll chip in with some insights. :-D >> +config BOARD_NOKIA_IP530 >> + bool "IP530" >> + select ARCH_X86 >> +## select CPU_INTEL_SLOT_1 >> + select CPU_INTEL_SOCKET_PGA370 > > Is this correct? If it's 440BX chipset it's very likely to be Slot 1. >> +chip northbridge/intel/i440bx # Northbridge >> + device apic_cluster 0 on # APIC cluster >> + chip cpu/intel/socket_PGA370 # CPU > > Slot 1? See above. > I found an ebay listing of an IP530 mainboard with picture (attached). It shows a socket 370. > >> + device pci 7.2 on end # USB >> + device pci 7.3 on end # ACPI >> + register "ide0_enable" = "1" >> + register "ide1_enable" = "1" >> + register "ide_legacy_enable" = "1" >> + # Enable UDMA/33 for higher speed if your IDE device(s) support it. >> + register "ide0_drive0_udma33_enable" = "0" >> + register "ide0_drive1_udma33_enable" = "0" >> + register "ide1_drive0_udma33_enable" = "0" >> + register "ide1_drive1_udma33_enable" = "0" > > I think you can safely set these to "1" too. Actually, we should do this > for all 440BX boards IMHO (per default). If any user should have issues > it's easy enough to set to "0". > There are also some discussions about detecting UDMA on connected IDE drives. I believe this can be done through some standard ATA commands, but adding support for this would, at a minumum, introduce much code from elsewhere that isn't otherwise needed by coreboot. It seems better to investigate what harm, if any, can be done enabling UDMA with a UDMA-incapable drive connected, so we know if it's appropriate to just enable them here. And the case we see here have none of the 8 (!) tulips, PCMCIA and whatnot working. From the listing provided it seems like nothing got any IRQ assigned except one of the tulips. But they all have I/O ports assigned and enabled. Some googling tells me this thing have 4 tulips built-in. Given its hardware class the other 4 tulips could be on add-on cards. I'll let the original poster report back. Dump the IRQ routing tables with one of the utilities in the coreboot tree while running OEM BIOS, and try it in your working copy. And according to http://coreboot.pastebin.com/mU5m0PfE, it has a SMSC superio. Cheers Keith

1 0

[PATCH] thomson ip1000 running seabios
by Stefan Reinauer 11 Apr '10

11 Apr '10

See patch -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

2 1

[commit] r5408 - in trunk/src: mainboard/thomson/ip1000 northbridge/intel/i82830
by repository service 11 Apr '10

11 Apr '10

Author: stepan Date: Sun Apr 11 22:04:50 2010 New Revision: 5408 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5408 Log: add int15 handler for thomson ip1000 fix mbi length detection, this will remove what looked like an endless loop during vga init in some cases. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/thomson/ip1000/mainboard.c trunk/src/northbridge/intel/i82830/i82830_smihandler.c trunk/src/northbridge/intel/i82830/vga.c Modified: trunk/src/mainboard/thomson/ip1000/mainboard.c ============================================================================== --- trunk/src/mainboard/thomson/ip1000/mainboard.c Sun Apr 11 22:02:47 2010 (r5407) +++ trunk/src/mainboard/thomson/ip1000/mainboard.c Sun Apr 11 22:04:50 2010 (r5408) @@ -22,6 +22,9 @@ #include <device/device.h> #include <boot/tables.h> #include <delay.h> +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +#include <x86emu/x86emu.h> +#endif #include <arch/coreboot_tables.h> #include <arch/io.h> #include "chip.h" @@ -102,6 +105,61 @@ } } + +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL +static int int15_handler(void) +{ + u8 display_id; +#define BOOT_DISPLAY_DEFAULT 0 +#define BOOT_DISPLAY_CRT (1 << 0) +#define BOOT_DISPLAY_TV (1 << 1) +#define BOOT_DISPLAY_EFP (1 << 2) +#define BOOT_DISPLAY_LCD (1 << 3) +#define BOOT_DISPLAY_CRT2 (1 << 4) +#define BOOT_DISPLAY_TV2 (1 << 5) +#define BOOT_DISPLAY_EFP2 (1 << 6) +#define BOOT_DISPLAY_LCD2 (1 << 7) + + printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n", + __func__, M.x86.R_AX, M.x86.R_BX, M.x86.R_CX, M.x86.R_DX); + + switch (M.x86.R_AX) { + case 0x5f35: /* Boot Display */ + M.x86.R_AX = 0x005f; // Success + // M.x86.R_CL = BOOT_DISPLAY_TV; + M.x86.R_CL = BOOT_DISPLAY_DEFAULT; + break; + case 0x5f36: /* Boot TV Format Hook */ + printk(BIOS_DEBUG, "Boot TV Format Hook. TODO\n"); + /* Interrupt was not handled */ + return 0; + case 0x5f31: /* Post Completion Hook */ + case 0x5f33: /* Hook After Mode Set */ + case 0x5f34: /* Set Panel Fitting Hook */ + case 0x5f38: /* Hook Before Mode Set */ + case 0x5f45: /* Hook Before VESA VBE/DDC */ + case 0x5f46: /* Hook Before VESA VBE/PM */ + case 0x5f47: /* Notif Display Switch Hook */ + case 0x5f65: /* Local Memory Initialization Hook */ + /* Interrupt was not handled */ + return 0; + default: + /* Interrupt was not handled */ + return 0; + } + + /* Interrupt handled */ + return 1; +} + +static void int15_install(void) +{ + typedef int (* yabel_handleIntFunc)(void); + extern yabel_handleIntFunc yabel_intFuncArray[256]; + yabel_intFuncArray[0x15] = int15_handler; +} +#endif + static void mainboard_init(device_t dev) { parport_gpios(); @@ -111,6 +169,10 @@ static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; +#if CONFIG_PCI_OPTION_ROM_RUN_YABEL + /* Install custom int15 handler for VGA OPROM */ + int15_install(); +#endif } struct chip_operations mainboard_ops = { Modified: trunk/src/northbridge/intel/i82830/i82830_smihandler.c ============================================================================== --- trunk/src/northbridge/intel/i82830/i82830_smihandler.c Sun Apr 11 22:02:47 2010 (r5407) +++ trunk/src/northbridge/intel/i82830/i82830_smihandler.c Sun Apr 11 22:04:50 2010 (r5408) @@ -187,7 +187,7 @@ int i, count=0; obj_header->banner.retsts = MSH_IF_NOT_FOUND; - for (i=0; i< mbi_len;) { + for (i=0; i<mbi_len;) { int len; if (!(mbi[i] == 0xf0 && mbi [i+1] == 0xf6)) { @@ -199,6 +199,12 @@ len = ALIGN((mbi_header->size * 16) + sizeof(mbi_header) + mbi_header->name_len, 16); if (obj_header->objnum == count) { +#ifdef DEBUG_SMI_I82830 + if (mbi_header->name_len == 0xff) { + printk(BIOS_DEBUG, "| |- corrupt.\n"); + break; + } +#endif int headerlen = ALIGN(sizeof(mbi_header) + mbi_header->name_len + 15, 16); #ifdef DEBUG_SMI_I82830 printk(BIOS_DEBUG, "| |- headerlen = %d\n", headerlen); Modified: trunk/src/northbridge/intel/i82830/vga.c ============================================================================== --- trunk/src/northbridge/intel/i82830/vga.c Sun Apr 11 22:02:47 2010 (r5407) +++ trunk/src/northbridge/intel/i82830/vga.c Sun Apr 11 22:04:50 2010 (r5408) @@ -42,7 +42,7 @@ "type %x\n", file->type, CBFS_TYPE_MBI); } else { mbi = (void *) CBFS_SUBHEADER(file); - mbi_len = file->len; + mbi_len = ntohl(file->len); } } else { printk(BIOS_INFO, "Could not find MBI.\n");

1 0

[commit] r5407 - trunk/src/southbridge/intel/i82801dx
by repository service 11 Apr '10

11 Apr '10

Author: stepan Date: Sun Apr 11 22:02:47 2010 New Revision: 5407 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5407 Log: do better error reporting in i82801dx early smbus functions. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c ============================================================================== --- trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c Sun Apr 11 21:02:10 2010 (r5406) +++ trunk/src/southbridge/intel/i82801dx/i82801dx_early_smbus.c Sun Apr 11 22:02:47 2010 (r5407) @@ -18,8 +18,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -//#define SMBUS_IO_BASE 0x1000 -//#define SMBUS_IO_BASE 0x0f00 +#include "i82801dx.h" #define SMBHSTSTAT 0x0 #define SMBHSTCTL 0x2 @@ -42,7 +41,7 @@ { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); - print_debug("SMBus controller enabled\n"); + printk(BIOS_DEBUG, "SMBus controller enabled\n"); /* set smbus iobase */ pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); /* Set smbus enable */ @@ -118,9 +117,9 @@ unsigned char global_status_register; unsigned char byte; - /*print_err("smbus_read_byte\n"); */ + /* printk(BIOS_ERR, "smbus_read_byte\n"); */ if (smbus_wait_until_ready() < 0) { - print_err_hex8(-2); + printk(BIOS_ERR, "SMBUS not ready (%02x)\n", -2); return -2; } @@ -146,13 +145,13 @@ SMBUS_IO_BASE + SMBHSTCTL); /* poll for it to start */ if (smbus_wait_until_active() < 0) { - print_err_hex8(-4); + printk(BIOS_ERR, "SMBUS not active (%02x)\n", -4); return -4; } /* poll for transaction completion */ if (smbus_wait_until_done() < 0) { - print_err_hex8(-3); + printk(BIOS_ERR, "SMBUS not completed (%02x)\n", -3); return -3; } @@ -162,14 +161,10 @@ byte = inb(SMBUS_IO_BASE + SMBHSTDAT0); if (global_status_register != 2) { - print_err_hex8(-1); + //printk(BIOS_SPEW, "%s: no device (%02x, %02x)\n", __func__, device, address); return -1; } -/* - print_err("smbus_read_byte: "); - print_err_hex32(device); print_err(" ad "); print_err_hex32(address); - print_err("value "); print_err_hex8(byte); print_err("\n"); - */ + //printk(BIOS_DEBUG, "%s: %02x@%02x = %02x\n", __func__, device, address, byte); return byte; }

1 0

[PATCH] IP1000 board specific GPIOs
by Stefan Reinauer 11 Apr '10

11 Apr '10

See patch

4 5

[commit] r5406 - in trunk/src: cpu/intel/socket_mPGA479M mainboard/digitallogic/adl855pc
by repository service 11 Apr '10

11 Apr '10

Author: stepan Date: Sun Apr 11 21:02:10 2010 New Revision: 5406 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5406 Log: The ADL855PC was never confirmed working (in fact it's pretty sure that code does not work as it is, but it's the only compile test case for i855pm). It's the only board left using an ICH4 that does not use CAR. Change that. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/intel/socket_mPGA479M/Kconfig trunk/src/mainboard/digitallogic/adl855pc/Kconfig trunk/src/mainboard/digitallogic/adl855pc/romstage.c Modified: trunk/src/cpu/intel/socket_mPGA479M/Kconfig ============================================================================== --- trunk/src/cpu/intel/socket_mPGA479M/Kconfig Sun Apr 11 20:57:10 2010 (r5405) +++ trunk/src/cpu/intel/socket_mPGA479M/Kconfig Sun Apr 11 21:02:10 2010 (r5406) @@ -1,6 +1,7 @@ config CPU_INTEL_SOCKET_MPGA479M bool select CPU_INTEL_MODEL_69X + select CPU_INTEL_MODEL_6BX select CPU_INTEL_MODEL_6DX select MMX select SSE Modified: trunk/src/mainboard/digitallogic/adl855pc/Kconfig ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/Kconfig Sun Apr 11 20:57:10 2010 (r5405) +++ trunk/src/mainboard/digitallogic/adl855pc/Kconfig Sun Apr 11 21:02:10 2010 (r5406) @@ -5,10 +5,12 @@ select NORTHBRIDGE_INTEL_I855 select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_WINBOND_W83627HF - select ROMCC select HAVE_PIRQ_TABLE select HAVE_HARD_RESET select BOARD_ROMSIZE_KB_1024 + select USE_PRINTK_IN_CAR + select USE_DCACHE_RAM + select TINY_BOOTBLOCK config MAINBOARD_DIR string @@ -20,6 +22,16 @@ default "smartModule855" depends on BOARD_DIGITALLOGIC_ADL855PC +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + depends on BOARD_DIGITALLOGIC_ADL855PC + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_DIGITALLOGIC_ADL855PC + config IRQ_SLOT_COUNT int default 5 Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/romstage.c Sun Apr 11 20:57:10 2010 (r5405) +++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c Sun Apr 11 21:02:10 2010 (r5406) @@ -57,7 +57,10 @@ #include "northbridge/intel/i855/reset_test.c" #include "lib/generic_sdram.c" -static void main(unsigned long bist) + +#include "cpu/intel/model_6bx/cache_as_ram_disable.c" + +void real_main(unsigned long bist) { static const struct mem_controller memctrl[] = { { @@ -67,7 +70,6 @@ }; if (bist == 0) { - early_mtrr_init(); #if 0 enable_lapic(); init_timer(); @@ -80,7 +82,6 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); - #if 0 print_pci_devices(); @@ -89,50 +90,25 @@ if(!bios_reset_detected()) { enable_smbus(); #if 0 - dump_spd_registers(&memctrl[0]); - // dump_smbus_registers(); + dump_spd_registers(&memctrl[0]); + dump_smbus_registers(); #endif - memreset_setup(); sdram_initialize(ARRAY_SIZE(memctrl), memctrl); } -#if 0 - else { - /* clear memory 1meg */ - __asm__ volatile( - "1: \n\t" - "movl %0, %%fs:(%1)\n\t" - "addl $4,%1\n\t" - "subl $4,%2\n\t" - "jnz 1b\n\t" - : - : "a" (0), "D" (0), "c" (1024*1024) - ); - - } -#endif #if 0 dump_pci_devices(); -#endif -#if 0 dump_pci_device(PCI_DEV(0, 0, 0)); -#endif -/* -#if 0 + // Check all of memory ram_check(0x00000000, msr.lo+(msr.hi<<32)); -#else -#if 0 // Check 16MB of memory @ 0 ram_check(0x00000000, 0x01000000); -#else // Check 16MB of memory @ 2GB ram_check(0x80000000, 0x81000000); #endif -#endif -*/ }

1 0

[commit] r5404 - trunk/src/northbridge/intel/i82830
by repository service 11 Apr '10

11 Apr '10

Author: stepan Date: Sun Apr 11 20:54:47 2010 New Revision: 5404 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5404 Log: simplify ram_read32 on i82830 Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/intel/i82830/raminit.c Modified: trunk/src/northbridge/intel/i82830/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i82830/raminit.c Sun Apr 11 18:36:13 2010 (r5403) +++ trunk/src/northbridge/intel/i82830/raminit.c Sun Apr 11 20:54:47 2010 (r5404) @@ -75,25 +75,18 @@ static void ram_read32(u8 dimm_start, u32 offset) { -#if CONFIG_DEBUG_RAM_SETUP + u32 reg32, base_addr = 32 * 1024 * 1024 * dimm_start; if (offset == 0x55aa55aa) { - PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", (dimm_start * 32 * 1024 * 1024), read32(dimm_start * 32 * 1024 * 1024)); - PRINTK_DEBUG(" Writing RAM at 0x%08x <= 0x%08x\n", (dimm_start * 32 * 1024 * 1024), offset); - write32(dimm_start * 32 * 1024 * 1024, offset); - PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", (dimm_start * 32 * 1024 * 1024), read32(dimm_start * 32 * 1024 * 1024)); + reg32 = read32(base_addr); + PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", base_addr, reg32); + PRINTK_DEBUG(" Writing RAM at 0x%08x <= 0x%08x\n", base_addr, offset); + write32(base_addr, offset); + reg32 = read32(base_addr); + PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", base_addr, reg32); } else { - PRINTK_DEBUG(" to 0x%08x\n", (dimm_start * 32 * 1024 * 1024) + offset); - read32((dimm_start * 32 * 1024 * 1024) + offset); + PRINTK_DEBUG(" to 0x%08x\n", base_addr + offset); + read32(base_addr + offset); } -#else - if (offset == 0x55aa55aa) { - read32(dimm_start * 32 * 1024 * 1024); - write32(dimm_start * 32 * 1024 * 1024, offset); - read32(dimm_start * 32 * 1024 * 1024); - } else { - read32((dimm_start * 32 * 1024 * 1024) + offset); - } -#endif } static void initialize_dimm_rows(void)

2 1

[commit] r5405 - trunk/src/mainboard/thomson/ip1000
by repository service 11 Apr '10

11 Apr '10

Author: stepan Date: Sun Apr 11 20:57:10 2010 New Revision: 5405 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5405 Log: add support for reading ip1000 gpios. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Ronald G. Minnich <rminnich(a)gmail.com> Modified: trunk/src/mainboard/thomson/ip1000/mainboard.c Modified: trunk/src/mainboard/thomson/ip1000/mainboard.c ============================================================================== --- trunk/src/mainboard/thomson/ip1000/mainboard.c Sun Apr 11 20:54:47 2010 (r5404) +++ trunk/src/mainboard/thomson/ip1000/mainboard.c Sun Apr 11 20:57:10 2010 (r5405) @@ -2,11 +2,11 @@ * This file is part of the coreboot project. * * Copyright (C) 2008-2010 Joseph Smith <joe(a)settoplinux.org> + * Copyright (C) 2010 Stefan Reinauer <stepan(a)openbios.org> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -18,9 +18,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <console/console.h> #include <device/device.h> #include <boot/tables.h> +#include <delay.h> #include <arch/coreboot_tables.h> +#include <arch/io.h> #include "chip.h" int add_mainboard_resources(struct lb_memory *mem) @@ -28,14 +31,85 @@ return add_northbridge_resources(mem); } +// setting the bit disables the led. +#define PARPORT_GPIO_LED_GREEN (1 << 0) +#define PARPORT_GPIO_LED_ORANGE (1 << 1) +#define PARPORT_GPIO_LED_RED (1 << 2) +#define PARPORT_GPIO_IR_PORT (1 << 6) + +static u8 get_parport_gpio(void) +{ + return inb(0x378); +} + +static void set_parport_gpio(u8 gpios) +{ + outb(gpios, 0x378); +} + +static void parport_gpios(void) +{ + u8 pp_gpios = get_parport_gpio(); + + /* disable red led */ + pp_gpios |= PARPORT_GPIO_LED_RED; + set_parport_gpio(pp_gpios); + + pp_gpios = get_parport_gpio(); + + printk(BIOS_DEBUG, "IP1000 GPIOs:\n"); + printk(BIOS_DEBUG, " GPIO mask: %02x\n", pp_gpios); + printk(BIOS_DEBUG, " green led: %s\n", + (pp_gpios & PARPORT_GPIO_LED_GREEN) ? "off" : "on"); + printk(BIOS_DEBUG, " orange led: %s\n", + (pp_gpios & PARPORT_GPIO_LED_ORANGE) ? "off" : "on"); + printk(BIOS_DEBUG, " red led: %s\n", + (pp_gpios & PARPORT_GPIO_LED_RED) ? "off" : "on"); + printk(BIOS_DEBUG, " IR port: %s\n", + (pp_gpios & PARPORT_GPIO_IR_PORT) ? "off" : "on"); +} + +static void flash_gpios(void) +{ + u32 flash_base = 0xfff80000; + u8 manufacturer_id, device_id; + + // reset mode + write8(flash_base, 0xff); + udelay(10); + // read id + write8(flash_base, 0x90); + udelay(10); + manufacturer_id = read8(flash_base); + device_id = read8(flash_base + 1); + // reset mode + write8(flash_base, 0xff); + udelay(10); + + if ((manufacturer_id == 0x20) && + ((device_id == 0x2c) || (device_id == 0x2d))) { + printk(BIOS_DEBUG, "Detected ST M50FW0%c0 flash:\n", + (device_id==0x2c)?'4':'8'); + u8 fgpi = read8(0xffbc0100); + printk(BIOS_DEBUG, " FGPI0 [%c] FGPI1 [%c] FGPI2 [%c] FGPI3 [%c] FGPI4 [%c]", + (fgpi & (1 << 0)) ? 'X' : ' ', + (fgpi & (1 << 1)) ? 'X' : ' ', + (fgpi & (1 << 2)) ? 'X' : ' ', + (fgpi & (1 << 3)) ? 'X' : ' ', + (fgpi & (1 << 4)) ? 'X' : ' '); + } else { + printk(BIOS_DEBUG, "No ST M50FW040/M50FW080 flash, don't read FGPI.\n"); + } +} + static void mainboard_init(device_t dev) { - // TODO Switch parport LEDs again + parport_gpios(); + flash_gpios(); } static void mainboard_enable(device_t dev) { - // TODO Switch parport LEDs dev->ops->init = mainboard_init; }

1 0

[commit] r5403 - trunk/src/northbridge/intel/i82830
by repository service 11 Apr '10

11 Apr '10

Author: linux_junkie Date: Sun Apr 11 18:36:13 2010 New Revision: 5403 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5403 Log: More trivial changes to i82830 raminit.c for USE_PRINTK_IN_CAR. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Joseph Smith <joe(a)settoplinux.org> Modified: trunk/src/northbridge/intel/i82830/raminit.c Modified: trunk/src/northbridge/intel/i82830/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i82830/raminit.c Sun Apr 11 07:50:08 2010 (r5402) +++ trunk/src/northbridge/intel/i82830/raminit.c Sun Apr 11 18:36:13 2010 (r5403) @@ -75,6 +75,7 @@ static void ram_read32(u8 dimm_start, u32 offset) { +#if CONFIG_DEBUG_RAM_SETUP if (offset == 0x55aa55aa) { PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", (dimm_start * 32 * 1024 * 1024), read32(dimm_start * 32 * 1024 * 1024)); PRINTK_DEBUG(" Writing RAM at 0x%08x <= 0x%08x\n", (dimm_start * 32 * 1024 * 1024), offset); @@ -84,6 +85,15 @@ PRINTK_DEBUG(" to 0x%08x\n", (dimm_start * 32 * 1024 * 1024) + offset); read32((dimm_start * 32 * 1024 * 1024) + offset); } +#else + if (offset == 0x55aa55aa) { + read32(dimm_start * 32 * 1024 * 1024); + write32(dimm_start * 32 * 1024 * 1024, offset); + read32(dimm_start * 32 * 1024 * 1024); + } else { + read32((dimm_start * 32 * 1024 * 1024) + offset); + } +#endif } static void initialize_dimm_rows(void) @@ -405,7 +415,7 @@ static void sdram_set_registers(void) { - PRINTK_DEBUG("Setting initial sdram registers....\n"); + printk(BIOS_DEBUG, "Setting initial SDRAM registers....\n"); /* Calculate the value for DRT DRAM Timing Register */ set_dram_timing(); @@ -419,7 +429,7 @@ /* Setup DRAM Row Attribute Registers */ set_dram_row_attributes(); - PRINTK_DEBUG("Initial sdram registers have been set.\n"); + printk(BIOS_DEBUG, "Initial SDRAM registers have been set.\n"); } static void northbridge_set_registers(void) @@ -427,7 +437,7 @@ u16 value; int igd_memory = 0; - PRINTK_DEBUG("Setting initial nothbridge registers....\n"); + printk(BIOS_DEBUG, "Setting initial Nothbridge registers....\n"); /* Set the value for Fixed DRAM Hole Control Register */ pci_write_config8(NORTHBRIDGE, FDHC, 0x00); @@ -473,7 +483,7 @@ value |= 1; // 64MB aperture pci_write_config16(NORTHBRIDGE, GCC1, value); - PRINTK_DEBUG("Initial northbridge registers have been set.\n"); + printk(BIOS_DEBUG, "Initial Northbridge registers have been set.\n"); } static void sdram_initialize(void)

1 0

[commit] r5402 - trunk/src/northbridge/intel/i82830
by repository service 11 Apr '10

11 Apr '10

Author: linux_junkie Date: Sun Apr 11 07:50:08 2010 New Revision: 5402 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5402 Log: Trivial changes to i82830 raminit.c for USE_PRINTK_IN_CAR. Signed-off-by: Joseph Smith <joe(a)settoplinux.org> Acked-by: Joseph Smith <joe(a)settoplinux.org> Modified: trunk/src/northbridge/intel/i82830/raminit.c Modified: trunk/src/northbridge/intel/i82830/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i82830/raminit.c Sat Apr 10 00:25:27 2010 (r5401) +++ trunk/src/northbridge/intel/i82830/raminit.c Sun Apr 11 07:50:08 2010 (r5402) @@ -30,16 +30,10 @@ /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP -#define PRINT_DEBUG(x) print_debug(x) -#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x) -#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x) -#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x) +#define PRINTK_DEBUG(x...) printk(BIOS_DEBUG, x) #define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0)) #else -#define PRINT_DEBUG(x) -#define PRINT_DEBUG_HEX8(x) -#define PRINT_DEBUG_HEX16(x) -#define PRINT_DEBUG_HEX32(x) +#define PRINTK_DEBUG(x...) #define DUMPNORTH() #endif @@ -75,37 +69,19 @@ /* Clear bits 29, 10-8, 6-4. */ reg32 &= 0xdffff88f; reg32 |= command << 4; + PRINTK_DEBUG(" Sending RAM command 0x%08x", reg32); pci_write_config32(NORTHBRIDGE, DRC, reg32); - PRINT_DEBUG("RAM command 0x"); - PRINT_DEBUG_HEX32(reg32); - PRINT_DEBUG("\n"); } static void ram_read32(u8 dimm_start, u32 offset) { if (offset == 0x55aa55aa) { - PRINT_DEBUG(" Reading RAM at 0x"); - PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024); - PRINT_DEBUG(" => 0x"); - PRINT_DEBUG_HEX32(read32(dimm_start * 32 * 1024 * 1024)); - PRINT_DEBUG("\n"); - - PRINT_DEBUG(" Writing RAM at 0x"); - PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024); - PRINT_DEBUG(" <= 0x"); - PRINT_DEBUG_HEX32(offset); - PRINT_DEBUG("\n"); + PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", (dimm_start * 32 * 1024 * 1024), read32(dimm_start * 32 * 1024 * 1024)); + PRINTK_DEBUG(" Writing RAM at 0x%08x <= 0x%08x\n", (dimm_start * 32 * 1024 * 1024), offset); write32(dimm_start * 32 * 1024 * 1024, offset); - - PRINT_DEBUG(" Reading RAM at 0x"); - PRINT_DEBUG_HEX32(dimm_start * 32 * 1024 * 1024); - PRINT_DEBUG(" => 0x"); - PRINT_DEBUG_HEX32(read32(dimm_start * 32 * 1024 * 1024)); - PRINT_DEBUG("\n"); + PRINTK_DEBUG(" Reading RAM at 0x%08x => 0x%08x\n", (dimm_start * 32 * 1024 * 1024), read32(dimm_start * 32 * 1024 * 1024)); } else { - PRINT_DEBUG(" Sending RAM command to 0x"); - PRINT_DEBUG_HEX32((dimm_start * 32 * 1024 * 1024) + offset); - PRINT_DEBUG("\n"); + PRINTK_DEBUG(" to 0x%08x\n", (dimm_start * 32 * 1024 * 1024) + offset); read32((dimm_start * 32 * 1024 * 1024) + offset); } } @@ -138,24 +114,22 @@ dimm_end = pci_read_config8(NORTHBRIDGE, DRB + row); if (dimm_end > dimm_start) { - print_debug("Initializing SDRAM Row "); - print_debug_hex8(row); - print_debug("\n"); + printk(BIOS_DEBUG, "Initializing SDRAM Row %u\n", row); /* NOP command */ - PRINT_DEBUG(" NOP "); + PRINTK_DEBUG(" NOP\n"); do_ram_command(RAM_COMMAND_NOP); ram_read32(dimm_start, 0); udelay(200); /* Pre-charge all banks (at least 200 us after NOP) */ - PRINT_DEBUG(" Pre-charging all banks "); + PRINTK_DEBUG(" Pre-charging all banks\n"); do_ram_command(RAM_COMMAND_PRECHARGE); ram_read32(dimm_start, 0); udelay(1); /* 8 CBR refreshes (Auto Refresh) */ - PRINT_DEBUG(" 8 CBR refreshes "); + PRINTK_DEBUG(" 8 CBR refreshes\n"); for (i = 0; i < 8; i++) { do_ram_command(RAM_COMMAND_CBR); ram_read32(dimm_start, 0); @@ -164,19 +138,19 @@ /* MRS command */ /* TODO: Set offset 0x1d0 according to DRT values */ - PRINT_DEBUG(" MRS "); + PRINTK_DEBUG(" MRS\n"); do_ram_command(RAM_COMMAND_MRS); ram_read32(dimm_start, 0x1d0); udelay(2); /* Set GMCH-M Mode Select bits back to NORMAL operation mode */ - PRINT_DEBUG(" Normal operation mode "); + PRINTK_DEBUG(" Normal operation mode\n"); do_ram_command(RAM_COMMAND_NORMAL); ram_read32(dimm_start, 0); udelay(1); /* Perform a dummy memory read/write cycle */ - PRINT_DEBUG(" Performing dummy read/write\n"); + PRINTK_DEBUG(" Performing dummy read/write\n"); ram_read32(dimm_start, 0x55aa55aa); udelay(1); } @@ -253,30 +227,22 @@ /* First check if a DIMM is actually present. */ if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) { - print_debug("Found DIMM in slot "); - print_debug_hex8(i); - print_debug("\n"); - + printk(BIOS_DEBUG, "Found DIMM in slot %u\n", i); sz = spd_get_dimm_size(device); - - /* WISHLIST: would be nice to display it as decimal? */ - print_debug("DIMM is 0x"); - print_debug_hex16(sz.side1); - print_debug(" on side 1\n"); - print_debug("DIMM is 0x"); - print_debug_hex16(sz.side2); - print_debug(" on side 2\n"); + printk(BIOS_DEBUG, " DIMM is %uMB on side 1\n", sz.side1); + printk(BIOS_DEBUG, " DIMM is %uMB on side 2\n", sz.side2); /* - Memory compatibility checks - */ + /* Test for PC133 (i82830 only supports PC133) */ /* PC133 SPD9 - cycle time is always 75 */ if (spd_read_byte(device, SPD_MIN_CYCLE_TIME_AT_CAS_MAX) != 0x75) { - print_err("SPD9 DIMM Is Not PC133 Compatable\n"); + printk(BIOS_ERR, "SPD9 DIMM Is Not PC133 Compatable\n"); die("HALT\n"); } /* PC133 SPD10 - access time is always 54 */ if (spd_read_byte(device, SPD_ACCESS_TIME_FROM_CLOCK) != 0x54) { - print_err("SPD10 DIMM Is Not PC133 Compatable\n"); + printk(BIOS_ERR, "SPD10 DIMM Is Not PC133 Compatable\n"); die("HALT\n"); } @@ -285,22 +251,20 @@ * side or larger than 256MB per side. */ if ((sz.side2 != 0) && (sz.side1 != sz.side2)) { - print_err("This northbridge only supports\n"); - print_err("symmetrical dual-sided DIMMs\n"); - print_err("booting as a single-sided DIMM\n"); + printk(BIOS_ERR, "This northbridge only supports\n"); + printk(BIOS_ERR, "symmetrical dual-sided DIMMs\n"); + printk(BIOS_ERR, "booting as a single-sided DIMM\n"); sz.side2 = 0; } if ((sz.side1 < 32)) { - print_err("DIMMs smaller than 32MB per side\n"); - print_err("are not supported on this northbridge\n"); + printk(BIOS_ERR, "DIMMs smaller than 32MB per side\n"); + printk(BIOS_ERR, "are not supported on this northbridge\n"); die("HALT\n"); } if ((sz.side1 > 256)) { - print_err - ("DIMMs larger than 256MB per side\n"); - print_err - ("are not supported on this northbridge\n"); + printk(BIOS_ERR, "DIMMs larger than 256MB per side\n"); + printk(BIOS_ERR, "are not supported on this northbridge\n"); die("HALT\n"); } /* - End Memory compatibility checks - */ @@ -313,9 +277,7 @@ if (sz.side2) drb2 = sz.side2 / 32; } else { - PRINT_DEBUG("No DIMM found in slot "); - PRINT_DEBUG_HEX8(i); - PRINT_DEBUG("\n"); + printk(BIOS_DEBUG, "No DIMM found in slot %u\n", i); /* If there's no DIMM in the slot, set value to 0. */ drb1 = 0; @@ -325,30 +287,14 @@ if (i == 0) { pci_write_config8(NORTHBRIDGE, DRB, drb1); pci_write_config8(NORTHBRIDGE, DRB + 1, drb1 + drb2); - PRINT_DEBUG("DRB 0x"); - PRINT_DEBUG_HEX8(DRB); - PRINT_DEBUG(" has been set to 0x"); - PRINT_DEBUG_HEX8(drb1); - PRINT_DEBUG("\n"); - PRINT_DEBUG("DRB1 0x"); - PRINT_DEBUG_HEX8(DRB + 1); - PRINT_DEBUG(" has been set to 0x"); - PRINT_DEBUG_HEX8(drb1 + drb2); - PRINT_DEBUG("\n"); + PRINTK_DEBUG(" DRB 0x%02x has been set to 0x%02x\n", DRB, drb1); + PRINTK_DEBUG(" DRB1 0x%02x has been set to 0x%02x\n", DRB + 1, drb1 + drb2); } else if (i == 1) { value = pci_read_config8(NORTHBRIDGE, DRB + 1); pci_write_config8(NORTHBRIDGE, DRB + 2, value + drb1); pci_write_config8(NORTHBRIDGE, DRB + 3, value + drb1 + drb2); - PRINT_DEBUG("DRB2 0x"); - PRINT_DEBUG_HEX8(DRB + 2); - PRINT_DEBUG(" has been set to 0x"); - PRINT_DEBUG_HEX8(value + drb1); - PRINT_DEBUG("\n"); - PRINT_DEBUG("DRB3 0x"); - PRINT_DEBUG_HEX8(DRB + 3); - PRINT_DEBUG(" has been set to 0x"); - PRINT_DEBUG_HEX8(value + drb1 + drb2); - PRINT_DEBUG("\n"); + PRINTK_DEBUG(" DRB2 0x%02x has been set to 0x%02x\n", DRB + 2, value + drb1); + PRINTK_DEBUG(" DRB3 0x%02x has been set to 0x%02x\n", DRB + 3, value + drb1 + drb2); /* We need to set the highest DRB value to 0x64 and 0x65. * These are supposed to be "Reserved" but memory will @@ -371,9 +317,7 @@ /* First check if a DIMM is actually present. */ if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) { - print_debug("Found DIMM in slot "); - print_debug_hex8(i); - print_debug(", setting DRA...\n"); + PRINTK_DEBUG("Found DIMM in slot %u\n", i); dra = 0x00; @@ -402,7 +346,7 @@ } else if (dra == 16) { dra = 0xF3; /* 16KB */ } else { - print_err("Page size not supported\n"); + printk(BIOS_ERR, "Page size not supported\n"); die("HALT\n"); } } else if (value == 2) { @@ -415,18 +359,16 @@ } else if (dra == 16) { dra = 0x33; /* 16KB */ } else { - print_err("Page size not supported\n"); + printk(BIOS_ERR, "Page size not supported\n"); die("HALT\n"); } } else { - print_err("# of banks of DIMM not supported\n"); + printk(BIOS_ERR, "# of banks of DIMM not supported\n"); die("HALT\n"); } } else { - PRINT_DEBUG("No DIMM found in slot "); - PRINT_DEBUG_HEX8(i); - PRINT_DEBUG(", setting DRA to 0xFF\n"); + PRINTK_DEBUG("No DIMM found in slot %u\n", i); /* If there's no DIMM in the slot, set dra value to 0xFF. */ dra = 0xFF; @@ -434,11 +376,7 @@ /* Set the value for DRAM Row Attribute Registers */ pci_write_config8(NORTHBRIDGE, DRA + i, dra); - PRINT_DEBUG("DRA 0x"); - PRINT_DEBUG_HEX8(DRA + i); - PRINT_DEBUG(" has been set to 0x"); - PRINT_DEBUG_HEX8(dra); - PRINT_DEBUG("\n"); + PRINTK_DEBUG(" DRA 0x%02x has been set to 0x%02x\n", DRA + i, dra); } } @@ -467,7 +405,7 @@ static void sdram_set_registers(void) { - PRINT_DEBUG("Setting initial sdram registers....\n"); + PRINTK_DEBUG("Setting initial sdram registers....\n"); /* Calculate the value for DRT DRAM Timing Register */ set_dram_timing(); @@ -481,7 +419,7 @@ /* Setup DRAM Row Attribute Registers */ set_dram_row_attributes(); - PRINT_DEBUG("Initial sdram registers have been set.\n"); + PRINTK_DEBUG("Initial sdram registers have been set.\n"); } static void northbridge_set_registers(void) @@ -489,7 +427,7 @@ u16 value; int igd_memory = 0; - PRINT_DEBUG("Setting initial nothbridge registers....\n"); + PRINTK_DEBUG("Setting initial nothbridge registers....\n"); /* Set the value for Fixed DRAM Hole Control Register */ pci_write_config8(NORTHBRIDGE, FDHC, 0x00); @@ -535,7 +473,7 @@ value |= 1; // 64MB aperture pci_write_config16(NORTHBRIDGE, GCC1, value); - PRINT_DEBUG("Initial northbridge registers have been set.\n"); + PRINTK_DEBUG("Initial northbridge registers have been set.\n"); } static void sdram_initialize(void) @@ -545,20 +483,20 @@ /* Setup Initial SDRAM Registers */ sdram_set_registers(); - /* 0. Wait until power/voltages and clocks are stable (200us). */ + /* Wait until power/voltages and clocks are stable (200us). */ udelay(200); /* Initialize each row of memory one at a time */ initialize_dimm_rows(); /* Enable Refresh */ - PRINT_DEBUG("Enabling Refresh\n"); + PRINTK_DEBUG("Enabling Refresh\n"); reg32 = pci_read_config32(NORTHBRIDGE, DRC); reg32 |= (RAM_COMMAND_REFRESH << 8); pci_write_config32(NORTHBRIDGE, DRC, reg32); /* Set initialization complete */ - PRINT_DEBUG("Setting initialization complete\n"); + PRINTK_DEBUG("Setting initialization complete\n"); reg32 = pci_read_config32(NORTHBRIDGE, DRC); reg32 |= (RAM_COMMAND_IC << 29); pci_write_config32(NORTHBRIDGE, DRC, reg32); @@ -566,6 +504,6 @@ /* Setup Initial Northbridge Registers */ northbridge_set_registers(); - PRINT_DEBUG("Northbridge following SDRAM init:\n"); + PRINTK_DEBUG("Northbridge following SDRAM init:\n"); DUMPNORTH(); }

3 7

← Newer
1
...
26
27
28
29
30
31
32
...
41
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot April 2010