coreboot April 2010

coreboot@coreboot.org

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[commit] r5393 - in trunk/src: arch/i386/lib cpu/x86/car mainboard/dell/s1850 mainboard/intel/jarrell mainboard/intel/mtarvon mainboard/intel/truxton mainboard/supermicro/x6dai_g mainboard/supermic...
by repository service 09 Apr '10

09 Apr '10

Author: stepan Date: Fri Apr 9 15:33:59 2010 New Revision: 5393 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5393 Log: Drop the need for cpu_reset, it's really just a short cut to stage2. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/src/arch/i386/lib/stages.c Modified: trunk/src/cpu/x86/car/cache_as_ram.lds trunk/src/mainboard/dell/s1850/romstage.c trunk/src/mainboard/intel/jarrell/romstage.c trunk/src/mainboard/intel/mtarvon/romstage.c trunk/src/mainboard/intel/truxton/romstage.c trunk/src/mainboard/supermicro/x6dai_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Added: trunk/src/arch/i386/lib/stages.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/arch/i386/lib/stages.c Fri Apr 9 15:33:59 2010 (r5393) @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +static void skip_romstage(void) +{ + asm volatile ( + "/* set the boot_complete flag */\n" + "movl $0xffffffff, %%ebp\n" + "jmp __main\n" + ); +} + Modified: trunk/src/cpu/x86/car/cache_as_ram.lds ============================================================================== --- trunk/src/cpu/x86/car/cache_as_ram.lds Fri Apr 9 15:31:07 2010 (r5392) +++ trunk/src/cpu/x86/car/cache_as_ram.lds Fri Apr 9 15:33:59 2010 (r5393) @@ -5,8 +5,7 @@ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. + * the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of Modified: trunk/src/mainboard/dell/s1850/romstage.c ============================================================================== --- trunk/src/mainboard/dell/s1850/romstage.c Fri Apr 9 15:31:07 2010 (r5392) +++ trunk/src/mainboard/dell/s1850/romstage.c Fri Apr 9 15:33:59 2010 (r5393) @@ -157,6 +157,8 @@ /* end IPMI garbage */ +#include "arch/i386/lib/stages.c" + static void main(unsigned long bist) { u8 b; @@ -277,7 +279,7 @@ /* Skip this if there was a built in self test failure */ early_mtrr_init(); if (memory_initialized()) { - asm volatile ("jmp __cpu_reset"); + skip_romstage(); } } /* Setup the console */ Modified: trunk/src/mainboard/intel/jarrell/romstage.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/romstage.c Fri Apr 9 15:31:07 2010 (r5392) +++ trunk/src/mainboard/intel/jarrell/romstage.c Fri Apr 9 15:33:59 2010 (r5393) @@ -50,6 +50,7 @@ #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" #include "debug.c" +#include "arch/i386/lib/stages.c" static void main(unsigned long bist) { @@ -75,7 +76,7 @@ /* Skip this if there was a built in self test failure */ early_mtrr_init(); if (memory_initialized()) { - asm volatile ("jmp __cpu_reset"); + skip_romstage(); } } /* Setup the console */ Modified: trunk/src/mainboard/intel/mtarvon/romstage.c ============================================================================== --- trunk/src/mainboard/intel/mtarvon/romstage.c Fri Apr 9 15:31:07 2010 (r5392) +++ trunk/src/mainboard/intel/mtarvon/romstage.c Fri Apr 9 15:33:59 2010 (r5393) @@ -58,6 +58,7 @@ #include "northbridge/intel/i3100/raminit.c" #include "lib/generic_sdram.c" #include "../jarrell/debug.c" +#include "arch/i386/lib/stages.c" static void main(unsigned long bist) { @@ -79,7 +80,7 @@ /* Skip this if there was a built in self test failure */ early_mtrr_init(); if (memory_initialized()) { - asm volatile ("jmp __cpu_reset"); + skip_romstage(); } } /* Set up the console */ Modified: trunk/src/mainboard/intel/truxton/romstage.c ============================================================================== --- trunk/src/mainboard/intel/truxton/romstage.c Fri Apr 9 15:31:07 2010 (r5392) +++ trunk/src/mainboard/intel/truxton/romstage.c Fri Apr 9 15:33:59 2010 (r5393) @@ -58,6 +58,7 @@ #include "northbridge/intel/i3100/raminit_ep80579.c" #include "lib/generic_sdram.c" #include "../../intel/jarrell/debug.c" +#include "arch/i386/lib/stages.c" /* #define TRUXTON_DEBUG */ @@ -77,7 +78,7 @@ /* Skip this if there was a built in self test failure */ early_mtrr_init(); if (memory_initialized()) { - asm volatile ("jmp __cpu_reset"); + skip_romstage(); } } Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/romstage.c Fri Apr 9 15:31:07 2010 (r5392) +++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c Fri Apr 9 15:33:59 2010 (r5393) @@ -51,6 +51,7 @@ #include "northbridge/intel/e7525/raminit.c" #include "lib/generic_sdram.c" +#include "arch/i386/lib/stages.c" static void main(unsigned long bist) { @@ -74,7 +75,7 @@ /* Skip this if there was a built in self test failure */ early_mtrr_init(); if (memory_initialized()) { - asm volatile ("jmp __cpu_reset"); + skip_romstage(); } } /* Setup the console */ Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Fri Apr 9 15:31:07 2010 (r5392) +++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Fri Apr 9 15:33:59 2010 (r5393) @@ -52,6 +52,7 @@ #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" +#include "arch/i386/lib/stages.c" static void main(unsigned long bist) { @@ -77,7 +78,7 @@ /* Skip this if there was a built in self test failure */ early_mtrr_init(); if (memory_initialized()) { - asm volatile ("jmp __cpu_reset"); + skip_romstage(); } } /* Setup the console */ Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Fri Apr 9 15:31:07 2010 (r5392) +++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Fri Apr 9 15:33:59 2010 (r5393) @@ -52,6 +52,7 @@ #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" +#include "arch/i386/lib/stages.c" static void main(unsigned long bist) { @@ -78,7 +79,7 @@ /* Skip this if there was a built in self test failure */ early_mtrr_init(); if (memory_initialized()) { - asm volatile ("jmp __cpu_reset"); + skip_romstage(); } } /* Setup the console */ Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Fri Apr 9 15:31:07 2010 (r5392) +++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Fri Apr 9 15:33:59 2010 (r5393) @@ -53,6 +53,7 @@ #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" +#include "arch/i386/lib/stages.c" static void main(unsigned long bist) { @@ -78,7 +79,7 @@ /* Skip this if there was a built in self test failure */ early_mtrr_init(); if (memory_initialized()) { - asm volatile ("jmp __cpu_reset"); + skip_romstage(); } } /* Setup the console */ Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Fri Apr 9 15:31:07 2010 (r5392) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Fri Apr 9 15:33:59 2010 (r5393) @@ -53,6 +53,7 @@ #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" +#include "arch/i386/lib/stages.c" static void main(unsigned long bist) { @@ -78,7 +79,7 @@ /* Skip this if there was a built in self test failure */ early_mtrr_init(); if (memory_initialized()) { - asm volatile ("jmp __cpu_reset"); + skip_romstage(); } } /* Setup the console */

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[commit] r5392 - in trunk/src/cpu: amd/car amd/dualcore x86/16bit x86/32bit x86/car
by repository service 09 Apr '10

09 Apr '10

Author: stepan Date: Fri Apr 9 15:31:07 2010 New Revision: 5392 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5392 Log: drop unused files drop some non-car code from amd/dualcore (there is no AMD dualcore without CAR) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Deleted: trunk/src/cpu/amd/car/cache_as_ram.lds trunk/src/cpu/x86/32bit/reset32.inc trunk/src/cpu/x86/32bit/reset32.lds Modified: trunk/src/cpu/amd/car/post_cache_as_ram.c trunk/src/cpu/amd/dualcore/dualcore.c trunk/src/cpu/x86/16bit/entry16.lds trunk/src/cpu/x86/car/cache_as_ram.lds Modified: trunk/src/cpu/amd/car/post_cache_as_ram.c ============================================================================== --- trunk/src/cpu/amd/car/post_cache_as_ram.c Fri Apr 9 13:55:43 2010 (r5391) +++ trunk/src/cpu/amd/car/post_cache_as_ram.c Fri Apr 9 15:31:07 2010 (r5392) @@ -1,6 +1,7 @@ /* 2005.6 by yhlu * 2006.3 yhlu add copy data from CAR to ram */ +#include <arch/stages.h> #include "cpu/amd/car/disable_cache_as_ram.c" static inline void print_debug_pcar(const char *strval, uint32_t val) Modified: trunk/src/cpu/amd/dualcore/dualcore.c ============================================================================== --- trunk/src/cpu/amd/dualcore/dualcore.c Fri Apr 9 13:55:43 2010 (r5391) +++ trunk/src/cpu/amd/dualcore/dualcore.c Fri Apr 9 15:31:07 2010 (r5392) @@ -70,95 +70,5 @@ } } -#if CONFIG_USE_DCACHE_RAM == 0 -static void do_k8_init_and_stop_secondaries(void) -{ - struct node_core_id id; - device_t dev; - unsigned apicid; - unsigned max_siblings; - msr_t msr; - - /* Skip this if there was a built in self test failure */ - if (is_cpu_pre_e0()) { - id.nodeid = lapicid() & 0x7; - id.coreid = 0; - } else { - /* Which cpu are we on? */ - id = get_node_core_id_x(); - /* Set NB_CFG_MSR - * Linux expect the core to be in the least signficant bits. - */ - msr = rdmsr(NB_CFG_MSR); - msr.hi |= (1<<(54-32)); // InitApicIdCpuIdLo - wrmsr(NB_CFG_MSR, msr); - } - - /* For now assume all cpus have the same number of siblings */ - max_siblings = (cpuid_ecx(0x80000008) & 0xff) + 1; - - /* Enable extended apic ids */ - device_t dev_f0 = PCI_DEV(0, 0x18+id.nodeid, 0); - unsigned val = pci_read_config32(dev_f0, 0x68); - val |= (1 << 18) | (1 << 17); - pci_write_config32(dev_f0, 0x68, val); - - /* Set the lapicid */ - #if (CONFIG_ENABLE_APIC_EXT_ID == 1) - unsigned initial_apicid = get_initial_apicid(); - #if CONFIG_LIFT_BSP_APIC_ID == 0 - if( initial_apicid != 0 ) // other than bsp - #endif - { - /* use initial apic id to lift it */ - uint32_t dword = lapic_read(LAPIC_ID); - dword &= ~(0xff<<24); - dword |= (((initial_apicid + CONFIG_APIC_ID_OFFSET) & 0xff)<<24); - - lapic_write(LAPIC_ID, dword); - } - - #if CONFIG_LIFT_BSP_APIC_ID == 1 - bsp_apicid += CONFIG_APIC_ID_OFFSET; - #endif - - #endif - - - /* Remember the cpuid */ - if (id.coreid == 0) { - dev = PCI_DEV(0, 0x18 + id.nodeid, 2); - pci_write_config32(dev, 0x9c, cpuid_eax(1)); - } - - /* Maybe call distinguish_cpu_resets only on the last core? */ - distinguish_cpu_resets(id.nodeid); - if (!boot_cpu()) { - stop_this_cpu(); - } -} - -static void k8_init_and_stop_secondaries(void) -{ - /* This doesn't work with Cache As Ram because it messes with - the MTRR state, which breaks the init detection. - do_k8_init_and_stop_secondaries should be usable by CAR code. - */ - - int init_detected; - - init_detected = early_mtrr_init_detected(); - amd_early_mtrr_init(); - - enable_lapic(); - init_timer(); - if (init_detected) { - asm volatile ("jmp __cpu_reset"); - } - - do_k8_init_and_stop_secondaries(); -} - -#endif Modified: trunk/src/cpu/x86/16bit/entry16.lds ============================================================================== --- trunk/src/cpu/x86/16bit/entry16.lds Fri Apr 9 13:55:43 2010 (r5391) +++ trunk/src/cpu/x86/16bit/entry16.lds Fri Apr 9 15:31:07 2010 (r5392) @@ -1,2 +1 @@ gdtptr16_offset = gdtptr16 & 0xffff; - _start_offset = _start & 0xffff; Modified: trunk/src/cpu/x86/car/cache_as_ram.lds ============================================================================== --- trunk/src/cpu/x86/car/cache_as_ram.lds Fri Apr 9 13:55:43 2010 (r5391) +++ trunk/src/cpu/x86/car/cache_as_ram.lds Fri Apr 9 15:31:07 2010 (r5392) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Stefan Reinauer + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + SECTIONS { .init . : { _init = .; @@ -7,5 +27,4 @@ . = ALIGN(16); _einit = .; } - }

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[commit] r5391 - in trunk/src/mainboard/amd: dbm690t mahogany pistachio
by repository service 09 Apr '10

09 Apr '10

Author: stepan Date: Fri Apr 9 13:55:43 2010 New Revision: 5391 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5391 Log: remove some amd mainboard warnings. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/amd/dbm690t/acpi_tables.c trunk/src/mainboard/amd/dbm690t/mainboard.c trunk/src/mainboard/amd/mahogany/get_bus_conf.c trunk/src/mainboard/amd/pistachio/mainboard.c Modified: trunk/src/mainboard/amd/dbm690t/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/acpi_tables.c Fri Apr 9 13:37:58 2010 (r5390) +++ trunk/src/mainboard/amd/dbm690t/acpi_tables.c Fri Apr 9 13:55:43 2010 (r5391) @@ -92,8 +92,6 @@ return current; } - - static void update_ssdtx(void *ssdtx, int i) { uint8_t *PCI; Modified: trunk/src/mainboard/amd/dbm690t/mainboard.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/mainboard.c Fri Apr 9 13:37:58 2010 (r5390) +++ trunk/src/mainboard/amd/dbm690t/mainboard.c Fri Apr 9 13:55:43 2010 (r5391) @@ -22,6 +22,7 @@ #include <device/pci.h> #include <arch/io.h> #include <boot/coreboot_tables.h> +#include <arch/coreboot_tables.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> @@ -57,7 +58,7 @@ * RRG4.2.3.1 GPM pins as Input * RRG4.2.3.2 GPM pins as Output ********************************************************/ -static void enable_onboard_nic() +static void enable_onboard_nic(void) { u8 byte; @@ -94,7 +95,7 @@ * IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to * get the cable type, 40 pin or 80 pin? ********************************************************/ -static void get_ide_dma66() +static void get_ide_dma66(void) { u8 byte; struct device *sm_dev; @@ -120,7 +121,7 @@ /* * set thermal config */ -static void set_thermal_config() +static void set_thermal_config(void) { u8 byte; u16 word; @@ -185,11 +186,8 @@ * enable the dedicated function in dbm690t board. * This function called early than rs690_enable. *************************************************/ -void dbm690t_enable(device_t dev) +static void dbm690t_enable(device_t dev) { - struct mainboard_config *mainboard = - (struct mainboard_config *)dev->chip_info; - printk(BIOS_INFO, "Mainboard DBM690T Enable. dev=0x%p\n", dev); #if (CONFIG_GFXUMA == 1) @@ -249,6 +247,7 @@ lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); #endif + return 0; } struct chip_operations mainboard_ops = { Modified: trunk/src/mainboard/amd/mahogany/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/get_bus_conf.c Fri Apr 9 13:37:58 2010 (r5390) +++ trunk/src/mainboard/amd/mahogany/get_bus_conf.c Fri Apr 9 13:55:43 2010 (r5391) @@ -63,8 +63,6 @@ static u32 get_bus_conf_done = 0; -void get_bus_conf(void); - void get_bus_conf(void) { u32 apicid_base; Modified: trunk/src/mainboard/amd/pistachio/mainboard.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/mainboard.c Fri Apr 9 13:37:58 2010 (r5390) +++ trunk/src/mainboard/amd/pistachio/mainboard.c Fri Apr 9 13:55:43 2010 (r5391) @@ -22,6 +22,7 @@ #include <device/pci.h> #include <arch/io.h> #include <boot/coreboot_tables.h> +#include <arch/coreboot_tables.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> @@ -57,7 +58,7 @@ * The R77 (on BRASS) / R81 (on Bronze) is not load! * So NIC can work whether this function runs. ********************************************************/ -static void enable_onboard_nic() +static void enable_onboard_nic(void) { u8 byte; @@ -77,7 +78,7 @@ /* * set thermal config */ -static void set_thermal_config() +static void set_thermal_config(void) { u8 byte, byte2; u16 word; @@ -256,11 +257,8 @@ * enable the dedicated function in pistachio board. * This function called early than rs690_enable. *************************************************/ -void pistachio_enable(device_t dev) +static void pistachio_enable(device_t dev) { - struct mainboard_config *mainboard = - (struct mainboard_config *)dev->chip_info; - printk(BIOS_INFO, "Mainboard Pistachio Enable. dev=0x%p\n", dev); #if (CONFIG_GFXUMA == 1) @@ -320,6 +318,7 @@ lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); #endif + return 0; } struct chip_operations mainboard_ops = {

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Will coreboot work on my machine?
by Помыткин Илья 09 Apr '10

09 Apr '10

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[commit] r5390 - in trunk/src/arch/i386: init lib
by repository service 09 Apr '10

09 Apr '10

Author: stepan Date: Fri Apr 9 13:37:58 2010 New Revision: 5390 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5390 Log: drop unused files, and we only use ASM_LOG_LEVEL in one file now (LX CAR) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Deleted: trunk/src/arch/i386/lib/jmp_auto.inc trunk/src/arch/i386/lib/jmp_auto_out.inc trunk/src/arch/i386/lib/noop_failover.inc Modified: trunk/src/arch/i386/init/crt0_prologue.inc Modified: trunk/src/arch/i386/init/crt0_prologue.inc ============================================================================== --- trunk/src/arch/i386/init/crt0_prologue.inc Fri Apr 9 13:34:59 2010 (r5389) +++ trunk/src/arch/i386/init/crt0_prologue.inc Fri Apr 9 13:37:58 2010 (r5390) @@ -6,18 +6,13 @@ * published by the Free Software Foundation; version 2 of the License. */ - #include <arch/asm.h> #include <arch/intel.h> #include <console/loglevel.h> -#ifndef ASM_CONSOLE_LOGLEVEL -#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL -#endif - /* - * This is the entry code the code in .reset section - * jumps to this address. + * This is the entry code. + * The code in the .reset section jumps to this address. * */ .section ".rom.data", "a", @progbits

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[commit] r5389 - in trunk/src: northbridge/intel/i440bx northbridge/intel/i440lx northbridge/intel/i82810 northbridge/intel/i82830 northbridge/via/cn400 northbridge/via/cn700 northbridge/via/cx700 ...
by repository service 09 Apr '10

09 Apr '10

Author: stepan Date: Fri Apr 9 13:34:59 2010 New Revision: 5389 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5389 Log: zero warning days. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/intel/i440bx/raminit.c trunk/src/northbridge/intel/i440lx/raminit.c trunk/src/northbridge/intel/i82810/raminit.c trunk/src/northbridge/intel/i82830/raminit.c trunk/src/northbridge/via/cn400/raminit.c trunk/src/northbridge/via/cn700/raminit.c trunk/src/northbridge/via/cx700/raminit.c trunk/src/northbridge/via/vx800/raminit.c trunk/src/southbridge/amd/rs690/rs690_gfx.c trunk/src/southbridge/amd/sb600/sb600_reset.c trunk/src/southbridge/amd/sb700/sb700_early_setup.c Modified: trunk/src/northbridge/intel/i440bx/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i440bx/raminit.c Fri Apr 9 13:10:25 2010 (r5388) +++ trunk/src/northbridge/intel/i440bx/raminit.c Fri Apr 9 13:34:59 2010 (r5389) @@ -20,7 +20,6 @@ */ #include <spd.h> -#include <sdram_mode.h> #include <delay.h> #include <stdlib.h> #include "i440bx.h" Modified: trunk/src/northbridge/intel/i440lx/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i440lx/raminit.c Fri Apr 9 13:10:25 2010 (r5388) +++ trunk/src/northbridge/intel/i440lx/raminit.c Fri Apr 9 13:34:59 2010 (r5389) @@ -20,7 +20,6 @@ */ #include <spd.h> -#include <sdram_mode.h> #include <delay.h> #include <stdlib.h> #include "i440lx.h" Modified: trunk/src/northbridge/intel/i82810/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i82810/raminit.c Fri Apr 9 13:10:25 2010 (r5388) +++ trunk/src/northbridge/intel/i82810/raminit.c Fri Apr 9 13:34:59 2010 (r5389) @@ -21,7 +21,6 @@ */ #include <spd.h> -#include <sdram_mode.h> #include <delay.h> #include "i82810.h" Modified: trunk/src/northbridge/intel/i82830/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i82830/raminit.c Fri Apr 9 13:10:25 2010 (r5388) +++ trunk/src/northbridge/intel/i82830/raminit.c Fri Apr 9 13:34:59 2010 (r5389) @@ -20,7 +20,6 @@ */ #include <spd.h> -#include <sdram_mode.h> #include <delay.h> #include "lib/debug.c" #include "i82830.h" Modified: trunk/src/northbridge/via/cn400/raminit.c ============================================================================== --- trunk/src/northbridge/via/cn400/raminit.c Fri Apr 9 13:10:25 2010 (r5388) +++ trunk/src/northbridge/via/cn400/raminit.c Fri Apr 9 13:34:59 2010 (r5389) @@ -29,7 +29,6 @@ /* ported from Via VT8263 Code*/ #include <spd.h> -#include <sdram_mode.h> #include <delay.h> #include <cpu/x86/mtrr.h> #include "cn400.h" Modified: trunk/src/northbridge/via/cn700/raminit.c ============================================================================== --- trunk/src/northbridge/via/cn700/raminit.c Fri Apr 9 13:10:25 2010 (r5388) +++ trunk/src/northbridge/via/cn700/raminit.c Fri Apr 9 13:34:59 2010 (r5389) @@ -21,7 +21,6 @@ */ #include <spd.h> -#include <sdram_mode.h> #include <delay.h> #include "cn700.h" Modified: trunk/src/northbridge/via/cx700/raminit.c ============================================================================== --- trunk/src/northbridge/via/cx700/raminit.c Fri Apr 9 13:10:25 2010 (r5388) +++ trunk/src/northbridge/via/cx700/raminit.c Fri Apr 9 13:34:59 2010 (r5389) @@ -20,7 +20,6 @@ #include <types.h> #include <spd.h> #include <spd_ddr2.h> -#include <sdram_mode.h> #include <delay.h> #include "cx700_registers.h" Modified: trunk/src/northbridge/via/vx800/raminit.c ============================================================================== --- trunk/src/northbridge/via/vx800/raminit.c Fri Apr 9 13:10:25 2010 (r5388) +++ trunk/src/northbridge/via/vx800/raminit.c Fri Apr 9 13:34:59 2010 (r5389) @@ -18,7 +18,6 @@ */ #include <spd.h> -#include <sdram_mode.h> #include <delay.h> #if CONFIG_DEBUG_RAM_SETUP Modified: trunk/src/southbridge/amd/rs690/rs690_gfx.c ============================================================================== --- trunk/src/southbridge/amd/rs690/rs690_gfx.c Fri Apr 9 13:10:25 2010 (r5388) +++ trunk/src/southbridge/amd/rs690/rs690_gfx.c Fri Apr 9 13:34:59 2010 (r5389) @@ -34,6 +34,7 @@ #define CLK_CNTL_INDEX 0x8 #define CLK_CNTL_DATA 0xC +#if 0 static u32 clkind_read(device_t dev, u32 index) { u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF; @@ -41,6 +42,7 @@ *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index & 0x7F; return *(u32*)(gfx_bar2+CLK_CNTL_DATA); } +#endif static void clkind_write(device_t dev, u32 index, u32 data) { @@ -73,8 +75,6 @@ static void internal_gfx_pci_dev_init(struct device *dev) { u16 deviceid, vendorid; - struct southbridge_amd_rs690_config *cfg = - (struct southbridge_amd_rs690_config *)dev->chip_info; deviceid = pci_read_config16(dev, PCI_DEVICE_ID); vendorid = pci_read_config16(dev, PCI_VENDOR_ID); printk(BIOS_INFO, "internal_gfx_pci_dev_init device=%x, vendor=%x.\n", Modified: trunk/src/southbridge/amd/sb600/sb600_reset.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_reset.c Fri Apr 9 13:10:25 2010 (r5388) +++ trunk/src/southbridge/amd/sb600/sb600_reset.c Fri Apr 9 13:34:59 2010 (r5389) @@ -18,39 +18,10 @@ */ #include <arch/io.h> +#include <arch/romcc_io.h> +#include <reset.h> -#define PCI_DEV(BUS, DEV, FN) ( \ - (((BUS) & 0xFFF) << 20) | \ - (((DEV) & 0x1F) << 15) | \ - (((FN) & 0x7) << 12)) - -typedef u32 device_t; - -static void pci_write_config8(device_t dev, unsigned where, unsigned char value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outb(value, 0xCFC + (addr & 3)); -} - -static void pci_write_config32(device_t dev, unsigned where, unsigned value) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - outl(value, 0xCFC); -} - -static unsigned pci_read_config32(device_t dev, unsigned where) -{ - unsigned addr; - addr = (dev>>4) | where; - outl(0x80000000 | (addr & ~3), 0xCF8); - return inl(0xCFC); -} - -#include "../../../northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/reset_test.c" void hard_reset(void) { Modified: trunk/src/southbridge/amd/sb700/sb700_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb700/sb700_early_setup.c Fri Apr 9 13:10:25 2010 (r5388) +++ trunk/src/southbridge/amd/sb700/sb700_early_setup.c Fri Apr 9 13:34:59 2010 (r5389) @@ -20,6 +20,7 @@ #ifndef _SB700_EARLY_SETUP_C_ #define _SB700_EARLY_SETUP_C_ +#include <reset.h> #include <arch/cpu.h> #include "sb700.h" #include "sb700_smbus.c" @@ -214,7 +215,7 @@ pmio_write(0x89, 0x10); } -static void hard_reset(void) +void hard_reset(void) { set_bios_reset(); @@ -223,7 +224,7 @@ outb(0x0e, 0x0cf9); } -static void soft_reset(void) +void soft_reset(void) { set_bios_reset(); /* link reset */

1 0

memset called to somewhere high on the stack (uncached)
by Myles Watson 09 Apr '10

09 Apr '10

I'm seeing code reads to memset() in coreboot_ram interleaved with byte writes to somewhere high on the stack (_estack -0x1fC). This is a k8. I can't find the place during the RAM stage when we are calling memset with caches disabled. Does this ring a bell for anyone? Thanks, Myles

4 8

[PATCH] CAR on Intel P6 Series - Support for model_6bx
by Joseph Smith 09 Apr '10

09 Apr '10

Hello, 1. This patch adds CAR for Intel P6 series processors. 2. Add support for Micro-FCBGA 479 Celeron and PIII's 3. Add support for model_6bx and microcode updates 4. Add support for CAR and Tinybootblock on RCA RM4100 and Thomson IP1000 Build and boot tested (bootlog attached). Signed-off-by: Joseph Smith <joe(a)settoplinux.org> -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

4 12

build service results for r5387
by coreboot information 09 Apr '10

09 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5387 to the coreboot repository. This caused the following changes: Change Log: copy_and_run.c is not needed twice, and it is used on non-car too. So move it to src/arch/i386/lib/cbfs_and_run.c Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of a-trend:atc-6220 has been fixed Compilation of a-trend:atc-6240 has been fixed Compilation of abit:be6-ii_v2_0 has been fixed Compilation of advantech:pcm-5820 has been fixed Compilation of amd:rumba has been fixed Compilation of asi:mb_5blgp has been fixed Compilation of asi:mb_5blmp has been fixed Compilation of asus:mew-am has been fixed Compilation of asus:mew-vm has been fixed Compilation of asus:p2b has been fixed Compilation of asus:p2b-d has been fixed Compilation of asus:p2b-ds has been fixed Compilation of asus:p2b-f has been fixed Compilation of asus:p2b-ls has been fixed Compilation of asus:p3b-f has been fixed Compilation of axus:tc320 has been fixed Compilation of azza:pt-6ibd has been fixed Compilation of bcom:winnet100 has been fixed Compilation of biostar:m6tba has been fixed Compilation of compaq:deskpro_en_sff_p600 has been fixed Compilation of dell:s1850 has been fixed Compilation of digitallogic:adl855pc has been fixed Compilation of digitallogic:msm586seg has been fixed Compilation of eaglelion:5bcm has been fixed Compilation of emulation:qemu-x86 has been fixed Compilation of gigabyte:ga-6bxc has been fixed Compilation of hp:e_vectra_p2706t has been fixed Compilation of iei:juki-511p has been fixed Compilation of iei:nova4899r has been fixed Compilation of intel:jarrell has been fixed Compilation of intel:mtarvon has been fixed Compilation of intel:truxton has been fixed Compilation of intel:xe7501devkit has been fixed Compilation of lippert:frontrunner has been fixed Compilation of mitac:6513wu has been fixed Compilation of msi:ms6119 has been fixed Compilation of msi:ms6147 has been fixed Compilation of msi:ms6156 has been fixed Compilation of msi:ms6178 has been fixed Compilation of nec:powermate2000 has been fixed Compilation of olpc:btest has been fixed Compilation of olpc:rev_a has been fixed Compilation of rca:rm4100 has been fixed Compilation of soyo:sy-6ba-plus-iii has been fixed Compilation of supermicro:x6dai_g has been fixed Compilation of supermicro:x6dhe_g has been fixed Compilation of supermicro:x6dhe_g2 has been fixed Compilation of supermicro:x6dhr_ig has been fixed Compilation of supermicro:x6dhr_ig2 has been fixed Compilation of technologic:ts5300 has been fixed Compilation of televideo:tc7020 has been fixed Compilation of thomson:ip1000 has been fixed Compilation of tyan:s1846 has been fixed Compilation of via:epia has been fixed Compilation of via:epia-cn has been fixed Compilation of via:epia-m has been fixed Compilation of via:epia-n has been fixed Compilation of via:pc2500e has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5387 - in trunk/src: arch/i386/lib cpu/amd/car cpu/intel/model_106cx cpu/intel/model_6ex cpu/intel/model_6fx cpu/x86/car mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogan...
by repository service 09 Apr '10

09 Apr '10

Author: stepan Date: Fri Apr 9 12:43:49 2010 New Revision: 5387 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5387 Log: copy_and_run.c is not needed twice, and it is used on non-car too. So move it to src/arch/i386/lib/cbfs_and_run.c Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Deleted: trunk/src/cpu/amd/car/copy_and_run.c trunk/src/cpu/x86/car/copy_and_run.c Modified: trunk/src/arch/i386/lib/cbfs_and_run.c trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c trunk/src/cpu/intel/model_6fx/cache_as_ram_disable.c trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/pistachio/romstage.c trunk/src/mainboard/amd/serengeti_cheetah/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/arima/hdama/romstage.c trunk/src/mainboard/asrock/939a785gmh/romstage.c trunk/src/mainboard/asus/a8n_e/romstage.c trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/asus/m2v-mx_se/romstage.c trunk/src/mainboard/broadcom/blast/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/ibm/e325/romstage.c trunk/src/mainboard/ibm/e326/romstage.c trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/msi/ms7135/romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/newisys/khepri/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/sunw/ultra40/romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/romstage.c trunk/src/mainboard/tyan/s2735/romstage.c trunk/src/mainboard/tyan/s2850/romstage.c trunk/src/mainboard/tyan/s2875/romstage.c trunk/src/mainboard/tyan/s2880/romstage.c trunk/src/mainboard/tyan/s2881/romstage.c trunk/src/mainboard/tyan/s2882/romstage.c trunk/src/mainboard/tyan/s2885/romstage.c trunk/src/mainboard/tyan/s2891/romstage.c trunk/src/mainboard/tyan/s2892/romstage.c trunk/src/mainboard/tyan/s2895/romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/mainboard/tyan/s4880/romstage.c trunk/src/mainboard/tyan/s4882/romstage.c trunk/src/mainboard/via/epia-m700/romstage.c trunk/src/mainboard/via/vt8454c/romstage.c trunk/src/northbridge/via/vx800/examples/romstage.c Modified: trunk/src/arch/i386/lib/cbfs_and_run.c ============================================================================== --- trunk/src/arch/i386/lib/cbfs_and_run.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/arch/i386/lib/cbfs_and_run.c Fri Apr 9 12:43:49 2010 (r5387) @@ -40,3 +40,21 @@ :: "a"(ebp), "D"(dst) ); } + +void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset); + +void __attribute__((regparm(0))) copy_and_run(unsigned cpu_reset) +{ + // FIXME fix input parameters instead normalizing them here. + if (cpu_reset == 1) cpu_reset = -1; + else cpu_reset = 0; + + cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ram", cpu_reset); +} + +#if CONFIG_AP_CODE_IN_CAR == 1 +static void __attribute__((regparm(0))) copy_and_run_ap_code_in_car(unsigned ret_addr) +{ + cbfs_and_run_core(CONFIG_CBFS_PREFIX "/coreboot_ap", ret_addr); +} +#endif Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c ============================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram_disable.c Fri Apr 9 12:43:49 2010 (r5387) @@ -17,7 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include "cpu/x86/car/copy_and_run.c" + /* called from assembler code */ void stage1_main(unsigned long bist); Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram_disable.c Fri Apr 9 12:43:49 2010 (r5387) @@ -19,7 +19,7 @@ * MA 02110-1301 USA */ -#include "cpu/x86/car/copy_and_run.c" + /* called from assembler code */ void stage1_main(unsigned long bist); Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram_disable.c ============================================================================== --- trunk/src/cpu/intel/model_6fx/cache_as_ram_disable.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/cpu/intel/model_6fx/cache_as_ram_disable.c Fri Apr 9 12:43:49 2010 (r5387) @@ -19,7 +19,7 @@ * MA 02110-1301 USA */ -#include "cpu/x86/car/copy_and_run.c" + void real_main(unsigned long bist); Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -88,7 +88,7 @@ #include "cpu/amd/dualcore/dualcore.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/amd/mahogany/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -88,7 +88,7 @@ #include "cpu/amd/dualcore/dualcore.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -99,7 +99,7 @@ #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" Modified: trunk/src/mainboard/amd/pistachio/romstage.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/amd/pistachio/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -82,7 +82,7 @@ #include "cpu/amd/dualcore/dualcore.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -128,7 +128,7 @@ #define DIMM6 0x56 #define DIMM7 0x57 -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -117,7 +117,7 @@ #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" Modified: trunk/src/mainboard/arima/hdama/romstage.c ============================================================================== --- trunk/src/mainboard/arima/hdama/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/arima/hdama/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -86,7 +86,7 @@ #define SECOND_CPU 1 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -93,7 +93,7 @@ #include "cpu/amd/dualcore/dualcore.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/asus/a8n_e/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/asus/a8n_e/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -87,7 +87,7 @@ #include "lib/generic_sdram.c" #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" #include "southbridge/nvidia/ck804/ck804_early_setup.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -111,7 +111,7 @@ #include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/via/k8t890/k8t890_early_car.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -96,7 +96,7 @@ #include "northbridge/amd/amdk8/incoherent_ht.c" #include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/broadcom/blast/romstage.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/broadcom/blast/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -87,7 +87,7 @@ #define DIMM2 0x52 #define DIMM3 0x53 -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -134,7 +134,7 @@ #include "southbridge/sis/sis966/sis966_early_setup_ss.h" #include "southbridge/sis/sis966/sis966_early_setup_car.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -132,7 +132,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -134,7 +134,7 @@ #define DIMM6 0x56 #define DIMM7 0x57 -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/ibm/e325/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e325/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/ibm/e325/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -83,7 +83,7 @@ #define SECOND_CPU 1 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/ibm/e326/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e326/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/ibm/e326/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -83,7 +83,7 @@ #define SECOND_CPU 1 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -113,7 +113,7 @@ #define DIMM6 0x56 #define DIMM7 0x57 -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -113,7 +113,7 @@ #define DIMM6 0x56 #define DIMM7 0x57 -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -113,7 +113,7 @@ #define DIMM6 0x56 #define DIMM7 0x57 -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/kontron/kt690/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -89,7 +89,7 @@ #include "cpu/amd/dualcore/dualcore.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/msi/ms7135/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -89,7 +89,7 @@ #include "lib/generic_sdram.c" #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" #include "southbridge/nvidia/ck804/ck804_early_setup_car.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/msi/ms7260/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -115,7 +115,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/msi/ms9185/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -129,7 +129,7 @@ #define DIMM6 0x56 #define DIMM7 0x57 -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/msi/ms9282/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -123,7 +123,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -122,7 +122,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/newisys/khepri/romstage.c ============================================================================== --- trunk/src/mainboard/newisys/khepri/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/newisys/khepri/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -88,7 +88,7 @@ #endif #include "cpu/amd/dualcore/dualcore.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -132,7 +132,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/sunw/ultra40/romstage.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/sunw/ultra40/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -100,7 +100,7 @@ #include "southbridge/nvidia/ck804/ck804_early_setup_car.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -175,7 +175,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -120,7 +120,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -111,7 +111,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -115,7 +115,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -88,7 +88,7 @@ #include "cpu/amd/dualcore/dualcore.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -88,7 +88,7 @@ #include "cpu/amd/dualcore/dualcore.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/tyan/s2735/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/tyan/s2735/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -63,7 +63,7 @@ #include "northbridge/intel/e7501/reset_test.c" #include "lib/generic_sdram.c" -#include "cpu/x86/car/copy_and_run.c" + void stage1_main(unsigned long bist) { Modified: trunk/src/mainboard/tyan/s2850/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2850/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/tyan/s2850/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -74,7 +74,7 @@ #endif #include "cpu/amd/dualcore/dualcore.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/tyan/s2875/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2875/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/tyan/s2875/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -76,7 +76,7 @@ #endif #include "cpu/amd/dualcore/dualcore.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/tyan/s2880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2880/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/tyan/s2880/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -76,7 +76,7 @@ #endif #include "cpu/amd/dualcore/dualcore.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/tyan/s2881/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2881/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/tyan/s2881/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -76,7 +76,7 @@ #include "cpu/amd/dualcore/dualcore.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/tyan/s2882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2882/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/tyan/s2882/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -80,7 +80,7 @@ #define SECOND_CPU 1 #define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/tyan/s2885/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2885/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/tyan/s2885/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -78,7 +78,7 @@ #endif #include "cpu/amd/dualcore/dualcore.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/tyan/s2891/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/tyan/s2891/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -68,7 +68,7 @@ #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" #include "southbridge/nvidia/ck804/ck804_early_setup.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/tyan/s2892/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/tyan/s2892/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -72,7 +72,7 @@ #include "southbridge/nvidia/ck804/ck804_early_setup_car.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/tyan/s2895/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/tyan/s2895/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -101,7 +101,7 @@ #include "southbridge/nvidia/ck804/ck804_early_setup_car.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/tyan/s2912/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -130,7 +130,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -121,7 +121,7 @@ #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/tyan/s4880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/tyan/s4880/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -102,7 +102,7 @@ #define DIMM2 0x52 #define DIMM3 0x53 -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/tyan/s4882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4882/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/tyan/s4882/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -110,7 +110,7 @@ #define DIMM2 0x52 #define DIMM3 0x53 -#include "cpu/amd/car/copy_and_run.c" + #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/via/epia-m700/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/via/epia-m700/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -47,7 +47,7 @@ #include "northbridge/via/vx800/raminit.h" #include "northbridge/via/vx800/raminit.c" -#include "cpu/x86/car/copy_and_run.c" + #include "wakeup.h" #include "superio/winbond/w83697hf/w83697hf_early_serial.c" Modified: trunk/src/mainboard/via/vt8454c/romstage.c ============================================================================== --- trunk/src/mainboard/via/vt8454c/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/mainboard/via/vt8454c/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -34,7 +34,7 @@ #define DEACTIVATE_CAR 1 #define DEACTIVATE_CAR_FILE "cpu/via/car/cache_as_ram_post.c" -#include "cpu/x86/car/copy_and_run.c" + #include "pc80/udelay_io.c" #include "lib/delay.c" #include "northbridge/via/cx700/cx700_early_smbus.c" Modified: trunk/src/northbridge/via/vx800/examples/romstage.c ============================================================================== --- trunk/src/northbridge/via/vx800/examples/romstage.c Fri Apr 9 12:12:18 2010 (r5386) +++ trunk/src/northbridge/via/vx800/examples/romstage.c Fri Apr 9 12:43:49 2010 (r5387) @@ -45,7 +45,7 @@ #include "northbridge/via/vx800/raminit.h" #include "northbridge/via/vx800/raminit.c" -#include "cpu/x86/car/copy_and_run.c" + int acpi_is_wakeup_early_via_vx800(void) {

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2003

2002

coreboot April 2010