coreboot April 2010

coreboot@coreboot.org

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402 discussions

[PATCH] clarify << and -
by Stefan Reinauer 14 Apr '10

14 Apr '10

Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Index: src/northbridge/amd/gx2/chipsetinit.c =================================================================== --- src/northbridge/amd/gx2/chipsetinit.c (revision 5425) +++ src/northbridge/amd/gx2/chipsetinit.c (working copy) @@ -275,7 +275,7 @@ if ((msr.lo&0xff) == 0x11) return; - totalmem = sizeram() << 20 - 1; + totalmem = (sizeram() << 20) - 1; totalmem >>= 12; totalmem = ~totalmem; totalmem &= 0xfffff; -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: info(a)coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866

3 6

[commit] r5437 - trunk
by repository service 14 Apr '10

14 Apr '10

Author: oxygene Date: Wed Apr 14 22:47:45 2010 New Revision: 5437 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5437 Log: Quote test -f argument, so it doesn't fail on spaces. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Wed Apr 14 22:42:42 2010 (r5436) +++ trunk/Makefile Wed Apr 14 22:47:45 2010 (r5437) @@ -295,7 +295,7 @@ printf "/* build system definitions (autogenerated) */\n" > $(obj)/build.ht printf "#ifndef __BUILD_H\n" >> $(obj)/build.ht printf "#define __BUILD_H\n\n" >> $(obj)/build.ht - printf "#define COREBOOT_VERSION \"$(KERNELVERSION)-r$(shell if [ -d $(top)/.svn -a -f `which svnversion` ]; then svnversion $(top); else if [ -d $(top)/.git -a -f `which git` ]; then git --git-dir=/$(top)/.git log|grep git-svn-id|cut -f 2 -d@|cut -f 1 -d' '|sort -g|tail -1; fi; fi)\"\n" >> $(obj)/build.ht + printf "#define COREBOOT_VERSION \"$(KERNELVERSION)-r$(shell if [ -d $(top)/.svn -a -f "`which svnversion`" ]; then svnversion $(top); else if [ -d $(top)/.git -a -f "`which git`" ]; then git --git-dir=/$(top)/.git log|grep git-svn-id|cut -f 2 -d@|cut -f 1 -d' '|sort -g|tail -1; fi; fi)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_EXTRA_VERSION \"$(COREBOOT_EXTRA_VERSION)\"\n" >> $(obj)/build.ht printf "#define COREBOOT_BUILD \"`LANG= date`\"\n" >> $(obj)/build.ht printf "\n" >> $(obj)/build.ht

1 0

[commit] r5436 - trunk/util/crossgcc
by repository service 14 Apr '10

14 Apr '10

Author: oxygene Date: Wed Apr 14 22:42:42 2010 New Revision: 5436 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5436 Log: Update mingw source versions and allow parallel builds in buildgcc Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/util/crossgcc/buildgcc Modified: trunk/util/crossgcc/buildgcc ============================================================================== --- trunk/util/crossgcc/buildgcc Wed Apr 14 20:59:42 2010 (r5435) +++ trunk/util/crossgcc/buildgcc Wed Apr 14 22:42:42 2010 (r5436) @@ -32,8 +32,8 @@ GCC_VERSION=4.4.2 BINUTILS_VERSION=2.20 GDB_VERSION=7.0 -W32API_VERSION=3.13 -MINGWRT_VERSION=3.16 +W32API_VERSION=3.14 +MINGWRT_VERSION=3.18 # archive locations GMP_ARCHIVE="ftp://ftp.gmplib.org/pub/gmp-${GMP_VERSION}/gmp-${GMP_VERSION}.tar.bz2" @@ -41,7 +41,7 @@ GCC_ARCHIVE="ftp://ftp.gwdg.de/pub/gnu/ftp/gnu/gcc/gcc-${GCC_VERSION}/gcc-core-${GCC_VERSION}.tar.bz2" BINUTILS_ARCHIVE="http://ftp.gnu.org/gnu/binutils/binutils-${BINUTILS_VERSION}.tar.bz2" GDB_ARCHIVE="http://ftp.gnu.org/gnu/gdb/gdb-${GDB_VERSION}.tar.bz2" -W32API_ARCHIVE="http://downloads.sourceforge.net/project/mingw/MinGW%20API%20for%20MS-Windo…" +W32API_ARCHIVE="http://downloads.sourceforge.net/project/mingw/MinGW%20API%20for%20MS-Windo…" MINGWRT_ARCHIVE="http://downloads.sourceforge.net/project/mingw/MinGW%20Runtime/mingwrt-${MI…" GMP_DIR="gmp-${GMP_VERSION}" @@ -103,6 +103,7 @@ printf " [-h|--help] print this help and exit\n" printf " [-c|--clean] remove temporary files before build\n" printf " [-t|--savetemps] don't remove temporary files after build\n" + printf " [-j|--jobs <num>] run <num> jobs in parallel in make\n" printf " [-p|--platform <platform>] target platform to build cross compiler for\n" printf " (defaults to $TARGETARCH)\n" printf " [-d|--directory <target dir>] target directory to install cross compiler to\n" @@ -140,11 +141,11 @@ getoptbrand="`getopt -V`" if [ "${getoptbrand:0:6}" == "getopt" ]; then # Detected GNU getopt that supports long options. - args=`getopt -l version,help,clean,directory:,platform:,destdir:,savetemps Vhcd:p:D:t -- "$@"` + args=`getopt -l version,help,clean,directory:,platform:,jobs:,destdir:,savetemps Vhcd:p:j:D:t -- "$@"` eval set "$args" else # Detected non-GNU getopt - args=`getopt Vhcd:p:D:t $*` + args=`getopt Vhcd:p:j:D:t $*` set -- $args fi @@ -162,6 +163,7 @@ -d|--directory) shift; TARGETDIR="$1"; shift;; -p|--platform) shift; TARGETARCH="$1"; shift;; -D|--destdir) shift; DESTDIR="$1"; shift;; + -j|--jobs) shift; JOBS="-j $1"; shift;; --) shift; break;; -*) printf "Invalid option\n\n"; myhelp; exit 1;; *) break;; @@ -245,7 +247,7 @@ ../${GMP_DIR}/configure --disable-shared --prefix=$TARGETDIR $OPTIONS \ || touch .failed - $MAKE || touch .failed + $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed if [ ! -f .failed ]; then touch .success; fi ) &> build-gmp/crossgcc-build.log @@ -272,7 +274,7 @@ ../${MPFR_DIR}/configure --disable-shared --prefix=$TARGETDIR \ --infodir=$TARGETDIR/info \ --with-gmp=$DESTDIR$TARGETDIR CFLAGS="$HOSTCFLAGS" || touch .failed - $MAKE || touch .failed + $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed # work around build problem of libgmp.la @@ -296,7 +298,7 @@ ../binutils-${BINUTILS_VERSION}/configure --prefix=$TARGETDIR --target=${TARGETARCH} \ --disable-werror --disable-nls \ CFLAGS="$HOSTCFLAGS" || touch .failed - $MAKE || touch .failed + $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed if [ ! -f .failed ]; then touch .success; fi ) &> build-binutils/crossgcc-build.log @@ -322,7 +324,7 @@ --disable-libssp --disable-bootstrap --disable-nls \ --with-gmp=$DESTDIR$TARGETDIR --with-mpfr=$DESTDIR$TARGETDIR \ || touch .failed - $MAKE CFLAGS_FOR_BUILD="$HOSTCFLAGS" || touch .failed + $MAKE $JOBS CFLAGS_FOR_BUILD="$HOSTCFLAGS" || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed if [ ! -f .failed ]; then touch .success; fi ) &> build-gcc/crossgcc-build.log @@ -340,7 +342,7 @@ rm -f .failed ../gdb-${GDB_VERSION}/configure --prefix=$TARGETDIR --target=${TARGETARCH} \ --disable-werror --disable-nls - $MAKE || touch .failed + $MAKE $JOBS || touch .failed $MAKE install DESTDIR=$DESTDIR || touch .failed if [ ! -f .failed ]; then touch .success; fi ) &> build-gdb/crossgcc-build.log

1 0

[commit] r5435 - in trunk/src: . arch/i386 mainboard/kontron/kt690 mainboard/msi/ms9282 mainboard/nvidia/l1_2pvv mainboard/supermicro/h8dme mainboard/supermicro/h8dmr mainboard/supermicro/h8dmr_fam...
by repository service 14 Apr '10

14 Apr '10

Author: stepan Date: Wed Apr 14 20:59:42 2010 New Revision: 5435 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5435 Log: zero warning days. Move RAMTOP and RAMBASE together. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/Kconfig trunk/src/arch/i386/Kconfig trunk/src/mainboard/kontron/kt690/mainboard.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/technexion/tim5690/Kconfig trunk/src/mainboard/technexion/tim5690/mainboard.c trunk/src/mainboard/technexion/tim8690/mainboard.c trunk/src/mainboard/tyan/s2735/reset.c trunk/src/mainboard/tyan/s2735/romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/mainboard/via/epia-cn/romstage.c trunk/src/southbridge/via/vt8237r/vt8237r_usb.c Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Wed Apr 14 19:18:34 2010 (r5434) +++ trunk/src/Kconfig Wed Apr 14 20:59:42 2010 (r5435) @@ -152,10 +152,6 @@ bool default n -config RAMTOP - hex - default 0x200000 - config ATI_RAGE_XL bool Modified: trunk/src/arch/i386/Kconfig ============================================================================== --- trunk/src/arch/i386/Kconfig Wed Apr 14 19:18:34 2010 (r5434) +++ trunk/src/arch/i386/Kconfig Wed Apr 14 20:59:42 2010 (r5435) @@ -30,6 +30,10 @@ hex default 0x100000 +config RAMTOP + hex + default 0x200000 + config STACK_SIZE hex default 0x8000 Modified: trunk/src/mainboard/kontron/kt690/mainboard.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/mainboard.c Wed Apr 14 19:18:34 2010 (r5434) +++ trunk/src/mainboard/kontron/kt690/mainboard.c Wed Apr 14 20:59:42 2010 (r5435) @@ -22,10 +22,11 @@ #include <device/pci.h> #include <arch/io.h> #include <boot/coreboot_tables.h> +#include <arch/coreboot_tables.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include <../southbridge/amd/sb600/sb600.h> +#include <southbridge/amd/sb600/sb600.h> #include "chip.h" #define ADT7461_ADDRESS 0x4C @@ -185,11 +186,8 @@ * enable the dedicated function in dbm690t board. * This function called early than rs690_enable. *************************************************/ -void kt690_enable(device_t dev) +static void kt690_enable(device_t dev) { - struct mainboard_config *mainboard = - (struct mainboard_config *)dev->chip_info; - printk(BIOS_INFO, "Mainboard KT690 Enable. dev=0x%p\n", dev); #if (CONFIG_GFXUMA == 1) @@ -229,8 +227,8 @@ /* TODO: TOP_MEM2 */ #else - uma_memory_size = 0x8000000; /* 128M recommended UMA */ - uma_memory_base = 0x38000000; /* 1GB system memory supposed */ + uma_memory_size = 0x0; + uma_memory_base = 0x0; #endif enable_onboard_nic(); @@ -249,6 +247,7 @@ lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); #endif + return 0; } struct chip_operations mainboard_ops = { Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Wed Apr 14 19:18:34 2010 (r5434) +++ trunk/src/mainboard/msi/ms9282/romstage.c Wed Apr 14 20:59:42 2010 (r5435) @@ -135,8 +135,6 @@ static void sio_setup(void) { - - unsigned value; uint32_t dword; uint8_t byte; @@ -147,7 +145,6 @@ dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); dword |= (1<<0); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); - } //CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1. @@ -156,19 +153,19 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const uint16_t spd_addr [] = { - RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6, - RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 - RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6, - RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7, -#endif - }; + static const uint16_t spd_addr[] = { + // Node 0 + RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6, + RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7, + // node 1 + RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6, + RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7, + }; - unsigned bsp_apicid = 0; + unsigned bsp_apicid = 0; int needs_reset; - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - char *p ; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Wed Apr 14 19:18:34 2010 (r5434) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Wed Apr 14 20:59:42 2010 (r5435) @@ -145,8 +145,6 @@ static void sio_setup(void) { - - unsigned value; uint32_t dword; uint8_t byte; @@ -161,21 +159,21 @@ dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); - } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { + // Node 0 (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 + // Node 1 (0xa<<3)|4, (0xa<<3)|6, 0, 0, (0xa<<3)|5, (0xa<<3)|7, 0, 0, -#endif }; - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Wed Apr 14 19:18:34 2010 (r5434) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Wed Apr 14 20:59:42 2010 (r5435) @@ -85,12 +85,7 @@ { } -static int smbus_send_byte_one(unsigned device, unsigned char val) -{ - return do_smbus_send_byte(SMBUS1_IO_BASE, device, val); -} - -static void dump_smbus_registers(void) +static inline void dump_smbus_registers(void) { u32 device; @@ -119,17 +114,22 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) { -/* We don't do any switching yet. +#if 0 +/* We don't do any switching yet. */ #define SMBUS_SWITCH1 0x48 #define SMBUS_SWITCH2 0x49 unsigned device=(ctrl->channel0[0])>>8; smbus_send_byte(SMBUS_SWITCH1, device); smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); -*/ - /* nothing to do */ +#endif +} + +#if 0 +static int smbus_send_byte_one(unsigned device, unsigned char val) +{ + return do_smbus_send_byte(SMBUS1_IO_BASE, device, val); } -/* static inline void change_i2c_mux(unsigned device) { #define SMBUS_SWITCH1 0x48 @@ -146,7 +146,7 @@ print_debug("change_i2c_mux ret="); print_debug_hex32(ret); print_debug("\n"); dump_smbus_registers(); } -*/ +#endif static inline int spd_read_byte(unsigned device, unsigned address) { @@ -188,8 +188,6 @@ static void sio_setup(void) { - - u32 value; uint32_t dword; uint8_t byte; @@ -208,7 +206,6 @@ dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4); dword |= (1 << 16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword); - } /* We have no idea where the SMBUS switch is. This doesn't do anything ATM. */ @@ -222,20 +219,20 @@ memory on each CPU must be an exact match. */ static const uint16_t spd_addr[] = { + // Node 0 RC0 | (0xa << 3) | 0, RC0 | (0xa << 3) | 2, RC0 | (0xa << 3) | 4, RC0 | (0xa << 3) | 6, RC0 | (0xa << 3) | 1, RC0 | (0xa << 3) | 3, RC0 | (0xa << 3) | 5, RC0 | (0xa << 3) | 7, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 + // Node 1 RC1 | (0xa << 3) | 0, RC1 | (0xa << 3) | 2, RC1 | (0xa << 3) | 4, RC1 | (0xa << 3) | 6, RC1 | (0xa << 3) | 1, RC1 | (0xa << 3) | 3, RC1 | (0xa << 3) | 5, RC1 | (0xa << 3) | 7, -#endif }; - struct sys_info *sysinfo = - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Wed Apr 14 19:18:34 2010 (r5434) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Wed Apr 14 20:59:42 2010 (r5435) @@ -133,8 +133,6 @@ static void sio_setup(void) { - - unsigned value; uint32_t dword; uint8_t byte; enable_smbus(); @@ -152,21 +150,21 @@ dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); - } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { + // Node 0 (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 + // Node 1 (0xa<<3)|4, (0xa<<3)|6, 0, 0, (0xa<<3)|5, (0xa<<3)|7, 0, 0, -#endif }; - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Wed Apr 14 19:18:34 2010 (r5434) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Wed Apr 14 20:59:42 2010 (r5435) @@ -116,8 +116,6 @@ static void sio_setup(void) { - - unsigned value; uint32_t dword; uint8_t byte; enable_smbus(); Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Wed Apr 14 19:18:34 2010 (r5434) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Wed Apr 14 20:59:42 2010 (r5435) @@ -120,8 +120,6 @@ static void sio_setup(void) { - - unsigned value; uint32_t dword; uint8_t byte; enable_smbus(); @@ -149,7 +147,7 @@ #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1) #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2) #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3) -void write_GPIO(void) +static void write_GPIO(void) { pnp_enter_ext_func_mode(GPIO1_DEV); pnp_set_logical_device(GPIO1_DEV); Modified: trunk/src/mainboard/technexion/tim5690/Kconfig ============================================================================== --- trunk/src/mainboard/technexion/tim5690/Kconfig Wed Apr 14 19:18:34 2010 (r5434) +++ trunk/src/mainboard/technexion/tim5690/Kconfig Wed Apr 14 20:59:42 2010 (r5435) @@ -110,7 +110,3 @@ default 0x4000 depends on BOARD_TECHNEXION_TIM5690 -config RAMBASE - hex - default 0x100000 - depends on BOARD_TECHNEXION_TIM5690 Modified: trunk/src/mainboard/technexion/tim5690/mainboard.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/mainboard.c Wed Apr 14 19:18:34 2010 (r5434) +++ trunk/src/mainboard/technexion/tim5690/mainboard.c Wed Apr 14 20:59:42 2010 (r5435) @@ -22,11 +22,12 @@ #include <device/pci.h> #include <arch/io.h> #include <boot/coreboot_tables.h> +#include <arch/coreboot_tables.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> -#include <../southbridge/amd/sb600/sb600.h> -#include <../superio/ite/it8712f/it8712f.h> +#include <southbridge/amd/sb600/sb600.h> +#include <superio/ite/it8712f/it8712f.h> #include "chip.h" #include "tn_post_code.h" #include "vgabios.h" @@ -57,7 +58,6 @@ #define TV_MODE_09 0x09 /* SCART-RGB */ #define TV_MODE_NO 0xff /* No TV Support */ - /* The base address is 0x2e or 0x4e, depending on config bytes. */ #define SIO_BASE 0x2e #define SIO_INDEX SIO_BASE @@ -75,12 +75,8 @@ #define IT8712F_CONFIGURATION_PORT 0x2e /* Write-only. */ #define IT8712F_SIMPLE_IO_BASE 0x200 /* Simple I/O base address */ - -extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); -extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, - u8 val); -extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type, - uint64_t start, uint64_t size); +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); #define ADT7461_read_byte(address) \ do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address) #define ARA_read_byte(address) \ @@ -88,15 +84,8 @@ #define ADT7461_write_byte(address, val) \ do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val) -/* previous - */ -void tim5690_enable(device_t dev); -int add_mainboard_resources(struct lb_memory *mem); - - uint64_t uma_memory_base, uma_memory_size; - /* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the LDN the register belongs to, before you can access the register. */ static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) @@ -126,7 +115,6 @@ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); } - /* set thermal config */ static void set_thermal_config(void) @@ -236,7 +224,7 @@ * enable the dedicated function in tim5690 board. * This function called early than rs690_enable. *************************************************/ -void tim5690_enable(device_t dev) +static void tim5690_enable(device_t dev) { struct mainboard_config *mainboard = (struct mainboard_config *)dev->chip_info; @@ -312,6 +300,7 @@ uma_memory_base, uma_memory_size); #endif technexion_post_code(LED_MESSAGE_FINISH); + return 0; } struct chip_operations mainboard_ops = { Modified: trunk/src/mainboard/technexion/tim8690/mainboard.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/mainboard.c Wed Apr 14 19:18:34 2010 (r5434) +++ trunk/src/mainboard/technexion/tim8690/mainboard.c Wed Apr 14 20:59:42 2010 (r5435) @@ -22,6 +22,7 @@ #include <device/pci.h> #include <arch/io.h> #include <boot/coreboot_tables.h> +#include <arch/coreboot_tables.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> #include <device/pci_def.h> @@ -145,11 +146,8 @@ * enable the dedicated function in tim8690 board. * This function called early than rs690_enable. *************************************************/ -void tim8690_enable(device_t dev) +static void tim8690_enable(device_t dev) { - struct mainboard_config *mainboard = - (struct mainboard_config *)dev->chip_info; - printk(BIOS_INFO, "Mainboard tim8690 Enable. dev=0x%p\n", dev); #if (CONFIG_GFXUMA == 1) @@ -208,6 +206,7 @@ lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); #endif + return 0; } struct chip_operations mainboard_ops = { Modified: trunk/src/mainboard/tyan/s2735/reset.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/reset.c Wed Apr 14 19:18:34 2010 (r5434) +++ trunk/src/mainboard/tyan/s2735/reset.c Wed Apr 14 20:59:42 2010 (r5435) @@ -1,3 +1,4 @@ +#include <reset.h> void i82801ex_hard_reset(void); /* FIXME: There's another hard_reset() in romstage.c. Why? */ Modified: trunk/src/mainboard/tyan/s2735/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/romstage.c Wed Apr 14 19:18:34 2010 (r5434) +++ trunk/src/mainboard/tyan/s2735/romstage.c Wed Apr 14 20:59:42 2010 (r5435) @@ -32,15 +32,6 @@ outb(0x0e, 0x0cf9); } -static void soft_reset(void) -{ -#if 1 - /* link reset */ - outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); -#endif -} - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -61,14 +52,10 @@ }, }; - unsigned cpu_reset = 0; - if (bist == 0) { enable_lapic(); } -// post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); @@ -76,8 +63,6 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); -// setup_s2735_resource_map(); - if(bios_reset_detected()) { hard_reset(); } Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Wed Apr 14 19:18:34 2010 (r5434) +++ trunk/src/mainboard/tyan/s2912/romstage.c Wed Apr 14 20:59:42 2010 (r5435) @@ -143,8 +143,6 @@ static void sio_setup(void) { - - unsigned value; uint32_t dword; uint8_t byte; @@ -160,21 +158,21 @@ dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); - } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { + // Node 0 (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 + // Node 1 (0xa<<3)|4, (0xa<<3)|6, 0, 0, (0xa<<3)|5, (0xa<<3)|7, 0, 0, -#endif }; - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset = 0; unsigned bsp_apicid = 0; Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Wed Apr 14 19:18:34 2010 (r5434) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Wed Apr 14 20:59:42 2010 (r5435) @@ -126,7 +126,6 @@ static void sio_setup(void) { - unsigned value; uint32_t dword; uint8_t byte; @@ -142,7 +141,6 @@ dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); dword |= (1<<16); pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); - } #include "spd_addr.h" Modified: trunk/src/mainboard/via/epia-cn/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-cn/romstage.c Wed Apr 14 19:18:34 2010 (r5434) +++ trunk/src/mainboard/via/epia-cn/romstage.c Wed Apr 14 20:59:42 2010 (r5435) @@ -48,7 +48,6 @@ static void enable_mainboard_devices(void) { device_t dev; - u8 reg; dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev == PCI_DEV_INVALID) @@ -84,9 +83,6 @@ void main(unsigned long bist) { - unsigned long x; - device_t dev; - /* Enable multifunction for northbridge. */ pci_write_config8(ctrl.d0f0, 0x4f, 0x01); Modified: trunk/src/southbridge/via/vt8237r/vt8237r_usb.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r_usb.c Wed Apr 14 19:18:34 2010 (r5434) +++ trunk/src/southbridge/via/vt8237r/vt8237r_usb.c Wed Apr 14 20:59:42 2010 (r5435) @@ -30,16 +30,15 @@ static void usb_i_init(struct device *dev) { - #if CONFIG_EPIA_VT8237R_INIT u8 reg8; printk(BIOS_DEBUG, "Entering %s\n", __func__); - printk(BIOS_SPEW, "%s Read %02X from PCI Command Reg\n", dev_path(dev), reg8); - reg8 = pci_read_config8(dev, 0x04); + printk(BIOS_SPEW, "%s Read %02X from PCI Command Reg\n", dev_path(dev), reg8); + reg8 = reg8 | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; pci_write_config8(dev, 0x04, reg8);

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[commit] r5434 - trunk/src/northbridge/amd/amdmct/mct
by repository service 14 Apr '10

14 Apr '10

Author: stepan Date: Wed Apr 14 19:18:34 2010 New Revision: 5434 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5434 Log: fix a case where the fam10 code would overwrite parts of a struct. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/amd/amdmct/mct/mctardk3.c trunk/src/northbridge/amd/amdmct/mct/mctardk4.c Modified: trunk/src/northbridge/amd/amdmct/mct/mctardk3.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctardk3.c Wed Apr 14 19:11:47 2010 (r5433) +++ trunk/src/northbridge/amd/amdmct/mct/mctardk3.c Wed Apr 14 19:18:34 2010 (r5434) @@ -18,7 +18,7 @@ */ -static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload, +static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL); Modified: trunk/src/northbridge/amd/amdmct/mct/mctardk4.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctardk4.c Wed Apr 14 19:11:47 2010 (r5433) +++ trunk/src/northbridge/amd/amdmct/mct/mctardk4.c Wed Apr 14 19:18:34 2010 (r5434) @@ -18,9 +18,9 @@ */ -static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload, +static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload, u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, - u32 *CMDmode); + u8 *CMDmode); void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat, @@ -102,7 +102,7 @@ static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload, u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL, - u32 *CMDmode) + u8 *CMDmode) { u8 *p;

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[commit] r5433 - in trunk/src: mainboard/via/epia-m700 northbridge/intel/e7501 northbridge/via/cn400 northbridge/via/vx800
by repository service 14 Apr '10

14 Apr '10

Author: stepan Date: Wed Apr 14 19:11:47 2010 New Revision: 5433 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5433 Log: drop setup_ics code that was blatantly copied from cx700 and was mainboard specific and unused there already. some more minor warning fixes. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/via/epia-m700/romstage.c trunk/src/northbridge/intel/e7501/debug.c trunk/src/northbridge/via/cn400/vgabios.c trunk/src/northbridge/via/vx800/rank_map.c trunk/src/northbridge/via/vx800/vgabios.c trunk/src/northbridge/via/vx800/vx800_early_smbus.c Modified: trunk/src/mainboard/via/epia-m700/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/romstage.c Wed Apr 14 18:50:16 2010 (r5432) +++ trunk/src/mainboard/via/epia-m700/romstage.c Wed Apr 14 19:11:47 2010 (r5433) @@ -24,6 +24,7 @@ #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 +#define PAYLOAD_IS_SEABIOS 0 #include <stdint.h> #include <device/pci_def.h> @@ -85,11 +86,6 @@ return result; } -static inline int spd_read_byte(unsigned device, unsigned address) -{ - return smbus_read_byte(device, address); -} - /* All content of this function came from the cx700 port of coreboot. */ static void enable_mainboard_devices(void) { @@ -273,7 +269,8 @@ #define gCom1Base 0x3f8 #define gCom2Base 0x2f8 -void EmbedComInit(void) +#if 0 +static void EmbedComInit(void) { u8 ByteVal; u16 ComBase; @@ -379,6 +376,7 @@ /* SOutput("Embedded COM output\n"); */ /* while(1); */ } +#endif /* cache_as_ram.inc jumps to here. */ void main(unsigned long bist) Modified: trunk/src/northbridge/intel/e7501/debug.c ============================================================================== --- trunk/src/northbridge/intel/e7501/debug.c Wed Apr 14 18:50:16 2010 (r5432) +++ trunk/src/northbridge/intel/e7501/debug.c Wed Apr 14 19:11:47 2010 (r5433) @@ -140,7 +140,7 @@ int j; #if CONFIG_USE_PRINTK_IN_CAR printk(BIOS_DEBUG, "dimm: %02x.1: %02x", i, device); -#else` +#else print_debug("dimm: "); print_debug_hex8(i); print_debug(".1: "); Modified: trunk/src/northbridge/via/cn400/vgabios.c ============================================================================== --- trunk/src/northbridge/via/cn400/vgabios.c Wed Apr 14 18:50:16 2010 (r5432) +++ trunk/src/northbridge/via/cn400/vgabios.c Wed Apr 14 19:11:47 2010 (r5433) @@ -336,7 +336,7 @@ { device_t dev; unsigned long busdevfn; - unsigned int rom = 0; + u32 rom; unsigned char *buf; unsigned int size = 64*1024; int i; @@ -357,7 +357,7 @@ /* declare rom address here - keep any config data out of the way * of core LXB stuff */ - rom = cbfs_load_optionrom(dev->vendor, dev->device, 0); + rom = (u32)cbfs_load_optionrom(dev->vendor, dev->device, 0); pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1); printk(BIOS_DEBUG, "VGA BIOS ROM base address: %x\n", rom); Modified: trunk/src/northbridge/via/vx800/rank_map.c ============================================================================== --- trunk/src/northbridge/via/vx800/rank_map.c Wed Apr 14 18:50:16 2010 (r5432) +++ trunk/src/northbridge/via/vx800/rank_map.c Wed Apr 14 19:11:47 2010 (r5433) @@ -17,12 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -extern void DRAMSetVRNum(DRAM_SYS_ATTR * DramAttr, - u8 PhyRank, u8 VirRank, BOOLEAN Enable); - -extern void SetEndingAddr(DRAM_SYS_ATTR * DramAttr, u8 VirRank, // Ending address register number indicator (INDEX - INT8 Value); // (value) add or subtract value to this and after banks - void DRAMClearEndingAddress(DRAM_SYS_ATTR * DramAttr); void DRAMSizingEachRank(DRAM_SYS_ATTR * DramAttr); Modified: trunk/src/northbridge/via/vx800/vgabios.c ============================================================================== --- trunk/src/northbridge/via/vx800/vgabios.c Wed Apr 14 18:50:16 2010 (r5432) +++ trunk/src/northbridge/via/vx800/vgabios.c Wed Apr 14 19:11:47 2010 (r5433) @@ -158,6 +158,7 @@ /* put the stack at the end of page zero. * that way we can easily share it between real and protected, * since the 16-bit ESP at segment 0 will work for any case. + */ /* Setup a stack */ " mov $0x0, %ax \n" " mov %ax, %ss \n" @@ -240,6 +241,7 @@ /* put the stack at the end of page zero. * that way we can easily share it between real and protected, * since the 16-bit ESP at segment 0 will work for any case. + */ /* Setup a stack */ " mov $0x0, %ax \n" " mov %ax, %ss \n" @@ -295,7 +297,7 @@ { device_t dev; unsigned long busdevfn; - unsigned int rom = 0; + u32 rom; unsigned char *buf; unsigned int size = 64 * 1024; int i; @@ -318,7 +320,7 @@ /* declare rom address here - keep any config data out of the way * of core LXB stuff */ - rom = cbfs_load_optionrom(dev->vendor, dev->device, 0); + rom = (u32)cbfs_load_optionrom(dev->vendor, dev->device, 0); pci_write_config32(dev, PCI_ROM_ADDRESS, rom | 1); printk(BIOS_DEBUG, "rom base: %x\n", rom); buf = (unsigned char *)rom; @@ -617,7 +619,7 @@ TF bit is set upon call to real mode */ idts[1].cs = 0; idts[1].offset = 16384; - memcpy(16384, &debughandle, &end_debughandle - &debughandle); + memcpy((void *)16384, &debughandle, &end_debughandle - &debughandle); } Modified: trunk/src/northbridge/via/vx800/vx800_early_smbus.c ============================================================================== --- trunk/src/northbridge/via/vx800/vx800_early_smbus.c Wed Apr 14 18:50:16 2010 (r5432) +++ trunk/src/northbridge/via/vx800/vx800_early_smbus.c Wed Apr 14 19:11:47 2010 (r5433) @@ -108,62 +108,6 @@ } /* Public functions */ -static unsigned int set_ics_data(unsigned char dev, int data, char len) -{ - smbus_reset(); - /* clear host data port */ - outb(0x00, SMBHSTDAT0); - SMBUS_DELAY(); - smbus_wait_until_ready(); - - /* read to reset block transfer counter */ - inb(SMBHSTCTL); - - /* fill blocktransfer array */ - if (dev == 0xd2) { - //char d2_data[] = {0x0d,0x00,0x3f,0xcd,0x7f,0xbf,0x1a,0x2a,0x01,0x0f,0x0b,0x00,0x8d,0x9b}; - outb(0x0d, SMBBLKDAT); - outb(0x00, SMBBLKDAT); - outb(0x3f, SMBBLKDAT); - outb(0xcd, SMBBLKDAT); - outb(0x7f, SMBBLKDAT); - outb(0xbf, SMBBLKDAT); - outb(0x1a, SMBBLKDAT); - outb(0x2a, SMBBLKDAT); - outb(0x01, SMBBLKDAT); - outb(0x0f, SMBBLKDAT); - outb(0x0b, SMBBLKDAT); - outb(0x80, SMBBLKDAT); - outb(0x8d, SMBBLKDAT); - outb(0x9b, SMBBLKDAT); - } else { - //char d4_data[] = {0x08,0xff,0x3f,0x00,0x00,0xff,0xff,0xff,0xff}; - outb(0x08, SMBBLKDAT); - outb(0xff, SMBBLKDAT); - outb(0x3f, SMBBLKDAT); - outb(0x00, SMBBLKDAT); - outb(0x00, SMBBLKDAT); - outb(0xff, SMBBLKDAT); - outb(0xff, SMBBLKDAT); - outb(0xff, SMBBLKDAT); - outb(0xff, SMBBLKDAT); - } - - //for (i=0; i < len; i++) - // outb(data[i],SMBBLKDAT); - - outb(dev, SMBXMITADD); - outb(0, SMBHSTCMD); - outb(len, SMBHSTDAT0); - outb(0x74, SMBHSTCTL); - - SMBUS_DELAY(); - - smbus_wait_until_ready(); - - smbus_reset(); - return 0; -} static unsigned int get_spd_data(unsigned int dimm, unsigned int offset) { @@ -219,13 +163,6 @@ /* Make it work for I/O ... */ pci_write_config16(dev, 0x04, 0x0003); - /* - coreboot hangs at this two lines after os reboot(this even happen after I change os - reboot to cold reboot, this also interfere S3 wakeup) */ - /* Setup clock chips */ - //set_ics_data(0xd2, 0, 14); - //set_ics_data(0xd4, 0, 9); - smbus_reset(); /* clear host data port */ outb(0x00, SMBHSTDAT0);

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[commit] r5432 - in trunk/src: arch/i386/include/arch mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/serengeti_cheetah mainboard/amd...
by repository service 14 Apr '10

14 Apr '10

Author: myles Date: Wed Apr 14 18:50:16 2010 New Revision: 5432 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5432 Log: Remove few more warnings and some dead code. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/arch/i386/include/arch/acpi.h trunk/src/mainboard/amd/dbm690t/acpi_tables.c trunk/src/mainboard/amd/mahogany/acpi_tables.c trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c trunk/src/mainboard/amd/pistachio/acpi_tables.c trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c trunk/src/mainboard/intel/eagleheights/acpi_tables.c trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c trunk/src/mainboard/kontron/kt690/acpi_tables.c trunk/src/mainboard/technexion/tim5690/acpi_tables.c trunk/src/mainboard/technexion/tim8690/acpi_tables.c trunk/src/mainboard/via/epia-m/acpi_tables.c trunk/src/mainboard/via/epia-m700/wakeup.c trunk/src/northbridge/amd/amdfam10/amdfam10_acpi.c trunk/src/northbridge/amd/amdk8/amdk8_acpi.c trunk/src/northbridge/via/vx800/examples/romstage.c trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Modified: trunk/src/arch/i386/include/arch/acpi.h ============================================================================== --- trunk/src/arch/i386/include/arch/acpi.h Wed Apr 14 18:39:30 2010 (r5431) +++ trunk/src/arch/i386/include/arch/acpi.h Wed Apr 14 18:50:16 2010 (r5432) @@ -365,6 +365,9 @@ void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id); void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt); +void update_ssdt(void* ssdt); +void update_ssdtx(void* ssdtx, int i); + /* These can be used by the target port */ u8 acpi_checksum(u8 *table, u32 length); Modified: trunk/src/mainboard/amd/dbm690t/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/acpi_tables.c Wed Apr 14 18:39:30 2010 (r5431) +++ trunk/src/mainboard/amd/dbm690t/acpi_tables.c Wed Apr 14 18:50:16 2010 (r5432) @@ -92,28 +92,6 @@ return current; } -static void update_ssdtx(void *ssdtx, int i) -{ - uint8_t *PCI; - uint8_t *HCIN; - uint8_t *UID; - - PCI = ssdtx + 0x32; - HCIN = ssdtx + 0x39; - UID = ssdtx + 0x40; - - if (i < 7) { - *PCI = (uint8_t) ('4' + i - 1); - } else { - *PCI = (uint8_t) ('A' + i - 1 - 6); - } - *HCIN = (uint8_t) i; - *UID = (uint8_t) (i + 3); - - /* FIXME: need to update the GSI id in the ssdtx too */ - -} - unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); Modified: trunk/src/mainboard/amd/mahogany/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/acpi_tables.c Wed Apr 14 18:39:30 2010 (r5431) +++ trunk/src/mainboard/amd/mahogany/acpi_tables.c Wed Apr 14 18:50:16 2010 (r5432) @@ -99,32 +99,6 @@ return current; } - - -#if CONFIG_ACPI_SSDTX_NUM >= 1 -static void update_ssdtx(void *ssdtx, int i) -{ - u8 *PCI; - u8 *HCIN; - u8 *UID; - - PCI = ssdtx + 0x32; - HCIN = ssdtx + 0x39; - UID = ssdtx + 0x40; - - if (i < 7) { - *PCI = (u8) ('4' + i - 1); - } else { - *PCI = (u8) ('A' + i - 1 - 6); - } - *HCIN = (u8) i; - *UID = (u8) (i + 3); - - /* FIXME: need to update the GSI id in the ssdtx too */ - -} -#endif - unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); Modified: trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c Wed Apr 14 18:39:30 2010 (r5431) +++ trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c Wed Apr 14 18:50:16 2010 (r5432) @@ -89,34 +89,6 @@ return current; } - -extern void update_ssdt(void *ssdt); - -/* not tested yet. */ -#if CONFIG_ACPI_SSDTX_NUM >= 1 -static void update_ssdtx(void *ssdtx, int i) -{ - u8 *PCI; - u8 *HCIN; - u8 *UID; - - PCI = ssdtx + 0x32; - HCIN = ssdtx + 0x39; - UID = ssdtx + 0x40; - - if (i < 7) { - *PCI = (u8) ('4' + i - 1); - } else { - *PCI = (u8) ('A' + i - 1 - 6); - } - *HCIN = (u8) i; - *UID = (u8) (i + 3); - - /* FIXME: need to update the GSI id in the ssdtx too */ - -} -#endif - unsigned long write_acpi_tables(unsigned long start) { unsigned long current; Modified: trunk/src/mainboard/amd/pistachio/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/acpi_tables.c Wed Apr 14 18:39:30 2010 (r5431) +++ trunk/src/mainboard/amd/pistachio/acpi_tables.c Wed Apr 14 18:50:16 2010 (r5432) @@ -92,30 +92,6 @@ return current; } - - -static void update_ssdtx(void *ssdtx, int i) -{ - uint8_t *PCI; - uint8_t *HCIN; - uint8_t *UID; - - PCI = ssdtx + 0x32; - HCIN = ssdtx + 0x39; - UID = ssdtx + 0x40; - - if (i < 7) { - *PCI = (uint8_t) ('4' + i - 1); - } else { - *PCI = (uint8_t) ('A' + i - 1 - 6); - } - *HCIN = (uint8_t) i; - *UID = (uint8_t) (i + 3); - - /* FIXME: need to update the GSI id in the ssdtx too */ - -} - unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); Modified: trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c Wed Apr 14 18:39:30 2010 (r5431) +++ trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c Wed Apr 14 18:50:16 2010 (r5432) @@ -150,31 +150,6 @@ return current; } - - -static void update_ssdtx(void *ssdtx, int i) -{ - u8 *PCI; - u8 *HCIN; - u8 *UID; - - PCI = ssdtx + 0x32; - HCIN = ssdtx + 0x39; - UID = ssdtx + 0x40; - - if(i<7) { - *PCI = (u8) ('4' + i - 1); - } - else { - *PCI = (u8) ('A' + i - 1 - 6); - } - *HCIN = (u8) i; - *UID = (u8) (i+3); - - /* FIXME: need to update the GSI id in the ssdtx too */ - -} - unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); return (unsigned long) (acpigen_get_current()); Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c Wed Apr 14 18:39:30 2010 (r5431) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c Wed Apr 14 18:50:16 2010 (r5432) @@ -160,32 +160,6 @@ return current; } - -extern void update_ssdt(void *ssdt); - -static void update_ssdtx(void *ssdtx, int i) -{ - u8 *PCI; - u8 *HCIN; - u8 *UID; - - PCI = ssdtx + 0x32; - HCIN = ssdtx + 0x39; - UID = ssdtx + 0x40; - - if(i<7) { - *PCI = (u8) ('4' + i - 1); - } - else { - *PCI = (u8) ('A' + i - 1 - 6); - } - *HCIN = (u8) i; - *UID = (u8) (i+3); - - /* FIXME: need to update the GSI id in the ssdtx too */ - -} - unsigned long write_acpi_tables(unsigned long start) { unsigned long current; Modified: trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c Wed Apr 14 18:39:30 2010 (r5431) +++ trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c Wed Apr 14 18:50:16 2010 (r5432) @@ -99,32 +99,6 @@ return current; } - - -#if CONFIG_ACPI_SSDTX_NUM >= 1 -static void update_ssdtx(void *ssdtx, int i) -{ - u8 *PCI; - u8 *HCIN; - u8 *UID; - - PCI = ssdtx + 0x32; - HCIN = ssdtx + 0x39; - UID = ssdtx + 0x40; - - if (i < 7) { - *PCI = (u8) ('4' + i - 1); - } else { - *PCI = (u8) ('A' + i - 1 - 6); - } - *HCIN = (u8) i; - *UID = (u8) (i + 3); - - /* FIXME: need to update the GSI id in the ssdtx too */ - -} -#endif - unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); Modified: trunk/src/mainboard/intel/eagleheights/acpi_tables.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/acpi_tables.c Wed Apr 14 18:39:30 2010 (r5431) +++ trunk/src/mainboard/intel/eagleheights/acpi_tables.c Wed Apr 14 18:50:16 2010 (r5432) @@ -50,7 +50,7 @@ return current; } -void acpi_create_intel_hpet(acpi_hpet_t * hpet) +static void acpi_create_intel_hpet(acpi_hpet_t * hpet) { #define HPET_ADDR 0xfed00000ULL acpi_header_t *header = &(hpet->header); Modified: trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c Wed Apr 14 18:39:30 2010 (r5431) +++ trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c Wed Apr 14 18:50:16 2010 (r5432) @@ -157,31 +157,6 @@ return current; } - - -static void update_ssdtx(void *ssdtx, int i) -{ - uint8_t *PCI; - uint8_t *HCIN; - uint8_t *UID; - - PCI = ssdtx + 0x32; - HCIN = ssdtx + 0x39; - UID = ssdtx + 0x40; - - if(i<7) { - *PCI = (uint8_t) ('4' + i - 1); - } - else { - *PCI = (uint8_t) ('A' + i - 1 - 6); - } - *HCIN = (uint8_t) i; - *UID = (uint8_t) (i+3); - - /* FIXME: need to update the GSI id in the ssdtx too */ - -} - unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); return (unsigned long) (acpigen_get_current()); Modified: trunk/src/mainboard/kontron/kt690/acpi_tables.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/acpi_tables.c Wed Apr 14 18:39:30 2010 (r5431) +++ trunk/src/mainboard/kontron/kt690/acpi_tables.c Wed Apr 14 18:50:16 2010 (r5432) @@ -92,30 +92,6 @@ return current; } - - -static void update_ssdtx(void *ssdtx, int i) -{ - uint8_t *PCI; - uint8_t *HCIN; - uint8_t *UID; - - PCI = ssdtx + 0x32; - HCIN = ssdtx + 0x39; - UID = ssdtx + 0x40; - - if (i < 7) { - *PCI = (uint8_t) ('4' + i - 1); - } else { - *PCI = (uint8_t) ('A' + i - 1 - 6); - } - *HCIN = (uint8_t) i; - *UID = (uint8_t) (i + 3); - - /* FIXME: need to update the GSI id in the ssdtx too */ - -} - unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); Modified: trunk/src/mainboard/technexion/tim5690/acpi_tables.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/acpi_tables.c Wed Apr 14 18:39:30 2010 (r5431) +++ trunk/src/mainboard/technexion/tim5690/acpi_tables.c Wed Apr 14 18:50:16 2010 (r5432) @@ -92,30 +92,6 @@ return current; } - - -static void update_ssdtx(void *ssdtx, int i) -{ - uint8_t *PCI; - uint8_t *HCIN; - uint8_t *UID; - - PCI = ssdtx + 0x32; - HCIN = ssdtx + 0x39; - UID = ssdtx + 0x40; - - if (i < 7) { - *PCI = (uint8_t) ('4' + i - 1); - } else { - *PCI = (uint8_t) ('A' + i - 1 - 6); - } - *HCIN = (uint8_t) i; - *UID = (uint8_t) (i + 3); - - /* FIXME: need to update the GSI id in the ssdtx too */ - -} - unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); Modified: trunk/src/mainboard/technexion/tim8690/acpi_tables.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/acpi_tables.c Wed Apr 14 18:39:30 2010 (r5431) +++ trunk/src/mainboard/technexion/tim8690/acpi_tables.c Wed Apr 14 18:50:16 2010 (r5432) @@ -92,30 +92,6 @@ return current; } - - -static void update_ssdtx(void *ssdtx, int i) -{ - uint8_t *PCI; - uint8_t *HCIN; - uint8_t *UID; - - PCI = ssdtx + 0x32; - HCIN = ssdtx + 0x39; - UID = ssdtx + 0x40; - - if (i < 7) { - *PCI = (uint8_t) ('4' + i - 1); - } else { - *PCI = (uint8_t) ('A' + i - 1 - 6); - } - *HCIN = (uint8_t) i; - *UID = (uint8_t) (i + 3); - - /* FIXME: need to update the GSI id in the ssdtx too */ - -} - unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); amd_model_fxx_generate_powernow(pm_base + 8, 6, 1); Modified: trunk/src/mainboard/via/epia-m/acpi_tables.c ============================================================================== --- trunk/src/mainboard/via/epia-m/acpi_tables.c Wed Apr 14 18:39:30 2010 (r5431) +++ trunk/src/mainboard/via/epia-m/acpi_tables.c Wed Apr 14 18:50:16 2010 (r5432) @@ -42,8 +42,6 @@ unsigned long current; acpi_rsdp_t *rsdp; acpi_rsdt_t *rsdt; - acpi_hpet_t *hpet; - acpi_madt_t *madt; acpi_fadt_t *fadt; acpi_facs_t *facs; acpi_header_t *dsdt; Modified: trunk/src/mainboard/via/epia-m700/wakeup.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/wakeup.c Wed Apr 14 18:39:30 2010 (r5431) +++ trunk/src/mainboard/via/epia-m700/wakeup.c Wed Apr 14 18:50:16 2010 (r5432) @@ -133,12 +133,12 @@ //jason_tsc_count_end(); unsigned long long *real_mode_gdt_entries_at_eseg; - real_mode_gdt_entries_at_eseg = WAKE_THUNK16_GDT; /* Copy from real_mode_gdt_entries and change limition to 1M and data base to 0; */ + real_mode_gdt_entries_at_eseg = (void *)WAKE_THUNK16_GDT; /* Copy from real_mode_gdt_entries and change limition to 1M and data base to 0; */ real_mode_gdt_entries_at_eseg[0] = 0x0000000000000000ULL; /* Null descriptor */ real_mode_gdt_entries_at_eseg[1] = 0x000f9a000000ffffULL; /* 16-bit real-mode 1M code at 0x00000000 */ real_mode_gdt_entries_at_eseg[2] = 0x000f93000000ffffULL; /* 16-bit real-mode 1M data at 0x00000000 */ - wake_thunk16_Xgt_desc = WAKE_THUNK16_XDTR; + wake_thunk16_Xgt_desc = (void *)WAKE_THUNK16_XDTR; wake_thunk16_Xgt_desc[0].size = sizeof(real_mode_gdt_entries) - 1; wake_thunk16_Xgt_desc[0].address = (long)real_mode_gdt_entries_at_eseg; wake_thunk16_Xgt_desc[1].size = 0x3ff; @@ -156,7 +156,7 @@ unsigned char *dest, *src; src = (unsigned char *)dwEip; - dest = WAKE_RECOVER1M_CODE; + dest = (void *)WAKE_RECOVER1M_CODE; u32 i; for (i = 0; i < 0x200; i++) dest[i] = src[i]; Modified: trunk/src/northbridge/amd/amdfam10/amdfam10_acpi.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/amdfam10_acpi.c Wed Apr 14 18:39:30 2010 (r5431) +++ trunk/src/northbridge/amd/amdfam10/amdfam10_acpi.c Wed Apr 14 18:50:16 2010 (r5432) @@ -268,6 +268,28 @@ } +void update_ssdtx(void *ssdtx, int i) +{ + u8 *PCI; + u8 *HCIN; + u8 *UID; + + PCI = ssdtx + 0x32; + HCIN = ssdtx + 0x39; + UID = ssdtx + 0x40; + + if (i < 7) { + *PCI = (u8) ('4' + i - 1); + } else { + *PCI = (u8) ('A' + i - 1 - 6); + } + *HCIN = (u8) i; + *UID = (u8) (i + 3); + + /* FIXME: need to update the GSI id in the ssdtx too */ + +} + static void update_sspr(void *sspr, u32 nodeid, u32 cpuindex) { u8 *CPU; @@ -291,7 +313,7 @@ CONTROL = sspr + 0x8d; STATUS = sspr + 0x8f; - sprintf(CPU, "%02x", (char)cpuindex); + sprintf((char*)CPU, "%02x", (char)cpuindex); *CPUIN = (u8) cpuindex; for(i=0;i<sysconf.p_state_num;i++) { Modified: trunk/src/northbridge/amd/amdk8/amdk8_acpi.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/amdk8_acpi.c Wed Apr 14 18:39:30 2010 (r5431) +++ trunk/src/northbridge/amd/amdk8/amdk8_acpi.c Wed Apr 14 18:50:16 2010 (r5432) @@ -291,3 +291,26 @@ acpigen_patch_len(lens - 1); return lens; } + +void update_ssdtx(void *ssdtx, int i) +{ + u8 *PCI; + u8 *HCIN; + u8 *UID; + + PCI = ssdtx + 0x32; + HCIN = ssdtx + 0x39; + UID = ssdtx + 0x40; + + if (i < 7) { + *PCI = (u8) ('4' + i - 1); + } else { + *PCI = (u8) ('A' + i - 1 - 6); + } + *HCIN = (u8) i; + *UID = (u8) (i + 3); + + /* FIXME: need to update the GSI id in the ssdtx too */ + +} + Modified: trunk/src/northbridge/via/vx800/examples/romstage.c ============================================================================== --- trunk/src/northbridge/via/vx800/examples/romstage.c Wed Apr 14 18:39:30 2010 (r5431) +++ trunk/src/northbridge/via/vx800/examples/romstage.c Wed Apr 14 18:50:16 2010 (r5432) @@ -47,7 +47,7 @@ #include "northbridge/via/vx800/raminit.c" -int acpi_is_wakeup_early_via_vx800(void) +static int acpi_is_wakeup_early_via_vx800(void) { device_t dev; u16 tmp, result; Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Wed Apr 14 18:39:30 2010 (r5431) +++ trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Wed Apr 14 18:50:16 2010 (r5432) @@ -295,9 +295,10 @@ pci_write_config8(dev, 0x41, 0x7f); } +#ifdef CONFIG_NORTHBRIDGE_AMD_K8 /* CN700 doesn't have the support yet */ #define ACPI_IS_WAKEUP_EARLY 1 -int acpi_is_wakeup_early(void) { +static int acpi_is_wakeup_early(void) { device_t dev; u16 tmp; @@ -325,6 +326,7 @@ print_debug_hex8(tmp); return ((tmp & (7 << 10)) >> 10) == 1 ? 3 : 0 ; } +#endif #if defined(__GNUC__) void vt8237_early_spi_init(void)

1 0

[commit] r5431 - in trunk/src: mainboard/via/epia-m700 northbridge/via/vx800 northbridge/via/vx800/examples southbridge/via/k8t890
by repository service 14 Apr '10

14 Apr '10

Author: stepan Date: Wed Apr 14 18:39:30 2010 New Revision: 5431 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5431 Log: geeesh! And this really compiles and even runs? Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/via/epia-m700/romstage.c trunk/src/northbridge/via/vx800/detection.c trunk/src/northbridge/via/vx800/dev_init.c trunk/src/northbridge/via/vx800/dram_init.h trunk/src/northbridge/via/vx800/drdy_bl.c trunk/src/northbridge/via/vx800/examples/chipset_init.c trunk/src/northbridge/via/vx800/pci_rawops.h trunk/src/northbridge/via/vx800/uma_ram_setting.c trunk/src/northbridge/via/vx800/vx800_early_smbus.c trunk/src/southbridge/via/k8t890/k8t890_early_car.c Modified: trunk/src/mainboard/via/epia-m700/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/romstage.c Wed Apr 14 17:45:02 2010 (r5430) +++ trunk/src/mainboard/via/epia-m700/romstage.c Wed Apr 14 18:39:30 2010 (r5431) @@ -58,7 +58,7 @@ * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list: * http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html. */ -int acpi_is_wakeup_early_via_vx800(void) +static int acpi_is_wakeup_early_via_vx800(void) { device_t dev; u16 tmp, result; @@ -94,8 +94,6 @@ static void enable_mainboard_devices(void) { device_t dev; - uint16_t values; - #if 0 /* * Add and close this switch, since some line cause error, some @@ -145,6 +143,8 @@ #if 0 dev = 0; dev = pci_locate_device(PCI_ID(0x1106, PCI_DEVICE_ID_VIA_VX855_IDE), 0); + + uint16_t values; values = pci_read_config16(dev, 0xBA); values &= ~0xffff; values |= 0x5324; @@ -202,68 +202,68 @@ */ static const struct VIA_PCI_REG_INIT_TABLE mNbStage1InitTbl[] = { /* VT3409 no PCI-E */ - 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E, // Set Exxxxxxx as pcie mmio config range - 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B, // Support extended cfg address of pcie - // 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02, // APIC Interrupt((BT_INTR)) Control + { 0x00, 0xFF, NB_APIC_REG(0x61), 0xFF, 0x0E }, // Set Exxxxxxx as pcie mmio config range + { 0x00, 0xFF, NB_APIC_REG(0x60), 0xF4, 0x0B }, // Support extended cfg address of pcie + // { 0x00, 0xFF, NB_APIC_REG(0x42), 0xF9, 0x02 }, // APIC Interrupt((BT_INTR)) Control // Set ROMSIP value by software /* - 0x00, 0xFF, NB_HOST_REG(0x70), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pullup Driving = 3 - 0x00, 0xFF, NB_HOST_REG(0x71), 0x77, 0x33, // 2x Host Adr Strobe/Pad Pulldown Driving = 3 - 0x00, 0xFF, NB_HOST_REG(0x72), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pullup Driving = 3 - 0x00, 0xFF, NB_HOST_REG(0x73), 0x77, 0x33, // 4x Host Dat Strobe/Pad Pulldown Driving = 3 - 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0x21, // Memory I/F timing ctrl - 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0xE1, // Memory I/F timing ctrl - 0x00, 0xFF, NB_HOST_REG(0x75), 0xFF, 0x18, // AGTL+ I/O Circuit - 0x00, 0xFF, NB_HOST_REG(0x76), 0xFB, 0x0C, // AGTL+ Compensation Status - 0x00, 0xFF, NB_HOST_REG(0x78), 0xFF, 0x33, // 2X AGTL+ Auto Compensation Offset - 0x00, 0xFF, NB_HOST_REG(0x79), 0xFF, 0x33, // 4X AGTL+ Auto Compensation Offset - 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x72, // AGTL Compensation Status - 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x77, // AGTL Compensation Status - 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x44, // Input Host Address / Host Strobe Delay Control for HA Group - 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x22, // Input Host Address / Host Strobe Delay Control for HA Group - 0x00, 0xFF, NB_HOST_REG(0x7C), 0xFF, 0x00, // Output Delay Control of PAD for HA Group - 0x00, 0xFF, NB_HOST_REG(0x7D), 0xFF, 0xAA, // Host Address / Address Clock Output Delay Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x10, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x40, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) - 0x00, 0xFF, NB_HOST_REG(0x80), 0x3F, 0x44, // Host Data Receiving Strobe Delay Ctrl 1 - 0x00, 0xFF, NB_HOST_REG(0x81), 0xFF, 0x44, // Host Data Receiving Strobe Delay Ctrl 2 - 0x00, 0xFF, NB_HOST_REG(0x82), 0xFF, 0x00, // Output Delay of PAD for HDSTB - 0x00, 0xFF, NB_HOST_REG(0x83), 0xFF, 0x00, // Output Delay of PAD for HD - 0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 0) - 0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 1) - 0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 2) - 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44, // Host Data / Strobe CKG Control (Group 3) + { 0x00, 0xFF, NB_HOST_REG(0x70), 0x77, 0x33 }, // 2x Host Adr Strobe/Pad Pullup Driving = 3 + { 0x00, 0xFF, NB_HOST_REG(0x71), 0x77, 0x33 }, // 2x Host Adr Strobe/Pad Pulldown Driving = 3 + { 0x00, 0xFF, NB_HOST_REG(0x72), 0x77, 0x33 }, // 4x Host Dat Strobe/Pad Pullup Driving = 3 + { 0x00, 0xFF, NB_HOST_REG(0x73), 0x77, 0x33 }, // 4x Host Dat Strobe/Pad Pulldown Driving = 3 + { 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0x21 }, // Memory I/F timing ctrl + { 0x00, 0xFF, NB_HOST_REG(0x74), 0xFF, 0xE1 }, // Memory I/F timing ctrl + { 0x00, 0xFF, NB_HOST_REG(0x75), 0xFF, 0x18 }, // AGTL+ I/O Circuit + { 0x00, 0xFF, NB_HOST_REG(0x76), 0xFB, 0x0C }, // AGTL+ Compensation Status + { 0x00, 0xFF, NB_HOST_REG(0x78), 0xFF, 0x33 }, // 2X AGTL+ Auto Compensation Offset + { 0x00, 0xFF, NB_HOST_REG(0x79), 0xFF, 0x33 }, // 4X AGTL+ Auto Compensation Offset + { 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x72 }, // AGTL Compensation Status + { 0x00, 0xFF, NB_HOST_REG(0x7A), 0x3F, 0x77 }, // AGTL Compensation Status + { 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x44 }, // Input Host Address / Host Strobe Delay Control for HA Group + { 0x00, 0xFF, NB_HOST_REG(0x7B), 0xFF, 0x22 }, // Input Host Address / Host Strobe Delay Control for HA Group + { 0x00, 0xFF, NB_HOST_REG(0x7C), 0xFF, 0x00 }, // Output Delay Control of PAD for HA Group + { 0x00, 0xFF, NB_HOST_REG(0x7D), 0xFF, 0xAA }, // Host Address / Address Clock Output Delay Control (Only for P4 Bus) + { 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x10 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) + { 0x00, 0xFF, NB_HOST_REG(0x7E), 0xFF, 0x40 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) + { 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x10 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) + { 0x00, 0xFF, NB_HOST_REG(0x7F), 0xFF, 0x40 }, // Host Address CKG Rising / Falling Time Control (Only for P4 Bus) + { 0x00, 0xFF, NB_HOST_REG(0x80), 0x3F, 0x44 }, // Host Data Receiving Strobe Delay Ctrl 1 + { 0x00, 0xFF, NB_HOST_REG(0x81), 0xFF, 0x44 }, // Host Data Receiving Strobe Delay Ctrl 2 + { 0x00, 0xFF, NB_HOST_REG(0x82), 0xFF, 0x00 }, // Output Delay of PAD for HDSTB + { 0x00, 0xFF, NB_HOST_REG(0x83), 0xFF, 0x00 }, // Output Delay of PAD for HD + { 0x00, 0xFF, NB_HOST_REG(0x84), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 0) + { 0x00, 0xFF, NB_HOST_REG(0x85), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 1) + { 0x00, 0xFF, NB_HOST_REG(0x86), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 2) + { 0x00, 0xFF, NB_HOST_REG(0x87), 0xFF, 0x44 }, // Host Data / Strobe CKG Control (Group 3) */ // CPU Host Bus Control - 0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8 - // 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW - 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW - 0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB, // CPU I/F Ctrl-2: Enable all for performance - // 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK - 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK - 0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C, // Misc Ctrl: Enable 8QW burst Mem Access - // 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06, // Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04, // Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63, // Write Policy 1 - // 0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL - // 0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00, // CPU Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2, // Write Policy - 0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88, // Bandwidth Timer - 0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46, // CPU Misc Ctrl - // 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B, // CPU Miscellaneous Control 3 - // 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B, // CPU Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A, // CPU Miscellaneous Control 2 - 0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41, // CPU Miscellaneous Control 3 - 0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06, // CPU Miscellaneous Control 4 + { 0x00, 0xFF, NB_HOST_REG(0x50), 0x1F, 0x08 }, // Request phase ctrl: Dynamic Defer Snoop Stall Count = 8 + // { 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7F }, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW + { 0x00, 0xFF, NB_HOST_REG(0x51), 0xFF, 0x7C }, // CPU I/F Ctrl-1: Disable Fast DRDY and RAW + { 0x00, 0xFF, NB_HOST_REG(0x52), 0xCB, 0xCB }, // CPU I/F Ctrl-2: Enable all for performance + // { 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x88 }, // Arbitration: Host/Master Occupancy timer = 8*4 HCLK + { 0x00, 0xFF, NB_HOST_REG(0x53), 0xFF, 0x44 }, // Arbitration: Host/Master Occupancy timer = 4*4 HCLK + { 0x00, 0xFF, NB_HOST_REG(0x54), 0x1E, 0x1C }, // Misc Ctrl: Enable 8QW burst Mem Access + // { 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x06 }, // Miscellaneous Control 2 + { 0x00, 0xFF, NB_HOST_REG(0x55), 0x06, 0x04 }, // Miscellaneous Control 2 + { 0x00, 0xFF, NB_HOST_REG(0x56), 0xF7, 0x63 }, // Write Policy 1 + // { 0x00, 0xFF, NB_HOST_REG(0x59), 0x3D, 0x01 }, // CPU Miscellaneous Control 1, enable Lowest-Priority IPL + // { 0x00, 0xFF, NB_HOST_REG(0x5c), 0xFF, 0x00 }, // CPU Miscellaneous Control 2 + { 0x00, 0xFF, NB_HOST_REG(0x5D), 0xFF, 0xA2 }, // Write Policy + { 0x00, 0xFF, NB_HOST_REG(0x5E), 0xFF, 0x88 }, // Bandwidth Timer + { 0x00, 0xFF, NB_HOST_REG(0x5F), 0x46, 0x46 }, // CPU Misc Ctrl + // { 0x00, 0xFF, NB_HOST_REG(0x90), 0xFF, 0x0B }, // CPU Miscellaneous Control 3 + // { 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0B }, // CPU Miscellaneous Control 2 + { 0x00, 0xFF, NB_HOST_REG(0x96), 0x0B, 0x0A }, // CPU Miscellaneous Control 2 + { 0x00, 0xFF, NB_HOST_REG(0x98), 0xC1, 0x41 }, // CPU Miscellaneous Control 3 + { 0x00, 0xFF, NB_HOST_REG(0x99), 0x0E, 0x06 }, // CPU Miscellaneous Control 4 // Set APIC and SMRAM - 0x00, 0xFF, NB_HOST_REG(0x97), 0xFF, 0x00, // APIC Related Control - 0x00, 0xFF, NB_DRAMC_REG(0x86), 0xD6, 0x29, // SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg - 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // End of the table + { 0x00, 0xFF, NB_HOST_REG(0x97), 0xFF, 0x00 }, // APIC Related Control + { 0x00, 0xFF, NB_DRAMC_REG(0x86), 0xD6, 0x29 }, // SMM and APIC Decoding: enable APIC, MSI and SMRAM A-Seg + { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } // End of the table }; #define USE_VCP 1 /* 0 means "use DVP". */ @@ -383,7 +383,6 @@ /* cache_as_ram.inc jumps to here. */ void main(unsigned long bist) { - unsigned cpu_reset = 0; u16 boot_mode; u8 rambits, Data8, Data; device_t device; Modified: trunk/src/northbridge/via/vx800/detection.c ============================================================================== --- trunk/src/northbridge/via/vx800/detection.c Wed Apr 14 17:45:02 2010 (r5430) +++ trunk/src/northbridge/via/vx800/detection.c Wed Apr 14 18:39:30 2010 (r5431) @@ -17,6 +17,11 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +/* FIXME this should go away */ +static const struct mem_controller ctrl = { + .channel0 = {0x50, 0x51}, +}; + #define SMBUS_ADDR_CH_A_1 0xA0 /* Dimmx */ #define SMBUS_ADDR_CH_A_2 0xA2 /* Dimmx */ #define SMBUS_ADDR_CH_B_1 0xA4 /* Dimmx */ Modified: trunk/src/northbridge/via/vx800/dev_init.c ============================================================================== --- trunk/src/northbridge/via/vx800/dev_init.c Wed Apr 14 17:45:02 2010 (r5430) +++ trunk/src/northbridge/via/vx800/dev_init.c Wed Apr 14 18:39:30 2010 (r5431) @@ -166,7 +166,7 @@ #define EXIST_TEST_PATTERN 0x55555555 #define NOT_EXIST_TEST_PATTERN 0xAAAAAAAA -BOOLEAN ChkForExistLowBank(void) +static BOOLEAN ChkForExistLowBank(void) { u32 *Address, data32; @@ -207,9 +207,6 @@ return TRUE; } -void InitDDR2CHC(DRAM_SYS_ATTR *DramAttr); -void InitDDR2CHB(DRAM_SYS_ATTR *DramAttr); - void DRAMInitializeProc(DRAM_SYS_ATTR *DramAttr) { u8 shift, idx; Modified: trunk/src/northbridge/via/vx800/dram_init.h ============================================================================== --- trunk/src/northbridge/via/vx800/dram_init.h Wed Apr 14 17:45:02 2010 (r5430) +++ trunk/src/northbridge/via/vx800/dram_init.h Wed Apr 14 18:39:30 2010 (r5431) @@ -121,10 +121,6 @@ u8 channel0[MAX_DIMMS]; }; -static const struct mem_controller ctrl = { - .channel0 = {0x50, 0x51}, -}; - typedef struct _DRAM_CONFIG_DATA { u8 DramClk; u8 DramTiming; Modified: trunk/src/northbridge/via/vx800/drdy_bl.c ============================================================================== --- trunk/src/northbridge/via/vx800/drdy_bl.c Wed Apr 14 17:45:02 2010 (r5430) +++ trunk/src/northbridge/via/vx800/drdy_bl.c Wed Apr 14 18:39:30 2010 (r5431) @@ -404,10 +404,7 @@ void DRAMDRDYSetting(DRAM_SYS_ATTR * DramAttr) { - u8 Data, CL, RDRPH; - u8 CpuFreq, DramFreq; - u8 ProgData[PT894_RDRDY_TBL_Width]; - + u8 Data; /* this function has 3 switchs, correspond to 3 level of Drdy setting. 0:Slowest, 1:Default, 2:Optimize @@ -464,6 +461,9 @@ } #endif #if 0 // 2:Optimize + u8 CpuFreq, DramFreq; + u8 CL, RDRPH; + //CL :reg6x[2:0] Data = pci_read_config8(MEMCTRL, 0x62); CL = Data & 0x07; @@ -484,6 +484,8 @@ DelayMode = CL + RDRPH; // RDELAYMD = bit0 of (CAS Latency + RDRPH) DelayMode &= 0x01; + u8 ProgData[PT894_RDRDY_TBL_Width]; + //In 364, there is no 128 bit if (DelayMode == 1) { // DelayMode 1 u8 Index; Modified: trunk/src/northbridge/via/vx800/examples/chipset_init.c ============================================================================== --- trunk/src/northbridge/via/vx800/examples/chipset_init.c Wed Apr 14 17:45:02 2010 (r5430) +++ trunk/src/northbridge/via/vx800/examples/chipset_init.c Wed Apr 14 18:39:30 2010 (r5431) @@ -43,12 +43,12 @@ {0x00, 0xFF, SB_VLINK_REG(0xE6), 0xFF, 0x39}, // Enable SMM A-Seg, MSI and Io APIC ///// SPI-BAR. //// SPI_BASE_ADDRESS = 0xFED1 0000 - 0x00, 0xFF, SB_LPC_REG(0xBC), 0xFF, 0x00, - 0x00, 0xFF, SB_LPC_REG(0xBD), 0xFF, 0xD1, - 0x00, 0xFF, SB_LPC_REG(0xBE), 0xFF, 0xFE, -// 0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBC), 0xFF, 0x00,//this , for the different macro -// 0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBD), 0xFF, 0xD1, -// 0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBE), 0xFF, 0xFE, + {0x00, 0xFF, SB_LPC_REG(0xBC), 0xFF, 0x00}, + {0x00, 0xFF, SB_LPC_REG(0xBD), 0xFF, 0xD1}, + {0x00, 0xFF, SB_LPC_REG(0xBE), 0xFF, 0xFE}, +// {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBC), 0xFF, 0x00},//this , for the different macro +// {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBD), 0xFF, 0xD1}, +// {0x00, 0xFF, ((0x11<<16)|(0x00<<8)|0xBE), 0xFF, 0xFE}, ///// End of 2008-04-17 {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table @@ -60,191 +60,184 @@ // D0F2~D0F3 is configured by MemoryInit Peim // D0F4: NB PMU - 0x00, 0xFF, NB_PMU_REG(0x84), 0x00, 0xDB, - 0x00, 0xFF, NB_PMU_REG(0x85), 0x00, 0x05, - 0x00, 0xFF, NB_PMU_REG(0x89), 0x00, 0xF8, - 0x00, 0xFF, NB_PMU_REG(0x8B), 0x00, 0xBF, - 0x00, 0xFF, NB_PMU_REG(0x8D), 0x00, 0xFC, - 0x00, 0xFF, NB_PMU_REG(0x8E), 0x00, 0x19, - 0x00, 0xFF, NB_PMU_REG(0x8F), 0x03, 0x00, - 0x00, 0xFF, NB_PMU_REG(0x90), 0x00, 0xFF, - 0x00, 0xFF, NB_PMU_REG(0x91), 0x00, 0xFF, - 0x00, 0xFF, NB_PMU_REG(0x92), 0x00, 0xCC, - 0x00, 0xFF, NB_PMU_REG(0xA0), 0x00, 0x80, - 0x00, 0xFF, NB_PMU_REG(0xA1), 0x00, 0xE0, - 0x00, 0xFF, NB_PMU_REG(0xA2), 0x00, 0xD6, - 0x00, 0xFF, NB_PMU_REG(0xA3), 0x00, 0x80, - 0x00, 0xFF, NB_PMU_REG(0xA8), 0x00, 0x20, + { 0x00, 0xFF, NB_PMU_REG(0x84), 0x00, 0xDB }, + { 0x00, 0xFF, NB_PMU_REG(0x85), 0x00, 0x05 }, + { 0x00, 0xFF, NB_PMU_REG(0x89), 0x00, 0xF8 }, + { 0x00, 0xFF, NB_PMU_REG(0x8B), 0x00, 0xBF }, + { 0x00, 0xFF, NB_PMU_REG(0x8D), 0x00, 0xFC }, + { 0x00, 0xFF, NB_PMU_REG(0x8E), 0x00, 0x19 }, + { 0x00, 0xFF, NB_PMU_REG(0x8F), 0x03, 0x00 }, + { 0x00, 0xFF, NB_PMU_REG(0x90), 0x00, 0xFF }, + { 0x00, 0xFF, NB_PMU_REG(0x91), 0x00, 0xFF }, + { 0x00, 0xFF, NB_PMU_REG(0x92), 0x00, 0xCC }, + { 0x00, 0xFF, NB_PMU_REG(0xA0), 0x00, 0x80 }, + { 0x00, 0xFF, NB_PMU_REG(0xA1), 0x00, 0xE0 }, + { 0x00, 0xFF, NB_PMU_REG(0xA2), 0x00, 0xD6 }, + { 0x00, 0xFF, NB_PMU_REG(0xA3), 0x00, 0x80 }, + { 0x00, 0xFF, NB_PMU_REG(0xA8), 0x00, 0x20 }, // D0F5: NB APIC, PXPTRF and MSGC //Note: the Rx6A, RCRBH Base Address, is not set, which is related to PCIE Root Complex. //Note: the Rx60, Extended CFG Address. Support and Rx61, Extended CFG Address, are set by NB Peim that is in the PEI Phase. //Note: the Rx42, APIC Interrupt((BT_INTR)) Control, is set by NB Peim that is in PEI phase. - 0x00, 0xFF, NB_PXPTRF_REG(0x50), 0x00, 0x00, - 0x00, 0xFF, NB_PXPTRF_REG(0x54), 0x00, 0x80, - 0x00, 0xFF, NB_PXPTRF_REG(0x55), 0x00, 0x04, - 0x00, 0xFF, NB_PXPTRF_REG(0x58), 0x00, 0x00, - 0x00, 0xFF, NB_PXPTRF_REG(0x59), 0x00, 0x02, - 0x00, 0xFF, NB_PXPTRF_REG(0x5E), 0x00, 0x00, - 0x00, 0xFF, NB_PXPTRF_REG(0x5F), 0x00, 0x06, - 0x00, 0xFF, NB_PXPTRF_REG(0x80), 0x00, 0x18, //Set RVC1DM, RTHBHIT, RUWRDYD, RUPRRDY1, RUWPOPHD to 1. - 0x00, 0xFF, NB_PXPTRF_REG(0x82), 0x00, 0x00, //Set RVC1RPSW, RVC1RQ1T to 1. - 0x00, 0xFF, NB_PXPTRF_REG(0x83), 0x00, 0x81, - 0x00, 0xFF, NB_PXPTRF_REG(0x84), 0x00, 0x28, - 0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0xC0, - 0x00, 0xFF, NB_MSGC_REG(0xA3), 0x00, 0x01, // RWAKEEN -// 0x00, 0xFF, NB_PXPTRF_REG(0x64), 0x40, 0x00, //RTDNP2B32EN - 0x00, 0xFF, NB_PXPTRF_REG(0xF3), 0xFC, 0x20, - 0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0x00, //RP2P1ABORT + { 0x00, 0xFF, NB_PXPTRF_REG(0x50), 0x00, 0x00 }, + { 0x00, 0xFF, NB_PXPTRF_REG(0x54), 0x00, 0x80 }, + { 0x00, 0xFF, NB_PXPTRF_REG(0x55), 0x00, 0x04 }, + { 0x00, 0xFF, NB_PXPTRF_REG(0x58), 0x00, 0x00 }, + { 0x00, 0xFF, NB_PXPTRF_REG(0x59), 0x00, 0x02 }, + { 0x00, 0xFF, NB_PXPTRF_REG(0x5E), 0x00, 0x00 }, + { 0x00, 0xFF, NB_PXPTRF_REG(0x5F), 0x00, 0x06 }, + { 0x00, 0xFF, NB_PXPTRF_REG(0x80), 0x00, 0x18 }, //Set RVC1DM, RTHBHIT, RUWRDYD, RUPRRDY1, RUWPOPHD to 1. + { 0x00, 0xFF, NB_PXPTRF_REG(0x82), 0x00, 0x00 }, //Set RVC1RPSW, RVC1RQ1T to 1. + { 0x00, 0xFF, NB_PXPTRF_REG(0x83), 0x00, 0x81 }, + { 0x00, 0xFF, NB_PXPTRF_REG(0x84), 0x00, 0x28 }, + { 0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0xC0 }, + { 0x00, 0xFF, NB_MSGC_REG(0xA3), 0x00, 0x01 }, // RWAKEEN + //{ 0x00, 0xFF, NB_PXPTRF_REG(0x64), 0x40, 0x00 }, //RTDNP2B32EN + { 0x00, 0xFF, NB_PXPTRF_REG(0xF3), 0xFC, 0x20 }, + { 0x00, 0xFF, NB_PXPTRF_REG(0x85), 0x00, 0x00 }, //RP2P1ABORT // fine-tune // If no settings, C7 will hang or reboot in XP, but CN will not. - 0x00, 0xFF, NB_HOST_REG(0x51), 0x84, 0x00, - 0x00, 0xFF, NB_HOST_REG(0x52), 0x0F, 0x03, - 0x00, 0xFF, NB_HOST_REG(0x54), 0x04, 0x00, - 0x00, 0xFF, NB_HOST_REG(0x55), 0x04, 0x00, - 0x00, 0xFF, NB_HOST_REG(0x59), 0x09, 0x01, - 0x00, 0xFF, NB_HOST_REG(0x5C), 0x10, 0x10, - 0x00, 0xFF, NB_HOST_REG(0x5F), 0x0E, 0x08, - 0x00, 0xFF, NB_HOST_REG(0x92), 0xFF, 0x04, // ACPI Base addr - 0x00, 0xFF, NB_HOST_REG(0x97), 0x01, 0x01, // APIC MSI - 0x00, 0xFF, NB_HOST_REG(0x99), 0x02, 0x00, // APIC MSI + { 0x00, 0xFF, NB_HOST_REG(0x51), 0x84, 0x00 }, + { 0x00, 0xFF, NB_HOST_REG(0x52), 0x0F, 0x03 }, + { 0x00, 0xFF, NB_HOST_REG(0x54), 0x04, 0x00 }, + { 0x00, 0xFF, NB_HOST_REG(0x55), 0x04, 0x00 }, + { 0x00, 0xFF, NB_HOST_REG(0x59), 0x09, 0x01 }, + { 0x00, 0xFF, NB_HOST_REG(0x5C), 0x10, 0x10 }, + { 0x00, 0xFF, NB_HOST_REG(0x5F), 0x0E, 0x08 }, + { 0x00, 0xFF, NB_HOST_REG(0x92), 0xFF, 0x04 }, // ACPI Base addr + { 0x00, 0xFF, NB_HOST_REG(0x97), 0x01, 0x01 }, // APIC MSI + { 0x00, 0xFF, NB_HOST_REG(0x99), 0x02, 0x00 }, // APIC MSI //GTL - 0x00, 0xFF, NB_HOST_REG(0x73), 0xFF, 0x66, - 0x00, 0xFF, NB_HOST_REG(0xB2), 0xFF, 0x33, - 0x00, 0xFF, NB_HOST_REG(0xB3), 0xFF, 0x33, - 0x00, 0xFF, NB_HOST_REG(0xBC), 0xFF, 0x33, - 0x00, 0xFF, NB_HOST_REG(0xBD), 0xFF, 0x33, - 0x00, 0xFF, NB_HOST_REG(0xC5), 0x30, 0x20, - 0x00, 0xFF, NB_HOST_REG(0xC8), 0x10, 0x00, + { 0x00, 0xFF, NB_HOST_REG(0x73), 0xFF, 0x66 }, + { 0x00, 0xFF, NB_HOST_REG(0xB2), 0xFF, 0x33 }, + { 0x00, 0xFF, NB_HOST_REG(0xB3), 0xFF, 0x33 }, + { 0x00, 0xFF, NB_HOST_REG(0xBC), 0xFF, 0x33 }, + { 0x00, 0xFF, NB_HOST_REG(0xBD), 0xFF, 0x33 }, + { 0x00, 0xFF, NB_HOST_REG(0xC5), 0x30, 0x20 }, + { 0x00, 0xFF, NB_HOST_REG(0xC8), 0x10, 0x00 }, // End of Table {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table - }; static const struct VIA_PCI_REG_INIT_TABLE mBusControllerInitTable[] = { // D17F0: LPC - 0x00, 0xFF, SB_LPC_REG(0x40), 0x44, 0x44, // Enable I/O Recovery Time, 4D0/4D1 Support - 0x00, 0xFF, SB_LPC_REG(0x42), 0xF8, 0xF0, // ENLBUF, GINTREN, FLUSHEN, RBRSTRD - 0x00, 0xFF, SB_LPC_REG(0x43), 0x0F, 0x0B, // RENDTX, ENWBTO, ENRBTO - // 0x00, 0xFF, SB_LPC_REG(0x46), 0x00, 0x10, // It is related to INTH# - //0x00, 0xFF, SB_LPC_REG(0x48), 0x00, 0x0C, //RMRPW, RIRPW // Reserved in 409 by Eric + { 0x00, 0xFF, SB_LPC_REG(0x40), 0x44, 0x44 }, // Enable I/O Recovery Time, 4D0/4D1 Support + { 0x00, 0xFF, SB_LPC_REG(0x42), 0xF8, 0xF0 }, // ENLBUF, GINTREN, FLUSHEN, RBRSTRD + { 0x00, 0xFF, SB_LPC_REG(0x43), 0x0F, 0x0B }, // RENDTX, ENWBTO, ENRBTO + //{ 0x00, 0xFF, SB_LPC_REG(0x46), 0x00, 0x10 }, // It is related to INTH# + //{ 0x00, 0xFF, SB_LPC_REG(0x48), 0x00, 0x0C }, //RMRPW, RIRPW // Reserved in 409 by Eric // Internal RTC, Mouse, Keyboard // set in PEI by Eric - //0x00, 0xFF, SB_LPC_REG(0x51), 0x10, 0x0D, // Enable Internal RTC, Internal PS2 Mouse/Keyboard + //{ 0x00, 0xFF, SB_LPC_REG(0x51), 0x10, 0x0D }, // Enable Internal RTC, Internal PS2 Mouse/Keyboard // RTC - 0x00, 0xFF, SB_LPC_REG(0x58), 0x00, 0x01, //RTC Rx32 Map to Centrury Byte + { 0x00, 0xFF, SB_LPC_REG(0x58), 0x00, 0x01 }, //RTC Rx32 Map to Centrury Byte - // 0x00, 0xFF, SB_LPC_REG(0x40), 0x00, 0x02, // RDMEGAS - //0x00, 0xFF, SB_LPC_REG(0x4E), 0x00, 0x08, // Enable RTC port 74/75, ENEXRTC // set in PEI by Eric + //{ 0x00, 0xFF, SB_LPC_REG(0x40), 0x00, 0x02 }, // RDMEGAS + //{ 0x00, 0xFF, SB_LPC_REG(0x4E), 0x00, 0x08 }, // Enable RTC port 74/75, ENEXRTC // set in PEI by Eric // Serial IRQ // set in PEI by Eric - //0x00, 0xFF, SB_LPC_REG(0x52), 0x0F, 0x09, // Enable Serial IRQ, Start Frame Width is 6 PCI Clock. + //{ 0x00, 0xFF, SB_LPC_REG(0x52), 0x0F, 0x09 }, // Enable Serial IRQ, Start Frame Width is 6 PCI Clock. // Enable 4D0h/4D1h Port - //0x00, 0xFF, SB_LPC_REG(0x40), 0x00, 0x04, // EISAXT // set in PEI by Eric + //{ 0x00, 0xFF, SB_LPC_REG(0x40), 0x00, 0x04 }, // EISAXT // set in PEI by Eric // Config ROM Interface // Enable SPI/Set SPI Memory Base Address // It is initialized in PEI Phase // Subsystem ID/Vendor ID Back Door - 0x00, 0xFF, SB_LPC_REG(0x70), 0xFF, 0x06, - 0x00, 0xFF, SB_LPC_REG(0x71), 0xFF, 0x11, - 0x00, 0xFF, SB_LPC_REG(0x72), 0xFF, 0x09, - 0x00, 0xFF, SB_LPC_REG(0x73), 0xFF, 0x34, - - 0x00, 0xFF, SB_LPC_REG(0x4C), 0xC0, 0x40, - 0x00, 0xFF, SB_LPC_REG(0x5B), 0x00, 0x51, // Orgin value 0x53, modify for 409 by Eric - 0x00, 0xFF, SB_LPC_REG(0x67), 0x03, 0x01, + { 0x00, 0xFF, SB_LPC_REG(0x70), 0xFF, 0x06 }, + { 0x00, 0xFF, SB_LPC_REG(0x71), 0xFF, 0x11 }, + { 0x00, 0xFF, SB_LPC_REG(0x72), 0xFF, 0x09 }, + { 0x00, 0xFF, SB_LPC_REG(0x73), 0xFF, 0x34 }, + + { 0x00, 0xFF, SB_LPC_REG(0x4C), 0xC0, 0x40 }, + { 0x00, 0xFF, SB_LPC_REG(0x5B), 0x00, 0x51 }, // Orgin value 0x53, modify for 409 by Eric + { 0x00, 0xFF, SB_LPC_REG(0x67), 0x03, 0x01 }, - 0x00, 0xFF, SB_LPC_REG(0x50), 0x7E, 0x00, // Setting PCI device enable - 0x00, 0xFF, SB_LPC_REG(0x51), 0xD0, 0x00, // Setting PCI device enable - 0x00, 0xFF, SB_VLINK_REG(0xD1), 0x04, 0x00, // Setting HDAC enable + { 0x00, 0xFF, SB_LPC_REG(0x50), 0x7E, 0x00 }, // Setting PCI device enable + { 0x00, 0xFF, SB_LPC_REG(0x51), 0xD0, 0x00 }, // Setting PCI device enable + { 0x00, 0xFF, SB_VLINK_REG(0xD1), 0x04, 0x00 }, // Setting HDAC enable {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table }; static const struct VIA_PCI_REG_INIT_TABLE mPCI1InitTable[] = { //PCI1 Programming Sequence //(1)Configure D17F7 - 0x00, 0xFF, SB_VLINK_REG(0x04), 0x00, 0x03, - 0x00, 0xFF, SB_VLINK_REG(0x0C), 0x00, 0x08, // Reserved in 409 by Eric - 0x00, 0xFF, SB_VLINK_REG(0x4F), 0x40, 0x41, //RENPPB, RP2CFLSH - 0x00, 0xFF, SB_VLINK_REG(0x77), 0x00, 0x48, //ROP2CFLSH, RFFTMR[1:0]. ROP2CFLSH work with Rx4F[0](RP2CFLSH) assertion - // 0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x80, //RSUB_DEC_P2P, RSUBDECOD(Window xp). If Bit7 is set, PCI lock will occured. - //0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x81, //RSUB_DEC_P2P, RSUBDECOD(Window Vista) + { 0x00, 0xFF, SB_VLINK_REG(0x04), 0x00, 0x03 }, + { 0x00, 0xFF, SB_VLINK_REG(0x0C), 0x00, 0x08 }, // Reserved in 409 by Eric + { 0x00, 0xFF, SB_VLINK_REG(0x4F), 0x40, 0x41 }, //RENPPB, RP2CFLSH + { 0x00, 0xFF, SB_VLINK_REG(0x77), 0x00, 0x48 }, //ROP2CFLSH, RFFTMR[1:0]. ROP2CFLSH work with Rx4F[0](RP2CFLSH) assertion + // { 0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x80 }, //RSUB_DEC_P2P, RSUBDECOD(Window xp). If Bit7 is set, PCI lock will occured. + // { 0x00, 0xFF, SB_VLINK_REG(0x51), 0x00, 0x81 }, //RSUB_DEC_P2P, RSUBDECOD(Window Vista) //(2)Configure D19F0 - 0x00, 0xFF, SB_P2PB_REG(0x04), 0x00, 0x07, + { 0x00, 0xFF, SB_P2PB_REG(0x04), 0x00, 0x07 }, //(3)Performance Recommended Setting //Save Power - 0x00, 0xFF, SB_VLINK_REG(0xE2), 0x1F, 0x01, - 0x00, 0xFF, SB_VLINK_REG(0xE3), 0xF1, 0x5E, - 0x00, 0xFF, SB_VLINK_REG(0x74), 0x40, 0x00, + { 0x00, 0xFF, SB_VLINK_REG(0xE2), 0x1F, 0x01 }, + { 0x00, 0xFF, SB_VLINK_REG(0xE3), 0xF1, 0x5E }, + { 0x00, 0xFF, SB_VLINK_REG(0x74), 0x40, 0x00 }, //Enhence Host To PCI cycle performance and PCI-To-Host Cycle performance - 0x00, 0xFF, SB_VLINK_REG(0x70), 0x00, 0x82, - 0x00, 0xFF, SB_VLINK_REG(0x71), 0x30, 0xC0, - 0x00, 0xFF, SB_VLINK_REG(0x72), 0x00, 0xEE, + { 0x00, 0xFF, SB_VLINK_REG(0x70), 0x00, 0x82 }, + { 0x00, 0xFF, SB_VLINK_REG(0x71), 0x30, 0xC0 }, + { 0x00, 0xFF, SB_VLINK_REG(0x72), 0x00, 0xEE }, //Cycle Control - 0x00, 0xFF, SB_VLINK_REG(0x73), 0x00, 0x01, - 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x0C, + { 0x00, 0xFF, SB_VLINK_REG(0x73), 0x00, 0x01 }, + { 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x0C }, //Arbitration control - 0x00, 0xFF, SB_VLINK_REG(0x75), 0x00, 0x0F, - 0x00, 0xFF, SB_VLINK_REG(0x76), 0x00, 0xD0, + { 0x00, 0xFF, SB_VLINK_REG(0x75), 0x00, 0x0F }, + { 0x00, 0xFF, SB_VLINK_REG(0x76), 0x00, 0xD0 }, {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table }; static const struct VIA_PCI_REG_INIT_TABLE mCCAInitTable[] = { - - 0x00, 0xFF, SB_VLINK_REG(0xFC), 0x02, 0x08, //RVWREQ, ROABKDOOR + { 0x00, 0xFF, SB_VLINK_REG(0xFC), 0x02, 0x08 }, //RVWREQ, ROABKDOOR //CCA's Register Programming sequence - 0x00, 0xFF, SB_VLINK_REG(0x50), 0x00, 0x08, //Config Azalia's upstream cycle high priority and other low priority - 0x00, 0xFF, SB_VLINK_REG(0x51), 0x40, 0x80, //Disable bypass asynchronous circuit - 0x00, 0xFF, SB_VLINK_REG(0x52), 0x00, 0x11, // Set SM Internal Device and HDAC Occupy Timer - 0x00, 0xFF, SB_VLINK_REG(0x53), 0x00, 0x11, // Set SM Internal Device and HDAC Promote Timer - 0x00, 0xFF, SB_VLINK_REG(0x54), 0xFF, 0x02, //Use SB internal devices's original REQ - 0x00, 0xFF, SB_VLINK_REG(0x73), 0x10, 0x00, //RPINOWSC. Enable APIC Cycle Block P2C Write Cycle - 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x3C, //RLCKXP2C, RFSBVK. - 0x00, 0xFF, SB_VLINK_REG(0xE1), 0x07, 0x00, //RBLKAPIC, RAZC3 - 0x00, 0xFF, SB_VLINK_REG(0x7C), 0x04, 0x02, //RNMIFSB, RFSBVK - 0x00, 0xFF, SB_VLINK_REG(0xE0), 0xF0, 0x90, //RCCA_NEWCLK, RCCA_CLKON. Use New dynamic clock scheme - 0x00, 0xFF, SB_VLINK_REG(0xE7), 0xFF, 0x00, //Let CCA use dynamic clock. + { 0x00, 0xFF, SB_VLINK_REG(0x50), 0x00, 0x08 }, //Config Azalia's upstream cycle high priority and other low priority + { 0x00, 0xFF, SB_VLINK_REG(0x51), 0x40, 0x80 }, //Disable bypass asynchronous circuit + { 0x00, 0xFF, SB_VLINK_REG(0x52), 0x00, 0x11 }, // Set SM Internal Device and HDAC Occupy Timer + { 0x00, 0xFF, SB_VLINK_REG(0x53), 0x00, 0x11 }, // Set SM Internal Device and HDAC Promote Timer + { 0x00, 0xFF, SB_VLINK_REG(0x54), 0xFF, 0x02 }, //Use SB internal devices's original REQ + { 0x00, 0xFF, SB_VLINK_REG(0x73), 0x10, 0x00 }, //RPINOWSC. Enable APIC Cycle Block P2C Write Cycle + { 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x3C }, //RLCKXP2C, RFSBVK. + { 0x00, 0xFF, SB_VLINK_REG(0xE1), 0x07, 0x00 }, //RBLKAPIC, RAZC3 + { 0x00, 0xFF, SB_VLINK_REG(0x7C), 0x04, 0x02 }, //RNMIFSB, RFSBVK + { 0x00, 0xFF, SB_VLINK_REG(0xE0), 0xF0, 0x90 }, //RCCA_NEWCLK, RCCA_CLKON. Use New dynamic clock scheme + { 0x00, 0xFF, SB_VLINK_REG(0xE7), 0xFF, 0x00 }, //Let CCA use dynamic clock. //The CCA is also relate to D17F0 - // 0x00, 0xFF, SB_LPC_REG(0x49), 0x1F, 0x00, //Disable CCA Test Mode - 0x00, 0xFF, SB_LPC_REG(0x74), 0xFF, 0x00, // Let DMA cycles from internal devices directly go to NB // Reserved in 409 by Eric + //{ 0x00, 0xFF, SB_LPC_REG(0x49), 0x1F, 0x00 }, //Disable CCA Test Mode + { 0x00, 0xFF, SB_LPC_REG(0x74), 0xFF, 0x00 }, // Let DMA cycles from internal devices directly go to NB // Reserved in 409 by Eric {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table }; static const struct VIA_PCI_REG_INIT_TABLE IDEC_INIT[] = { - - // 0x00, 0xFF, SB_IDEC_REG(0x09), 0x00, 0x05, //set to native mode - 0x00, 0xFF, SB_IDEC_REG(0x04), 0x00, 0x07, - //0x00, 0xFF, SB_VLINK_REG(0x7C), 0x00, 0x7F, + //{0x00, 0xFF, SB_IDEC_REG(0x09), 0x00, 0x05}, //set to native mode + {0x00, 0xFF, SB_IDEC_REG(0x04), 0x00, 0x07}, + //{0x00, 0xFF, SB_VLINK_REG(0x7C), 0x00, 0x7F}, {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table - }; static const struct VIA_PCI_REG_INIT_TABLE mSbApicInitTable[] = { - 0x00, 0xFF, SB_LPC_REG(0x4D), 0x04, 0x00, - 0x00, 0xFF, SB_LPC_REG(0x5B), 0x0E, 0x00, - 0x00, 0xFF, SB_LPC_REG(0x6C), 0x08, 0x00, - 0x00, 0xFF, SB_LPC_REG(0x58), 0x00, 0x40, - 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x04, - //0x00, 0xFF, SB_VLINK_REG(0x7C), 0x00, 0x7F, - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table - + { 0x00, 0xFF, SB_LPC_REG(0x4D), 0x04, 0x00 }, + { 0x00, 0xFF, SB_LPC_REG(0x5B), 0x0E, 0x00 }, + { 0x00, 0xFF, SB_LPC_REG(0x6C), 0x08, 0x00 }, + { 0x00, 0xFF, SB_LPC_REG(0x58), 0x00, 0x40 }, + { 0x00, 0xFF, SB_VLINK_REG(0x74), 0x00, 0x04 }, + //{ 0x00, 0xFF, SB_VLINK_REG(0x7C), 0x00, 0x7F }, + { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // End of Table }; - - void AcpiInit(void) { device_t_raw rawdevice = 0; @@ -268,10 +261,8 @@ // Close all SMI/Io Traps outb(0x00, VX800_ACPI_IO_BASE + 0x42); - } - void Stage2NbInit(void) { device_t_raw rawdevice = 0; @@ -290,7 +281,6 @@ //vx855 NB no pcie bus //vx855 NB no apic - } void IDECSupportOption(u8 sbchiprev) @@ -313,7 +303,6 @@ IDECSupportOption(sbchiprev); } - void InitUHCI(u8 Number, u8 bEnable) { u8 Mask, Value; @@ -374,25 +363,24 @@ static const struct VIA_PCI_REG_INIT_TABLE mEHCIInitTable[] = { //EHCI - 0x00, 0xFF, SB_EHCI_REG(0x43), 0x00, 0xC0, - 0x00, 0xFF, SB_EHCI_REG(0x50), 0x00, 0x80, - 0x00, 0xFF, SB_EHCI_REG(0x48), 0x20, 0x9E, - 0x00, 0xFF, SB_EHCI_REG(0x49), 0x10, 0x68, - 0x00, 0xFF, SB_EHCI_REG(0x4B), 0x00, 0x69, - 0x00, 0xFF, SB_EHCI_REG(0x4D), 0x00, 0x94, - 0x00, 0xFF, SB_EHCI_REG(0x52), 0x08, 0x00, - 0x00, 0xFF, SB_EHCI_REG(0x5A), 0x00, 0x8A, - 0x00, 0xFF, SB_EHCI_REG(0x5B), 0x00, 0x89, - 0x00, 0xFF, SB_EHCI_REG(0x5C), 0x00, 0x03, - 0x00, 0xFF, SB_EHCI_REG(0x5D), 0x00, 0x9A, - 0x00, 0xFF, SB_EHCI_REG(0x5E), 0x00, 0x00, - 0x00, 0xFF, SB_EHCI_REG(0x6B), 0x00, 0x00, - 0x00, 0xFF, SB_EHCI_REG(0x6D), 0x00, 0x00, - 0x00, 0xFF, SB_EHCI_REG(0x6F), 0xF0, 0x00, - 0x00, 0xFF, SB_EHCI_REG(0x4E), 0x01, 0x01, - 0x00, 0xFF, SB_EHCI_REG(0x4F), 0x00, 0x11, - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table - + { 0x00, 0xFF, SB_EHCI_REG(0x43), 0x00, 0xC0 }, + { 0x00, 0xFF, SB_EHCI_REG(0x50), 0x00, 0x80 }, + { 0x00, 0xFF, SB_EHCI_REG(0x48), 0x20, 0x9E }, + { 0x00, 0xFF, SB_EHCI_REG(0x49), 0x10, 0x68 }, + { 0x00, 0xFF, SB_EHCI_REG(0x4B), 0x00, 0x69 }, + { 0x00, 0xFF, SB_EHCI_REG(0x4D), 0x00, 0x94 }, + { 0x00, 0xFF, SB_EHCI_REG(0x52), 0x08, 0x00 }, + { 0x00, 0xFF, SB_EHCI_REG(0x5A), 0x00, 0x8A }, + { 0x00, 0xFF, SB_EHCI_REG(0x5B), 0x00, 0x89 }, + { 0x00, 0xFF, SB_EHCI_REG(0x5C), 0x00, 0x03 }, + { 0x00, 0xFF, SB_EHCI_REG(0x5D), 0x00, 0x9A }, + { 0x00, 0xFF, SB_EHCI_REG(0x5E), 0x00, 0x00 }, + { 0x00, 0xFF, SB_EHCI_REG(0x6B), 0x00, 0x00 }, + { 0x00, 0xFF, SB_EHCI_REG(0x6D), 0x00, 0x00 }, + { 0x00, 0xFF, SB_EHCI_REG(0x6F), 0xF0, 0x00 }, + { 0x00, 0xFF, SB_EHCI_REG(0x4E), 0x01, 0x01 }, + { 0x00, 0xFF, SB_EHCI_REG(0x4F), 0x00, 0x11 }, + { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // End of Table }; void InitEHCI(u8 Number, u8 bEnable) @@ -483,23 +471,23 @@ static const struct VIA_PCI_REG_INIT_TABLE mPMUInitTable[] = { // Power Management - 0x00, 0xFF, SB_LPC_REG(0x80), 0x00, 0x20, - 0x00, 0xFF, SB_LPC_REG(0x8C), 0x02, 0x00, - 0x00, 0xFF, SB_LPC_REG(0x8D), 0x00, 0x18, + { 0x00, 0xFF, SB_LPC_REG(0x80), 0x00, 0x20 }, + { 0x00, 0xFF, SB_LPC_REG(0x8C), 0x02, 0x00 }, + { 0x00, 0xFF, SB_LPC_REG(0x8D), 0x00, 0x18 }, //Miscellaneous Configuration 1 - 0x00, 0xFF, SB_LPC_REG(0x94), 0xF0, 0x28, - 0x00, 0xFF, SB_LPC_REG(0x95), 0x00, 0xC1, - 0x00, 0xFF, SB_LPC_REG(0x96), 0xFF, 0x10, - 0x00, 0xFF, SB_LPC_REG(0x97), 0x00, 0xB2, + { 0x00, 0xFF, SB_LPC_REG(0x94), 0xF0, 0x28 }, + { 0x00, 0xFF, SB_LPC_REG(0x95), 0x00, 0xC1 }, + { 0x00, 0xFF, SB_LPC_REG(0x96), 0xFF, 0x10 }, + { 0x00, 0xFF, SB_LPC_REG(0x97), 0x00, 0xB2 }, //Voltage Change Function Enable - 0x00, 0xFF, SB_LPC_REG(0x9F), 0x00, 0x21, + { 0x00, 0xFF, SB_LPC_REG(0x9F), 0x00, 0x21 }, //Internal PCIe and NM PLL Control - 0x00, 0xFF, SB_LPC_REG(0xE2), 0x00, 0xEA, + { 0x00, 0xFF, SB_LPC_REG(0xE2), 0x00, 0xEA }, - 0x00, 0xFF, SB_LPC_REG(0xE7), 0x00, 0x80, - {0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // End of Table + { 0x00, 0xFF, SB_LPC_REG(0xE7), 0x00, 0x80 }, + { 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }, // End of Table }; void InitPMU(u8 sbchiprev) @@ -589,7 +577,6 @@ } - void init_VIA_chipset(void) { printk(BIOS_DEBUG, "In: init_VIA_chipset\n"); @@ -633,7 +620,6 @@ printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); #if 0 - pci_rawwrite_config8(PCI_RAWDEV(0, 0, 4), 0xa3, 0x80); pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0x60, 0x20); pci_rawwrite_config8(PCI_RAWDEV(0, 17, 7), 0xE5, @@ -656,7 +642,6 @@ printk(BIOS_INFO, "=================SB 50h=%02x \n", pci_rawread_config8(PCI_RAWDEV(0, 0x11, 0), 0x50)); - /* FIXME: Is there a better way to handle this? */ init_timer(); printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); @@ -690,9 +675,7 @@ y = 0; for (; y < 16; y++) { printk(BIOS_INFO, "%02x ", - pci_rawread_config8(PCI_RAWDEV - (0, 0x10, 4), - x * 16 + y)); + pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y)); } printk(BIOS_INFO, "\n"); } @@ -710,9 +693,7 @@ y = 0; for (; y < 16; y++) { printk(BIOS_INFO, "%02x ", - pci_rawread_config8(PCI_RAWDEV - (0, 0x10, 4), - x * 16 + y)); + pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y)); } printk(BIOS_INFO, "\n"); } @@ -722,7 +703,6 @@ post_code(0x89); printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); - // pci_rawwrite_config16(PCI_RAWDEV(0, 0xf, 0), 0xBA, 0x0571); #if 0 @@ -732,17 +712,13 @@ y = 0; for (; y < 16; y++) { printk(BIOS_INFO, "%02x ", - pci_rawread_config8(PCI_RAWDEV - (0, 0x10, 4), - x * 16 + y)); + pci_rawread_config8(PCI_RAWDEV (0, 0x10, 4), x * 16 + y)); } printk(BIOS_INFO, "\n"); } #endif - #if 0 - y = pci_rawread_config8(PCI_RAWDEV(0, 0xf, 0), 0x0d); y &= 0x0f; y |= 0x40; @@ -750,8 +726,6 @@ #endif #if 0 - - static const d0f0pcitable[5] = { 0xD0, 0, 0, 0, 0xFD }; static const d0f2pcitable[16 * 7 + 1] = { 0x88, 0xF8, 0xEF, 0x44, 0x7C, 0x24, 0x63, 0x01, 0x00, 0x09, @@ -911,7 +885,6 @@ 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, }; - #define OPTION_1 1 #define NOOPTION_1 1 #ifdef OPTION_1 @@ -943,24 +916,19 @@ }; #endif - - u8 i; /* error form ---- but add the chance to resume -for(i=0;i<5;i++){ + for(i=0;i<5;i++) { pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i, d0f0pcitable[i+0xcb]); } - - */ /* RO reg -for(i=0;i<5;i++){ + for(i=0;i<5;i++) { pci_rawwrite_config8(PCI_RAWDEV(0, 0, 0), i+0xcb, d0f0pcitable[i]); } */ - //boot ok, resume still err in linux #if 1 for (i = 0; i < 9; i++) { @@ -1052,11 +1020,7 @@ //d15f0 - - - #if 1 - pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 0), 0x4a, 0xa2); // no affect. pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 1), 0x4a, 0xa2); pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 2), 0x4a, 0xa2); @@ -1077,8 +1041,6 @@ pci_rawwrite_config8(PCI_RAWDEV(0, 0x10, 4), 0x6f, 0x80); #endif - - #if 1 //before (11.0)is add, s3 resume has already always dead in first resume(more frequenly), and sleep ok // for(i=0;i<192;i++){ @@ -1094,7 +1056,6 @@ d11f0pcitable[i]); } - for (i = 18; i < 21; i++) { //sleep ok , sleep err 1, resume pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 0), i + 0x40, d11f0pcitable[i]); @@ -1225,7 +1186,6 @@ pci_rawwrite_config16(PCI_RAWDEV(0, 0x11, 0), 0x72, PCI_DEVICE_ID_VIA_VX855_LPC); - //boot ok, resume still err in linux for (i = 0; i < 192; i++) { pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), i + 0x40, @@ -1240,17 +1200,12 @@ pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0x88, 0x02); pci_rawwrite_config8(PCI_RAWDEV(0, 0x11, 7), 0xe6, 0x3f); #endif - pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x40, 0x20); pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x41, 0x31); - - #ifdef OPTION_1 pci_rawwrite_config8(PCI_RAWDEV(0, 0x14, 0), 0x40, 0x00); #endif - - #endif u8 i911; @@ -1262,10 +1217,9 @@ i911 |= 0x01; pci_rawwrite_config8(PCI_RAWDEV(0, 0x1, 0), 0xb0, i911); - #if 1 struct device *dev; - printk(BIOS_INFO, "=========zjldump all devices...\n"); + printk(BIOS_INFO, "========= dump all devices...\n"); for (dev = all_devices; dev; dev = dev->next) { if (dev->path.type == DEVICE_PATH_PCI) { printk(BIOS_DEBUG, "%s dump\n", dev_path(dev)); @@ -1274,25 +1228,14 @@ y = 0; for (; y < 16; y++) { printk(BIOS_INFO, "%02x ", - pci_read_config8(dev, - x * - 16 + - y)); + pci_read_config8(dev, x * 16 + y)); } printk(BIOS_INFO, "\n"); } - } printk(BIOS_INFO, "\n"); } #endif - - - - //pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x04, 0x17, 0x17);// -// pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x0c, 0x08, 0xff);/// - - - + //pci_rawmodify_config8(PCI_RAWDEV(0, 0x10, 4), 0x0c, 0x08, 0xff);/// } Modified: trunk/src/northbridge/via/vx800/pci_rawops.h ============================================================================== --- trunk/src/northbridge/via/vx800/pci_rawops.h Wed Apr 14 17:45:02 2010 (r5430) +++ trunk/src/northbridge/via/vx800/pci_rawops.h Wed Apr 14 18:39:30 2010 (r5431) @@ -37,13 +37,16 @@ u8 Mask; u8 Value; }; + typedef unsigned device_t_raw; /* pci and pci_mmio need to have different ways to have dev */ +#warning "FIXME: get rid of this extra copy of pci access functions." + /* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G, * We don't need to set %fs, and %gs anymore * Before that We need to use %gs, and leave %fs to other RAM access */ -u8 pci_io_rawread_config8(device_t_raw dev, unsigned where) +static u8 pci_io_rawread_config8(device_t_raw dev, unsigned where) { unsigned addr; #if CONFIG_PCI_IO_CFG_EXT == 0 @@ -56,14 +59,14 @@ } #if CONFIG_MMCONF_SUPPORT -u8 pci_mmio_rawread_config8(device_t_raw dev, unsigned where) +static u8 pci_mmio_rawread_config8(device_t_raw dev, unsigned where) { unsigned addr; addr = dev | where; return read8x(addr); } #endif -u8 pci_rawread_config8(device_t_raw dev, unsigned where) +static u8 pci_rawread_config8(device_t_raw dev, unsigned where) { #if CONFIG_MMCONF_SUPPORT return pci_mmio_rawread_config8(dev, where); @@ -72,7 +75,7 @@ #endif } -u16 pci_io_rawread_config16(device_t_raw dev, unsigned where) +static u16 pci_io_rawread_config16(device_t_raw dev, unsigned where) { unsigned addr; #if CONFIG_PCI_IO_CFG_EXT == 0 @@ -85,7 +88,7 @@ } #if CONFIG_MMCONF_SUPPORT -u16 pci_mmio_rawread_config16(device_t_raw dev, unsigned where) +static u16 pci_mmio_rawread_config16(device_t_raw dev, unsigned where) { unsigned addr; addr = dev | where; @@ -93,7 +96,7 @@ } #endif -u16 pci_rawread_config16(device_t_raw dev, unsigned where) +static u16 pci_rawread_config16(device_t_raw dev, unsigned where) { #if CONFIG_MMCONF_SUPPORT return pci_mmio_rawread_config16(dev, where); @@ -102,7 +105,7 @@ #endif } -u32 pci_io_rawread_config32(device_t_raw dev, unsigned where) +static u32 pci_io_rawread_config32(device_t_raw dev, unsigned where) { unsigned addr; #if CONFIG_PCI_IO_CFG_EXT == 0 @@ -115,7 +118,7 @@ } #if CONFIG_MMCONF_SUPPORT -u32 pci_mmio_rawread_config32(device_t_raw dev, unsigned where) +static u32 pci_mmio_rawread_config32(device_t_raw dev, unsigned where) { unsigned addr; addr = dev | where; @@ -123,7 +126,7 @@ } #endif -u32 pci_rawread_config32(device_t_raw dev, unsigned where) +static u32 pci_rawread_config32(device_t_raw dev, unsigned where) { #if CONFIG_MMCONF_SUPPORT return pci_mmio_rawread_config32(dev, where); @@ -132,7 +135,7 @@ #endif } -void pci_io_rawwrite_config8(device_t_raw dev, unsigned where, u8 value) +static void pci_io_rawwrite_config8(device_t_raw dev, unsigned where, u8 value) { unsigned addr; #if CONFIG_PCI_IO_CFG_EXT == 0 @@ -145,7 +148,7 @@ } #if CONFIG_MMCONF_SUPPORT -void pci_mmio_rawwrite_config8(device_t_raw dev, unsigned where, u8 value) +static void pci_mmio_rawwrite_config8(device_t_raw dev, unsigned where, u8 value) { unsigned addr; addr = dev | where; @@ -153,7 +156,7 @@ } #endif -void pci_rawwrite_config8(device_t_raw dev, unsigned where, u8 value) +static void pci_rawwrite_config8(device_t_raw dev, unsigned where, u8 value) { #if CONFIG_MMCONF_SUPPORT pci_mmio_rawwrite_config8(dev, where, value); @@ -162,7 +165,7 @@ #endif } -void pci_io_rawwrite_config16(device_t_raw dev, unsigned where, u16 value) +static void pci_io_rawwrite_config16(device_t_raw dev, unsigned where, u16 value) { unsigned addr; #if CONFIG_PCI_IO_CFG_EXT == 0 @@ -175,7 +178,7 @@ } #if CONFIG_MMCONF_SUPPORT -void pci_mmio_rawwrite_config16(device_t_raw dev, unsigned where, +static void pci_mmio_rawwrite_config16(device_t_raw dev, unsigned where, u16 value) { unsigned addr; @@ -184,7 +187,7 @@ } #endif -void pci_rawwrite_config16(device_t_raw dev, unsigned where, u16 value) +static void pci_rawwrite_config16(device_t_raw dev, unsigned where, u16 value) { #if CONFIG_MMCONF_SUPPORT pci_mmio_rawwrite_config16(dev, where, value); @@ -193,7 +196,7 @@ #endif } -void pci_io_rawwrite_config32(device_t_raw dev, unsigned where, u32 value) +static void pci_io_rawwrite_config32(device_t_raw dev, unsigned where, u32 value) { unsigned addr; #if CONFIG_PCI_IO_CFG_EXT == 0 @@ -206,8 +209,7 @@ } #if CONFIG_MMCONF_SUPPORT -void pci_mmio_rawwrite_config32(device_t_raw dev, unsigned where, - u32 value) +static void pci_mmio_rawwrite_config32(device_t_raw dev, unsigned where, u32 value) { unsigned addr; addr = dev | where; @@ -215,7 +217,7 @@ } #endif -void pci_rawwrite_config32(device_t_raw dev, unsigned where, u32 value) +static void pci_rawwrite_config32(device_t_raw dev, unsigned where, u32 value) { #if CONFIG_MMCONF_SUPPORT pci_mmio_rawwrite_config32(dev, where, value); @@ -224,7 +226,7 @@ #endif } -void pci_rawmodify_config8(device_t_raw dev, unsigned where, u8 orval, u8 mask) +static void pci_rawmodify_config8(device_t_raw dev, unsigned where, u8 orval, u8 mask) { u8 data = pci_rawread_config8(dev, where); data &= (~mask); @@ -232,7 +234,7 @@ pci_rawwrite_config8(dev, where, data); } -void pci_rawmodify_config16(device_t_raw dev, unsigned where, u16 orval, u16 mask) +static void pci_rawmodify_config16(device_t_raw dev, unsigned where, u16 orval, u16 mask) { u16 data = pci_rawread_config16(dev, where); data &= (~mask); @@ -240,7 +242,7 @@ pci_rawwrite_config16(dev, where, data); } -void pci_rawmodify_config32(device_t_raw dev, unsigned where, u32 orval, u32 mask) +static void pci_rawmodify_config32(device_t_raw dev, unsigned where, u32 orval, u32 mask) { u32 data = pci_rawread_config32(dev, where); data &= (~mask); @@ -248,7 +250,7 @@ pci_rawwrite_config32(dev, where, data); } -void io_rawmodify_config8(u16 where, u8 orval, u8 mask) +static void io_rawmodify_config8(u16 where, u8 orval, u8 mask) { u8 data = inb(where); data &= (~mask); @@ -256,8 +258,8 @@ outb(data, where); } -void via_pci_inittable(u8 chipversion, - struct VIA_PCI_REG_INIT_TABLE *initdata) +static void via_pci_inittable(u8 chipversion, + const struct VIA_PCI_REG_INIT_TABLE *initdata) { u8 i = 0; device_t_raw devbxdxfx; Modified: trunk/src/northbridge/via/vx800/uma_ram_setting.c ============================================================================== --- trunk/src/northbridge/via/vx800/uma_ram_setting.c Wed Apr 14 17:45:02 2010 (r5430) +++ trunk/src/northbridge/via/vx800/uma_ram_setting.c Wed Apr 14 18:39:30 2010 (r5431) @@ -71,7 +71,7 @@ u8 ramregs[] = { 0x43, 0x42, 0x41, 0x40 }; device_t vga_dev = PCI_DEV(0, 1, 0), d0f0_dev = PCI_DEV(0, 0, 0); u8 ByteVal, temp; - UMARAM *pUMARamTable; + const UMARAM *pUMARamTable; u16 UmaSize; u8 SLD0F3Val, SLD1F0Val, VgaPortVal; u32 RamSize, SLBase, Tmp; Modified: trunk/src/northbridge/via/vx800/vx800_early_smbus.c ============================================================================== --- trunk/src/northbridge/via/vx800/vx800_early_smbus.c Wed Apr 14 17:45:02 2010 (r5430) +++ trunk/src/northbridge/via/vx800/vx800_early_smbus.c Wed Apr 14 18:39:30 2010 (r5431) @@ -244,14 +244,14 @@ * be created just for it. If some other chip needs/wants it, we can * worry about it then. * - * @param ctrl The memory controller and SMBus addresses. + * @param mem_ctrl The memory controller and SMBus addresses. */ -void smbus_fixup(const struct mem_controller *ctrl) +static void smbus_fixup(const struct mem_controller *mem_ctrl) { int i, ram_slots, current_slot = 0; u8 result = 0; - ram_slots = ARRAY_SIZE(ctrl->channel0); + ram_slots = ARRAY_SIZE(mem_ctrl->channel0); if (!ram_slots) { print_err("smbus_fixup() thinks there are no RAM slots!\n"); return; @@ -272,7 +272,7 @@ if (current_slot > ram_slots) current_slot = 0; - result = get_spd_data(ctrl->channel0[current_slot], + result = get_spd_data(mem_ctrl->channel0[current_slot], SPD_MEMORY_TYPE); current_slot++; PRINT_DEBUG("."); Modified: trunk/src/southbridge/via/k8t890/k8t890_early_car.c ============================================================================== --- trunk/src/southbridge/via/k8t890/k8t890_early_car.c Wed Apr 14 17:45:02 2010 (r5430) +++ trunk/src/southbridge/via/k8t890/k8t890_early_car.c Wed Apr 14 18:39:30 2010 (r5431) @@ -34,7 +34,7 @@ /* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */ -static ldtreg[3] = {0x86, 0xa6, 0xc6}; +static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; /* This functions sets KT890 link frequency and width to same values as * it has been setup on K8 side, by AMD NB init.

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[commit] r5430 - trunk/src/northbridge/amd/amdmct/mct
by repository service 14 Apr '10

14 Apr '10

Author: stepan Date: Wed Apr 14 17:45:02 2010 New Revision: 5430 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5430 Log: HWHoleSz must be u32... Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/amd/amdmct/mct/mctndi_d.c Modified: trunk/src/northbridge/amd/amdmct/mct/mctndi_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mctndi_d.c Wed Apr 14 17:44:21 2010 (r5429) +++ trunk/src/northbridge/amd/amdmct/mct/mctndi_d.c Wed Apr 14 17:45:02 2010 (r5430) @@ -33,7 +33,7 @@ u8 DoIntlv; u8 _NdIntCap; u8 _SWHole; - u8 HWHoleSz; + u32 HWHoleSz; u32 DramHoleAddrReg; u32 HoleBase; u32 dev0;

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[commit] r5429 - in trunk/src: mainboard/supermicro/h8qme_fam10 northbridge/amd/amdfam10
by repository service 14 Apr '10

14 Apr '10

Author: stepan Date: Wed Apr 14 17:44:21 2010 New Revision: 5429 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5429 Log: udelay_tsc does not exist in the whole tree. Neither does quadcore.h (anymore) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c trunk/src/northbridge/amd/amdfam10/debug.c trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c Modified: trunk/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c Wed Apr 14 16:41:30 2010 (r5428) +++ trunk/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c Wed Apr 14 17:44:21 2010 (r5429) @@ -25,7 +25,7 @@ #include <string.h> #include <stdint.h> #if CONFIG_LOGICAL_CPUS==1 -#include <cpu/amd/quadcore.h> +#include <cpu/amd/multicore.h> #endif #include <cpu/amd/amdfam10_sysconf.h> Modified: trunk/src/northbridge/amd/amdfam10/debug.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/debug.c Wed Apr 14 16:41:30 2010 (r5428) +++ trunk/src/northbridge/amd/amdfam10/debug.c Wed Apr 14 17:44:21 2010 (r5429) @@ -23,8 +23,6 @@ #include "amdfam10_pci.c" -static void udelay_tsc(u32 us); - static inline void print_debug_addr(const char *str, void *val) { #if CACHE_AS_RAM_ADDRESS_DEBUG == 1 @@ -296,7 +294,7 @@ { int i; - udelay_tsc(2000); + udelay(2000); printk(BIOS_DEBUG, "%04x:\n", port); for(i=0;i<256;i++) { u8 val; Modified: trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c Wed Apr 14 16:41:30 2010 (r5428) +++ trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c Wed Apr 14 17:44:21 2010 (r5429) @@ -42,7 +42,7 @@ /* give the NB a break, many CPUs spinning on one bit makes a * lot of traffic and time is not too important to APs. */ - udelay_tsc(1000); + udelay(1000); if(get_htic_bit(0, 9)) return; } }

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coreboot April 2010