coreboot April 2010

coreboot@coreboot.org

64 participants
402 discussions

Hello,,,I've been trying to bring coreboot up on an EP80579 reference platform (not Truxton) and I have thus far been thwarted.,,I'm using svn revision 5442 and the boot hangs with just the welcome to coreboot line:,,coreboot-4.0-r5422M Tue Apr 13 18:13:08 PDT 2010 starting...,,I've put several print_info statements in romstage.c and narrowed it down to the following line in i3100_early_lpc.c:,,pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 << 7)); ,,Further debug shows that in g
by Dustin Harrison 15 Apr '10

15 Apr '10

Hello, I've been trying to bring coreboot up on an EP80579 reference platform (not Truxton) and I have thus far been thwarted. I'm using svn revision 5442 and the boot hangs with just the welcome to coreboot line: coreboot-4.0-r5422M Tue Apr 13 18:13:08 PDT 2010 starting... I've put several print_info statements in romstage.c and narrowed it down to the following line in i3100_early_lpc.c: pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 << 7)); Further debug shows that in general I can not read a value and then use the value. If I just perfrom a read operation it executes the instruction and contiues. But if I do a read and try to use a print_info_hexXX function it just hangs. I'm really at a loss where to go from here for debugging. I don't have a JTAG TAP that I can step through code to identify the assembly code I'm getting stuck on. I've tried the Truxton BIOS in my reference board and this works fine. I can also get the boot farther along if I remove the pci_read_config32 commands (for example in the above line I just use the default value for register 0x44 instead of reading it in). I'm using gcc version 4.3.2 (Gentoo 4.3.2-r3 p1.6, pie-10.1.5) Any ideas on what to try next? Is there a recommended toolchain? Thanks in advance for any help!

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Re: [coreboot] #28: Finish Intel 440BX port
by coreboot 15 Apr '10

15 Apr '10

#28: Finish Intel 440BX port ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: task | Status: closed Priority: critical | Milestone: Going mainstream Component: coreboot | Resolution: fixed Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Changes (by stepan): * status: new => closed * resolution: => fixed Comment: No software is ever "finished" as long as it is not obsolete. Closing this down since 440BX underwent considerable improvements including making the code more generic, and even ACPI is being developed for it at the moment. -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/28#comment:3> coreboot <http://www.coreboot.org/>

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Re: [coreboot] #82: Fix the memory map in coreboot v3
by coreboot 15 Apr '10

15 Apr '10

#82: Fix the memory map in coreboot v3 -------------------------+-------------------------------------------------- Reporter: oxygene | Owner: hailfinger Type: defect | Status: new Priority: major | Milestone: Setting up coreboot v3 Component: coreboot | Keywords: Dependencies: | Patchstatus: there is no patch -------------------------+-------------------------------------------------- Changes (by stepan): * owner: oxygene => hailfinger -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/82#comment:2> coreboot <http://www.coreboot.org/>

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#108: Add int 10 VESA video driver to libpayload
by coreboot 15 Apr '10

15 Apr '10

#108: Add int 10 VESA video driver to libpayload ---------------------------------+------------------------------------------ Reporter: stuge | Owner: somebody Type: enhancement | Status: new Priority: major | Milestone: Component: libpayload | Version: Keywords: video | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/108> coreboot <http://www.coreboot.org/>

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#129: Add support for high_tables_base for all chipsets that don't support it yet.
by coreboot 15 Apr '10

15 Apr '10

#129: Add support for high_tables_base for all chipsets that don't support it yet. ---------------------------------+------------------------------------------ Reporter: oxygene | Owner: somebody Type: defect | Status: new Priority: critical | Milestone: Component: coreboot | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Without tables in high memory, seabios won't run on your chipset properly. it overwrites your tables in the F segment, as seabios itself lives there. Also, once there is support for high_tables_base everywhere, the code in src/arch/i386/boot/tables.c can be cleaned up and simplified considerably. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/129> coreboot <http://www.coreboot.org/>

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#139: flashrom: -c option should be case insensitive
by coreboot 15 Apr '10

15 Apr '10

#139: flashrom: -c option should be case insensitive ---------------------------------+------------------------------------------ Reporter: uwe | Owner: somebody Type: enhancement | Status: new Priority: minor | Milestone: Component: flashrom | Version: Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ flashrom's -c option requires you to enter extact chip names. It should probably be case insensitive for easier usage. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/139> coreboot <http://www.coreboot.org/>

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#148: Component defaults to adlo for new tickets in the tracker
by coreboot 15 Apr '10

15 Apr '10

#148: Component defaults to adlo for new tickets in the tracker ------------------------------------+--------------------------------------- Reporter: stuge | Owner: somebody Type: defect | Status: new Priority: minor | Milestone: Component: wiki/website/tracker | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ------------------------------------+--------------------------------------- Maybe coreboot would be better -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/148> coreboot <http://www.coreboot.org/>

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#150: AMD DB800 dev board PLL strapping leaves CPU and GLIU in non-optimal clock
by coreboot 15 Apr '10

15 Apr '10

#150: AMD DB800 dev board PLL strapping leaves CPU and GLIU in non-optimal clock -------------------------------------------+-------------------------------- Reporter: edwin_beasant@… | Owner: somebody Type: enhancement | Status: new Priority: minor | Milestone: Component: coreboot | Version: v2 Keywords: | Dependencies: Patchstatus: patch needs review | -------------------------------------------+-------------------------------- The AMD DB800 board PLL strappings are left open as supplied, and leave the CPU/Memory in the sub-optimal 400MHz CPU,266MHz GLIU configuration. This requires a manual PLL strapping to achieve 500Mhz CPU and 400MHz GLIU as is normally used in the dev-kits (and the commercial GeodeRom). These are the correct (manual) strappings for a DB800: #define PLLMSRhi 0x000005DD #define PLLMSRlo 0x00DE60EE Patch attached. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/150> coreboot <http://www.coreboot.org/>

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#156: Add Layout File capability to v3 and LAR tool
by coreboot 15 Apr '10

15 Apr '10

#156: Add Layout File capability to v3 and LAR tool --------------------------------------------+------------------------------- Reporter: edwin_beasant@… | Owner: stepan@… Type: enhancement | Status: new Priority: major | Milestone: Component: coreboot | Keywords: flashrom lar layout image v3 Dependencies: | Patchstatus: patch needs review --------------------------------------------+------------------------------- This patch adds the ability to specify a layout file within the v3 Kconfig menu system, and then to enable LAR to read and setup a flash image with respect to this layout file. This operates by padding the blank space with '(padding)' images, using a similar method to the zero padding that LAR uses to finalise an image. I have also included the patch to optionally disable fallback booting: this speeds things up a bit on the DB800 board which seems to have RTC byte read/write issues somewhere... The layout file format is the same as current flashrom. It also allows addition/specification of the VSA within the Kconfig setup for Geode targets, which will then be added to the LAR in a sensible place. Example tested layout for 49LF008A device: 00000000:0003ffff fallback 00040000:0004ffff vsa 00050000:0008ffff normal 000f0000:000f0000 bootblock Note that the fallback image is 'below' the normal image: This allows for the fallback image to be 'golden': if you repeatedly flash the only the 'normal' area, you will always have a working accessible VSA and fallback image if the normal flash fails. This does not prevent you from flashing the fallback image (just ba cautious)... This has been tested as working on the Zoom DB800 development platform. Comments and review please! -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/156> coreboot <http://www.coreboot.org/>

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#157: utils/inteltool has outdated pciutils check in Makefile
by coreboot 15 Apr '10

15 Apr '10

#157: utils/inteltool has outdated pciutils check in Makefile --------------------------+------------------------------------------------- Reporter: anonymous | Owner: stepan@… Type: defect | Status: new Priority: minor | Milestone: Component: misc | Keywords: Dependencies: | Patchstatus: there is no patch --------------------------+------------------------------------------------- The current test compile bails out with: undefined reference to `pci_alloc' If i simply remove the test inteltool compiles and runs as expected. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/157> coreboot <http://www.coreboot.org/>

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coreboot April 2010