#150: AMD DB800 dev board PLL strapping leaves CPU and GLIU in non-optimal clock - coreboot

1 Dec 2009


      #150: AMD DB800 dev board PLL strapping leaves CPU and GLIU in non-optimal clock
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   Reporter:  edwin_beasant@…              |          Owner:  somebody
       Type:  enhancement                  |         Status:  new     
   Priority:  minor                        |      Milestone:          
  Component:  coreboot                     |        Version:  v2      
   Keywords:                               |   Dependencies:          
Patchstatus:  patch needs review           |  
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 The AMD DB800 board PLL strappings are left open as supplied, and leave
 the CPU/Memory in the sub-optimal 400MHz CPU,266MHz GLIU configuration.
 This requires a manual PLL strapping to achieve 500Mhz CPU and 400MHz GLIU
 as is normally used in the dev-kits (and the commercial GeodeRom).
 These are the correct (manual) strappings for a DB800:
 #define PLLMSRhi 0x000005DD
 #define PLLMSRlo 0x00DE60EE
 Patch attached.
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Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/150
coreboot http://www.coreboot.org/