coreboot April 2010

coreboot@coreboot.org

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[commit] r5460 - in trunk/src/arch/i386: boot init lib smp
by repository service 20 Apr '10

20 Apr '10

Author: stepan Date: Tue Apr 20 15:22:02 2010 New Revision: 5460 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5460 Log: - move src/arch/i386/smp/ioapic.c to src/arch/i386/lib/ioapic.c (has nothing to do with SMP) - move src/arch/i386/smp/mpspec.c to src/arch/i386/boot/mpspec.c (where acpi, pirq and coreboot table generation lives) - modify src/arch/i386/boot/Makefile.inc, src/arch/i386/lib/Makefile.inc and src/arch/i386/smp/Makefile.inc accordingly - src/arch/i386/smp is now empty. drop it. - drop src/arch/i386/init/car.S (unused) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Added: trunk/src/arch/i386/boot/mpspec.c - copied unchanged from r5458, trunk/src/arch/i386/smp/mpspec.c trunk/src/arch/i386/lib/ioapic.c - copied unchanged from r5458, trunk/src/arch/i386/smp/ioapic.c Deleted: trunk/src/arch/i386/init/car.S trunk/src/arch/i386/smp/ Modified: trunk/src/arch/i386/boot/Makefile.inc trunk/src/arch/i386/lib/Makefile.inc Modified: trunk/src/arch/i386/boot/Makefile.inc ============================================================================== --- trunk/src/arch/i386/boot/Makefile.inc Tue Apr 20 13:03:41 2010 (r5459) +++ trunk/src/arch/i386/boot/Makefile.inc Tue Apr 20 15:22:02 2010 (r5460) @@ -3,6 +3,7 @@ obj-$(CONFIG_MULTIBOOT) += multiboot.o obj-y += gdt.o obj-y += tables.o +obj-$(CONFIG_GENERATE_MP_TABLE) += mpspec.o obj-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.o obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpi.o obj-$(CONFIG_GENERATE_ACPI_TABLES) += acpigen.o Copied: trunk/src/arch/i386/boot/mpspec.c (from r5458, trunk/src/arch/i386/smp/mpspec.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/arch/i386/boot/mpspec.c Tue Apr 20 15:22:02 2010 (r5460, copy of r5458, trunk/src/arch/i386/smp/mpspec.c) @@ -0,0 +1,306 @@ +#include <console/console.h> +#include <device/path.h> +#include <device/pci_ids.h> +#include <cpu/cpu.h> +#include <arch/smp/mpspec.h> +#include <string.h> +#include <arch/cpu.h> +#include <cpu/x86/lapic.h> + +unsigned char smp_compute_checksum(void *v, int len) +{ + unsigned char *bytes; + unsigned char checksum; + int i; + bytes = v; + checksum = 0; + for(i = 0; i < len; i++) { + checksum -= bytes[i]; + } + return checksum; +} + +void *smp_write_floating_table(unsigned long addr) +{ + /* 16 byte align the table address */ + addr = (addr + 0xf) & (~0xf); + return smp_write_floating_table_physaddr(addr, addr + SMP_FLOATING_TABLE_LEN); +} + +void *smp_write_floating_table_physaddr(unsigned long addr, unsigned long mpf_physptr) +{ + struct intel_mp_floating *mf; + void *v; + + v = (void *)addr; + mf = v; + mf->mpf_signature[0] = '_'; + mf->mpf_signature[1] = 'M'; + mf->mpf_signature[2] = 'P'; + mf->mpf_signature[3] = '_'; + mf->mpf_physptr = mpf_physptr; + mf->mpf_length = 1; + mf->mpf_specification = 4; + mf->mpf_checksum = 0; + mf->mpf_feature1 = 0; + mf->mpf_feature2 = 0; + mf->mpf_feature3 = 0; + mf->mpf_feature4 = 0; + mf->mpf_feature5 = 0; + mf->mpf_checksum = smp_compute_checksum(mf, mf->mpf_length*16); + return v; +} + +void *smp_next_mpc_entry(struct mp_config_table *mc) +{ + void *v; + v = (void *)(((char *)mc) + mc->mpc_length); + return v; +} +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +void *smp_next_mpe_entry(struct mp_config_table *mc) +{ + void *v; + v = (void *)(((char *)mc) + mc->mpc_length + mc->mpe_length); + return v; +} +static void smp_add_mpe_entry(struct mp_config_table *mc, mpe_t mpe) +{ + mc->mpe_length += mpe->mpe_length; +} + +void smp_write_processor(struct mp_config_table *mc, + unsigned char apicid, unsigned char apicver, + unsigned char cpuflag, unsigned int cpufeature, + unsigned int featureflag) +{ + struct mpc_config_processor *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_PROCESSOR; + mpc->mpc_apicid = apicid; + mpc->mpc_apicver = apicver; + mpc->mpc_cpuflag = cpuflag; + mpc->mpc_cpufeature = cpufeature; + mpc->mpc_featureflag = featureflag; + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +/* If we assume a symmetric processor configuration we can + * get all of the information we need to write the processor + * entry from the bootstrap processor. + * Plus I don't think linux really even cares. + * Having the proper apicid's in the table so the non-bootstrap + * processors can be woken up should be enough. + */ +void smp_write_processors(struct mp_config_table *mc) +{ + int boot_apic_id; + unsigned apic_version; + unsigned cpu_features; + unsigned cpu_feature_flags; + struct cpuid_result result; + device_t cpu; + + boot_apic_id = lapicid(); + apic_version = lapic_read(LAPIC_LVR) & 0xff; + result = cpuid(1); + cpu_features = result.eax; + cpu_feature_flags = result.edx; + for(cpu = all_devices; cpu; cpu = cpu->next) { + unsigned long cpu_flag; + if ((cpu->path.type != DEVICE_PATH_APIC) || + (cpu->bus->dev->path.type != DEVICE_PATH_APIC_CLUSTER)) + { + continue; + } + if (!cpu->enabled) { + continue; + } + cpu_flag = MPC_CPU_ENABLED; + if (boot_apic_id == cpu->path.apic.apic_id) { + cpu_flag = MPC_CPU_ENABLED | MPC_CPU_BOOTPROCESSOR; + } + smp_write_processor(mc, + cpu->path.apic.apic_id, apic_version, + cpu_flag, cpu_features, cpu_feature_flags + ); + } +} + +void smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +void smp_write_ioapic(struct mp_config_table *mc, + unsigned char id, unsigned char ver, + unsigned long apicaddr) +{ + struct mpc_config_ioapic *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_IOAPIC; + mpc->mpc_apicid = id; + mpc->mpc_apicver = ver; + mpc->mpc_flags = MPC_APIC_USABLE; + mpc->mpc_apicaddr = apicaddr; + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +void smp_write_intsrc(struct mp_config_table *mc, + unsigned char irqtype, unsigned short irqflag, + unsigned char srcbus, unsigned char srcbusirq, + unsigned char dstapic, unsigned char dstirq) +{ + struct mpc_config_intsrc *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_INTSRC; + mpc->mpc_irqtype = irqtype; + mpc->mpc_irqflag = irqflag; + mpc->mpc_srcbus = srcbus; + mpc->mpc_srcbusirq = srcbusirq; + mpc->mpc_dstapic = dstapic; + mpc->mpc_dstirq = dstirq; + smp_add_mpc_entry(mc, sizeof(*mpc)); +#ifdef DEBUG_MPTABLE + printk(BIOS_DEBUG, "add intsrc srcbus 0x%x srcbusirq 0x%x, dstapic 0x%x, dstirq 0x%x\n", + srcbus, srcbusirq, dstapic, dstirq); + hexdump(__func__, mpc, sizeof(*mpc)); +#endif +} + +void smp_write_intsrc_pci_bridge(struct mp_config_table *mc, + unsigned char irqtype, unsigned short irqflag, + struct device *dev, + unsigned char dstapic, unsigned char *dstirq) +{ + struct device *child; + + int linkn; + int i; + int srcbus; + int slot; + + struct bus *link; + unsigned char dstirq_x[4]; + + for (linkn = 0; linkn < dev->links; linkn++) { + + link = &dev->link[linkn]; + child = link->children; + srcbus = link->secondary; + + while (child) { + if (child->path.type != DEVICE_PATH_PCI) + goto next; + + slot = (child->path.pci.devfn >> 3); + /* round pins */ + for (i = 0; i < 4; i++) + dstirq_x[i] = dstirq[(i + slot) % 4]; + + if ((child->class >> 16) != PCI_BASE_CLASS_BRIDGE) { + /* pci device */ + printk(BIOS_DEBUG, "route irq: %s\n", dev_path(child)); + for (i = 0; i < 4; i++) + smp_write_intsrc(mc, irqtype, irqflag, srcbus, (slot<<2)|i, dstapic, dstirq_x[i]); + goto next; + } + + switch (child->class>>8) { + case PCI_CLASS_BRIDGE_PCI: + case PCI_CLASS_BRIDGE_PCMCIA: + case PCI_CLASS_BRIDGE_CARDBUS: + printk(BIOS_DEBUG, "route irq bridge: %s\n", dev_path(child)); + smp_write_intsrc_pci_bridge(mc, irqtype, irqflag, child, dstapic, dstirq_x); + } + + next: + child = child->sibling; + } + + } +} + +void smp_write_lintsrc(struct mp_config_table *mc, + unsigned char irqtype, unsigned short irqflag, + unsigned char srcbusid, unsigned char srcbusirq, + unsigned char destapic, unsigned char destapiclint) +{ + struct mpc_config_lintsrc *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_LINTSRC; + mpc->mpc_irqtype = irqtype; + mpc->mpc_irqflag = irqflag; + mpc->mpc_srcbusid = srcbusid; + mpc->mpc_srcbusirq = srcbusirq; + mpc->mpc_destapic = destapic; + mpc->mpc_destapiclint = destapiclint; + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +void smp_write_address_space(struct mp_config_table *mc, + unsigned char busid, unsigned char address_type, + unsigned int address_base_low, unsigned int address_base_high, + unsigned int address_length_low, unsigned int address_length_high) +{ + struct mp_exten_system_address_space *mpe; + mpe = smp_next_mpe_entry(mc); + memset(mpe, '\0', sizeof(*mpe)); + mpe->mpe_type = MPE_SYSTEM_ADDRESS_SPACE; + mpe->mpe_length = sizeof(*mpe); + mpe->mpe_busid = busid; + mpe->mpe_address_type = address_type; + mpe->mpe_address_base_low = address_base_low; + mpe->mpe_address_base_high = address_base_high; + mpe->mpe_address_length_low = address_length_low; + mpe->mpe_address_length_high = address_length_high; + smp_add_mpe_entry(mc, (mpe_t)mpe); +} + + +void smp_write_bus_hierarchy(struct mp_config_table *mc, + unsigned char busid, unsigned char bus_info, + unsigned char parent_busid) +{ + struct mp_exten_bus_hierarchy *mpe; + mpe = smp_next_mpe_entry(mc); + memset(mpe, '\0', sizeof(*mpe)); + mpe->mpe_type = MPE_BUS_HIERARCHY; + mpe->mpe_length = sizeof(*mpe); + mpe->mpe_busid = busid; + mpe->mpe_bus_info = bus_info; + mpe->mpe_parent_busid = parent_busid; + smp_add_mpe_entry(mc, (mpe_t)mpe); +} + +void smp_write_compatibility_address_space(struct mp_config_table *mc, + unsigned char busid, unsigned char address_modifier, + unsigned int range_list) +{ + struct mp_exten_compatibility_address_space *mpe; + mpe = smp_next_mpe_entry(mc); + memset(mpe, '\0', sizeof(*mpe)); + mpe->mpe_type = MPE_COMPATIBILITY_ADDRESS_SPACE; + mpe->mpe_length = sizeof(*mpe); + mpe->mpe_busid = busid; + mpe->mpe_address_modifier = address_modifier; + mpe->mpe_range_list = range_list; + smp_add_mpe_entry(mc, (mpe_t)mpe); +} + Modified: trunk/src/arch/i386/lib/Makefile.inc ============================================================================== --- trunk/src/arch/i386/lib/Makefile.inc Tue Apr 20 13:03:41 2010 (r5459) +++ trunk/src/arch/i386/lib/Makefile.inc Tue Apr 20 15:22:02 2010 (r5460) @@ -5,6 +5,7 @@ obj-y += pci_ops_mmconf.o obj-y += pci_ops_auto.o obj-y += exception.o +obj-$(CONFIG_IOAPIC) += ioapic.o initobj-y += printk_init.o initobj-y += cbfs_and_run.o Copied: trunk/src/arch/i386/lib/ioapic.c (from r5458, trunk/src/arch/i386/smp/ioapic.c) ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/arch/i386/lib/ioapic.c Tue Apr 20 15:22:02 2010 (r5460, copy of r5458, trunk/src/arch/i386/smp/ioapic.c) @@ -0,0 +1,135 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/ioapic.h> +#include <console/console.h> +#include <cpu/x86/lapic.h> + +static u32 io_apic_read(u32 ioapic_base, u32 reg) +{ + write32(ioapic_base, reg); + return read32(ioapic_base + 0x10); +} + +static void io_apic_write(u32 ioapic_base, u32 reg, u32 value) +{ + write32(ioapic_base, reg); + write32(ioapic_base + 0x10, value); +} + + +void clear_ioapic(u32 ioapic_base) +{ + u32 low, high; + u32 i, ioapic_interrupts; + + printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base); + + /* Read the available number of interrupts */ + ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff; + if (!ioapic_interrupts || ioapic_interrupts == 0xff) + ioapic_interrupts = 24; + printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); + + low = DISABLED; + high = NONE; + + for (i = 0; i < ioapic_interrupts; i++) { + io_apic_write(ioapic_base, i * 2 + 0x10, low); + io_apic_write(ioapic_base, i * 2 + 0x11, high); + + printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low); + } + + if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) { + printk(BIOS_WARNING, "IO APIC not responding.\n"); + return; + } +} + +void setup_ioapic(u32 ioapic_base, u8 ioapic_id) +{ + u32 bsp_lapicid = lapicid(); + u32 low, high; + u32 i, ioapic_interrupts; + + printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n", ioapic_base); + printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = %02x\n", + bsp_lapicid); + + if (ioapic_id) { + printk(BIOS_DEBUG, "IOAPIC: ID = 0x%02x\n", ioapic_id); + /* Set IOAPIC ID if it has been specified */ + io_apic_write(ioapic_base, 0x00, + (io_apic_read(ioapic_base, 0x00) & 0xfff0ffff) | + (ioapic_id << 24)); + } + + /* Read the available number of interrupts */ + ioapic_interrupts = (io_apic_read(ioapic_base, 1) >> 16) & 0xff; + if (!ioapic_interrupts || ioapic_interrupts == 0xff) + ioapic_interrupts = 24; + printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts); + + +// XXX this decision should probably be made elsewhere, and +// it's the C3, not the EPIA this depends on. +#if defined(CONFIG_EPIA_VT8237R_INIT) && CONFIG_EPIA_VT8237R_INIT +#define IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS +#else +#define IOAPIC_INTERRUPTS_ON_FSB +#endif + +#ifdef IOAPIC_INTERRUPTS_ON_FSB + /* For the Pentium 4 and above APICs deliver their interrupts + * on the front side bus, enable that. + */ + printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on FSB\n"); + io_apic_write(ioapic_base, 0x03, io_apic_read(ioapic_base, 0x03) | (1 << 0)); +#endif +#ifdef IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS + printk(BIOS_DEBUG, "IOAPIC: Enabling interrupts on APIC serial bus\n"); + io_apic_write(ioapic_base, 0x03, 0); +#endif + + /* Enable Virtual Wire Mode */ + low = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT; + high = bsp_lapicid << (56 - 32); + + io_apic_write(ioapic_base, 0x10, low); + io_apic_write(ioapic_base, 0x11, high); + + if (io_apic_read(ioapic_base, 0x10) == 0xffffffff) { + printk(BIOS_WARNING, "IO APIC not responding.\n"); + return; + } + + printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", 0, high, low); + + low = DISABLED; + high = NONE; + + for (i = 1; i < ioapic_interrupts; i++) { + io_apic_write(ioapic_base, i * 2 + 0x10, low); + io_apic_write(ioapic_base, i * 2 + 0x11, high); + + printk(BIOS_SPEW, "IOAPIC: reg 0x%08x value 0x%08x 0x%08x\n", i, high, low); + } +}

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Re: [coreboot] #43: Add graphics memory hole to e820 map
by coreboot 20 Apr '10

20 Apr '10

#43: Add graphics memory hole to e820 map ---------------------------------+------------------------------------------ Reporter: stepan | Owner: stepan Type: defect | Status: closed Priority: major | Milestone: Component: coreboot | Resolution: fixed Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ Changes (by stepan): * status: new => closed * resolution: => fixed Comment: We do have a mechanism to cleanly do this for UMA architectures now. Check i945/kontron 986lcd-m for an example. -- Ticket URL: <https://tracker.coreboot.org/trac/coreboot/ticket/43#comment:2> coreboot <http://www.coreboot.org/>

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[PATCH] remove 6bx cpus from model_6xx
by Stefan Reinauer 19 Apr '10

19 Apr '10

They're supported by the model_6bx code... Signed-off-by: <stepan(a)coresystems.de> Index: src/cpu/intel/model_6xx/model_6xx_init.c =================================================================== --- src/cpu/intel/model_6xx/model_6xx_init.c (revision 5456) +++ src/cpu/intel/model_6xx/model_6xx_init.c (working copy) @@ -57,9 +57,6 @@ { X86_VENDOR_INTEL, 0x06A0 }, { X86_VENDOR_INTEL, 0x06A1 }, { X86_VENDOR_INTEL, 0x06A4 }, - { X86_VENDOR_INTEL, 0x06B0 }, /* Mobile Celeron FCBGA */ - { X86_VENDOR_INTEL, 0x06B1 }, /* Celeron (Tualatin) */ - { X86_VENDOR_INTEL, 0x06B4 }, { 0, 0 }, };

1 0

[commit] r5458 - in trunk/src/mainboard: . nokia nokia/ip530
by repository service 19 Apr '10

19 Apr '10

Author: uwe Date: Mon Apr 19 23:21:54 2010 New Revision: 5458 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5458 Log: Add support for the Nokia IP530. It's currently its able to run coreboot + seabios + sgabios. The following hardware works; P3 i440BX northbridge 82371 southbridge IDE normal disks + CF The following hardware doesn't work: 4x NIC 21143-PD 2x PCMCIA PCI1225PDV Signed-off-by: Marc Bertens <mbertens(a)xs4all.nl> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/src/mainboard/nokia/ trunk/src/mainboard/nokia/Kconfig trunk/src/mainboard/nokia/ip530/ trunk/src/mainboard/nokia/ip530/Kconfig trunk/src/mainboard/nokia/ip530/chip.h trunk/src/mainboard/nokia/ip530/devicetree.cb trunk/src/mainboard/nokia/ip530/irq_tables.c trunk/src/mainboard/nokia/ip530/mainboard.c trunk/src/mainboard/nokia/ip530/romstage.c Modified: trunk/src/mainboard/Kconfig Modified: trunk/src/mainboard/Kconfig ============================================================================== --- trunk/src/mainboard/Kconfig Mon Apr 19 22:47:29 2010 (r5457) +++ trunk/src/mainboard/Kconfig Mon Apr 19 23:21:54 2010 (r5458) @@ -68,6 +68,8 @@ bool "NEC" config VENDOR_NEWISYS bool "Newisys" +config VENDOR_NOKIA + bool "Nokia" config VENDOR_NVIDIA bool "NVIDIA" config VENDOR_OLPC @@ -273,6 +275,11 @@ config MAINBOARD_VENDOR string + default "Nokia" + depends on VENDOR_NOKIA + +config MAINBOARD_VENDOR + string default "NVIDIA" depends on VENDOR_NVIDIA @@ -398,6 +405,7 @@ source "src/mainboard/msi/Kconfig" source "src/mainboard/nec/Kconfig" source "src/mainboard/newisys/Kconfig" +source "src/mainboard/nokia/Kconfig" source "src/mainboard/nvidia/Kconfig" source "src/mainboard/olpc/Kconfig" source "src/mainboard/pcengines/Kconfig" Added: trunk/src/mainboard/nokia/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/nokia/Kconfig Mon Apr 19 23:21:54 2010 (r5458) @@ -0,0 +1,28 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Marc Bertens <mbertens(a)xs4all.nl> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +choice + prompt "Mainboard model" + depends on VENDOR_NOKIA + +source "src/mainboard/nokia/ip530/Kconfig" + +endchoice + Added: trunk/src/mainboard/nokia/ip530/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/nokia/ip530/Kconfig Mon Apr 19 23:21:54 2010 (r5458) @@ -0,0 +1,52 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Marc Bertens <mbertens(a)xs4all.nl> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_NOKIA_IP530 + bool "IP530" + select ARCH_X86 + select CPU_INTEL_SOCKET_PGA370 + select NORTHBRIDGE_INTEL_I440BX + select SOUTHBRIDGE_INTEL_I82371EB + select SUPERIO_SMSC_SMSCSUPERIO + select ROMCC + select HAVE_PIRQ_TABLE + select UDELAY_TSC + select BOARD_ROMSIZE_KB_256 + +config MAINBOARD_DIR + string + default nokia/ip530 + depends on BOARD_NOKIA_IP530 + +config MAINBOARD_PART_NUMBER + string + default "IP530" + depends on BOARD_NOKIA_IP530 + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_NOKIA_IP530 + +config IRQ_SLOT_COUNT + int + default 6 + depends on BOARD_NOKIA_IP530 + Added: trunk/src/mainboard/nokia/ip530/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/nokia/ip530/chip.h Mon Apr 19 23:21:54 2010 (r5458) @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Marc Bertens <mbertens(a)xs4all.nl> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; +struct mainboard_config {}; Added: trunk/src/mainboard/nokia/ip530/devicetree.cb ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/nokia/ip530/devicetree.cb Mon Apr 19 23:21:54 2010 (r5458) @@ -0,0 +1,94 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Marc Bertens <mbertens(a)xs4all.nl> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +chip northbridge/intel/i440bx # Northbridge + device apic_cluster 0 on # APIC cluster + chip cpu/intel/socket_PGA370 # CPU + device apic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + device pci 0.0 on end # Host bridge + device pci 1.0 on end # PCI/AGP bridge + chip southbridge/intel/i82371eb # Southbridge + device pci 7.0 on # ISA bridge + chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37C878) + device pnp 3f0.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 3f0.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 3f0.4 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 3f0.5 on # COM2 / IR + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 3f0.7 on # PS/2 keyboard / mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 # PS/2 keyboard interrupt + irq 0x72 = 12 # PS/2 mouse interrupt + end + device pnp 3f0.9 on # Game port + io 0x60 = 0x201 + end + device pnp 3f0.a on # Power-management events (PME) + io 0x60 = 0x600 + end + device pnp 3f0.b on # MIDI port (MPU-401) + io 0x60 = 0x330 + irq 0x70 = 5 + end + end + end + device pci 7.1 on end # IDE + device pci 7.2 on end # USB + device pci 7.3 on end # ACPI + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "ide_legacy_enable" = "1" + # Enable UDMA/33 for higher speed if your IDE device(s) support it. + register "ide0_drive0_udma33_enable" = "0" + register "ide0_drive1_udma33_enable" = "0" + register "ide1_drive0_udma33_enable" = "0" + register "ide1_drive1_udma33_enable" = "0" + end + device pci 0d.0 on end # NIC (DEC DECchip 21142/43) + device pci 0e.0 on end # NIC (DEC DECchip 21142/43) + device pci 0f.0 on end # CardBus bridge (TI PCI1225) + device pci 0f.1 on end # CardBus bridge (TI PCI1225) + end + device pci_domain 1 on # PCI domain 1 + device pci 00.0 on end # PCI bridge (DEC DECchip 21150) + end + device pci_domain 2 on # PCI domain 2 + device pci 04.0 on end # NIC (DECchip 21142/43) + device pci 04.0 on end # NIC (DECchip 21142/43) + end +end + Added: trunk/src/mainboard/nokia/ip530/irq_tables.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/nokia/ip530/irq_tables.c Mon Apr 19 23:21:54 2010 (r5458) @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Marc Bertens <mbertens(a)xs4all.nl> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */ + 0x00, /* Interrupt router bus */ + (0x07 << 3) | 0x0, /* Interrupt router dev */ + 0, /* IRQs devoted exclusively to PCI usage */ + 0x8086, /* Vendor */ + 0x122e, /* Device */ + 0, /* Miniport */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x36, /* Checksum */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + {0x00, (0x07 << 3) | 0x0, {{0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x63, 0x0ea8}}, 0x0, 0x0}, + {0x00, (0x0c << 3) | 0x0, {{0x61, 0x06a8}, {0x62, 0x06a8}, {0x00, 0x06a8}, {0x00, 0x06a8}}, 0x0, 0x0}, + {0x00, (0x0d << 3) | 0x0, {{0x60, 0x0ea8}, {0x61, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x1, 0x0}, + {0x00, (0x09 << 3) | 0x0, {{0x62, 0x0ea8}, {0x63, 0x0ea8}, {0x60, 0x0ea8}, {0x61, 0x0ea8}}, 0x2, 0x0}, + {0x00, (0x0a << 3) | 0x0, {{0x63, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0}, + {0x01, (0x00 << 3) | 0x0, {{0x60, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +} Added: trunk/src/mainboard/nokia/ip530/mainboard.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/nokia/ip530/mainboard.c Mon Apr 19 23:21:54 2010 (r5458) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Marc Bertens <mbertens(a)xs4all.nl> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("Nokia IP530 Mainboard") +}; Added: trunk/src/mainboard/nokia/ip530/romstage.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/nokia/ip530/romstage.c Mon Apr 19 23:21:54 2010 (r5458) @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Marc Bertens <mbertens(a)xs4all.nl> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <arch/hlt.h> +#include <stdlib.h> +#include "pc80/serial.c" +#include "console/console.c" +#include "lib/ramtest.c" +#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c" +#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c" +#include "northbridge/intel/i440bx/raminit.h" +#include "lib/debug.c" +#include "pc80/udelay_io.c" +#include "lib/delay.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" + +#define SERIAL_DEV PNP_DEV(0x3f0, SMSCSUPERIO_SP1) + +static inline int spd_read_byte(unsigned int device, unsigned int address) +{ + return smbus_read_byte(device, address); +} + +#include "northbridge/intel/i440bx/raminit.c" +#include "northbridge/intel/i440bx/debug.c" + +static void main(unsigned long bist) +{ + if (bist == 0) + early_mtrr_init(); + + smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); + console_init(); + report_bist_failure(bist); + + /* Enable access to the full ROM chip, needed very early by CBFS. */ + i82371eb_enable_rom(PCI_DEV(0, 7, 0) ); /* ISA bridge at 00:07.0. */ + + enable_smbus(); + /* dump_spd_registers(); */ + sdram_set_registers(); + sdram_set_spd_registers(); + sdram_enable(); + /* ram_check(0, 640 * 1024); */ +}

3 2

(no subject)
by Marc Bertens 19 Apr '10

19 Apr '10

Hi all, Here is my svn diff for the Nokia IP530, currently its able to run coreboot + seabios + sgabios. The following hardware works; P3 i440BX northbridge 82371 southbridge IDE normal disks + CF The following hardware does'nt work: 4x NIC 21143-PD 2x PCMCIA PCI1225PDV For flashing the the bios you need the following patches from patchwork http://patchwork.coreboot.org/patch/1185/ Intel 28F004/28F400 support http://patchwork.coreboot.org/patch/1195/ [v2,compilable] Board enable for IP530 I will work on the remaining issues, when someone has any good ideas to tackle the remainder issues that will be apriciated. Marc

3 4

[commit] r5457 - trunk
by repository service 19 Apr '10

19 Apr '10

Author: stepan Date: Mon Apr 19 22:47:29 2010 New Revision: 5457 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5457 Log: (trivial) utils are not depending on config.h. This slipped in by accident. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Mon Apr 19 22:39:22 2010 (r5456) +++ trunk/Makefile Mon Apr 19 22:47:29 2010 (r5457) @@ -155,7 +155,7 @@ mkdir -p $(obj)/mainboard/$(MAINBOARDDIR) $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR) -$(objutil)/%.o: $(objutil)/%.c $(obj)/config.h +$(objutil)/%.o: $(objutil)/%.c @printf " HOSTCC $(subst $(objutil)/,,$(@))\n" $(HOSTCC) -MMD $(HOSTCFLAGS) -c -o $@ $<

1 0

[commit] r5456 - in trunk: . src/arch/i386 util/abuild
by repository service 19 Apr '10

19 Apr '10

Author: oxygene Date: Mon Apr 19 22:39:22 2010 New Revision: 5456 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5456 Log: - Make abuild -sb work again - More explicit rules for obj/%.c->obj/%.o builds - Hide printf even with verbose make Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/Makefile trunk/src/arch/i386/Makefile.inc trunk/util/abuild/abuild Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Sat Apr 17 19:59:40 2010 (r5455) +++ trunk/Makefile Mon Apr 19 22:39:22 2010 (r5456) @@ -155,6 +155,14 @@ mkdir -p $(obj)/mainboard/$(MAINBOARDDIR) $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR) +$(objutil)/%.o: $(objutil)/%.c $(obj)/config.h + @printf " HOSTCC $(subst $(objutil)/,,$(@))\n" + $(HOSTCC) -MMD $(HOSTCFLAGS) -c -o $@ $< + +$(obj)/%.o: $(obj)/%.c $(obj)/config.h + @printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -MMD $(CFLAGS) -c -o $@ $< + objs:=$(obj)/mainboard/$(MAINBOARDDIR)/static.o initobjs:= drivers:= @@ -215,7 +223,7 @@ # $4 additional compiler flags de$(EMPTY)fine $(1)_$(2)_template $(obj)/$$(1)%$(3).o: src/$$(1)%.$(2) $(obj)/config.h - printf " CC $$$$(subst $$$$(obj)/,,$$$$(@))\n" + @printf " CC $$$$(subst $$$$(obj)/,,$$$$(@))\n" $(CC) $(4) -MMD $$$$(CFLAGS) -c -o $$$$@ $$$$< en$(EMPTY)def endef Modified: trunk/src/arch/i386/Makefile.inc ============================================================================== --- trunk/src/arch/i386/Makefile.inc Sat Apr 17 19:59:40 2010 (r5455) +++ trunk/src/arch/i386/Makefile.inc Mon Apr 19 22:39:22 2010 (r5456) @@ -27,7 +27,7 @@ endif $(obj)/coreboot.rom: $(obj)/coreboot.pre $(obj)/coreboot_ram $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) - printf " CBFS $(subst $(obj)/,,$(@))\n" + @printf " CBFS $(subst $(obj)/,,$(@))\n" cp $(obj)/coreboot.pre $@.tmp if [ -f $(obj)/coreboot_ap ]; \ then \ @@ -35,25 +35,25 @@ fi $(CBFSTOOL) $@.tmp add-stage $(obj)/coreboot_ram $(CONFIG_CBFS_PREFIX)/coreboot_ram $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) - printf " PAYLOAD \e[1;31mnone (as specified by user)\e[0m\n" + @printf " PAYLOAD \e[1;31mnone (as specified by user)\e[0m\n" else - printf " PAYLOAD $(CONFIG_FALLBACK_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_NAME))\n" + @printf " PAYLOAD $(CONFIG_FALLBACK_PAYLOAD_FILE) (compression: $(CBFS_PAYLOAD_COMPRESS_NAME))\n" $(CBFSTOOL) $@.tmp add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE) $(CONFIG_CBFS_PREFIX)/payload $(CBFS_PAYLOAD_COMPRESS_FLAG) endif ifeq ($(CONFIG_VGA_BIOS),y) - printf " VGABIOS $(CONFIG_FALLBACK_VGA_BIOS_FILE) $(CONFIG_FALLBACK_VGA_BIOS_ID)\n" + @printf " VGABIOS $(CONFIG_FALLBACK_VGA_BIOS_FILE) $(CONFIG_FALLBACK_VGA_BIOS_ID)\n" $(CBFSTOOL) $@.tmp add $(CONFIG_FALLBACK_VGA_BIOS_FILE) "pci$(CONFIG_FALLBACK_VGA_BIOS_ID).rom" optionrom endif ifeq ($(CONFIG_INTEL_MBI),y) - printf " MBI $(CONFIG_FALLBACK_MBI_FILE)\n" + @printf " MBI $(CONFIG_FALLBACK_MBI_FILE)\n" $(CBFSTOOL) $@.tmp add $(CONFIG_FALLBACK_MBI_FILE) mbi.bin mbi endif ifeq ($(CONFIG_BOOTSPLASH),y) - printf " BOOTSPLASH $(CONFIG_FALLBACK_BOOTSPLASH_FILE)\n" + @printf " BOOTSPLASH $(CONFIG_FALLBACK_BOOTSPLASH_FILE)\n" $(CBFSTOOL) $@.tmp add $(CONFIG_FALLBACK_BOOTSPLASH_FILE) bootsplash.jpg bootsplash endif mv $@.tmp $@ - printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" + @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print ####################################################################### @@ -174,11 +174,11 @@ $(CC) -MMD $(CFLAGS) -I$(src) -I. -c $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h - printf " CC romstage.inc\n" + @printf " CC romstage.inc\n" $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -c -S $< -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc - printf " POST romstage.inc\n" + @printf " POST romstage.inc\n" sed -e 's/\.rodata/.rom.data/g' -e 's/\.text/.section .rom.text/g' $^ > $@.tmp mv $@.tmp $@ endif Modified: trunk/util/abuild/abuild ============================================================================== --- trunk/util/abuild/abuild Sat Apr 17 19:59:40 2010 (r5455) +++ trunk/util/abuild/abuild Mon Apr 19 22:39:22 2010 (r5456) @@ -430,12 +430,15 @@ stime=`perl -e 'print time();' 2>/dev/null || date +%s` create_buildenv $VENDOR $MAINBOARD $CONFIG if [ $? -eq 0 -a $configureonly -eq 0 ]; then + if [ "$scanbuild" = "true" ]; then + rm -rf $TARGET/scan-build-results-tmp + fi compile_target $VENDOR $MAINBOARD && xml " <status>ok</status>" || xml "<status>broken</status>" if [ "$scanbuild" = "true" ]; then + rm -rf $TARGET/${VENDOR}_${MAINBOARD}-scanbuild mv `dirname $TARGET/scan-build-results-tmp/*/index.html` $TARGET/${VENDOR}_${MAINBOARD}-scanbuild - MAKE=$origMAKE fi fi # Not calculated here because we still print it in compile_target

1 0

[PATCH]Fix abuild -sb
by Patrick Georgi 19 Apr '10

19 Apr '10

Hi, abuild's scanbuild support was broken, and we didn't noticed. Following patch also cleans up some rough edges. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Index: util/abuild/abuild =================================================================== --- util/abuild/abuild (revision 5455) +++ util/abuild/abuild (working copy) @@ -430,12 +430,15 @@ stime=`perl -e 'print time();' 2>/dev/null || date +%s` create_buildenv $VENDOR $MAINBOARD $CONFIG if [ $? -eq 0 -a $configureonly -eq 0 ]; then + if [ "$scanbuild" = "true" ]; then + rm -rf $TARGET/scan-build-results-tmp + fi compile_target $VENDOR $MAINBOARD && xml " <status>ok</status>" || xml "<status>broken</status>" if [ "$scanbuild" = "true" ]; then + rm -rf $TARGET/${VENDOR}_${MAINBOARD}-scanbuild mv `dirname $TARGET/scan-build-results-tmp/*/index.html` $TARGET/${VENDOR}_${MAINBOARD}-scanbuild - MAKE=$origMAKE fi fi # Not calculated here because we still print it in compile_target Index: Makefile =================================================================== --- Makefile (revision 5455) +++ Makefile (working copy) @@ -155,6 +155,10 @@ mkdir -p $(obj)/mainboard/$(MAINBOARDDIR) $(objutil)/sconfig/sconfig $(MAINBOARDDIR) $(obj)/mainboard/$(MAINBOARDDIR) +$(obj)/%.o: $(obj)/%.c $(obj)/config.h + printf " CC $(subst $(obj)/,,$(@))\n" + $(CC) -MMD $(CFLAGS) -c -o $@ $< + objs:=$(obj)/mainboard/$(MAINBOARDDIR)/static.o initobjs:= drivers:=

2 4

Trac reminder: list of new ticket(s)
by coreboot tracker 19 Apr '10

19 Apr '10

1 0

[patch] Buildrom support for Asus M2V-MX SE
by Cristi Magherusan 18 Apr '10

18 Apr '10

Here's the patch: http://panzer.utcluj.ro/cgi-bin/cgit.cgi/avatt/patch/?id=1f45b765097fd8ba21… Signed-off by: Cristi Măgherușan <cristi.magherusan(a)net.utcluj.ro> I'm unable to say which others may worth it, but someone who's interested by buildrom can also cherry-pick some changesets/patches from my git repos at http://panzer.utcluj.ro/cgi-bin/cgit.cgi/ and include them in the main buildrom repo. A few of them are merged in the buildrom repo, while others are still in AVATT (I'm using braid to track my buildrom repo from AVATT, so it's easy to do it), but they will be merged eventually when I have some spare time.. From 1f45b765097fd8ba2139a078bd57679e16ac4699 Mon Sep 17 00:00:00 2001 From: Cristi Măgherușan <cristi.magherusan(a)net.utcluj.ro> Date: Thu, 16 Jul 2009 18:16:13 +0000 Subject: Added support for my Asus M2V-MX SE --- diff --git a/buildrom/buildrom-devel/config/platforms/Config.in b/buildrom/buildrom-devel/config/platforms/Config.in index e8a0a8b..1fa6a12 100644 --- a/buildrom/buildrom-devel/config/platforms/Config.in +++ b/buildrom/buildrom-devel/config/platforms/Config.in @@ -104,6 +104,13 @@ config PLATFORM_ASUS_A8N_E select PLATFORM select PLATFORM_SUPPORT_64BIT +config PLATFORM_ASUS_M2V_MX_SE + bool "ASUS M2V-MX SE" + depends on VENDOR_ASUS + depends on COREBOOT_V2 + select PLATFORM + select PLATFORM_SUPPORT_64BIT + config PLATFORM_GA_2761GXDK bool "GIGABYTE GA-2761GXDK" depends on VENDOR_GIGABYTE diff --git a/buildrom/buildrom-devel/config/platforms/asus_m2v-mx_se.conf b/buildrom/buildrom-devel/config/platforms/asus_m2v-mx_se.conf new file mode 100644 index 0000000..a78863e --- a/dev/null +++ b/buildrom/buildrom-devel/config/platforms/asus_m2v-mx_se.conf @@ -0,0 +1,28 @@ +# Support for the ASUS A8V-E SE board + +#### Platform configuration + +ifeq ($(CONFIG_TARGET_64BIT),y) +TARGET_ARCH=x86_64 +CFLAGS_platform = +else +TARGET_ARCH=i686 +CFLAGS_platform = +endif + +# kernel configuration (for LAB) + +# TODO + +UCLIBC_ARCH=$(TARGET_ARCH) + +# Etherboot configuration + +ETHERBOOT_ARCH=i386 + +# coreboot configuration + +COREBOOT_VENDOR=asus +COREBOOT_BOARD=m2v-mx_se +CBV2_TDIR=m2v-mx_se +CBV2_TAG=4426 diff --git a/buildrom/buildrom-devel/config/platforms/platforms.conf b/buildrom/buildrom-devel/config/platforms/platforms.conf index 733ca73..f5f62f8 100644 --- a/buildrom/buildrom-devel/config/platforms/platforms.conf +++ b/buildrom/buildrom-devel/config/platforms/platforms.conf @@ -23,6 +23,7 @@ PLATFORM-$(CONFIG_PLATFORM_DBE61) = dbe61.conf PLATFORM-$(CONFIG_PLATFORM_GA_M57SLI_S4) = m57sli.conf PLATFORM-$(CONFIG_PLATFORM_ASUS_A8V_E_SE) = asus_a8v-e_se.conf PLATFORM-$(CONFIG_PLATFORM_ASUS_A8N_E) = asus_a8n-e.conf +PLATFORM-$(CONFIG_PLATFORM_ASUS_M2V_MX_SE) = asus_m2v-mx_se.conf PLATFORM-$(CONFIG_PLATFORM_TYAN_S2881) = tyan-s2881.conf PLATFORM-$(CONFIG_PLATFORM_TYAN_S2882) = tyan-s2882.conf PLATFORM-$(CONFIG_PLATFORM_TYAN_S2891) = tyan-s2891.conf -- Ing. Cristi Măgherușan, System/Network Engineer Technical University of Cluj-Napoca, Romania http://cc.utcluj.ro +40264 401247

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coreboot April 2010