coreboot April 2010

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by Илья 16 Apr '10

16 Apr '10

Can someone answer my question? http://www.coreboot.org/pipermail/coreboot/2010-April/057236.html

2 1

[commit] r5452 - trunk/src/include/cpu/amd
by repository service 16 Apr '10

16 Apr '10

Author: myles Date: Fri Apr 16 15:43:49 2010 New Revision: 5452 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5452 Log: Fix a typo to remove a few more warnings. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/include/cpu/amd/microcode.h Modified: trunk/src/include/cpu/amd/microcode.h ============================================================================== --- trunk/src/include/cpu/amd/microcode.h Fri Apr 16 13:45:16 2010 (r5451) +++ trunk/src/include/cpu/amd/microcode.h Fri Apr 16 15:43:49 2010 (r5452) @@ -1,5 +1,5 @@ #ifndef CPU_AMD_MICROCODE_H -#define CPU_AMD_MICORCODE_H +#define CPU_AMD_MICROCODE_H void amd_update_microcode(void *microcode_updates, unsigned processor_rev_id); void update_microcode(u32 processor_rev_id);

1 0

ASUS M2V-TVM....
by Chi Min Wang 16 Apr '10

16 Apr '10

Hi,here is the POST output by the serial console.... ====================================================== > coreboot-4.0-r Mon Apr 12 13:20:12 CST 2010 starting... > now booting... real_main > Enabling routing table for node 00 done. > Enabling UP settings > Disabling read/write/fill probes for UP... done. > coherent_ht_finalize > done > core0 started: > now booting... Core0 started > started ap apicid: > SBLink=00 > NC node|link=00 > 00entering optimize_link_incoherent_ht > sysinfo->link_pair_num=0x1 > entering ht_optimize_link > pos=0x8a, unfiltered freq_cap=0x8035 > pos=0x8a, filtered freq_cap=0x35 > pos=0x6e, unfiltered freq_cap=0x75 > pos=0x6e, filtered freq_cap=0x75 > freq_cap1=0x35, freq_cap2=0x75 > dev1 old_freq=0x0, freq=0x5, needs_reset=0x1 > dev2 old_freq=0x0, freq=0x5, needs_reset=0x1 > width_cap1=0x11, width_cap2=0x11 > dev1 input ln_width1=0x4, ln_width2=0x4 > dev1 input width=0x1 > dev1 output ln_width1=0x4, ln_width2=0x4 > dev1 input|output width=0x11 > old dev1 input|output width=0x11 > dev2 input|output width=0x11 > old dev2 input|output width=0x11 > after ht_optimize_link for link pair 0, reset_needed=0x1 > after optimize_link_read_pointers_chain, reset_needed=0x1 > 01K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT > freq: 05 VIA HT caps: 0075 > 0101Xht reset - > soft reset > > > coreboot-4.0-r Mon Apr 12 13:20:12 CST 2010 starting... > now booting... real_main > Enabling routing table for node 00 done. > Enabling UP settings > Disabling read/write/fill probes for UP... done. > coherent_ht_finalize > done > core0 started: > now booting... Core0 started > started ap apicid: > SBLink=00 > NC node|link=00 > 00entering optimize_link_incoherent_ht > sysinfo->link_pair_num=0x1 > entering ht_optimize_link > pos=0x8a, unfiltered freq_cap=0x8035 > pos=0x8a, filtered freq_cap=0x35 > pos=0x6e, unfiltered freq_cap=0x75 > pos=0x6e, filtered freq_cap=0x75 > freq_cap1=0x35, freq_cap2=0x75 > dev1 old_freq=0x5, freq=0x5, needs_reset=0x0 > dev2 old_freq=0x5, freq=0x5, needs_reset=0x0 > width_cap1=0x11, width_cap2=0x11 > dev1 input ln_width1=0x4, ln_width2=0x4 > dev1 input width=0x1 > dev1 output ln_width1=0x4, ln_width2=0x4 > dev1 input|output width=0x11 > old dev1 input|output width=0x11 > dev2 input|output width=0x11 > old dev2 input|output width=0x11 > after ht_optimize_link for link pair 0, reset_needed=0x0 > after optimize_link_read_pointers_chain, reset_needed=0x0 > 00K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT > freq: 05 VIA HT caps: 0075 > 00after enable_fid_change

3 6

build service results for r5450
by coreboot information 15 Apr '10

15 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5450 to the coreboot repository. This caused the following changes: Change Log: fix romcc compiled i3100 boards. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of intel:mtarvon has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5450 - trunk/src/northbridge/intel/i3100
by repository service 15 Apr '10

15 Apr '10

Author: stepan Date: Fri Apr 16 03:45:44 2010 New Revision: 5450 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5450 Log: fix romcc compiled i3100 boards. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/intel/i3100/raminit.h Modified: trunk/src/northbridge/intel/i3100/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i3100/raminit.h Fri Apr 16 03:14:50 2010 (r5449) +++ trunk/src/northbridge/intel/i3100/raminit.h Fri Apr 16 03:45:44 2010 (r5450) @@ -30,6 +30,8 @@ u16 channel1[DIMM_SOCKETS]; }; +#ifndef __ROMCC__ void sdram_initialize(int controllers, const struct mem_controller *ctrl); +#endif #endif

1 0

build service results for r5449
by coreboot information 15 Apr '10

15 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5449 to the coreboot repository. This caused the following changes: Change Log: fix up sb600 and it8712f tree. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:dbm690t has been fixed Compilation of amd:pistachio has been fixed Compilation of asus:a8n_e has been fixed Compilation of asus:m2v-mx_se has been fixed Compilation of intel:mtarvon is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5449&device=mtarvon&vendor… Compilation of lippert:roadrunner-lx has been fixed Compilation of lippert:spacerunner-lx has been fixed Compilation of technexion:tim5690 has been fixed Compilation of technexion:tim8690 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5449 - in trunk/src: southbridge/amd/sb600 superio/ite/it8712f
by repository service 15 Apr '10

15 Apr '10

Author: stepan Date: Fri Apr 16 03:14:50 2010 New Revision: 5449 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5449 Log: fix up sb600 and it8712f tree. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/southbridge/amd/sb600/sb600_early_setup.c trunk/src/superio/ite/it8712f/it8712f.h trunk/src/superio/ite/it8712f/it8712f_early_serial.c Modified: trunk/src/southbridge/amd/sb600/sb600_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_early_setup.c Fri Apr 16 02:31:44 2010 (r5448) +++ trunk/src/southbridge/amd/sb600/sb600_early_setup.c Fri Apr 16 03:14:50 2010 (r5449) @@ -17,6 +17,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <reset.h> #include <arch/cpu.h> #include "sb600.h" #include "sb600_smbus.c" @@ -196,7 +197,7 @@ } -static void hard_reset(void) +void hard_reset(void) { set_bios_reset(); @@ -205,14 +206,13 @@ outb(0x0e, 0x0cf9); } -static void soft_reset(void) +void soft_reset(void) { set_bios_reset(); /* link reset */ outb(0x06, 0x0cf9); } - static void sb600_pci_port80(void) { u8 byte; Modified: trunk/src/superio/ite/it8712f/it8712f.h ============================================================================== --- trunk/src/superio/ite/it8712f/it8712f.h Fri Apr 16 02:31:44 2010 (r5448) +++ trunk/src/superio/ite/it8712f/it8712f.h Fri Apr 16 03:14:50 2010 (r5449) @@ -36,6 +36,6 @@ #ifndef __ROMCC__ void it8712f_kill_watchdog(void); void it8712f_enable_serial(device_t dev, unsigned iobase); -void it8712f_24mhz_clkin(void) -void it8712f_enable_3vsbsw(void) +void it8712f_24mhz_clkin(void); +void it8712f_enable_3vsbsw(void); #endif Modified: trunk/src/superio/ite/it8712f/it8712f_early_serial.c ============================================================================== --- trunk/src/superio/ite/it8712f/it8712f_early_serial.c Fri Apr 16 02:31:44 2010 (r5448) +++ trunk/src/superio/ite/it8712f/it8712f_early_serial.c Fri Apr 16 03:14:50 2010 (r5449) @@ -91,7 +91,7 @@ it8712f_exit_conf(); } -static void it8712f_kill_watchdog(void) +void it8712f_kill_watchdog(void) { it8712f_enter_conf();

1 0

build service results for r5448
by coreboot information 15 Apr '10

15 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5448 to the coreboot repository. This caused the following changes: Change Log: zero warnings days: unify mp tables. fix warnings. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:dbm690t has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5448&device=dbm690t&vendor… Compilation of amd:pistachio has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5448&device=pistachio&vend… Compilation of asus:a8n_e has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5448&device=a8n_e&vendor=a… Compilation of asus:m2v-mx_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5448&device=m2v-mx_se&vend… Compilation of intel:mtarvon has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5448&device=mtarvon&vendor… Compilation of lippert:roadrunner-lx has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5448&device=roadrunner-lx&… Compilation of lippert:spacerunner-lx has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5448&device=spacerunner-lx… Compilation of technexion:tim5690 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5448&device=tim5690&vendor… Compilation of technexion:tim8690 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5448&device=tim8690&vendor… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5448 - in trunk/src: mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/serengeti_cheetah mainboard/amd/serengeti_cheetah_fam1...
by repository service 15 Apr '10

15 Apr '10

Author: stepan Date: Fri Apr 16 02:31:44 2010 New Revision: 5448 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5448 Log: zero warnings days: unify mp tables. fix warnings. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/amd/dbm690t/mptable.c trunk/src/mainboard/amd/mahogany/mptable.c trunk/src/mainboard/amd/mahogany_fam10/mptable.c trunk/src/mainboard/amd/pistachio/mptable.c trunk/src/mainboard/amd/serengeti_cheetah/mptable.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c trunk/src/mainboard/arima/hdama/mptable.c trunk/src/mainboard/asrock/939a785gmh/mptable.c trunk/src/mainboard/asus/a8n_e/mptable.c trunk/src/mainboard/asus/a8v-e_se/mptable.c trunk/src/mainboard/broadcom/blast/mptable.c trunk/src/mainboard/dell/s1850/mptable.c trunk/src/mainboard/gigabyte/ga_2761gxdk/mptable.c trunk/src/mainboard/gigabyte/m57sli/mptable.c trunk/src/mainboard/hp/dl145_g3/mptable.c trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/ibm/e325/mptable.c trunk/src/mainboard/ibm/e326/mptable.c trunk/src/mainboard/intel/eagleheights/debug.c trunk/src/mainboard/intel/eagleheights/mptable.c trunk/src/mainboard/intel/jarrell/mptable.c trunk/src/mainboard/intel/mtarvon/mptable.c trunk/src/mainboard/intel/truxton/mptable.c trunk/src/mainboard/intel/xe7501devkit/mptable.c trunk/src/mainboard/iwill/dk8_htx/mptable.c trunk/src/mainboard/iwill/dk8s2/mptable.c trunk/src/mainboard/iwill/dk8x/mptable.c trunk/src/mainboard/kontron/kt690/mptable.c trunk/src/mainboard/msi/ms7135/mptable.c trunk/src/mainboard/msi/ms7260/mptable.c trunk/src/mainboard/msi/ms9185/mptable.c trunk/src/mainboard/msi/ms9282/mptable.c trunk/src/mainboard/msi/ms9652_fam10/mptable.c trunk/src/mainboard/newisys/khepri/mptable.c trunk/src/mainboard/nvidia/l1_2pvv/mptable.c trunk/src/mainboard/sunw/ultra40/mptable.c trunk/src/mainboard/sunw/ultra40/romstage.c trunk/src/mainboard/supermicro/h8dme/mptable.c trunk/src/mainboard/supermicro/h8dmr/mptable.c trunk/src/mainboard/supermicro/h8dmr_fam10/mptable.c trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c trunk/src/mainboard/supermicro/x6dai_g/mptable.c trunk/src/mainboard/supermicro/x6dhe_g/mptable.c trunk/src/mainboard/supermicro/x6dhe_g2/mptable.c trunk/src/mainboard/supermicro/x6dhr_ig/mptable.c trunk/src/mainboard/supermicro/x6dhr_ig2/mptable.c trunk/src/mainboard/technexion/tim5690/mptable.c trunk/src/mainboard/technexion/tim8690/mptable.c trunk/src/mainboard/tyan/s2735/mptable.c trunk/src/mainboard/tyan/s2850/mptable.c trunk/src/mainboard/tyan/s2875/mptable.c trunk/src/mainboard/tyan/s2880/mptable.c trunk/src/mainboard/tyan/s2881/mptable.c trunk/src/mainboard/tyan/s2882/mptable.c trunk/src/mainboard/tyan/s2885/mptable.c trunk/src/mainboard/tyan/s2891/mptable.c trunk/src/mainboard/tyan/s2892/mptable.c trunk/src/mainboard/tyan/s2895/mptable.c trunk/src/mainboard/tyan/s2912/get_bus_conf.c trunk/src/mainboard/tyan/s2912/mptable.c trunk/src/mainboard/tyan/s2912_fam10/mptable.c trunk/src/mainboard/tyan/s4880/mptable.c trunk/src/mainboard/tyan/s4882/mptable.c trunk/src/mainboard/via/epia-n/mptable.c trunk/src/mainboard/via/pc2500e/mptable.c trunk/src/northbridge/amd/amdmct/mct/mct_d.c trunk/src/northbridge/amd/amdmct/mct/mct_d_gcc.h trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c trunk/src/northbridge/intel/i3100/raminit.h trunk/src/superio/ite/it8712f/it8712f.h trunk/src/superio/ite/it8712f/it8712f_early_serial.c Modified: trunk/src/mainboard/amd/dbm690t/mptable.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/amd/dbm690t/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "ATI "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "DBM690T "; struct mp_config_table *mc; int j; Modified: trunk/src/mainboard/amd/mahogany/mptable.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/amd/mahogany/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -42,7 +42,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "AMD "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "MAHOGANY "; struct mp_config_table *mc; int j; Modified: trunk/src/mainboard/amd/mahogany_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/amd/mahogany_fam10/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -42,7 +42,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "AMD "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "MAHOGANY "; struct mp_config_table *mc; int j; Modified: trunk/src/mainboard/amd/pistachio/mptable.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/amd/pistachio/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "ATI "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "PISTACHIO "; struct mp_config_table *mc; int j; Modified: trunk/src/mainboard/amd/serengeti_cheetah/mptable.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/amd/serengeti_cheetah/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "AMD "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "SERENGETI "; struct mp_config_table *mc; Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "AMD "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "SERENGETI "; struct mp_config_table *mc; Modified: trunk/src/mainboard/arima/hdama/mptable.c ============================================================================== --- trunk/src/mainboard/arima/hdama/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/arima/hdama/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -110,7 +110,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "LNXI "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "HDAMA "; struct mp_config_table *mc; unsigned char bus_num; Modified: trunk/src/mainboard/asrock/939a785gmh/mptable.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/asrock/939a785gmh/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -42,7 +42,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "AMD "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "MAHOGANY "; struct mp_config_table *mc; int j; Modified: trunk/src/mainboard/asus/a8n_e/mptable.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/asus/a8n_e/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -37,7 +37,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "ASUS "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "A8N-E "; struct mp_config_table *mc; unsigned sbdn; Modified: trunk/src/mainboard/asus/a8v-e_se/mptable.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/asus/a8v-e_se/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -26,7 +26,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "LNXB "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "A8V-E SE "; struct mp_config_table *mc; int bus_isa = 42; Modified: trunk/src/mainboard/broadcom/blast/mptable.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/broadcom/blast/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -24,7 +24,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "BROADCOM"; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "BLAST "; struct mp_config_table *mc; Modified: trunk/src/mainboard/dell/s1850/mptable.c ============================================================================== --- trunk/src/mainboard/dell/s1850/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/dell/s1850/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -7,7 +7,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "DELL "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "S2850 "; struct mp_config_table *mc; unsigned char bus_num; Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/mptable.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "GIGABYTE"; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "GA-2761GXDK "; struct mp_config_table *mc; unsigned sbdn; Modified: trunk/src/mainboard/gigabyte/m57sli/mptable.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/gigabyte/m57sli/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -39,7 +39,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "GIGABYTE"; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "M57SLI "; struct mp_config_table *mc; unsigned sbdn; Modified: trunk/src/mainboard/hp/dl145_g3/mptable.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/hp/dl145_g3/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -46,7 +46,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "HP "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "TREX "; struct mp_config_table *mc; Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Fri Apr 16 02:31:44 2010 (r5448) @@ -185,7 +185,8 @@ DIMM5, DIMM7, 0, 0, }; - struct sys_info *sysinfo = (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; unsigned bsp_apicid = 0; @@ -216,8 +217,7 @@ // setup_early_ipmi_serial(); pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - - print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); + printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram @@ -243,7 +243,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + printk(BIOS_DEBUG, "begin msr fid, vid %08x %08x\n", msr.hi, msr.lo); } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); @@ -252,7 +252,7 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); + printk(BIOS_DEBUG, "end msr fid, vid %08x %08x\n", msr.hi, msr.lo); } #endif @@ -261,7 +261,7 @@ // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { - print_info("ht reset -\n"); + printk(BIOS_INFO, "ht reset -\n"); soft_reset(); } @@ -278,6 +278,5 @@ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); - } Modified: trunk/src/mainboard/ibm/e325/mptable.c ============================================================================== --- trunk/src/mainboard/ibm/e325/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/ibm/e325/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -7,7 +7,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "IBM "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "E325 "; struct mp_config_table *mc; @@ -49,6 +49,7 @@ bus_isa++; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); + bus_8111_0 = 1; bus_8111_1 = 4; bus_isa = 5; } Modified: trunk/src/mainboard/ibm/e326/mptable.c ============================================================================== --- trunk/src/mainboard/ibm/e326/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/ibm/e326/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -7,7 +7,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "IBM "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "E325 "; struct mp_config_table *mc; @@ -49,6 +49,7 @@ bus_isa++; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n"); + bus_8111_0 = 1; bus_8111_1 = 4; bus_isa = 5; } @@ -57,7 +58,6 @@ dev = dev_find_slot(1, PCI_DEVFN(0x01,0)); if (dev) { bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n"); bus_8131_1 = 2; Modified: trunk/src/mainboard/intel/eagleheights/debug.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/debug.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/intel/eagleheights/debug.c Fri Apr 16 02:31:44 2010 (r5448) @@ -210,7 +210,7 @@ print_debug("\n"); } -static void dump_pci_devices(void) +static inline void dump_pci_devices(void) { device_t dev; for(dev = PCI_DEV(0, 0, 0); Modified: trunk/src/mainboard/intel/eagleheights/mptable.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/intel/eagleheights/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -61,7 +61,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "Intel "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "EagleHeights"; struct mp_config_table *mc; unsigned char bus_num, bus_chipset, bus_isa, bus_pci; Modified: trunk/src/mainboard/intel/jarrell/mptable.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/intel/jarrell/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -7,7 +7,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "LNXI "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "SE7520JR20 "; struct mp_config_table *mc; unsigned char bus_num; @@ -16,7 +16,7 @@ unsigned char bus_pxhd_2; unsigned char bus_pxhd_3 = 0; unsigned char bus_pxhd_4 = 0; - unsigned char bus_pxhd_x; + unsigned char bus_pxhd_x = 0; unsigned char bus_ich5r_1; unsigned int bus_pxhd_id; @@ -137,6 +137,7 @@ else { printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n"); } + /* pxhd apic 5 */ if(bus_pxhd_3) { /* Active riser pxhd */ dev = dev_find_slot(bus_pxhd_x, PCI_DEVFN(0x00,1)); @@ -164,7 +165,6 @@ } } } - /* ISA backward compatibility interrupts */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, @@ -218,8 +218,8 @@ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0x00, MP_APIC_ALL, 0x01); + /* FIXME verify I have the irqs handled for all of the risers */ -#warning "FIXME verify I have the irqs handled for all of the risers" /* 2:3.0 PCI Slot 1 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_pxhd_1, (3<<2)|0, 0x9, 0x0); Modified: trunk/src/mainboard/intel/mtarvon/mptable.c ============================================================================== --- trunk/src/mainboard/intel/mtarvon/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/intel/mtarvon/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -29,7 +29,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "Intel "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "Mt. Arvon "; struct mp_config_table *mc; u8 bus_isa = 7; Modified: trunk/src/mainboard/intel/truxton/mptable.c ============================================================================== --- trunk/src/mainboard/intel/truxton/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/intel/truxton/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -27,7 +27,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "Intel "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "Truxton "; struct mp_config_table *mc; u8 bus_num; Modified: trunk/src/mainboard/intel/xe7501devkit/mptable.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/intel/xe7501devkit/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -145,7 +145,7 @@ static void *smp_write_config_table(void* v) { static const char sig[4] = MPC_SIGNATURE; - static const char oem[8] = "INTEL "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "XE7501DEVKIT"; struct mp_config_table *mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); Modified: trunk/src/mainboard/iwill/dk8_htx/mptable.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/iwill/dk8_htx/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -15,7 +15,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "IWILL "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "DK8-HTX "; struct mp_config_table *mc; Modified: trunk/src/mainboard/iwill/dk8s2/mptable.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/iwill/dk8s2/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -7,7 +7,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "IWILL "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "DK8X "; struct mp_config_table *mc; unsigned char bus_num; Modified: trunk/src/mainboard/iwill/dk8x/mptable.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/iwill/dk8x/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -7,7 +7,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "IWILL "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "DK8X "; struct mp_config_table *mc; unsigned char bus_num; Modified: trunk/src/mainboard/kontron/kt690/mptable.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/kontron/kt690/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "KONTRON "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "KT690 "; struct mp_config_table *mc; int j; Modified: trunk/src/mainboard/msi/ms7135/mptable.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/msi/ms7135/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "MSI "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "MS7135 "; struct mp_config_table *mc; unsigned sbdn; Modified: trunk/src/mainboard/msi/ms7260/mptable.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/msi/ms7260/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "MSI "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "MS-7260 "; struct mp_config_table *mc; unsigned int sbdn; Modified: trunk/src/mainboard/msi/ms9185/mptable.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/msi/ms9185/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -43,7 +43,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "MSI "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "MS9185 "; struct mp_config_table *mc; Modified: trunk/src/mainboard/msi/ms9282/mptable.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/msi/ms9282/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -37,7 +37,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "MSI "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "MS9282 "; struct mp_config_table *mc; struct mb_sysconf_t *m; Modified: trunk/src/mainboard/msi/ms9652_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/msi/ms9652_fam10/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "MSI "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "K9ND MS-9652"; struct mp_config_table *mc; struct mb_sysconf_t *m; Modified: trunk/src/mainboard/newisys/khepri/mptable.c ============================================================================== --- trunk/src/mainboard/newisys/khepri/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/newisys/khepri/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -7,7 +7,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "NEWISYS "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "KHEPRI "; struct mp_config_table *mc; unsigned char bus_num; Modified: trunk/src/mainboard/nvidia/l1_2pvv/mptable.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/nvidia/l1_2pvv/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "NVIDIA "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "L1_2PVV "; struct mp_config_table *mc; struct mb_sysconf_t *m; Modified: trunk/src/mainboard/sunw/ultra40/mptable.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/sunw/ultra40/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -36,7 +36,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "SUNW "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "ultra40 "; struct mp_config_table *mc; Modified: trunk/src/mainboard/sunw/ultra40/romstage.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/romstage.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/sunw/ultra40/romstage.c Fri Apr 16 02:31:44 2010 (r5448) @@ -41,10 +41,6 @@ #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1) -static void memreset_setup(void) -{ -} - static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -53,16 +49,17 @@ #define SUPERIO_GPIO_IO_BASE 0x400 -static void sio_gpio_setup(void){ - +#ifdef ENABLE_ONBOARD_SCSI +static void sio_gpio_setup(void) +{ unsigned value; /*Enable onboard scsi*/ lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c); lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1))); - } +#endif static inline void activate_spd_rom(const struct mem_controller *ctrl) { @@ -111,11 +108,9 @@ static void sio_setup(void) { - unsigned value; uint32_t dword; uint8_t byte; - pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1, 0), 0xac, 0x047f0400); @@ -127,25 +122,22 @@ dword |= (1<<29)|(1<<0); pci_write_config32(PCI_DEV(0, CK804_DEVN_BASE+1 , 0), 0xa0, dword); -#if 1 lpc47b397_enable_serial(SUPERIO_GPIO_DEV, SUPERIO_GPIO_IO_BASE); value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x77); value &= 0xbf; lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x77, value); -#endif - } void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { + // Node 0 (0xa<<3)|0, (0xa<<3)|2, 0, 0, (0xa<<3)|1, (0xa<<3)|3, 0, 0, -#if CONFIG_MAX_PHYSICAL_CPUS > 1 + // Node 1 (0xa<<3)|4, (0xa<<3)|6, 0, 0, (0xa<<3)|5, (0xa<<3)|7, 0, 0, -#endif }; int needs_reset; @@ -205,7 +197,6 @@ enable_smbus(); - memreset_setup(); sdram_initialize(nodes, ctrl); post_cache_as_ram(); Modified: trunk/src/mainboard/supermicro/h8dme/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/supermicro/h8dme/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "SUPERMIC"; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "H8DMR "; struct mp_config_table *mc; unsigned sbdn; Modified: trunk/src/mainboard/supermicro/h8dmr/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/supermicro/h8dmr/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -38,7 +38,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "SUPERMIC"; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "H8DMR "; struct mp_config_table *mc; unsigned sbdn; Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "SUPERMIC"; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "H8DMR "; struct mp_config_table *mc; struct mb_sysconf_t *m; Modified: trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "SUPERMIC"; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "H8QME "; struct mp_config_table *mc; struct mb_sysconf_t *m; Modified: trunk/src/mainboard/supermicro/x6dai_g/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/supermicro/x6dai_g/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -7,7 +7,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "LNXI "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "X6DAI-G "; struct mp_config_table *mc; unsigned char bus_num; Modified: trunk/src/mainboard/supermicro/x6dhe_g/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/supermicro/x6dhe_g/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -7,7 +7,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "LNXI "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "X6DHE "; struct mp_config_table *mc; unsigned char bus_num; @@ -43,11 +43,9 @@ dev = dev_find_slot(0, PCI_DEVFN(0x1c,0)); if (dev) { bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1c.0, using defaults\n"); - - bus_esb6300_2 = 6; + bus_esb6300_1 = 6; } /* esb6300_1 */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); @@ -55,33 +53,25 @@ bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; - } - else { + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); - - bus_esb6300_1 = 7; + bus_esb6300_2 = 7; bus_isa = 8; } /* pxhd-1 */ dev = dev_find_slot(1, PCI_DEVFN(0x0,0)); if (dev) { bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n"); - bus_pxhd_1 = 2; } /* pxhd-2 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,2)); if (dev) { bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n"); - bus_pxhd_2 = 3; } } @@ -106,8 +96,7 @@ if (res) { smp_write_ioapic(mc, 0x04, 0x20, res->base); } - } - else { + } else { printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n"); printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev); } @@ -118,14 +107,12 @@ if (res) { smp_write_ioapic(mc, 0x05, 0x20, res->base); } - } - else { + } else { printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n"); printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev); } } - /* ISA backward compatibility interrupts */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, 0x02, 0x00); @@ -182,7 +169,7 @@ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, MP_APIC_ALL, 0x01); -#warning "FIXME verify I have the irqs handled for all of the risers" + /* FIXME verify I have the irqs handled for all of the risers */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); Modified: trunk/src/mainboard/supermicro/x6dhe_g2/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/supermicro/x6dhe_g2/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -7,7 +7,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "LNXI "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "X6DHE "; struct mp_config_table *mc; unsigned char bus_num; @@ -43,11 +43,9 @@ dev = dev_find_slot(0, PCI_DEVFN(0x1c,0)); if (dev) { bus_esb6300_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1c.0, using defaults\n"); - - bus_esb6300_2 = 6; + bus_esb6300_1 = 6; } /* esb6300_1 */ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); @@ -55,33 +53,25 @@ bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); bus_isa++; - } - else { + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); - - bus_esb6300_1 = 7; + bus_esb6300_2 = 7; bus_isa = 8; } /* pxhd-1 */ dev = dev_find_slot(1, PCI_DEVFN(0x0,0)); if (dev) { bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.1, using defaults\n"); - bus_pxhd_1 = 2; } /* pxhd-2 */ dev = dev_find_slot(1, PCI_DEVFN(0x00,2)); if (dev) { bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - - } - else { + } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n"); - bus_pxhd_2 = 3; } } @@ -106,8 +96,7 @@ if (res) { smp_write_ioapic(mc, 0x04, 0x20, res->base); } - } - else { + } else { printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.1\n"); printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev); } @@ -118,14 +107,12 @@ if (res) { smp_write_ioapic(mc, 0x05, 0x20, res->base); } - } - else { + } else { printk(BIOS_DEBUG, "ERROR - could not find IOAPIC PCI 1:00.3\n"); printk(BIOS_DEBUG, "CONFIG_DEBUG: Dev= %p\n", dev); } } - /* ISA backward compatibility interrupts */ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, 0x02, 0x00); @@ -182,7 +169,7 @@ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x00, MP_APIC_ALL, 0x01); -#warning "FIXME verify I have the irqs handled for all of the risers" + /* FIXME verify I have the irqs handled for all of the risers */ /* Compute the checksums */ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length); Modified: trunk/src/mainboard/supermicro/x6dhr_ig/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/supermicro/x6dhr_ig/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -7,7 +7,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "LNXI "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "X6DHR-iG "; struct mp_config_table *mc; unsigned char bus_num; Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -7,7 +7,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "LNXI "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "X6DHR-iG "; struct mp_config_table *mc; unsigned char bus_num; Modified: trunk/src/mainboard/technexion/tim5690/mptable.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/technexion/tim5690/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "ATI "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "TIM5690 "; struct mp_config_table *mc; int j; Modified: trunk/src/mainboard/technexion/tim8690/mptable.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/technexion/tim8690/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -41,7 +41,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "ATI "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "TIM8690 "; struct mp_config_table *mc; int j; Modified: trunk/src/mainboard/tyan/s2735/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/tyan/s2735/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -7,7 +7,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "TYAN "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "S2735 "; struct mp_config_table *mc; Modified: trunk/src/mainboard/tyan/s2850/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2850/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/tyan/s2850/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -46,7 +46,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "TYAN "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "S2850 "; struct mp_config_table *mc; Modified: trunk/src/mainboard/tyan/s2875/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2875/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/tyan/s2875/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -44,7 +44,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "TYAN "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "S2875 "; struct mp_config_table *mc; Modified: trunk/src/mainboard/tyan/s2880/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2880/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/tyan/s2880/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -46,7 +46,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "TYAN "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "S2880 "; struct mp_config_table *mc; Modified: trunk/src/mainboard/tyan/s2881/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2881/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/tyan/s2881/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -23,7 +23,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "TYAN "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "S2881 "; struct mp_config_table *mc; Modified: trunk/src/mainboard/tyan/s2882/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2882/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/tyan/s2882/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -46,7 +46,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "TYAN "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "S2882 "; struct mp_config_table *mc; Modified: trunk/src/mainboard/tyan/s2885/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2885/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/tyan/s2885/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -27,7 +27,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "TYAN "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "S2885 "; struct mp_config_table *mc; Modified: trunk/src/mainboard/tyan/s2891/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/tyan/s2891/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -27,7 +27,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "TYAN "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "S2891 "; struct mp_config_table *mc; unsigned sbdn; Modified: trunk/src/mainboard/tyan/s2892/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/tyan/s2892/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -27,7 +27,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "TYAN "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "S2892 "; struct mp_config_table *mc; unsigned sbdn; Modified: trunk/src/mainboard/tyan/s2895/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/tyan/s2895/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "TYAN "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "S2895 "; struct mp_config_table *mc; unsigned sbdn; Modified: trunk/src/mainboard/tyan/s2912/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/get_bus_conf.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/tyan/s2912/get_bus_conf.c Fri Apr 16 02:31:44 2010 (r5448) @@ -27,9 +27,7 @@ #if CONFIG_LOGICAL_CPUS==1 #include <cpu/amd/multicore.h> #endif - #include <cpu/amd/amdk8_sysconf.h> - #include <stdlib.h> #include "mb_sysconf.h" @@ -37,8 +35,11 @@ struct mb_sysconf_t mb_sysconf; unsigned pci1234x[] = -{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not - //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail +{ + // Here you only need to set value in pci1234 for HT-IO that could be + // installed or not. + // You may need to preset pci1234 for HTIO board, please refer to + // src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail 0x0000ff0, 0x0000ff0, 0x0000ff0, @@ -49,7 +50,9 @@ // 0x0000ff0 }; unsigned hcdnx[] = -{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most +{ + // HT Chain device num, actually it is unit id base of every ht device + // in chain, assume every chain only have 4 ht device at most 0x20202020, 0x20202020, 0x20202020, @@ -60,39 +63,10 @@ // 0x20202020, }; - - - static unsigned get_bus_conf_done = 0; -static unsigned get_hcid(unsigned i) -{ - unsigned id = 0; - - unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff; - - unsigned devn = sysconf.hcdn[i] & 0xff; - - device_t dev; - - dev = dev_find_slot(busn, PCI_DEVFN(devn,0)); - - switch (dev->device) { - case 0x0369: //IO55 - id = 4; - break; - } - - // we may need more way to find out hcid: subsystem id? GPIO read ? - - // we need use id for 1. bus num, 2. mptable, 3. acpi table - - return id; -} - void get_bus_conf(void) { - unsigned apicid_base; struct mb_sysconf_t *m; @@ -122,24 +96,22 @@ m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff; - /* MCP55 */ - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0)); - if (dev) { - m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); - } + /* MCP55 */ + dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x06,0)); + if (dev) { + m->bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sysconf.sbdn + 0x06); + } - for(i=2; i<8;i++) { - dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); - if (dev) { - m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 ); - } + for(i=2; i<8;i++) { + dev = dev_find_slot(m->bus_mcp55[0], PCI_DEVFN(sysconf.sbdn + 0x0a + i - 2 , 0)); + if (dev) { + m->bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); + } else { + printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_mcp55[0], sysconf.sbdn + 0x0a + i - 2 ); } + } for(i=0; i< sysconf.hc_possible_num; i++) { if(!(sysconf.pci1234[i] & 0x1) ) continue; @@ -160,5 +132,5 @@ apicid_base = CONFIG_MAX_PHYSICAL_CPUS; #endif m->apicid_mcp55 = apicid_base+0; - } + Modified: trunk/src/mainboard/tyan/s2912/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/tyan/s2912/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "TYAN "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "S2895 "; struct mp_config_table *mc; struct mb_sysconf_t *m; Modified: trunk/src/mainboard/tyan/s2912_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/tyan/s2912_fam10/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -34,7 +34,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "TYAN "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "S2895 "; struct mp_config_table *mc; struct mb_sysconf_t *m; Modified: trunk/src/mainboard/tyan/s4880/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/tyan/s4880/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -44,7 +44,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "TYAN "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "S4880 "; struct mp_config_table *mc; Modified: trunk/src/mainboard/tyan/s4882/mptable.c ============================================================================== --- trunk/src/mainboard/tyan/s4882/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/tyan/s4882/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -45,7 +45,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "TYAN "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "S4882 "; struct mp_config_table *mc; Modified: trunk/src/mainboard/via/epia-n/mptable.c ============================================================================== --- trunk/src/mainboard/via/epia-n/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/via/epia-n/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -9,7 +9,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "LNXI "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "P4DPE "; struct mp_config_table *mc; Modified: trunk/src/mainboard/via/pc2500e/mptable.c ============================================================================== --- trunk/src/mainboard/via/pc2500e/mptable.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/mainboard/via/pc2500e/mptable.c Fri Apr 16 02:31:44 2010 (r5448) @@ -35,7 +35,7 @@ static void *smp_write_config_table(void *v) { static const char sig[4] = "PCMP"; - static const char oem[8] = "VIA "; + static const char oem[8] = "COREBOOT"; static const char productid[12] = "PC2500 "; struct mp_config_table *mc; Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct_d.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/northbridge/amd/amdmct/mct/mct_d.c Fri Apr 16 02:31:44 2010 (r5448) @@ -476,7 +476,7 @@ } } - +#ifdef UNUSED_CODE static void ResetNBECCstat_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) { @@ -503,7 +503,7 @@ } } } - +#endif static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) @@ -3337,7 +3337,7 @@ } - +#ifdef UNUSED_CODE static void SetCKETriState(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) { @@ -3377,7 +3377,7 @@ Set_NB32_index_wait(dev, index_reg, index, val); } - +#endif static void SetODTTriState(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct) @@ -3856,7 +3856,7 @@ } } - +#ifdef UNUSED_CODE static void mct_SetupSync_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat) { @@ -3878,6 +3878,7 @@ Set_NB32(dev, 0x78, val); } } +#endif static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) { Modified: trunk/src/northbridge/amd/amdmct/mct/mct_d_gcc.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/mct/mct_d_gcc.h Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/northbridge/amd/amdmct/mct/mct_d_gcc.h Fri Apr 16 02:31:44 2010 (r5448) @@ -161,7 +161,7 @@ return value; } - +#ifdef UNUSED_CODE static u8 read8_fs(u32 addr_lo) { u8 byte; @@ -173,7 +173,7 @@ ); return byte; } - +#endif static void FlushDQSTestPattern_L9(u32 addr_lo) { @@ -369,6 +369,7 @@ } +#ifdef UNUSED_CODE static void oemSet_NB32(u32 addr, u32 val, u8 *valid) { } @@ -379,6 +380,7 @@ *valid = 0; return 0xffffffff; } +#endif static u8 oemNodePresent_D(u8 Node, u8 *ret) Modified: trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c ============================================================================== --- trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c Fri Apr 16 02:31:44 2010 (r5448) @@ -233,10 +233,12 @@ pDCTstat->PresetmaxFreq = 400; } - +#ifdef UNUSED_CODE static void mctAdjustAutoCycTmg(void) { } +#endif + static void mctAdjustAutoCycTmg_D(void) { @@ -292,10 +294,11 @@ { } - +#ifdef UNUSED_CODE static void mctInitMemGPIOs_A(void) { } +#endif static void mctInitMemGPIOs_A_D(void) @@ -308,9 +311,12 @@ } +#ifdef UNUSED_CODE static void mctWarmReset(void) { } +#endif + static void mctWarmReset_D(void) { Modified: trunk/src/northbridge/intel/i3100/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i3100/raminit.h Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/northbridge/intel/i3100/raminit.h Fri Apr 16 02:31:44 2010 (r5448) @@ -30,4 +30,6 @@ u16 channel1[DIMM_SOCKETS]; }; +void sdram_initialize(int controllers, const struct mem_controller *ctrl); + #endif Modified: trunk/src/superio/ite/it8712f/it8712f.h ============================================================================== --- trunk/src/superio/ite/it8712f/it8712f.h Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/superio/ite/it8712f/it8712f.h Fri Apr 16 02:31:44 2010 (r5448) @@ -32,3 +32,10 @@ #define IT8712F_MIDI 0x08 /* MIDI port */ #define IT8712F_GAME 0x09 /* GAME port */ #define IT8712F_IR 0x0a /* Consumer IR */ + +#ifndef __ROMCC__ +void it8712f_kill_watchdog(void); +void it8712f_enable_serial(device_t dev, unsigned iobase); +void it8712f_24mhz_clkin(void) +void it8712f_enable_3vsbsw(void) +#endif Modified: trunk/src/superio/ite/it8712f/it8712f_early_serial.c ============================================================================== --- trunk/src/superio/ite/it8712f/it8712f_early_serial.c Fri Apr 16 01:01:59 2010 (r5447) +++ trunk/src/superio/ite/it8712f/it8712f_early_serial.c Fri Apr 16 02:31:44 2010 (r5448) @@ -66,7 +66,7 @@ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); } -static void it8712f_24mhz_clkin(void) +void it8712f_24mhz_clkin(void) { it8712f_enter_conf(); @@ -76,7 +76,7 @@ it8712f_exit_conf(); } -static void it8712f_enable_3vsbsw(void) +void it8712f_enable_3vsbsw(void) { /* We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2! @@ -102,7 +102,7 @@ } /* Enable the peripheral devices on the IT8712F Super I/O chip. */ -static void it8712f_enable_serial(device_t dev, unsigned iobase) +void it8712f_enable_serial(device_t dev, unsigned iobase) { /* (1) Enter the configuration state (MB PnP mode). */

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[commit] r5447 - in trunk/src: mainboard/amd/mahogany_fam10 mainboard/amd/serengeti_cheetah_fam10 mainboard/asus/a8v-e_se mainboard/msi/ms9282 mainboard/msi/ms9652_fam10 mainboard/supermicro/h8dmr_...
by repository service 15 Apr '10

15 Apr '10

Author: stepan Date: Fri Apr 16 01:01:59 2010 New Revision: 5447 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5447 Log: remove more warnings. move ROOT_COMPLEX selection to fam10 Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/amd/mahogany_fam10/Kconfig trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/msi/ms9652_fam10/Kconfig trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig trunk/src/mainboard/tyan/s2912_fam10/Kconfig trunk/src/northbridge/amd/amdfam10/Kconfig trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c trunk/src/northbridge/amd/amdfam10/northbridge.c trunk/src/northbridge/amd/lx/northbridge.c trunk/src/northbridge/amd/lx/northbridge.h trunk/src/northbridge/amd/lx/raminit.h trunk/src/northbridge/via/cn400/northbridge.c trunk/src/northbridge/via/cn400/vga.c trunk/src/southbridge/amd/rs690/rs690_gfx.c trunk/src/southbridge/amd/rs780/rs780_gfx.c Modified: trunk/src/mainboard/amd/mahogany_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/Kconfig Thu Apr 15 16:55:01 2010 (r5446) +++ trunk/src/mainboard/amd/mahogany_fam10/Kconfig Fri Apr 16 01:01:59 2010 (r5447) @@ -3,7 +3,6 @@ select ARCH_X86 select CPU_AMD_SOCKET_AM2R2 select NORTHBRIDGE_AMD_AMDFAM10 - select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX select SOUTHBRIDGE_AMD_RS780 select SOUTHBRIDGE_AMD_SB700 select SUPERIO_ITE_IT8718F Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig Thu Apr 15 16:55:01 2010 (r5446) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig Fri Apr 16 01:01:59 2010 (r5447) @@ -3,7 +3,6 @@ select ARCH_X86 select CPU_AMD_SOCKET_F_1207 select NORTHBRIDGE_AMD_AMDFAM10 - select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8132 select SUPERIO_WINBOND_W83627HF Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Thu Apr 15 16:55:01 2010 (r5446) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Fri Apr 16 01:01:59 2010 (r5447) @@ -67,10 +67,6 @@ #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC) -static void memreset_setup(void) -{ -} - static void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -80,11 +76,11 @@ return smbus_read_byte(device, address); } -void activate_spd_rom(const struct mem_controller *ctrl) +static void activate_spd_rom(const struct mem_controller *ctrl) { } -void soft_reset(void) +static void soft_reset(void) { uint8_t tmp; @@ -247,7 +243,6 @@ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); - memreset_setup(); sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); } Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Thu Apr 15 16:55:01 2010 (r5446) +++ trunk/src/mainboard/msi/ms9282/romstage.c Fri Apr 16 01:01:59 2010 (r5447) @@ -120,8 +120,6 @@ #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" - - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" @@ -151,12 +149,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - // Node 0 - RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6, - RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7, - // node 1 - RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6, - RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7, + // Node 0 + RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6, + RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7, + // node 1 + RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6, + RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7, }; unsigned bsp_apicid = 0; @@ -181,18 +179,18 @@ bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } - w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - uart_init(); - console_init(); + w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + uart_init(); + console_init(); - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); - setup_ms9282_resource_map(); + setup_ms9282_resource_map(); - setup_coherent_ht_domain(); + setup_coherent_ht_domain(); - wait_all_core0_started(); + wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/Kconfig Thu Apr 15 16:55:01 2010 (r5446) +++ trunk/src/mainboard/msi/ms9652_fam10/Kconfig Fri Apr 16 01:01:59 2010 (r5447) @@ -3,7 +3,6 @@ select ARCH_X86 select CPU_AMD_SOCKET_F_1207 select NORTHBRIDGE_AMD_AMDFAM10 - select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 select SUPERIO_WINBOND_W83627EHG select HAVE_BUS_CONFIG Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig Thu Apr 15 16:55:01 2010 (r5446) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig Fri Apr 16 01:01:59 2010 (r5447) @@ -3,7 +3,6 @@ select ARCH_X86 select CPU_AMD_SOCKET_F_1207 select NORTHBRIDGE_AMD_AMDFAM10 - select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG Modified: trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig Thu Apr 15 16:55:01 2010 (r5446) +++ trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig Fri Apr 16 01:01:59 2010 (r5447) @@ -3,7 +3,6 @@ select ARCH_X86 select CPU_AMD_SOCKET_F_1207 select NORTHBRIDGE_AMD_AMDFAM10 - select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8132 select SOUTHBRIDGE_NVIDIA_MCP55 select SUPERIO_WINBOND_W83627HF Modified: trunk/src/mainboard/tyan/s2912_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/Kconfig Thu Apr 15 16:55:01 2010 (r5446) +++ trunk/src/mainboard/tyan/s2912_fam10/Kconfig Fri Apr 16 01:01:59 2010 (r5447) @@ -3,7 +3,6 @@ select ARCH_X86 select CPU_AMD_SOCKET_F_1207 select NORTHBRIDGE_AMD_AMDFAM10 - select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_MCP55 select SUPERIO_WINBOND_W83627HF select HAVE_BUS_CONFIG Modified: trunk/src/northbridge/amd/amdfam10/Kconfig ============================================================================== --- trunk/src/northbridge/amd/amdfam10/Kconfig Thu Apr 15 16:55:01 2010 (r5446) +++ trunk/src/northbridge/amd/amdfam10/Kconfig Fri Apr 16 01:01:59 2010 (r5447) @@ -21,6 +21,7 @@ bool select HAVE_HIGH_TABLES select HYPERTRANSPORT_PLUGIN_SUPPORT + select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX config AGP_APERTURE_SIZE hex Modified: trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c Thu Apr 15 16:55:01 2010 (r5446) +++ trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c Fri Apr 16 01:01:59 2010 (r5447) @@ -152,7 +152,7 @@ return sel_m; } - +#ifdef UNUSED_CODE static void set_DctSelHiEn(u32 i, u32 val) { device_t dev; @@ -168,6 +168,7 @@ pci_write_config32(dev, DRAM_CTRL_SEL_LOW, dcs_lo); } +#endif static u32 get_DctSelHiEn(u32 i) { @@ -200,6 +201,7 @@ } +#ifdef UNUSED_CODE static u32 get_DctSelBaseOffset(u32 i) { device_t dev; @@ -215,6 +217,8 @@ sel_off_m = dcs_hi>>(20+DCSH_DctSelBaseOffset_47_26_SHIFT-26); return sel_off_m; } +#endif + #if CONFIG_AMDMCT == 0 static u32 get_one_DCT(struct mem_info *meminfo) @@ -231,9 +235,8 @@ return one_DCT; } -#endif #if CONFIG_HW_MEM_HOLE_SIZEK != 0 - +// See that other copy in northbridge.c static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes) { u32 ii; @@ -313,7 +316,8 @@ return carry_over; } -#endif +#endif +#endif // CONFIG_AMDMCT #if CONFIG_EXT_CONF_SUPPORT Modified: trunk/src/northbridge/amd/amdfam10/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/northbridge.c Thu Apr 15 16:55:01 2010 (r5446) +++ trunk/src/northbridge/amd/amdfam10/northbridge.c Fri Apr 16 01:01:59 2010 (r5447) @@ -795,7 +795,8 @@ return mem_hole; } - +// WHY this check? CONFIG_AMDMCT is enabled on all Fam10 boards. +// Does it make sense not to? #if CONFIG_AMDMCT == 0 static void disable_hoist_memory(unsigned long hole_startk, int i) { Modified: trunk/src/northbridge/amd/lx/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/lx/northbridge.c Thu Apr 15 16:55:01 2010 (r5446) +++ trunk/src/northbridge/amd/lx/northbridge.c Fri Apr 16 01:01:59 2010 (r5447) @@ -77,9 +77,7 @@ extern void graphics_init(void); extern void cpubug(void); extern void chipsetinit(void); -extern uint32_t get_systop(void); -void northbridge_init_early(void); void setup_realmode_idt(void); void do_vsmbios(void); Modified: trunk/src/northbridge/amd/lx/northbridge.h ============================================================================== --- trunk/src/northbridge/amd/lx/northbridge.h Thu Apr 15 16:55:01 2010 (r5446) +++ trunk/src/northbridge/amd/lx/northbridge.h Fri Apr 16 01:01:59 2010 (r5447) @@ -17,11 +17,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <cpu/amd/lxdef.h> #ifndef NORTHBRIDGE_AMD_LX_H #define NORTHBRIDGE_AMD_LX_H -extern unsigned int lx_scan_root_bus(device_t root, unsigned int max); +#include <cpu/amd/lxdef.h> + +/* northbridge.c */ +unsigned int lx_scan_root_bus(device_t root, unsigned int max); int sizeram(void); -#endif /* NORTHBRIDGE_AMD_LX_H */ +/* northbridgeinit.c */ +void northbridge_init_early(void); +uint32_t get_systop(void); +#endif Modified: trunk/src/northbridge/amd/lx/raminit.h ============================================================================== --- trunk/src/northbridge/amd/lx/raminit.h Thu Apr 15 16:55:01 2010 (r5446) +++ trunk/src/northbridge/amd/lx/raminit.h Fri Apr 16 01:01:59 2010 (r5447) @@ -27,4 +27,6 @@ uint16_t channel0[DIMM_SOCKETS]; }; -#endif /* RAMINIT_H */ +void sdram_initialize(int controllers, const struct mem_controller *ctrl); + +#endif Modified: trunk/src/northbridge/via/cn400/northbridge.c ============================================================================== --- trunk/src/northbridge/via/cn400/northbridge.c Thu Apr 15 16:55:01 2010 (r5446) +++ trunk/src/northbridge/via/cn400/northbridge.c Fri Apr 16 01:01:59 2010 (r5447) @@ -46,8 +46,8 @@ vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_CN400_VLINK, 0); - /* Setup Low Memory Top */ - /* 0x47 == HA(32:25) */ + /* Setup Low Memory Top */ + /* 0x47 == HA(32:25) */ /* 0x84/85 == HA(31:20) << 4 | DRAM Granularity */ ranks = pci_read_config8(dev, 0x47); reg16 = (((u16)(ranks - 1) << 9) & 0xFFF0) | 0x01F0; @@ -175,6 +175,7 @@ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } +#ifdef UNUSED_CODE static void ram_reservation(device_t dev, unsigned long index, unsigned long base, unsigned long size) { @@ -188,6 +189,7 @@ res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } +#endif static void tolm_test(void *gp, struct device *dev, struct resource *new) { @@ -278,7 +280,7 @@ return max; } -static const struct device_operations pci_domain_ops = { +static struct device_operations pci_domain_ops = { .read_resources = cn400_domain_read_resources, .set_resources = cn400_domain_set_resources, .enable_resources = enable_childrens_resources, @@ -295,7 +297,7 @@ { } -static const struct device_operations cpu_bus_ops = { +static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, .set_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop, @@ -305,7 +307,7 @@ static void enable_dev(struct device *dev) { - printk(BIOS_SPEW, "In cn400 enable_dev for device %s.\n", dev_path(dev)); + printk(BIOS_SPEW, "CN400: enable_dev for device %s.\n", dev_path(dev)); /* Set the operations if it is a special bus type. */ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { Modified: trunk/src/northbridge/via/cn400/vga.c ============================================================================== --- trunk/src/northbridge/via/cn400/vga.c Thu Apr 15 16:55:01 2010 (r5446) +++ trunk/src/northbridge/via/cn400/vga.c Fri Apr 16 01:01:59 2010 (r5447) @@ -58,7 +58,7 @@ * This is for compatibility with the VGA ROM's BIOS callbacks. */ //memcpy(0xf0000, (0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000); - memcpy(0xf0000, temp, 0x10000); + memcpy((void *)0xf0000, (void *)temp, 0x10000); printk(BIOS_DEBUG, "Initializing VGA\n"); /* Set memory rate to 200 MHz. */ @@ -103,7 +103,7 @@ outb(reg8, SR_DATA); /* Clear the BOCHS BIOS out of memory, so it doesn't confuse Linux. */ - memset(0xf0000, 0, 0x10000); + memset((void *)0xf0000, 0, 0x10000); #ifdef DEBUG_CN400 printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev)); Modified: trunk/src/southbridge/amd/rs690/rs690_gfx.c ============================================================================== --- trunk/src/southbridge/amd/rs690/rs690_gfx.c Thu Apr 15 16:55:01 2010 (r5446) +++ trunk/src/southbridge/amd/rs690/rs690_gfx.c Fri Apr 16 01:01:59 2010 (r5447) @@ -34,7 +34,7 @@ #define CLK_CNTL_INDEX 0x8 #define CLK_CNTL_DATA 0xC -#if 0 +#ifdef UNUSED_CODE static u32 clkind_read(device_t dev, u32 index) { u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF; Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_gfx.c Thu Apr 15 16:55:01 2010 (r5446) +++ trunk/src/southbridge/amd/rs780/rs780_gfx.c Fri Apr 16 01:01:59 2010 (r5447) @@ -39,12 +39,17 @@ void set_pcie_reset(void); void set_pcie_dereset(void); +/* Trust the original resource allocation. Don't do it again. */ +#undef DONT_TRUST_RESOURCE_ALLOCATION +//#define DONT_TRUST_RESOURCE_ALLOCATION + #define CLK_CNTL_INDEX 0x8 #define CLK_CNTL_DATA 0xC /* The Integrated Info Table. */ ATOM_INTEGRATED_SYSTEM_INFO_V2 vgainfo; +#ifdef UNUSED_CODE static u32 clkind_read(device_t dev, u32 index) { u32 gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF; @@ -52,6 +57,7 @@ *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index & 0x7F; return *(u32*)(gfx_bar2+CLK_CNTL_DATA); } +#endif static void clkind_write(device_t dev, u32 index, u32 data) { @@ -174,6 +180,7 @@ return n; } +#ifdef DONT_TRUST_RESOURCE_ALLOCATION static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) { CIM_STATUS Status = CIM_UNSUPPORTED; @@ -288,6 +295,7 @@ pci_write_config32(k8_f1, 0x80+MmioReg*8, Base); } } +#endif static void internal_gfx_pci_dev_init(struct device *dev) { @@ -490,7 +498,7 @@ pci_write_config8(dev, 0x4, temp8); } -#if 0 /* Trust the original resource allocation. Don't do it again. */ +#ifdef DONT_TRUST_RESOURCE_ALLOCATION /* NB_SetupMGMMIO. */ /* clear MMIO and CreativeMMIO. */

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coreboot April 2010