[commit] r5447 - in trunk/src: mainboard/amd/mahogany_fam10 mainboard/amd/serengeti_cheetah_fam10 mainboard/asus/a8v-e_se mainboard/msi/ms9282 mainboard/msi/ms9652_fam10 mainboard/supermicro/h8dmr_...

[repository service]

Author: stepan
Date: Fri Apr 16 01:01:59 2010
New Revision: 5447
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5447

Log:
remove more warnings. move ROOT_COMPLEX selection to fam10

Signed-off-by: Stefan Reinauer 
Acked-by: Stefan Reinauer

Modified:
   trunk/src/mainboard/amd/mahogany_fam10/Kconfig
   trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
   trunk/src/mainboard/asus/a8v-e_se/romstage.c
   trunk/src/mainboard/msi/ms9282/romstage.c
   trunk/src/mainboard/msi/ms9652_fam10/Kconfig
   trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig
   trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig
   trunk/src/mainboard/tyan/s2912_fam10/Kconfig
   trunk/src/northbridge/amd/amdfam10/Kconfig
   trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c
   trunk/src/northbridge/amd/amdfam10/northbridge.c
   trunk/src/northbridge/amd/lx/northbridge.c
   trunk/src/northbridge/amd/lx/northbridge.h
   trunk/src/northbridge/amd/lx/raminit.h
   trunk/src/northbridge/via/cn400/northbridge.c
   trunk/src/northbridge/via/cn400/vga.c
   trunk/src/southbridge/amd/rs690/rs690_gfx.c
   trunk/src/southbridge/amd/rs780/rs780_gfx.c

Modified: trunk/src/mainboard/amd/mahogany_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/Kconfig	Thu Apr 15 16:55:01 2010	(r5446)
+++ trunk/src/mainboard/amd/mahogany_fam10/Kconfig	Fri Apr 16 01:01:59 2010	(r5447)
@@ -3,7 +3,6 @@
    select ARCH_X86
    select CPU_AMD_SOCKET_AM2R2
    select NORTHBRIDGE_AMD_AMDFAM10
-	select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
    select SOUTHBRIDGE_AMD_RS780
    select SOUTHBRIDGE_AMD_SB700
    select SUPERIO_ITE_IT8718F

Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig	Thu Apr 15 16:55:01 2010	(r5446)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/Kconfig	Fri Apr 16 01:01:59 2010	(r5447)
@@ -3,7 +3,6 @@
    select ARCH_X86
    select CPU_AMD_SOCKET_F_1207
    select NORTHBRIDGE_AMD_AMDFAM10
-	select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
    select SOUTHBRIDGE_AMD_AMD8111
    select SOUTHBRIDGE_AMD_AMD8132
    select SUPERIO_WINBOND_W83627HF

Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_se/romstage.c	Thu Apr 15 16:55:01 2010	(r5446)
+++ trunk/src/mainboard/asus/a8v-e_se/romstage.c	Fri Apr 16 01:01:59 2010	(r5447)
@@ -67,10 +67,6 @@
 #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
 #define RTC_DEV PNP_DEV(0x2e, W83627EHG_RTC)

-static void memreset_setup(void)
-{
-}
-
 static void memreset(int controllers, const struct mem_controller *ctrl)
 {
 }
@@ -80,11 +76,11 @@
    return smbus_read_byte(device, address);
 }

-void activate_spd_rom(const struct mem_controller *ctrl)
+static void activate_spd_rom(const struct mem_controller *ctrl)
 {
 }

-void soft_reset(void)
+static void soft_reset(void)
 {
    uint8_t tmp;

@@ -247,7 +243,6 @@
    fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);

enable_smbus();
-	memreset_setup();
    sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
    post_cache_as_ram();
 }

Modified: trunk/src/mainboard/msi/ms9282/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/romstage.c	Thu Apr 15 16:55:01 2010	(r5446)
+++ trunk/src/mainboard/msi/ms9282/romstage.c	Fri Apr 16 01:01:59 2010	(r5447)
@@ -120,8 +120,6 @@

#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"

-
-
 #include "cpu/amd/car/post_cache_as_ram.c"

#include "cpu/amd/model_fxx/init_cpus.c"
@@ -151,12 +149,12 @@
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
    static const uint16_t spd_addr[] = {
-			// Node 0
-			RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
-			RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
-			// node 1
-			RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
-			RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
+		// Node 0
+		RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6,
+		RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7,
+		// node 1
+		RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6,
+		RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7,
    };

unsigned bsp_apicid = 0;
@@ -181,18 +179,18 @@
                bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
         }

-       w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-        uart_init();
-        console_init();
+	w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+	uart_init();
+	console_init();

-       /* Halt if there was a built in self test failure */
-       report_bist_failure(bist);
+	/* Halt if there was a built in self test failure */
+	report_bist_failure(bist);

-        setup_ms9282_resource_map();
+	setup_ms9282_resource_map();

-       setup_coherent_ht_domain();
+	setup_coherent_ht_domain();

-        wait_all_core0_started();
+	wait_all_core0_started();

#if CONFIG_LOGICAL_CPUS==1
         // It is said that we should start core1 after all core0 launched

Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/Kconfig	Thu Apr 15 16:55:01 2010	(r5446)
+++ trunk/src/mainboard/msi/ms9652_fam10/Kconfig	Fri Apr 16 01:01:59 2010	(r5447)
@@ -3,7 +3,6 @@
    select ARCH_X86
    select CPU_AMD_SOCKET_F_1207
    select NORTHBRIDGE_AMD_AMDFAM10
-	select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
    select SOUTHBRIDGE_NVIDIA_MCP55
    select SUPERIO_WINBOND_W83627EHG
    select HAVE_BUS_CONFIG

Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig	Thu Apr 15 16:55:01 2010	(r5446)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/Kconfig	Fri Apr 16 01:01:59 2010	(r5447)
@@ -3,7 +3,6 @@
    select ARCH_X86
    select CPU_AMD_SOCKET_F_1207
    select NORTHBRIDGE_AMD_AMDFAM10
-	select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
    select SOUTHBRIDGE_NVIDIA_MCP55
    select SUPERIO_WINBOND_W83627HF
    select HAVE_BUS_CONFIG

Modified: trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig	Thu Apr 15 16:55:01 2010	(r5446)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/Kconfig	Fri Apr 16 01:01:59 2010	(r5447)
@@ -3,7 +3,6 @@
    select ARCH_X86
    select CPU_AMD_SOCKET_F_1207
    select NORTHBRIDGE_AMD_AMDFAM10
-	select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
    select SOUTHBRIDGE_AMD_AMD8132
    select SOUTHBRIDGE_NVIDIA_MCP55
    select SUPERIO_WINBOND_W83627HF

Modified: trunk/src/mainboard/tyan/s2912_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/Kconfig	Thu Apr 15 16:55:01 2010	(r5446)
+++ trunk/src/mainboard/tyan/s2912_fam10/Kconfig	Fri Apr 16 01:01:59 2010	(r5447)
@@ -3,7 +3,6 @@
    select ARCH_X86
    select CPU_AMD_SOCKET_F_1207
    select NORTHBRIDGE_AMD_AMDFAM10
-	select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX
    select SOUTHBRIDGE_NVIDIA_MCP55
    select SUPERIO_WINBOND_W83627HF
    select HAVE_BUS_CONFIG

Modified: trunk/src/northbridge/amd/amdfam10/Kconfig
==============================================================================
--- trunk/src/northbridge/amd/amdfam10/Kconfig	Thu Apr 15 16:55:01 2010	(r5446)
+++ trunk/src/northbridge/amd/amdfam10/Kconfig	Fri Apr 16 01:01:59 2010	(r5447)
@@ -21,6 +21,7 @@
    bool
    select HAVE_HIGH_TABLES
    select HYPERTRANSPORT_PLUGIN_SUPPORT
+	select NORTHBRIDGE_AMD_AMDFAM10_ROOT_COMPLEX

config AGP_APERTURE_SIZE
    hex

Modified: trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c
==============================================================================
--- trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c	Thu Apr 15 16:55:01 2010	(r5446)
+++ trunk/src/northbridge/amd/amdfam10/amdfam10_conf.c	Fri Apr 16 01:01:59 2010	(r5447)
@@ -152,7 +152,7 @@
    return sel_m;
 }

-
+#ifdef UNUSED_CODE
 static void set_DctSelHiEn(u32 i, u32 val)
 {
    device_t dev;
@@ -168,6 +168,7 @@
    pci_write_config32(dev, DRAM_CTRL_SEL_LOW, dcs_lo);

}
+#endif

static u32 get_DctSelHiEn(u32 i)
 {
@@ -200,6 +201,7 @@

}

+#ifdef UNUSED_CODE
 static u32 get_DctSelBaseOffset(u32 i)
 {
    device_t dev;
@@ -215,6 +217,8 @@
    sel_off_m = dcs_hi>>(20+DCSH_DctSelBaseOffset_47_26_SHIFT-26);
    return sel_off_m;
 }
+#endif
+
 #if CONFIG_AMDMCT == 0

static u32 get_one_DCT(struct mem_info *meminfo)
@@ -231,9 +235,8 @@

return one_DCT;
 }
-#endif
 #if CONFIG_HW_MEM_HOLE_SIZEK != 0
-
+// See that other copy in northbridge.c
 static u32 hoist_memory(u32 hole_startk, u32 i, u32 one_DCT, u32 nodes)
 {
    u32 ii;
@@ -313,7 +316,8 @@

return carry_over;
 }
-#endif
+#endif 
+#endif // CONFIG_AMDMCT

#if CONFIG_EXT_CONF_SUPPORT

Modified: trunk/src/northbridge/amd/amdfam10/northbridge.c
==============================================================================
--- trunk/src/northbridge/amd/amdfam10/northbridge.c	Thu Apr 15 16:55:01 2010	(r5446)
+++ trunk/src/northbridge/amd/amdfam10/northbridge.c	Fri Apr 16 01:01:59 2010	(r5447)
@@ -795,7 +795,8 @@
    	return mem_hole;
 }

-
+// WHY this check? CONFIG_AMDMCT is enabled on all Fam10 boards.
+// Does it make sense not to?
 #if CONFIG_AMDMCT == 0
 static void disable_hoist_memory(unsigned long hole_startk, int i)
 {

Modified: trunk/src/northbridge/amd/lx/northbridge.c
==============================================================================
--- trunk/src/northbridge/amd/lx/northbridge.c	Thu Apr 15 16:55:01 2010	(r5446)
+++ trunk/src/northbridge/amd/lx/northbridge.c	Fri Apr 16 01:01:59 2010	(r5447)
@@ -77,9 +77,7 @@
 extern void graphics_init(void);
 extern void cpubug(void);
 extern void chipsetinit(void);
-extern uint32_t get_systop(void);

-void northbridge_init_early(void);
 void setup_realmode_idt(void);
 void do_vsmbios(void);

Modified: trunk/src/northbridge/amd/lx/northbridge.h
==============================================================================
--- trunk/src/northbridge/amd/lx/northbridge.h	Thu Apr 15 16:55:01 2010	(r5446)
+++ trunk/src/northbridge/amd/lx/northbridge.h	Fri Apr 16 01:01:59 2010	(r5447)
@@ -17,11 +17,16 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */

-#include <cpu/amd/lxdef.h>
 #ifndef NORTHBRIDGE_AMD_LX_H
 #define NORTHBRIDGE_AMD_LX_H

-extern unsigned int lx_scan_root_bus(device_t root, unsigned int max);
+#include <cpu/amd/lxdef.h>
+
+/* northbridge.c */
+unsigned int lx_scan_root_bus(device_t root, unsigned int max);
 int sizeram(void);

-#endif				/* NORTHBRIDGE_AMD_LX_H */
+/* northbridgeinit.c */
+void northbridge_init_early(void);
+uint32_t get_systop(void);
+#endif

Modified: trunk/src/northbridge/amd/lx/raminit.h
==============================================================================
--- trunk/src/northbridge/amd/lx/raminit.h	Thu Apr 15 16:55:01 2010	(r5446)
+++ trunk/src/northbridge/amd/lx/raminit.h	Fri Apr 16 01:01:59 2010	(r5447)
@@ -27,4 +27,6 @@
    uint16_t channel0[DIMM_SOCKETS];
 };

-#endif				/* RAMINIT_H */
+void sdram_initialize(int controllers, const struct mem_controller *ctrl);
+
+#endif

Modified: trunk/src/northbridge/via/cn400/northbridge.c
==============================================================================
--- trunk/src/northbridge/via/cn400/northbridge.c	Thu Apr 15 16:55:01 2010	(r5446)
+++ trunk/src/northbridge/via/cn400/northbridge.c	Fri Apr 16 01:01:59 2010	(r5447)
@@ -46,8 +46,8 @@
    vlink_dev = dev_find_device(PCI_VENDOR_ID_VIA,
    			    PCI_DEVICE_ID_VIA_CN400_VLINK, 0);
    
-	/* Setup Low Memory Top 						*/
-	/* 0x47 == HA(32:25)						    */
+	/* Setup Low Memory Top */
+	/* 0x47 == HA(32:25)    */
    /* 0x84/85 == HA(31:20) << 4 | DRAM Granularity */
    ranks = pci_read_config8(dev, 0x47);
    reg16 = (((u16)(ranks - 1) << 9) & 0xFFF0) | 0x01F0;
@@ -175,6 +175,7 @@
        IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 }

+#ifdef UNUSED_CODE
 static void ram_reservation(device_t dev, unsigned long index,
    		 unsigned long base, unsigned long size)
 {
@@ -188,6 +189,7 @@
    res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
    	     IORESOURCE_STORED | IORESOURCE_ASSIGNED;
 }
+#endif

static void tolm_test(void *gp, struct device *dev, struct resource *new)
 {
@@ -278,7 +280,7 @@
    return max;
 }

-static const struct device_operations pci_domain_ops = {
+static struct device_operations pci_domain_ops = {
    .read_resources   = cn400_domain_read_resources,
    .set_resources    = cn400_domain_set_resources,
    .enable_resources = enable_childrens_resources,
@@ -295,7 +297,7 @@
 {
 }

-static const struct device_operations cpu_bus_ops = {
+static struct device_operations cpu_bus_ops = {
    .read_resources   = cpu_bus_noop,
    .set_resources    = cpu_bus_noop,
    .enable_resources = cpu_bus_noop,
@@ -305,7 +307,7 @@

static void enable_dev(struct device *dev)
 {
-	printk(BIOS_SPEW, "In cn400 enable_dev for device %s.\n", dev_path(dev));
+	printk(BIOS_SPEW, "CN400: enable_dev for device %s.\n", dev_path(dev));

/* Set the operations if it is a special bus type. */
    if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {

Modified: trunk/src/northbridge/via/cn400/vga.c
==============================================================================
--- trunk/src/northbridge/via/cn400/vga.c	Thu Apr 15 16:55:01 2010	(r5446)
+++ trunk/src/northbridge/via/cn400/vga.c	Fri Apr 16 01:01:59 2010	(r5447)
@@ -58,7 +58,7 @@
     * This is for compatibility with the VGA ROM's BIOS callbacks.
     */
    //memcpy(0xf0000, (0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000);
-	memcpy(0xf0000, temp, 0x10000);
+	memcpy((void *)0xf0000, (void *)temp, 0x10000);
    printk(BIOS_DEBUG, "Initializing VGA\n");

/* Set memory rate to 200 MHz. */
@@ -103,7 +103,7 @@
    outb(reg8, SR_DATA);

/* Clear the BOCHS BIOS out of memory, so it doesn't confuse Linux. */
-	memset(0xf0000, 0, 0x10000);
+	memset((void *)0xf0000, 0, 0x10000);

#ifdef DEBUG_CN400
    printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev));

Modified: trunk/src/southbridge/amd/rs690/rs690_gfx.c
==============================================================================
--- trunk/src/southbridge/amd/rs690/rs690_gfx.c	Thu Apr 15 16:55:01 2010	(r5446)
+++ trunk/src/southbridge/amd/rs690/rs690_gfx.c	Fri Apr 16 01:01:59 2010	(r5447)
@@ -34,7 +34,7 @@
 #define CLK_CNTL_INDEX	0x8
 #define CLK_CNTL_DATA	0xC

-#if 0
+#ifdef UNUSED_CODE
 static u32 clkind_read(device_t dev, u32 index)
 {
    u32	gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;

Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c
==============================================================================
--- trunk/src/southbridge/amd/rs780/rs780_gfx.c	Thu Apr 15 16:55:01 2010	(r5446)
+++ trunk/src/southbridge/amd/rs780/rs780_gfx.c	Fri Apr 16 01:01:59 2010	(r5447)
@@ -39,12 +39,17 @@
 void set_pcie_reset(void);
 void set_pcie_dereset(void);

+/* Trust the original resource allocation. Don't do it again. */
+#undef DONT_TRUST_RESOURCE_ALLOCATION
+//#define DONT_TRUST_RESOURCE_ALLOCATION
+
 #define CLK_CNTL_INDEX	0x8
 #define CLK_CNTL_DATA	0xC

/* The Integrated Info Table. */
 ATOM_INTEGRATED_SYSTEM_INFO_V2 vgainfo;

+#ifdef UNUSED_CODE
 static u32 clkind_read(device_t dev, u32 index)
 {
    u32	gfx_bar2 = pci_read_config32(dev, 0x18) & ~0xF;
@@ -52,6 +57,7 @@
    *(u32*)(gfx_bar2+CLK_CNTL_INDEX) = index & 0x7F;
    return *(u32*)(gfx_bar2+CLK_CNTL_DATA);
 }
+#endif

static void clkind_write(device_t dev, u32 index, u32 data)
 {
@@ -174,6 +180,7 @@
    return n;
 }

+#ifdef DONT_TRUST_RESOURCE_ALLOCATION
 static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
 {
    CIM_STATUS Status = CIM_UNSUPPORTED;
@@ -288,6 +295,7 @@
    	pci_write_config32(k8_f1, 0x80+MmioReg*8, Base);
    }
 }
+#endif

static void internal_gfx_pci_dev_init(struct device *dev)
 {
@@ -490,7 +498,7 @@
    	pci_write_config8(dev, 0x4, temp8);
    }

-#if 0 /* Trust the original resource allocation. Don't do it again. */
+#ifdef DONT_TRUST_RESOURCE_ALLOCATION
    /* NB_SetupMGMMIO. */

/* clear MMIO and CreativeMMIO. */