coreboot April 2010

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build service results for r5368
by coreboot information 07 Apr '10

07 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5368 to the coreboot repository. This caused the following changes: Change Log: clean up age old via epia target. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of via:epia is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5368&device=epia&vendor=vi… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r5367
by coreboot information 07 Apr '10

07 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5367 to the coreboot repository. This caused the following changes: Change Log: drop the use of function pointers from romcc code. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of via:epia is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5367&device=epia&vendor=vi… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5369 - trunk/src/northbridge/via/vt8601
by repository service 07 Apr '10

07 Apr '10

Author: stepan Date: Wed Apr 7 05:41:39 2010 New Revision: 5369 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5369 Log: it's a long term, give the compiler a chance to breathe .. ;-) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/via/vt8601/raminit.c Modified: trunk/src/northbridge/via/vt8601/raminit.c ============================================================================== --- trunk/src/northbridge/via/vt8601/raminit.c Wed Apr 7 05:40:37 2010 (r5368) +++ trunk/src/northbridge/via/vt8601/raminit.c Wed Apr 7 05:41:39 2010 (r5369) @@ -201,7 +201,8 @@ /* grand total. You have rows+cols addressing, * times of banks, times * width of data in bytes */ /* Width is assumed to be 64 bits == 8 bytes */ - value = (1 << (cols + rows)) * banks * 8; + value = (1 << (cols + rows)); + value *= banks * 8; print_info_hex32(value); print_info(" bytes "); /* Return in 8MB units */

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[commit] r5368 - in trunk/src: . cpu/x86/mtrr mainboard/via/epia mainboard/via/epia-m northbridge/via/vt8601 southbridge/via/vt8231
by repository service 07 Apr '10

07 Apr '10

Author: stepan Date: Wed Apr 7 05:40:37 2010 New Revision: 5368 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5368 Log: clean up age old via epia target. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/Kconfig trunk/src/cpu/x86/mtrr/earlymtrr.c trunk/src/mainboard/via/epia-m/romstage.c trunk/src/mainboard/via/epia/romstage.c trunk/src/northbridge/via/vt8601/raminit.c trunk/src/southbridge/via/vt8231/vt8231.c trunk/src/southbridge/via/vt8231/vt8231_early_serial.c trunk/src/southbridge/via/vt8231/vt8231_early_smbus.c trunk/src/southbridge/via/vt8231/vt8231_lpc.c Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Wed Apr 7 05:11:28 2010 (r5367) +++ trunk/src/Kconfig Wed Apr 7 05:40:37 2010 (r5368) @@ -622,7 +622,8 @@ || NORTHBRIDGE_VIA_VX800 \ || NORTHBRIDGE_VIA_CX700 \ || NORTHBRIDGE_AMD_AMDK8 \ - || NORTHBRIDGE_AMD_AMDFAM10) + || NORTHBRIDGE_AMD_AMDFAM10 \ + || SOUTHBRIDGE_VIA_VT8231) help This option enables additional SMBus (and SPD) debug messages. Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c ============================================================================== --- trunk/src/cpu/x86/mtrr/earlymtrr.c Wed Apr 7 05:11:28 2010 (r5367) +++ trunk/src/cpu/x86/mtrr/earlymtrr.c Wed Apr 7 05:40:37 2010 (r5368) @@ -53,7 +53,7 @@ } #endif -static void cache_lbmem(int type) +static inline void cache_lbmem(int type) { /* Enable caching for 0 - 1MB using variable mtrr */ disable_cache(); @@ -118,7 +118,7 @@ enable_cache(); } -static int early_mtrr_init_detected(void) +static inline int early_mtrr_init_detected(void) { msr_t msr; /* See if MTRR's are enabled. Modified: trunk/src/mainboard/via/epia-m/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m/romstage.c Wed Apr 7 05:11:28 2010 (r5367) +++ trunk/src/mainboard/via/epia-m/romstage.c Wed Apr 7 05:40:37 2010 (r5368) @@ -78,7 +78,6 @@ static void main(unsigned long bist) { - unsigned long x; device_t dev; /* Modified: trunk/src/mainboard/via/epia/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia/romstage.c Wed Apr 7 05:11:28 2010 (r5367) +++ trunk/src/mainboard/via/epia/romstage.c Wed Apr 7 05:40:37 2010 (r5368) @@ -13,7 +13,6 @@ #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/lapic/boot_cpu.c" #include "lib/debug.c" #include "southbridge/via/vt8231/vt8231_early_smbus.c" #include "southbridge/via/vt8231/vt8231_early_serial.c" @@ -76,10 +75,8 @@ pci_write_config8(dev, 0x63, shadowreg); } -static void main(unsigned long bist) +void main(unsigned long bist) { - unsigned long x; - if (bist == 0) { early_mtrr_init(); } Modified: trunk/src/northbridge/via/vt8601/raminit.c ============================================================================== --- trunk/src/northbridge/via/vt8601/raminit.c Wed Apr 7 05:11:28 2010 (r5367) +++ trunk/src/northbridge/via/vt8601/raminit.c Wed Apr 7 05:40:37 2010 (r5368) @@ -47,7 +47,7 @@ #define DIMM_CL2 0 #endif -void dimms_read(unsigned long x) +static void dimms_read(unsigned long x) { uint8_t c; unsigned long eax; @@ -59,7 +59,7 @@ } } -void dimms_write(int x) +static void dimms_write(int x) { uint8_t c; unsigned long eax = x; @@ -69,7 +69,8 @@ } } -void dumpnorth(device_t north) +#ifdef CONFIG_DEBUG_RAM_SETUP +static void dumpnorth(device_t north) { unsigned int r, c; for (r = 0;; r += 16) { @@ -84,11 +85,11 @@ break; } } +#endif static void sdram_set_registers(const struct mem_controller *ctrl) { device_t north = (device_t) PCI_DEV(0, 0, 0); - uint8_t c, r; print_err("vt8601 init starting\n"); print_debug_hex32(north); @@ -175,7 +176,7 @@ * module. This is just a very early first cut at sizing. */ /* we may run out of registers ... */ - unsigned int banks, rows, cols, reg; + unsigned int banks, rows, cols; unsigned int value = 0; /* unsigned int module = ((0x50 + slot) << 1) + 1; */ unsigned int module = 0x50 + slot; @@ -213,9 +214,9 @@ } print_info("\n"); return value; - } +#if 0 static int spd_num_chips(unsigned char slot) { unsigned int module = 0x50 + slot; @@ -226,6 +227,7 @@ width = 8; return 64 / width; } +#endif static void sdram_set_spd_registers(const struct mem_controller *ctrl) { @@ -275,7 +277,6 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl) { - unsigned char i; static const uint8_t ramregs[] = { 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 }; Modified: trunk/src/southbridge/via/vt8231/vt8231.c ============================================================================== --- trunk/src/southbridge/via/vt8231/vt8231.c Wed Apr 7 05:11:28 2010 (r5367) +++ trunk/src/southbridge/via/vt8231/vt8231.c Wed Apr 7 05:40:37 2010 (r5368) @@ -12,11 +12,6 @@ /* Base 8231 controller */ static device_t lpc_dev; -void hard_reset(void) -{ - printk(BIOS_ERR, "NO HARD RESET ON VT8231! FIX ME!\n"); -} - static void keyboard_on(void) { unsigned char regval; Modified: trunk/src/southbridge/via/vt8231/vt8231_early_serial.c ============================================================================== --- trunk/src/southbridge/via/vt8231/vt8231_early_serial.c Wed Apr 7 05:11:28 2010 (r5367) +++ trunk/src/southbridge/via/vt8231/vt8231_early_serial.c Wed Apr 7 05:40:37 2010 (r5368) @@ -31,7 +31,6 @@ static void enable_vt8231_serial(void) { - unsigned long x; uint8_t c; device_t dev; outb(6, 0x80); Modified: trunk/src/southbridge/via/vt8231/vt8231_early_smbus.c ============================================================================== --- trunk/src/southbridge/via/vt8231/vt8231_early_smbus.c Wed Apr 7 05:11:28 2010 (r5367) +++ trunk/src/southbridge/via/vt8231/vt8231_early_smbus.c Wed Apr 7 05:40:37 2010 (r5368) @@ -107,6 +107,7 @@ return loops ? 0 : -3; } +#if 0 void smbus_reset(void) { outb(HOST_RESET, SMBUS_IO_BASE + SMBHSTSTAT); @@ -119,7 +120,9 @@ print_debug_hex8(inb(SMBUS_IO_BASE + SMBHSTSTAT)); print_debug("\n"); } +#endif +#if CONFIG_DEBUG_SMBUS static void smbus_print_error(unsigned char host_status_register) { @@ -142,6 +145,7 @@ print_err("Host Busy\n"); } } +#endif /* * Copied from intel/i82801dbm early smbus code - suggested by rgm. @@ -150,7 +154,6 @@ */ static int smbus_read_byte(unsigned device, unsigned address) { - unsigned char global_control_register; unsigned char global_status_register; unsigned char byte; Modified: trunk/src/southbridge/via/vt8231/vt8231_lpc.c ============================================================================== --- trunk/src/southbridge/via/vt8231/vt8231_lpc.c Wed Apr 7 05:11:28 2010 (r5367) +++ trunk/src/southbridge/via/vt8231/vt8231_lpc.c Wed Apr 7 05:40:37 2010 (r5368) @@ -10,7 +10,6 @@ /* PIRQ init */ -void pci_assign_irqs(unsigned bus, unsigned slot, const unsigned char pIntAtoD[4]); static const unsigned char southbridgeIrqs[4] = { 11, 5, 10, 12 }; static const unsigned char enetIrqs[4] = { 11, 5, 10, 12 }; static const unsigned char slotIrqs[4] = { 5, 10, 12, 11 }; @@ -55,7 +54,6 @@ static void vt8231_init(struct device *dev) { unsigned char enables; - struct southbridge_via_vt8231_config *conf = dev->chip_info; printk(BIOS_DEBUG, "vt8231 init\n"); @@ -130,7 +128,7 @@ rtc_init(0); } -void vt8231_read_resources(device_t dev) +static void vt8231_read_resources(device_t dev) { struct resource *res;

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build service results for r5366
by coreboot information 07 Apr '10

07 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5366 to the coreboot repository. This caused the following changes: Change Log: fix epia-m700 compilation, and remove more warnings. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of via:epia is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5366&device=epia&vendor=vi… Compilation of via:epia-m700 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5367 - trunk/src/mainboard/digitallogic/msm586seg
by repository service 07 Apr '10

07 Apr '10

Author: stepan Date: Wed Apr 7 05:11:28 2010 New Revision: 5367 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5367 Log: drop the use of function pointers from romcc code. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/digitallogic/msm586seg/romstage.c Modified: trunk/src/mainboard/digitallogic/msm586seg/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/romstage.c Wed Apr 7 04:30:57 2010 (r5366) +++ trunk/src/mainboard/digitallogic/msm586seg/romstage.c Wed Apr 7 05:11:28 2010 (r5367) @@ -40,8 +40,6 @@ #include "cpu/amd/sc520/raminit.c" -typedef void (*lj)(void); - struct mem_controller { int i; };

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build service results for r5365
by coreboot information 07 Apr '10

07 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5365 to the coreboot repository. This caused the following changes: Change Log: no duplicate names in cmos.layout. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of via:epia is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5365&device=epia&vendor=vi… Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5365&device=epia-m700&vend… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r5364
by coreboot information 07 Apr '10

07 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5364 to the coreboot repository. This caused the following changes: Change Log: switch some ROMCC boards back to ROMCC. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of via:epia has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5364&device=epia&vendor=vi… Compilation of via:epia-m700 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5364&device=epia-m700&vend… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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Need confirmation if HP nx6310 will work with coreboot
by secretocean＠gmx.de 07 Apr '10

07 Apr '10

Hi, I've got an HP nx6310 notebook with Linux as operating system and I'm thinking of trying coreboot to get rid of the non-free HP BIOS. Though I'm quite confident that the chipset is supported, it'll be nice if someone would confirm that and perhaps give further instructions on how to use coreboot with my mainboard. Notebook: HP nx6310 EY366EA#ABD no extensions at all, except a PCMCIA WLAN card with Atheros chipset BIOS version: F.0E CPU: Intel Celeron M 1,46GHz RAM: 1GB (512MB by default) Graphics card: on board, Intel GMA 945 Sound card: on board, Intel HDA ... (don't know the exact model) Outputs of lspci -tvnn, superiotool -dV and flashrom -V: see text files Hopefully someone can help. I'd love to help making coreboot better but without shooting my mainboard. Thanks! -- GRATIS für alle GMX-Mitglieder: Die maxdome Movie-FLAT! Jetzt freischalten unter http://portal.gmx.net/de/go/maxdome01

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[commit] r5366 - in trunk/src: mainboard/artecgroup/dbe61 mainboard/intel/eagleheights mainboard/intel/xe7501devkit northbridge/via/vx800 southbridge/intel/i82801cx superio/smsc/lpc47b272
by repository service 07 Apr '10

07 Apr '10

Author: stepan Date: Wed Apr 7 04:30:57 2010 New Revision: 5366 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5366 Log: fix epia-m700 compilation, and remove more warnings. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/artecgroup/dbe61/mainboard.c trunk/src/mainboard/intel/eagleheights/acpi_tables.c trunk/src/mainboard/intel/eagleheights/fadt.c trunk/src/mainboard/intel/eagleheights/mainboard.c trunk/src/mainboard/intel/eagleheights/mptable.c trunk/src/mainboard/intel/xe7501devkit/mptable.c trunk/src/northbridge/via/vx800/vx800.h trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c trunk/src/superio/smsc/lpc47b272/superio.c Modified: trunk/src/mainboard/artecgroup/dbe61/mainboard.c ============================================================================== --- trunk/src/mainboard/artecgroup/dbe61/mainboard.c Wed Apr 7 04:09:54 2010 (r5365) +++ trunk/src/mainboard/artecgroup/dbe61/mainboard.c Wed Apr 7 04:30:57 2010 (r5366) @@ -28,7 +28,7 @@ #include "../../../southbridge/amd/cs5536/cs5536.h" #include "chip.h" -static void init_gpio() +static void init_gpio(void) { msr_t msr; printk(BIOS_DEBUG, "Checking GPIO module...\n"); Modified: trunk/src/mainboard/intel/eagleheights/acpi_tables.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/acpi_tables.c Wed Apr 7 04:09:54 2010 (r5365) +++ trunk/src/mainboard/intel/eagleheights/acpi_tables.c Wed Apr 7 04:30:57 2010 (r5366) @@ -91,7 +91,6 @@ { unsigned int irq_start = 0; device_t dev = 0; - struct resource* res = NULL; unsigned char bus_isa; /* Local Apic */ @@ -141,7 +140,6 @@ unsigned long write_acpi_tables(unsigned long start) { unsigned long current; - int i; acpi_rsdp_t *rsdp; acpi_rsdt_t *rsdt; acpi_hpet_t *hpet; Modified: trunk/src/mainboard/intel/eagleheights/fadt.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/fadt.c Wed Apr 7 04:09:54 2010 (r5365) +++ trunk/src/mainboard/intel/eagleheights/fadt.c Wed Apr 7 04:30:57 2010 (r5366) @@ -115,9 +115,9 @@ fadt->res3 = 0; fadt->res4 = 0; fadt->res5 = 0; - fadt->x_firmware_ctl_l = facs; + fadt->x_firmware_ctl_l = (u32)facs; fadt->x_firmware_ctl_h = 0; - fadt->x_dsdt_l = dsdt; + fadt->x_dsdt_l = (u32)dsdt; fadt->x_dsdt_h = 0; fadt->x_pm1a_evt_blk.space_id = 1; Modified: trunk/src/mainboard/intel/eagleheights/mainboard.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/mainboard.c Wed Apr 7 04:09:54 2010 (r5365) +++ trunk/src/mainboard/intel/eagleheights/mainboard.c Wed Apr 7 04:30:57 2010 (r5366) @@ -21,10 +21,13 @@ #include <device/device.h> +#include <boot/tables.h> +#include <arch/coreboot_tables.h> #include "chip.h" int add_mainboard_resources(struct lb_memory *mem) { + return 0; } struct chip_operations mainboard_ops = { Modified: trunk/src/mainboard/intel/eagleheights/mptable.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/mptable.c Wed Apr 7 04:09:54 2010 (r5365) +++ trunk/src/mainboard/intel/eagleheights/mptable.c Wed Apr 7 04:30:57 2010 (r5366) @@ -75,7 +75,7 @@ dev = dev_find_slot(0, PCI_DEVFN(0x1F,0)); res = find_resource(dev, RCBA); if (!res) { - return; + return NULL; } rcba = res->base; Modified: trunk/src/mainboard/intel/xe7501devkit/mptable.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/mptable.c Wed Apr 7 04:09:54 2010 (r5365) +++ trunk/src/mainboard/intel/xe7501devkit/mptable.c Wed Apr 7 04:30:57 2010 (r5366) @@ -69,7 +69,7 @@ smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_B, P64H2_IOAPIC_VERSION, res->base); } -void xe7501devkit_register_interrupts(struct mp_config_table *mc) +static void xe7501devkit_register_interrupts(struct mp_config_table *mc) { // Chipset PCI bus // Type Trigger | Polarity Bus ID IRQ APIC ID PIN# Modified: trunk/src/northbridge/via/vx800/vx800.h ============================================================================== --- trunk/src/northbridge/via/vx800/vx800.h Wed Apr 7 04:09:54 2010 (r5365) +++ trunk/src/northbridge/via/vx800/vx800.h Wed Apr 7 04:30:57 2010 (r5366) @@ -21,6 +21,7 @@ #define VX800_H 1 #ifndef __PRE_RAM__ +#include <device/device.h> static inline void vx800_noop(device_t dev) { } Modified: trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c ============================================================================== --- trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c Wed Apr 7 04:09:54 2010 (r5365) +++ trunk/src/southbridge/intel/i82801cx/i82801cx_lpc.c Wed Apr 7 04:30:57 2010 (r5366) @@ -23,7 +23,7 @@ #define MAINBOARD_POWER_ON 1 -void i82801cx_enable_ioapic( struct device *dev) +static void i82801cx_enable_ioapic( struct device *dev) { uint32_t dword; volatile uint32_t* ioapic_index = (volatile uint32_t*)0xfec00000; @@ -54,7 +54,7 @@ } // This is how interrupts are received from the Super I/O chip -void i82801cx_enable_serial_irqs( struct device *dev) +static void i82801cx_enable_serial_irqs( struct device *dev) { // Recognize serial IRQs, continuous mode, frame size 21, 4 clock start frame pulse width pci_write_config8(dev, SERIRQ_CNTL, (1 << 7)|(1 << 6)|((21 - 17) << 2)|(0<< 0)); @@ -69,7 +69,7 @@ // Return Value: None // Description: Route all DMA channels to either PCI or LPC. // -void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask) +static void i82801cx_lpc_route_dma( struct device *dev, uint8_t mask) { uint16_t dmaConfig; int channelIndex; @@ -84,7 +84,7 @@ pci_write_config16(dev, PCI_DMA_CFG, dmaConfig); } -void i82801cx_rtc_init(struct device *dev) +static void i82801cx_rtc_init(struct device *dev) { uint32_t dword; int rtc_failed; @@ -116,7 +116,7 @@ } -void i82801cx_1f0_misc(struct device *dev) +static void i82801cx_1f0_misc(struct device *dev) { // Prevent LPC disabling, enable parity errors, and SERR# (System Error) pci_write_config16(dev, PCI_COMMAND, 0x014f); Modified: trunk/src/superio/smsc/lpc47b272/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47b272/superio.c Wed Apr 7 04:09:54 2010 (r5365) +++ trunk/src/superio/smsc/lpc47b272/superio.c Wed Apr 7 04:30:57 2010 (r5366) @@ -45,7 +45,7 @@ static void pnp_enter_conf_state(device_t dev); static void pnp_exit_conf_state(device_t dev); -static void dump_pnp_device(device_t dev); +//static void dump_pnp_device(device_t dev); struct chip_operations superio_smsc_lpc47b272_ops = { CHIP_NAME("SMSC LPC47B272 Super I/O")

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coreboot April 2010