coreboot April 2010

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build service results for r5355
by coreboot information 03 Apr '10

03 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5355 to the coreboot repository. This caused the following changes: Change Log: device_t wants device/device.h Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of via:epia-n has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5355 - trunk/src/southbridge/via/vt8237r
by repository service 03 Apr '10

03 Apr '10

Author: stepan Date: Sat Apr 3 17:41:27 2010 New Revision: 5355 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5355 Log: device_t wants device/device.h Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/southbridge/via/vt8237r/vt8237r.h Modified: trunk/src/southbridge/via/vt8237r/vt8237r.h ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r.h Sat Apr 3 16:19:22 2010 (r5354) +++ trunk/src/southbridge/via/vt8237r/vt8237r.h Sat Apr 3 17:41:27 2010 (r5355) @@ -104,6 +104,7 @@ ; #ifndef __PRE_RAM__ +#include <device/device.h> void writeback(struct device *dev, u16 where, u8 what); void dump_south(device_t dev); #endif

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build service results for r5354
by coreboot information 03 Apr '10

03 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5354 to the coreboot repository. This caused the following changes: Change Log: no need to udelay() Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of a-trend:atc-6220 has been fixed Compilation of a-trend:atc-6240 has been fixed Compilation of abit:be6-ii_v2_0 has been fixed Compilation of asus:mew-am has been fixed Compilation of asus:mew-vm has been fixed Compilation of asus:p2b has been fixed Compilation of asus:p2b-d has been fixed Compilation of asus:p2b-ds has been fixed Compilation of asus:p2b-f has been fixed Compilation of asus:p2b-ls has been fixed Compilation of asus:p3b-f has been fixed Compilation of azza:pt-6ibd has been fixed Compilation of biostar:m6tba has been fixed Compilation of compaq:deskpro_en_sff_p600 has been fixed Compilation of gigabyte:ga-6bxc has been fixed Compilation of mitac:6513wu has been fixed Compilation of msi:ms6119 has been fixed Compilation of msi:ms6147 has been fixed Compilation of msi:ms6156 has been fixed Compilation of soyo:sy-6ba-plus-iii has been fixed Compilation of tyan:s1846 has been fixed Compilation of via:epia-n is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5354&device=epia-n&vendor=… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5354 - trunk/src/lib
by repository service 03 Apr '10

03 Apr '10

Author: stepan Date: Sat Apr 3 16:19:22 2010 New Revision: 5354 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5354 Log: no need to udelay() Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/lib/debug.c Modified: trunk/src/lib/debug.c ============================================================================== --- trunk/src/lib/debug.c Sat Apr 3 15:33:01 2010 (r5353) +++ trunk/src/lib/debug.c Sat Apr 3 16:19:22 2010 (r5354) @@ -88,7 +88,6 @@ { int i; - udelay(2000); print_debug_hex16(port); print_debug(":\n"); for (i = 0; i < 256; i++) {

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build service results for r5353
by coreboot information 03 Apr '10

03 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5353 to the coreboot repository. This caused the following changes: Change Log: remove more warnings. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of a-trend:atc-6220 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=atc-6220&vendo… Compilation of a-trend:atc-6240 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=atc-6240&vendo… Compilation of abit:be6-ii_v2_0 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=be6-ii_v2_0&ve… Compilation of asus:mew-am is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=mew-am&vendor=… Compilation of asus:mew-vm is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=mew-vm&vendor=… Compilation of asus:p2b is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=p2b&vendor=asu… Compilation of asus:p2b-d is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=p2b-d&vendor=a… Compilation of asus:p2b-ds is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=p2b-ds&vendor=… Compilation of asus:p2b-f is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=p2b-f&vendor=a… Compilation of asus:p2b-ls is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=p2b-ls&vendor=… Compilation of asus:p3b-f is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=p3b-f&vendor=a… Compilation of azza:pt-6ibd is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=pt-6ibd&vendor… Compilation of biostar:m6tba is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=m6tba&vendor=b… Compilation of compaq:deskpro_en_sff_p600 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=deskpro_en_sff… Compilation of gigabyte:ga-6bxc is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=ga-6bxc&vendor… Compilation of mitac:6513wu is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=6513wu&vendor=… Compilation of msi:ms6119 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=ms6119&vendor=… Compilation of msi:ms6147 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=ms6147&vendor=… Compilation of msi:ms6156 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=ms6156&vendor=… Compilation of soyo:sy-6ba-plus-iii is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=sy-6ba-plus-ii… Compilation of tyan:s1846 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=s1846&vendor=t… Compilation of via:epia-n has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5353&device=epia-n&vendor=… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r5352
by coreboot information 03 Apr '10

03 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5352 to the coreboot repository. This caused the following changes: Change Log: remove more warnings rename amd64_main to stage1_main.. copy src/mainboard/via/vt8454c/debug.c to src/lib/debug.c Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of a-trend:atc-6220 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=atc-6220&vendo… Compilation of a-trend:atc-6240 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=atc-6240&vendo… Compilation of abit:be6-ii_v2_0 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=be6-ii_v2_0&ve… Compilation of asus:mew-am has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=mew-am&vendor=… Compilation of asus:mew-vm has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=mew-vm&vendor=… Compilation of asus:p2b has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=p2b&vendor=asu… Compilation of asus:p2b-d has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=p2b-d&vendor=a… Compilation of asus:p2b-ds has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=p2b-ds&vendor=… Compilation of asus:p2b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=p2b-f&vendor=a… Compilation of asus:p2b-ls has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=p2b-ls&vendor=… Compilation of asus:p3b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=p3b-f&vendor=a… Compilation of azza:pt-6ibd has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=pt-6ibd&vendor… Compilation of biostar:m6tba has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=m6tba&vendor=b… Compilation of compaq:deskpro_en_sff_p600 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=deskpro_en_sff… Compilation of gigabyte:ga-6bxc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=ga-6bxc&vendor… Compilation of mitac:6513wu has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=6513wu&vendor=… Compilation of msi:ms6119 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=ms6119&vendor=… Compilation of msi:ms6147 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=ms6147&vendor=… Compilation of msi:ms6156 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=ms6156&vendor=… Compilation of soyo:sy-6ba-plus-iii has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=sy-6ba-plus-ii… Compilation of tyan:s1846 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5352&device=s1846&vendor=t… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5353 - in trunk/src: cpu/amd/mtrr cpu/x86/mtrr mainboard/asus/m2v-mx_se mainboard/via/pc2500e northbridge/amd/amdk8 northbridge/via/cn700 southbridge/via/k8t890 southbridge/via/vt8237r
by repository service 03 Apr '10

03 Apr '10

Author: stepan Date: Sat Apr 3 15:33:01 2010 New Revision: 5353 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5353 Log: remove more warnings. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/amd/mtrr/amd_earlymtrr.c trunk/src/cpu/x86/mtrr/earlymtrr.c trunk/src/mainboard/asus/m2v-mx_se/Kconfig trunk/src/mainboard/asus/m2v-mx_se/romstage.c trunk/src/mainboard/via/pc2500e/mptable.c trunk/src/northbridge/amd/amdk8/debug.c trunk/src/northbridge/amd/amdk8/raminit_f.c trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c trunk/src/northbridge/via/cn700/cn700.h trunk/src/northbridge/via/cn700/northbridge.c trunk/src/northbridge/via/cn700/vga.c trunk/src/northbridge/via/cn700/vgabios.c trunk/src/southbridge/via/k8t890/k8t890.h trunk/src/southbridge/via/k8t890/k8t890_ctrl.c trunk/src/southbridge/via/k8t890/k8t890_early_car.c trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c trunk/src/southbridge/via/vt8237r/vt8237r.c trunk/src/southbridge/via/vt8237r/vt8237r.h trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c trunk/src/southbridge/via/vt8237r/vt8237r_ide.c trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c Modified: trunk/src/cpu/amd/mtrr/amd_earlymtrr.c ============================================================================== --- trunk/src/cpu/amd/mtrr/amd_earlymtrr.c Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/cpu/amd/mtrr/amd_earlymtrr.c Sat Apr 3 15:33:01 2010 (r5353) @@ -42,12 +42,6 @@ wrmsr(TOP_MEM, msr); #if defined(CONFIG_XIP_ROM_SIZE) -#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK -extern unsigned long AUTO_XIP_ROM_BASE; -#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE -#else -#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE -#endif /* enable write through caching so we can do execute in place * on the flash rom. */ Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c ============================================================================== --- trunk/src/cpu/x86/mtrr/earlymtrr.c Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/cpu/x86/mtrr/earlymtrr.c Sat Apr 3 15:33:01 2010 (r5353) @@ -26,6 +26,15 @@ # error "CONFIG_RAMTOP must be a power of 2" #endif +#if defined(CONFIG_XIP_ROM_SIZE) +# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK + extern unsigned long AUTO_XIP_ROM_BASE; +# define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE +# else +# define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE +# endif +#endif + static void disable_var_mtrr(unsigned reg) { /* The invalid bit is kept in the mask so we simply @@ -100,12 +109,6 @@ } #if defined(CONFIG_XIP_ROM_SIZE) -#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK -extern unsigned long AUTO_XIP_ROM_BASE; -#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE -#else -#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE -#endif /* enable write through caching so we can do execute in place * on the flash rom. */ Modified: trunk/src/mainboard/asus/m2v-mx_se/Kconfig ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/Kconfig Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/mainboard/asus/m2v-mx_se/Kconfig Sat Apr 3 15:33:01 2010 (r5353) @@ -29,7 +29,6 @@ select SUPERIO_ITE_IT8712F select USE_PRINTK_IN_CAR select USE_DCACHE_RAM - select HAVE_HARD_RESET select HAVE_OPTION_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_512 Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Sat Apr 3 15:33:01 2010 (r5353) @@ -116,12 +116,6 @@ #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/resourcemap.c" -#warning No hard_reset implemented for this board! -void hard_reset(void) -{ - print_info("NO HARD RESET. FIX ME!\n"); -} - void soft_reset(void) { uint8_t tmp; @@ -164,7 +158,6 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx) { - msr_t msr; static const uint16_t spd_addr[] = { (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, @@ -176,9 +169,7 @@ unsigned bsp_apicid = 0; int needs_reset = 0; struct sys_info *sysinfo = - (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - char *p; - u8 reg; + (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); sio_init(); it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); Modified: trunk/src/mainboard/via/pc2500e/mptable.c ============================================================================== --- trunk/src/mainboard/via/pc2500e/mptable.c Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/mainboard/via/pc2500e/mptable.c Sat Apr 3 15:33:01 2010 (r5353) @@ -40,7 +40,6 @@ struct mp_config_table *mc; int bus_num; - int i; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); Modified: trunk/src/northbridge/amd/amdk8/debug.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/debug.c Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/northbridge/amd/amdk8/debug.c Sat Apr 3 15:33:01 2010 (r5353) @@ -20,7 +20,7 @@ printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); } -static void print_pci_devices(void) +static inline void print_pci_devices(void) { device_t dev; for(dev = PCI_DEV(0, 0, 0); @@ -63,7 +63,7 @@ #if CONFIG_K8_REV_F_SUPPORT == 1 static uint32_t pci_read_config32_index_wait(device_t dev, uint32_t index_reg, uint32_t index); -static void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) +static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) { int i; print_debug_pci_dev(dev); @@ -109,7 +109,7 @@ } } -static void dump_pci_devices_on_bus(unsigned busn) +static inline void dump_pci_devices_on_bus(unsigned busn) { device_t dev; for(dev = PCI_DEV(busn, 0, 0); @@ -208,7 +208,7 @@ } #endif -static void dump_io_resources(unsigned port) +static inline void dump_io_resources(unsigned port) { int i; @@ -228,7 +228,7 @@ } } -static void dump_mem(unsigned start, unsigned end) +static inline void dump_mem(unsigned start, unsigned end) { unsigned i; print_debug("dump_mem:"); Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f.c Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/northbridge/amd/amdk8/raminit_f.c Sat Apr 3 15:33:01 2010 (r5353) @@ -1690,7 +1690,7 @@ static const uint8_t latency_indicies[] = { 25, 23, 9 }; -int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsigned *min_cycle_time) +static int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsigned *min_cycle_time) { int new_cycle_time, new_latency; int index; @@ -1938,7 +1938,7 @@ return valuex; } -int get_dimm_Trc_clocks(u32 spd_device, const struct mem_param *param) +static int get_dimm_Trc_clocks(u32 spd_device, const struct mem_param *param) { int value; int value2; Modified: trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Sat Apr 3 15:33:01 2010 (r5353) @@ -125,7 +125,7 @@ } -static inline void enable_sse2() +static inline void enable_sse2(void) { unsigned long cr4; cr4 = read_cr4(); @@ -133,7 +133,7 @@ write_cr4(cr4); } -static inline void disable_sse2() +static inline void disable_sse2(void) { unsigned long cr4; cr4 = read_cr4(); Modified: trunk/src/northbridge/via/cn700/cn700.h ============================================================================== --- trunk/src/northbridge/via/cn700/cn700.h Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/northbridge/via/cn700/cn700.h Sat Apr 3 15:33:01 2010 (r5353) @@ -19,7 +19,8 @@ */ #if !defined (__PRE_RAM__) -static void cn700_noop() +// HACK +static inline void cn700_noop(device_t dev) { } #endif Modified: trunk/src/northbridge/via/cn700/northbridge.c ============================================================================== --- trunk/src/northbridge/via/cn700/northbridge.c Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/northbridge/via/cn700/northbridge.c Sat Apr 3 15:33:01 2010 (r5353) @@ -202,7 +202,7 @@ assign_resources(&dev->link[0]); } -static const struct device_operations pci_domain_ops = { +static struct device_operations pci_domain_ops = { .read_resources = pci_domain_read_resources, .set_resources = pci_domain_set_resources, .enable_resources = enable_childrens_resources, @@ -219,7 +219,7 @@ { } -static const struct device_operations cpu_bus_ops = { +static struct device_operations cpu_bus_ops = { .read_resources = cpu_bus_noop, .set_resources = cpu_bus_noop, .enable_resources = cpu_bus_noop, Modified: trunk/src/northbridge/via/cn700/vga.c ============================================================================== --- trunk/src/northbridge/via/cn700/vga.c Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/northbridge/via/cn700/vga.c Sat Apr 3 15:33:01 2010 (r5353) @@ -52,7 +52,7 @@ * Copy BOCHS BIOS from 4G-CONFIG_ROM_SIZE-64k (in flash) to 0xf0000 (in RAM) * This is for compatibility with the VGA ROM's BIOS callbacks. */ - memcpy(0xf0000, (0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000); + memcpy((void *)0xf0000, (const void *)(0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000); printk(BIOS_DEBUG, "Initializing VGA\n"); @@ -98,7 +98,7 @@ outb(reg8, SR_DATA); /* Clear the BOCHS BIOS out of memory, so it doesn't confuse Linux. */ - memset(0xf0000, 0, 0x10000); + memset((void *)0xf0000, 0, 0x10000); } static const struct device_operations vga_operations = { Modified: trunk/src/northbridge/via/cn700/vgabios.c ============================================================================== --- trunk/src/northbridge/via/cn700/vgabios.c Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/northbridge/via/cn700/vgabios.c Sat Apr 3 15:33:01 2010 (r5353) @@ -4,7 +4,7 @@ #include <device/pci_ops.h> #undef __KERNEL__ #include <arch/io.h> -//#include <printk.h> +#include <stddef.h> #include <string.h> #include "vgachip.h" #include <cbfs.h> @@ -176,6 +176,7 @@ /* put the stack at the end of page zero. * that way we can easily share it between real and protected, * since the 16-bit ESP at segment 0 will work for any case. + */ /* Setup a stack */ " mov $0x0, %ax \n" " mov %ax, %ss \n" @@ -271,6 +272,7 @@ /* put the stack at the end of page zero. * that way we can easily share it between real and protected, * since the 16-bit ESP at segment 0 will work for any case. + */ /* Setup a stack */ " mov $0x0, %ax \n" " mov %ax, %ss \n" @@ -336,7 +338,7 @@ { device_t dev; unsigned long busdevfn; - unsigned int rom = 0; + unsigned char *rom; unsigned char *buf; unsigned int size = 64*1024; int i; @@ -357,9 +359,9 @@ /* declare rom address here - keep any config data out of the way * of core LXB stuff */ - rom = cbfs_load_optionrom(dev->vendor, dev->device, 0); - pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1); - printk(BIOS_DEBUG, "rom base, size: %x\n", rom); + rom = cbfs_load_optionrom(dev->vendor, dev->device, NULL); + pci_write_config32(dev, PCI_ROM_ADDRESS, (u32)rom | 1); + printk(BIOS_DEBUG, "rom base: %p\n", rom); buf = (unsigned char *) rom; if ((buf[0] == 0x55) && (buf[1] == 0xaa)) { @@ -635,7 +637,7 @@ // and get it that way. But that's really disgusting. for (i = 0; i < 256; i++) { idts[i].cs = 0; - codeptr = (char*) 4096 + i * codesize; + codeptr = (unsigned char*) 4096 + i * codesize; idts[i].offset = (unsigned) codeptr; memcpy(codeptr, &idthandle, codesize); intbyte = codeptr + 3; @@ -648,7 +650,7 @@ // int10. // calling convention here is the same as INTs, we can reuse // the int entry code. - codeptr = (char*) 0xff065; + codeptr = (unsigned char*) 0xff065; memcpy(codeptr, &idthandle, codesize); intbyte = codeptr + 3; *intbyte = 0x42; /* int42 is the relocated int10 */ @@ -657,7 +659,7 @@ TF bit is set upon call to real mode */ idts[1].cs = 0; idts[1].offset = 16384; - memcpy(16384, &debughandle, &end_debughandle - &debughandle); + memcpy((void *)16384, &debughandle, &end_debughandle - &debughandle); } @@ -687,16 +689,7 @@ unsigned long *pesp, unsigned long *pebx, unsigned long *pedx, unsigned long *pecx, unsigned long *peax, unsigned long *pflags) { - unsigned long edi = *pedi; - unsigned long esi = *pesi; - unsigned long ebp = *pebp; - unsigned long esp = *pesp; - unsigned long ebx = *pebx; - unsigned long edx = *pedx; - unsigned long ecx = *pecx; - unsigned long eax = *peax; - unsigned long flags = *pflags; - unsigned short func = (unsigned short) eax; + unsigned short func = (unsigned short) (*peax); int retval = 0; unsigned short devid, vendorid, devfn; short devindex; /* Use short to get rid of garbage in upper half of 32-bit register */ Modified: trunk/src/southbridge/via/k8t890/k8t890.h ============================================================================== --- trunk/src/southbridge/via/k8t890/k8t890.h Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/southbridge/via/k8t890/k8t890.h Sat Apr 3 15:33:01 2010 (r5353) @@ -40,8 +40,12 @@ #include <device/device.h> +#if 0 extern void writeback(struct device *dev, u16 where, u8 what); extern void dump_south(device_t dev); +#endif +#include <southbridge/via/vt8237r/vt8237r.h> + int k8m890_host_fb_size_get(void); //void k8m890_host_fb_direct_set(uint32_t fb_address); Modified: trunk/src/southbridge/via/k8t890/k8t890_ctrl.c ============================================================================== --- trunk/src/southbridge/via/k8t890/k8t890_ctrl.c Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/southbridge/via/k8t890/k8t890_ctrl.c Sat Apr 3 15:33:01 2010 (r5353) @@ -29,7 +29,7 @@ static void vt8237r_cfg(struct device *dev, struct device *devsb) { - u8 regm, regm2, regm3; + u8 regm, regm3; device_t devfun3; Modified: trunk/src/southbridge/via/k8t890/k8t890_early_car.c ============================================================================== --- trunk/src/southbridge/via/k8t890/k8t890_early_car.c Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/southbridge/via/k8t890/k8t890_early_car.c Sat Apr 3 15:33:01 2010 (r5353) @@ -59,6 +59,7 @@ pci_write_config8(PCI_DEV(0, 0x0, 2), 0xa1, reg); /* check if connected non coherent, initcomplete (find the SB on K8 side) */ + ldtnr = 0; if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0x98)) { ldtnr = 0; } else if (0x7 == pci_read_config8(PCI_DEV(0, 0x18, 0), 0xb8)) { Modified: trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c Sat Apr 3 15:33:01 2010 (r5353) @@ -22,12 +22,13 @@ #include <device/pci_ops.h> #include <device/pci_ids.h> #include <console/console.h> +#include "vt8237r.h" /* We support here K8M890/K8T890 and VT8237/S/A PCI1/Vlink */ static void vt8237_cfg(struct device *dev) { - u8 regm, regm2, regm3; + u8 regm, regm3; device_t devfun3; devfun3 = dev_find_device(PCI_VENDOR_ID_VIA, @@ -69,6 +70,7 @@ regm = pci_read_config8(devfun3, 0x83); pci_write_config8(dev, 0x63, regm); + // FIXME is this really supposed to be regm3? regm3 = pci_read_config8(devfun3, 0x82);/* Shadow page E */ pci_write_config8(dev, 0x64, regm); @@ -167,8 +169,6 @@ pci_write_config8(dev, 0x4f, 0x43); } -extern void dump_south(device_t dev); - static void ctrl_init(struct device *dev) { /* Modified: trunk/src/southbridge/via/vt8237r/vt8237r.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r.c Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/southbridge/via/vt8237r/vt8237r.c Sat Apr 3 15:33:01 2010 (r5353) @@ -21,6 +21,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> +#include "vt8237r.h" #include "chip.h" /* @@ -28,11 +29,6 @@ * VT8237R_SouthBridge_Revision2.06_Lead-Free.zip */ -void hard_reset(void) -{ - printk(BIOS_ERR, "NO HARD RESET ON VT8237R! FIX ME!\n"); -} - #if CONFIG_DEFAULT_CONSOLE_LOGLEVEL > 7 void writeback(struct device *dev, u16 where, u8 what) { Modified: trunk/src/southbridge/via/vt8237r/vt8237r.h ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r.h Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/southbridge/via/vt8237r/vt8237r.h Sat Apr 3 15:33:01 2010 (r5353) @@ -103,4 +103,9 @@ #endif ; +#ifndef __PRE_RAM__ +void writeback(struct device *dev, u16 where, u8 what); +void dump_south(device_t dev); +#endif + #endif Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Sat Apr 3 15:33:01 2010 (r5353) @@ -61,8 +61,9 @@ PRINT_DEBUG("Waiting until SMBus ready\n"); - loops = 0; /* Yes, this is a mess, but it's the easiest way to do it. */ + /* XXX not so messy, but an explanation of the hack would have been better */ + loops = 0; while ((inb(SMBHSTSTAT) & 1) == 1 && loops < SMBUS_TIMEOUT) ++loops; @@ -464,6 +465,8 @@ pci_write_config32(dev, 0x5c, tmp | 0x01000000); /* Toggle SEEPR. */ /* Yes, this is a mess, but it's the easiest way to do it. */ + /* XXX not so messy, but an explanation of the hack would have been better */ + loops = 0; while ((((pci_read_config32(dev, 0x5c) >> 25) & 1) == 0) && (loops < LAN_TIMEOUT)) { ++loops; Modified: trunk/src/southbridge/via/vt8237r/vt8237r_ide.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r_ide.c Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/southbridge/via/vt8237r/vt8237r_ide.c Sat Apr 3 15:33:01 2010 (r5353) @@ -35,10 +35,8 @@ struct southbridge_via_vt8237r_config *sb = (struct southbridge_via_vt8237r_config *)dev->chip_info; - u8 enables, reg8; + u8 enables; u32 cablesel; - device_t lpc_dev; - int i, j; printk(BIOS_INFO, "%s IDE interface %s\n", "Primary", sb->ide0_enable ? "enabled" : "disabled"); @@ -98,6 +96,8 @@ pci_write_config32(dev, IDE_UDMA, cablesel); #if CONFIG_EPIA_VT8237R_INIT + device_t lpc_dev; + /* Set PATA Output Drive Strength */ lpc_dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); Modified: trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c Sat Apr 3 14:41:41 2010 (r5352) +++ trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c Sat Apr 3 15:33:01 2010 (r5353) @@ -34,7 +34,6 @@ #include "vt8237r.h" #include "chip.h" -extern void dump_south(device_t dev); static void southbridge_init_common(struct device *dev); #if CONFIG_EPIA_VT8237R_INIT @@ -248,7 +247,7 @@ static void vt8237r_init(struct device *dev) { - u8 enables, reg8; + u8 enables; #if CONFIG_EPIA_VT8237R_INIT printk(BIOS_SPEW, "Entering vt8237r_init, for EPIA.\n");

1 0

[commit] r5352 - in trunk/src: cpu/via/car cpu/x86/car lib mainboard/tyan/s2735 mainboard/via/epia-m700 mainboard/via/vt8454c northbridge/via/cx700 northbridge/via/vx800/examples superio/via/vt1211
by repository service 03 Apr '10

03 Apr '10

Author: stepan Date: Sat Apr 3 14:41:41 2010 New Revision: 5352 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5352 Log: remove more warnings rename amd64_main to stage1_main.. copy src/mainboard/via/vt8454c/debug.c to src/lib/debug.c Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Deleted: trunk/src/mainboard/via/vt8454c/debug.c Modified: trunk/src/cpu/via/car/cache_as_ram.inc trunk/src/cpu/x86/car/cache_as_ram.inc trunk/src/lib/debug.c trunk/src/mainboard/tyan/s2735/romstage.c trunk/src/mainboard/via/epia-m700/romstage.c trunk/src/mainboard/via/vt8454c/acpi_tables.c trunk/src/mainboard/via/vt8454c/romstage.c trunk/src/northbridge/via/cx700/cx700_early_smbus.c trunk/src/northbridge/via/cx700/cx700_lpc.c trunk/src/northbridge/via/cx700/cx700_reset.c trunk/src/northbridge/via/cx700/raminit.c trunk/src/northbridge/via/vx800/examples/romstage.c trunk/src/superio/via/vt1211/vt1211.c Modified: trunk/src/cpu/via/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.inc Sat Apr 3 02:03:07 2010 (r5351) +++ trunk/src/cpu/via/car/cache_as_ram.inc Sat Apr 3 14:41:41 2010 (r5352) @@ -163,7 +163,7 @@ /* We need to set ebp ? No need */ movl %esp, %ebp pushl %eax /* bist */ - call amd64_main + call stage1_main /* We will not go back */ fixed_mtrr_msr: Modified: trunk/src/cpu/x86/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/x86/car/cache_as_ram.inc Sat Apr 3 02:03:07 2010 (r5351) +++ trunk/src/cpu/x86/car/cache_as_ram.inc Sat Apr 3 14:41:41 2010 (r5352) @@ -289,7 +289,7 @@ /* We need to set ebp ? No need */ movl %esp, %ebp pushl %eax /* bist */ - call amd64_main + call stage1_main /* We will not go back */ fixed_mtrr_msr: Modified: trunk/src/lib/debug.c ============================================================================== --- trunk/src/lib/debug.c Sat Apr 3 02:03:07 2010 (r5351) +++ trunk/src/lib/debug.c Sat Apr 3 14:41:41 2010 (r5352) @@ -1,3 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ static void print_debug_pci_dev(unsigned dev) { @@ -9,17 +29,16 @@ print_debug_hex8((dev >> 8) & 7); } -static void print_pci_devices(void) +static inline void print_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; + for (dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) { + u32 id; id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) + || (((id >> 16) & 0xffff) == 0xffff) + || (((id >> 16) & 0xffff) == 0x0000)) { continue; } print_debug_pci_dev(dev); @@ -32,8 +51,8 @@ int i; print_debug_pci_dev(dev); print_debug("\n"); - - for(i = 0; i <= 255; i++) { + + for (i = 0; i <= 255; i++) { unsigned char val; if ((i & 0x0f) == 0) { print_debug_hex8(i); @@ -48,19 +67,42 @@ } } -static void dump_pci_devices(void) +static inline void dump_pci_devices(void) { device_t dev; - for(dev = PCI_DEV(0, 0, 0); - dev <= PCI_DEV(0, 0x1f, 0x7); - dev += PCI_DEV(0,0,1)) { - uint32_t id; + for (dev = PCI_DEV(0, 0, 0); + dev <= PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) { + u32 id; id = pci_read_config32(dev, PCI_VENDOR_ID); - if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0xffff) || - (((id >> 16) & 0xffff) == 0x0000)) { + if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) + || (((id >> 16) & 0xffff) == 0xffff) + || (((id >> 16) & 0xffff) == 0x0000)) { continue; } dump_pci_device(dev); } } + + +static inline void dump_io_resources(unsigned port) +{ + + int i; + udelay(2000); + print_debug_hex16(port); + print_debug(":\n"); + for (i = 0; i < 256; i++) { + u8 val; + if ((i & 0x0f) == 0) { + print_debug_hex8(i); + print_debug_char(':'); + } + val = inb(port); + print_debug_char(' '); + print_debug_hex8(val); + if ((i & 0x0f) == 0x0f) { + print_debug("\n"); + } + port++; + } +} Modified: trunk/src/mainboard/tyan/s2735/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/romstage.c Sat Apr 3 02:03:07 2010 (r5351) +++ trunk/src/mainboard/tyan/s2735/romstage.c Sat Apr 3 14:41:41 2010 (r5352) @@ -65,7 +65,7 @@ #include "cpu/x86/car/copy_and_run.c" -void amd64_main(unsigned long bist) +void stage1_main(unsigned long bist) { static const struct mem_controller memctrl[] = { { Modified: trunk/src/mainboard/via/epia-m700/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/romstage.c Sat Apr 3 02:03:07 2010 (r5351) +++ trunk/src/mainboard/via/epia-m700/romstage.c Sat Apr 3 14:41:41 2010 (r5352) @@ -394,7 +394,7 @@ } /* cache_as_ram.inc jumps to here. */ -void amd64_main(unsigned long bist) +void stage1_main(unsigned long bist) { unsigned cpu_reset = 0; u16 boot_mode; Modified: trunk/src/mainboard/via/vt8454c/acpi_tables.c ============================================================================== --- trunk/src/mainboard/via/vt8454c/acpi_tables.c Sat Apr 3 02:03:07 2010 (r5351) +++ trunk/src/mainboard/via/vt8454c/acpi_tables.c Sat Apr 3 14:41:41 2010 (r5352) @@ -52,7 +52,7 @@ } -void acpi_create_via_hpet(acpi_hpet_t * hpet) +static void acpi_create_via_hpet(acpi_hpet_t * hpet) { #define HPET_ADDR 0xfe800000ULL acpi_header_t *header = &(hpet->header); @@ -182,7 +182,7 @@ dsdt = (acpi_header_t *) current; current += AmlCode.length; memcpy((void *) dsdt, &AmlCode,AmlCode.length); -#if DONT_TRUST_IASL +#ifdef DONT_TRUST_IASL dsdt->checksum = 0; // don't trust intel iasl compiler to get this right dsdt->checksum = acpi_checksum(dsdt, dsdt->length); #endif Modified: trunk/src/mainboard/via/vt8454c/romstage.c ============================================================================== --- trunk/src/mainboard/via/vt8454c/romstage.c Sat Apr 3 02:03:07 2010 (r5351) +++ trunk/src/mainboard/via/vt8454c/romstage.c Sat Apr 3 14:41:41 2010 (r5352) @@ -30,7 +30,6 @@ #include "console/console.c" #include "lib/ramtest.c" #include "northbridge/via/cx700/raminit.h" -#include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #define DEACTIVATE_CAR 1 @@ -38,9 +37,8 @@ #include "cpu/x86/car/copy_and_run.c" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/via/cx700/cx700_early_smbus.c" -#include "debug.c" +#include "lib/debug.c" #include "northbridge/via/cx700/cx700_early_serial.c" #include "northbridge/via/cx700/raminit.c" @@ -126,7 +124,8 @@ copy_and_run(0); } -void amd64_main(unsigned long bist) { +void stage1_main(unsigned long bist) +{ main(bist); } Modified: trunk/src/northbridge/via/cx700/cx700_early_smbus.c ============================================================================== --- trunk/src/northbridge/via/cx700/cx700_early_smbus.c Sat Apr 3 02:03:07 2010 (r5351) +++ trunk/src/northbridge/via/cx700/cx700_early_smbus.c Sat Apr 3 14:41:41 2010 (r5352) @@ -57,6 +57,7 @@ #endif /* Internal functions */ +#if CONFIG_DEBUG_SMBUS static void smbus_print_error(unsigned char host_status_register, int loops) { /* Check if there actually was an error */ @@ -87,6 +88,7 @@ print_err("Host Busy\n"); } } +#endif static void smbus_wait_until_ready(void) { @@ -127,7 +129,7 @@ inb(SMBHSTCTL); /* fill blocktransfer array */ - if (dev = 0xd2) { + if (dev == 0xd2) { //char d2_data[] = {0x0d,0x00,0x3f,0xcd,0x7f,0xbf,0x1a,0x2a,0x01,0x0f,0x0b,0x00,0x8d,0x9b}; outb(0x0d, SMBBLKDAT); outb(0x00, SMBBLKDAT); @@ -231,7 +233,7 @@ } /* Debugging Function */ -#ifdef CONFIG_DEBUG_SMBUS +#if CONFIG_DEBUG_SMBUS static void dump_spd_data(const struct mem_controller *ctrl) { int dimm, offset, regs; Modified: trunk/src/northbridge/via/cx700/cx700_lpc.c ============================================================================== --- trunk/src/northbridge/via/cx700/cx700_lpc.c Sat Apr 3 02:03:07 2010 (r5351) +++ trunk/src/northbridge/via/cx700/cx700_lpc.c Sat Apr 3 14:41:41 2010 (r5352) @@ -84,7 +84,7 @@ * can't figure out how to do !!!! */ -void setup_pm(device_t dev) +static void setup_pm(device_t dev) { /* Debounce LID and PWRBTN# Inputs for 16ms. */ pci_write_config8(dev, 0x80, 0x20); @@ -236,7 +236,7 @@ } -void cx700_read_resources(device_t dev) +static void cx700_read_resources(device_t dev) { struct resource *res; @@ -258,7 +258,7 @@ res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } -void cx700_set_resources(device_t dev) +static void cx700_set_resources(device_t dev) { struct resource *resource; resource = find_resource(dev, 1); @@ -266,7 +266,7 @@ pci_dev_set_resources(dev); } -void cx700_enable_resources(device_t dev) +static void cx700_enable_resources(device_t dev) { /* Enable SuperIO decoding */ pci_dev_enable_resources(dev); Modified: trunk/src/northbridge/via/cx700/cx700_reset.c ============================================================================== --- trunk/src/northbridge/via/cx700/cx700_reset.c Sat Apr 3 02:03:07 2010 (r5351) +++ trunk/src/northbridge/via/cx700/cx700_reset.c Sat Apr 3 14:41:41 2010 (r5352) @@ -18,6 +18,7 @@ */ #include <arch/io.h> +#include <reset.h> void hard_reset(void) { Modified: trunk/src/northbridge/via/cx700/raminit.c ============================================================================== --- trunk/src/northbridge/via/cx700/raminit.c Sat Apr 3 02:03:07 2010 (r5351) +++ trunk/src/northbridge/via/cx700/raminit.c Sat Apr 3 14:41:41 2010 (r5352) @@ -103,15 +103,15 @@ } while ( 0 ) #define REGISTERPRESET(bus,dev,fun,bdfspec) \ - { u8 i, reg; \ - for (i=0; i<(sizeof((bdfspec))/sizeof(struct regmask)); i++) { \ + { u8 j, reg; \ + for (j=0; j<(sizeof((bdfspec))/sizeof(struct regmask)); j++) { \ printk(BIOS_DEBUG, "Writing bus " #bus " dev " #dev " fun " #fun " register "); \ - printk(BIOS_DEBUG, "%02x", (bdfspec)[i].reg); \ + printk(BIOS_DEBUG, "%02x", (bdfspec)[j].reg); \ printk(BIOS_DEBUG, "\n"); \ - reg = pci_read_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[i].reg); \ - reg &= (bdfspec)[i].mask; \ - reg |= (bdfspec)[i].val; \ - pci_write_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[i].reg, reg); \ + reg = pci_read_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[j].reg); \ + reg &= (bdfspec)[j].mask; \ + reg |= (bdfspec)[j].val; \ + pci_write_config8(PCI_DEV((bus), (dev), (fun)), (bdfspec)[j].reg, reg); \ } \ } @@ -1436,23 +1436,23 @@ { 0x67, ~0x03, 0x01}, { 0x5b, ~0x01, 0x00}, { 0x8d, ~0x02, 0x02}, - { 0x97, ~0x80, 0x00}, + { 0x97, 0x7f, 0x00}, { 0xd2, ~0x18, 0x00}, { 0xe2, ~0x36, 0x06}, - { 0xe4, ~0x80, 0x00}, + { 0xe4, 0x7f, 0x00}, { 0xe5, 0x00, 0x40}, { 0xe6, 0x00, 0x20}, - { 0xe7, ~0xd0, 0xc0}, + { 0xe7, 0x2f, 0xc0}, { 0xec, ~0x08, 0x00} }, b0d17f7[] = { - { 0x4e, ~0x80, 0x80}, + { 0x4e, 0x7f, 0x80}, { 0x4f, ~(1 << 6), 1 << 6 }, /* PG_CX700: 14.1.1 enable P2P Bridge Header for External PCI Bus */ { 0x74, ~0x00, 0x04}, /* PG_CX700: 14.1.2 APIC FSB directly up to snmic, not on pci */ { 0x7c, ~0x00, 0x02}, /* PG_CX700: 14.1.1 APIC FSB directly up to snmic, not on pci */ { 0xe6, 0x0, 0x04} // MSI post }, b0d19f0[] = { /* P2PE */ { 0x42, ~0x08, 0x08}, // Disable HD Audio, - { 0x40, ~0xc0, 0x80} // 14.1.3.1.1 of the PG: extended cfg mode for pcie. enable capability, but don't activate + { 0x40, 0x3f, 0x80} // 14.1.3.1.1 of the PG: extended cfg mode for pcie. enable capability, but don't activate }, b0d0f2[] = { { 0x50, ~0x40, 0x88}, { 0x51, 0x80, 0x7b}, Modified: trunk/src/northbridge/via/vx800/examples/romstage.c ============================================================================== --- trunk/src/northbridge/via/vx800/examples/romstage.c Sat Apr 3 02:03:07 2010 (r5351) +++ trunk/src/northbridge/via/vx800/examples/romstage.c Sat Apr 3 14:41:41 2010 (r5352) @@ -300,7 +300,7 @@ /* cache_as_ram.inc jump to here */ -void amd64_main(unsigned long bist) +void stage1_main(unsigned long bist) { unsigned cpu_reset = 0; u16 boot_mode; Modified: trunk/src/superio/via/vt1211/vt1211.c ============================================================================== --- trunk/src/superio/via/vt1211/vt1211.c Sat Apr 3 02:03:07 2010 (r5351) +++ trunk/src/superio/via/vt1211/vt1211.c Sat Apr 3 14:41:41 2010 (r5352) @@ -117,7 +117,7 @@ } } -void vt1211_pnp_enable_resources(device_t dev) +static void vt1211_pnp_enable_resources(device_t dev) { printk(BIOS_DEBUG, "%s - enabling\n",dev_path(dev)); pnp_enter_ext_func_mode(dev); @@ -125,7 +125,7 @@ pnp_exit_ext_func_mode(dev); } -void vt1211_pnp_set_resources(struct device *dev) +static void vt1211_pnp_set_resources(struct device *dev) { int i; struct resource *resource; @@ -178,7 +178,7 @@ pnp_exit_ext_func_mode(dev); } -void vt1211_pnp_enable(device_t dev) +static void vt1211_pnp_enable(device_t dev) { if (!dev->enabled) { pnp_enter_ext_func_mode(dev);

1 0

build service results for r5349
by coreboot information 03 Apr '10

03 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5349 to the coreboot repository. This caused the following changes: Change Log: oops, sorry, overlapping work Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of emulation:qemu-x86 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

build service results for r5348
by coreboot information 03 Apr '10

03 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5348 to the coreboot repository. This caused the following changes: Change Log: remove some more warnings Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of emulation:qemu-x86 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5348&device=qemu-x86&vendo… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot April 2010