[commit] r5348 - in trunk/src: cpu/amd/model_gx2 include/console mainboard/advantech/pcm-5820 mainboard/amd/db800 northbridge/amd/lx southbridge/amd/cs5536

[repository service]

Author: stepan
Date: Sat Apr  3 00:11:20 2010
New Revision: 5348
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5348

Log:
remove some more warnings

Signed-off-by: Stefan Reinauer 
Acked-by: Stefan Reinauer

Modified:
   trunk/src/cpu/amd/model_gx2/vsmsetup.c
   trunk/src/include/console/console.h
   trunk/src/mainboard/advantech/pcm-5820/irq_tables.c
   trunk/src/mainboard/amd/db800/romstage.c
   trunk/src/northbridge/amd/lx/pll_reset.c
   trunk/src/northbridge/amd/lx/raminit.c
   trunk/src/southbridge/amd/cs5536/cs5536.c
   trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c

Modified: trunk/src/cpu/amd/model_gx2/vsmsetup.c
==============================================================================
--- trunk/src/cpu/amd/model_gx2/vsmsetup.c	Fri Apr  2 23:39:12 2010	(r5347)
+++ trunk/src/cpu/amd/model_gx2/vsmsetup.c	Sat Apr  3 00:11:20 2010	(r5348)
@@ -35,7 +35,6 @@
 #include <arch/io.h>
 #include <cbfs.h>

-u32 VSA_vrRead(u16 classIndex);
 void do_vsmbios(void);

#define VSA2_BUFFER		0x60000
@@ -150,7 +149,7 @@

/* andrei: Some VSA virtual register helpers: raw read and MSR read. */

-u32 VSA_vrRead(u16 classIndex)
+static u32 VSA_vrRead(u16 classIndex)
 {
    unsigned eax, ebx, ecx, edx;
    asm volatile (
@@ -166,7 +165,7 @@
    return eax;
 }

-u32 VSA_msrRead(u32 msrAddr)
+static u32 VSA_msrRead(u32 msrAddr)
 {
    unsigned eax, ebx, ecx, edx;
    asm volatile (

Modified: trunk/src/include/console/console.h
==============================================================================
--- trunk/src/include/console/console.h	Fri Apr  2 23:39:12 2010	(r5347)
+++ trunk/src/include/console/console.h	Sat Apr  3 00:11:20 2010	(r5348)
@@ -44,6 +44,9 @@
 #endif

#ifndef __ROMCC__
+void console_init(void);
+void post_code(u8 value);
+void __attribute__ ((noreturn)) die(const char *msg);
 int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));

#undef WE_CLEANED_UP_ALL_SIDE_EFFECTS

Modified: trunk/src/mainboard/advantech/pcm-5820/irq_tables.c
==============================================================================
--- trunk/src/mainboard/advantech/pcm-5820/irq_tables.c	Fri Apr  2 23:39:12 2010	(r5347)
+++ trunk/src/mainboard/advantech/pcm-5820/irq_tables.c	Sat Apr  3 00:11:20 2010	(r5348)
@@ -30,7 +30,7 @@
    0x1078,			/* Vendor */
    0x2,			/* Device */
    0,			/* Crap (miniport) */
-	// { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
    0xde,			/* Checksum */
    {
    	/* bus,        dev | fn,   {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap},  slot, rfu */

Modified: trunk/src/mainboard/amd/db800/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/db800/romstage.c	Fri Apr  2 23:39:12 2010	(r5347)
+++ trunk/src/mainboard/amd/db800/romstage.c	Sat Apr  3 00:11:20 2010	(r5348)
@@ -24,6 +24,7 @@
 #include <device/pnp_def.h>
 #include <arch/hlt.h>
 #include "pc80/serial.c"
+#include <console/console.h>
 #include "console/console.c"
 #include "lib/ramtest.c"
 #include "cpu/x86/bist.h"

Modified: trunk/src/northbridge/amd/lx/pll_reset.c
==============================================================================
--- trunk/src/northbridge/amd/lx/pll_reset.c	Fri Apr  2 23:39:12 2010	(r5347)
+++ trunk/src/northbridge/amd/lx/pll_reset.c	Sat Apr  3 00:11:20 2010	(r5348)
@@ -72,6 +72,7 @@
    return;
 }

+#if 0 // Unused
 static unsigned int CPUSpeed(void)
 {
    unsigned int speed;
@@ -84,6 +85,8 @@
    }
    return (speed);
 }
+#endif
+
 static unsigned int GeodeLinkSpeed(void)
 {
    unsigned int speed;
@@ -96,6 +99,8 @@
    }
    return (speed);
 }
+
+#if 0 // Unused
 static unsigned int PCISpeed(void)
 {
    msr_t msr;
@@ -107,3 +112,4 @@
    	return (33);
    }
 }
+#endif

Modified: trunk/src/northbridge/amd/lx/raminit.c
==============================================================================
--- trunk/src/northbridge/amd/lx/raminit.c	Fri Apr  2 23:39:12 2010	(r5347)
+++ trunk/src/northbridge/amd/lx/raminit.c	Sat Apr  3 00:11:20 2010	(r5348)
@@ -514,6 +514,8 @@
    wrmsr(MC_CF07_DATA, msr);
 }

+#undef TLA_MEMORY_DEBUG
+#ifdef TLA_MEMORY_DEBUG
 static void EnableMTest(void)
 {
    msr_t msr;
@@ -534,6 +536,7 @@

print_info("Enabled MTest for TLA debug\n");
 }
+#endif

static void sdram_set_registers(const struct mem_controller *ctrl)
 {
@@ -642,8 +645,10 @@
 ;********************************************************************/
    post_code(POST_MEM_ENABLE);	// post_76h

+#ifdef TLA_MEMORY_DEBUG
    /* Only enable MTest for TLA memory debug */
-	/*EnableMTest(); */
+	EnableMTest();
+#endif

/* If both Page Size = "Not Installed" we have a problems and should halt. */
    msr = rdmsr(MC_CF07_DATA);

Modified: trunk/src/southbridge/amd/cs5536/cs5536.c
==============================================================================
--- trunk/src/southbridge/amd/cs5536/cs5536.c	Fri Apr  2 23:39:12 2010	(r5347)
+++ trunk/src/southbridge/amd/cs5536/cs5536.c	Sat Apr  3 00:11:20 2010	(r5348)
@@ -77,7 +77,7 @@
    {PMS_IO_BASE + PM_SIDD, 0x000008C02},
    {PMS_IO_BASE + PM_WKD, 0x0000000A0},
    {PMS_IO_BASE + PM_WKXD, 0x0000000A0},
-	{0, 0, 0}
+	{0, 0}
 };

struct FLASH_DEVICE {
@@ -197,7 +197,7 @@
 /*		Run after VSA init to enable the flash PCI device header */
 /* **/
 /* ***************************************************************************/
-static void enable_ide_nand_flash_header()
+static void enable_ide_nand_flash_header(void)
 {
    /* Tell VSA to use FLASH PCI header. Not IDE header. */
    outl(0x80007A40, 0xCF8);

Modified: trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c
==============================================================================
--- trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c	Fri Apr  2 23:39:12 2010	(r5347)
+++ trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c	Sat Apr  3 00:11:20 2010	(r5348)
@@ -156,7 +156,7 @@
  *
  * See page 412 of the AMD Geode CS5536 Companion Device data book.
  */
-void cs5536_setup_onchipuart1(void)
+static void cs5536_setup_onchipuart1(void)
 {
    msr_t msr;

@@ -196,7 +196,7 @@
    wrmsr(MDD_UART1_CONF, msr);
 }

-void cs5536_setup_onchipuart2(void)
+static void cs5536_setup_onchipuart2(void)
 {
    msr_t msr;

[Myles Watson]

> Modified: trunk/src/include/console/console.h
>
> ==============================================================================
> --- trunk/src/include/console/console.h Fri Apr  2 23:39:12 2010
>  (r5347)
> +++ trunk/src/include/console/console.h Sat Apr  3 00:11:20 2010
>  (r5348)
> @@ -44,6 +44,9 @@
>  #endif
>
> #ifndef __ROMCC__
> +void console_init(void);
> +void post_code(u8 value);
> +void __attribute__ ((noreturn)) die(const char *msg);
>  int do_printk(int msg_level, const char *fmt, ...)
> __attribute__((format(printf, 2, 3)));

This looks redundant as of 5347.
> Modified: trunk/src/mainboard/amd/db800/romstage.c
>
> ==============================================================================
> --- trunk/src/mainboard/amd/db800/romstage.c    Fri Apr  2 23:39:12 2010
>      (r5347)
> +++ trunk/src/mainboard/amd/db800/romstage.c    Sat Apr  3 00:11:20 2010
>      (r5348)
> @@ -24,6 +24,7 @@
>  #include <device/pnp_def.h>
>  #include <arch/hlt.h>
>  #include "pc80/serial.c"
> +#include <console/console.h>
>  #include "console/console.c"

This shouldn't be necessary, since console.c includes console.h

Thanks,
Myles