coreboot April 2010

coreboot@coreboot.org

64 participants
402 discussions

H8QME-2+ boot problems on different machines.
by Knut Kujat 06 May '10

06 May '10

Hi, I have a strange problem trying to install/flash my Coreboot to several machines in the cluster some worked just fine and other hang at a really early moment. The machines are identical: H8QME-2+ with 16 GB RAM and 4 quadcore AMD Opterons 8350. I guess that from the point where it hangs that it must be some kind of CPU issue (I haven't switched CPUs yet). here the serial output: coreboot-4.0-r5224M Wed Apr 28 12:50:59 CEST 2010 starting... BSP Family_Model: 00100f22 *sysinfo range: [000cc000,000cdfa0] bsp_apicid = 00 cpu_init_detectedx = 00000000 After Set_sysinfo_in_ram microcode: equivalent rev id = 0x1022, current patch id = 0x00000000 microcode: patch id to apply = 0x01000095 microcode: updated to patch id = 0x01000095 success After update_microcode cpuSetAMDMSR done After cpuSetAMDMSR Enter amd_ht_init() AMD_CB_EventNotify() event class: 05 event: 1004 data: 04 00 00 01 AMD_CB_EventNotify() event class: 05 event: 1004 data: 04 00 01 02 AMD_CB_EventNotify() event class: 05 event: 1004 data: 04 01 01 03 AMD_CB_ManualBUIDSwapList() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 00 02 ff AMD_CB_ManualBUIDSwapList() AMD_CB_EventNotify() event class: 05 event: 2006 data: 04 01 02 00 Exit amd_ht_init() After amd_ht_init cpuSetAMDPCI 00 done cpuSetAMDPCI 01 done cpuSetAMDPCI 02 done cpuSetAMDPCI 03 done Prep FID/VID Node:00 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f24 F3xD8: 03001815 F3xDC: 00005428 Prep FID/VID Node:01 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f24 F3xD8: 03001815 F3xDC: 00005428 Prep FID/VID Node:02 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f24 F3xD8: 03001815 F3xDC: 00005428 Prep FID/VID Node:03 F3x80: e600a681 F3x84: a0e641e6 F3xD4: c3310f24 F3xD8: 03001815 F3xDC: 00005428 setup_remote_node: 01 done Start node 01 done. se tucpor_ere0:mo t e--_-no {de : A 0PI2C IdoDn =e 0S4 tNarODt EnIDod =e 0012 dCOoRnEeI. Dc or=see 00t0u: }p _ -r---e-m- o{t emi _cnAProIdocCeo:IDd 0e =3: ed08oqu nieNOvD alESetIDna rt =tr 0en2ov d iCed OR 0E3 =I Dd o0=nx1 e c.0020o2 }re,A -0 fct-: ue- rrr --efmi-nicn t{ ra lpoc iatzoAPcedeIh_:nC Ii oDddeq e u_== is e0v0ctxal u00peNO0ntD0 0 EArIF00eDT0Ev =R i d 0m si3 ecrtC= ouOR0cpo_Ex1dmID0eb _2:2 =r,ep 0 sato0cucu} rhr-cr ei-end-t tM poema sicstaprcapgoh leco iy dAd =e= :0 Mxee0x0squs010ia000vg0e0a0l0 90e0052nt0 rMmeeimiscvcsr oiracgdo coe ode=0de: 30: ux pp1M0eada2stct2shae,d g ecidt ur0 o r4tope anttaMce pphspasl itay dcg=e h= 0i0x04d b0x0=101 0M000x0e0s0090s00a5950g 0e 0m0is004curccoc c emioMsscdesreo: sca ogupdece dpu:0atS 4edeptadA t tMMcheoDM s psSidaaR tgcet d oh o0a5inepd p Can someone please give me an advice on even how to start to narrow down the problem? I already started to put a 0 in Config Logical CPUs but no changes. :( Thx, Knut Kujat.

7 18

Porting to RS780/SB700 board
by Ed Swierk 05 May '10

05 May '10

I'm attempting to port Coreboot to an Asus M4A78XTD board, which has an RS780/SB700 chipset with a socket AM3 (Fam10h+DDR3) CPU. Starting with the tilapia_10h mainboard code, the first problem I'm hitting occurs very early on: any attempt to call pci_locate_device(), for example in sb700_lpc_init(), hangs forever (or at least longer than I'm willing to wait), unless I disable all the PCIe bridges on the 780 by inserting the following into enable_rs780_dev8(): set_nbmisc_enable_bits(PCI_DEV(0, 0, 0), 0x0c, 0, 0x000300fc); If I leave even one of the bridges enabled, I get the hang. See section 2.5.6 in http://support.amd.com/us/Embedded_TechDocs/43291_rs780_rpr_pub_1.01.pdf for a description of this register. With the PCIe bridges out of the picture, I get through memory initialization (woo hoo!), but for some reason ram_fill() and ram_verify() take many minutes to complete, and it hangs shortly thereafter. Boot log attached. Any clues would be appreciated! --Ed

6 15

#146: memalign faild with 4k boundary
by coreboot 05 May '10

05 May '10

#146: memalign faild with 4k boundary -------------------------------------+-------------------------------------- Reporter: wangqingpei@… | Owner: somebody Type: defect | Status: new Priority: blocker | Milestone: Component: libpayload | Version: v2 Keywords: memalign crashed | Dependencies: Patchstatus: there is no patch | -------------------------------------+-------------------------------------- with libpayload/libc/malloc.c memalign, it crash if tring to memalign with 4kb about 4k boundary -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/146> coreboot <http://www.coreboot.org/>

1 3

#153: resume from suspend on epia-m
by coreboot 03 May '10

03 May '10

#153: resume from suspend on epia-m ---------------------------------------+------------------------------------ Reporter: bam <mybigspam@…> | Owner: stepan Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Version: v2 Keywords: s3 suspend epia | Dependencies: Patchstatus: there is no patch | ---------------------------------------+------------------------------------ When I enter suspend mode from linux, the board suspends, but the led is stayed on instead of blinking. On waking up (on button or wol) the board reboots.[[BR]] I've follow instructions in [http://www.coreboot.org/VIA_EPIA-M#Advanced_ACPI] on changing dsdt.c. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/153> coreboot <http://www.coreboot.org/>

1 1

#142: remove #warnings in the code
by coreboot 03 May '10

03 May '10

#142: remove #warnings in the code ---------------------------------+------------------------------------------ Reporter: myles | Owner: somebody Type: defect | Status: new Priority: major | Milestone: Component: coreboot | Version: v2 Keywords: | Dependencies: Patchstatus: there is no patch | ---------------------------------+------------------------------------------ #warnings in the code should be converted to tickets in trac, or fixed. Compiler warnings don't seem to be useful to get things fixed. They also obscure real warnings. The medium-term goal would be to have warning-free compilation. After that -Werror would be nice. It seems like a small thing to ask that code compile without warnings. -- Ticket URL: <http://tracker.coreboot.org/trac/coreboot/ticket/142> coreboot <http://www.coreboot.org/>

1 1

computers with Coreboot BIOS
by Peter Link 01 May '10

01 May '10

Recently I inquired with Inatux Computers, which sells pre-installed systems that include gNewSense and Trisquel, among others, about plans for offering coreboot BIOS as an option. After a few emails back and forth, they quickly added some information on their website on the following page: http://inatux.com/?gnu (text is below) <<<< Free BIOS (Coreboot, etc.): --------------------------- Our computers are not yet available with a Free BIOS, but we are very interested in offering that option in the future. We can build systems with Coreboot as the BIOS, but there will be some limitations as to certain video cards (ATI for 3D), processors, motherboards, memory, WiFi, and other areas as well. Please write us if you are interested. >>>> I think that this is good news, and I hope it gets around. --pete link

4 4

run away pci scan
by Marc Jones 01 May '10

01 May '10

I'm working with amd/mahogany_fam10 mainboard and having problems in ramstage. It is going through pci device scanning when it starts finding the same devices again and malloc memory until it dies. It also looks like it never goes down a bridge, always staying on bus0. The problem starts at CPU: APIC: 03, it starts scanning bus0 again. Enumerating buses... Show all devs...Before Device Enumeration. Root Device: enabled 1, 0 resources APIC_CLUSTER: 0: enabled 1, 0 resources APIC: 00: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources ... normal device init happens..... CPU: APIC: 00 enabled malloc Enter, size 1092, free_mem_ptr 00270000 malloc 00270000 CPU: APIC: 01 enabled malloc Enter, size 1092, free_mem_ptr 00270444 malloc 00270444 CPU: APIC: 02 enabled malloc Enter, size 1092, free_mem_ptr 00270888 malloc 00270888 CPU: APIC: 03 enabled PCI_DOMAIN: 0000 scanning... Anyone have thoughts on what is happening here? Attached complete serial log. Thanks! Marc -- http://se-eng.com

4 4

Re: [coreboot] Warnings
by Nils 01 May '10

01 May '10

Hi Stefan, First of all thanks for the great improvements in Geode (GX2). On 4/30/10 7:50 PM, Stefan Reinauer wrote: > src/northbridge/amd/gx2/chipsetinit.c:271: warning: suggest > parentheses around '-' inside '<<' > This would need help from someone with a GX2 (or willing to check out the data sheets ;-) I would be happy if i could be of any help with this, I have a GX2 board i can test on. I saw your discussion about the warning before and it inspired me to dedicate my spare free time to again update my working rev5446 patches to current trunk. But unfortunately i can`t get it to work anymore on rev5120 and some other rev`s i tried. (Linux errors out with: "hda: lost interrupt") I will send the details in a separate mail. Thanks,Nils

2 1

[commit] r5520 - in trunk/src/superio: ite/it8718f nsc/pc87417 winbond/w83627ehg winbond/w83627hf
by repository service 30 Apr '10

30 Apr '10

Author: stepan Date: Fri Apr 30 22:44:30 2010 New Revision: 5520 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5520 Log: fix superio warnings. interesting side node: most superio .h files have no guards. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/superio/ite/it8718f/it8718f.h trunk/src/superio/ite/it8718f/it8718f_early_serial.c trunk/src/superio/nsc/pc87417/pc87417.h trunk/src/superio/nsc/pc87417/pc87417_early_serial.c trunk/src/superio/winbond/w83627ehg/w83627ehg.h trunk/src/superio/winbond/w83627ehg/w83627ehg_early_init.c trunk/src/superio/winbond/w83627ehg/w83627ehg_early_serial.c trunk/src/superio/winbond/w83627hf/w83627hf.h trunk/src/superio/winbond/w83627hf/w83627hf_early_serial.c Modified: trunk/src/superio/ite/it8718f/it8718f.h ============================================================================== --- trunk/src/superio/ite/it8718f/it8718f.h Fri Apr 30 22:36:02 2010 (r5519) +++ trunk/src/superio/ite/it8718f/it8718f.h Fri Apr 30 22:44:30 2010 (r5520) @@ -30,3 +30,8 @@ #define IT8718F_KBCM 0x06 /* Mouse */ #define IT8718F_IR 0x0a /* Consumer IR */ +#if defined(__PRE_RAM__) && !defined(__ROMCC__) +void it8718f_24mhz_clkin(void); +void it8718f_enable_serial(device_t dev, unsigned iobase); +#endif + Modified: trunk/src/superio/ite/it8718f/it8718f_early_serial.c ============================================================================== --- trunk/src/superio/ite/it8718f/it8718f_early_serial.c Fri Apr 30 22:36:02 2010 (r5519) +++ trunk/src/superio/ite/it8718f/it8718f_early_serial.c Fri Apr 30 22:44:30 2010 (r5520) @@ -64,7 +64,7 @@ it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02); } -static void it8718f_24mhz_clkin(void) +void it8718f_24mhz_clkin(void) { it8718f_enter_conf(); @@ -75,7 +75,7 @@ } /* Enable the peripheral devices on the IT8718F Super I/O chip. */ -static void it8718f_enable_serial(device_t dev, unsigned iobase) +void it8718f_enable_serial(device_t dev, unsigned iobase) { /* (1) Enter the configuration state (MB PnP mode). */ it8718f_enter_conf(); Modified: trunk/src/superio/nsc/pc87417/pc87417.h ============================================================================== --- trunk/src/superio/nsc/pc87417/pc87417.h Fri Apr 30 22:36:02 2010 (r5519) +++ trunk/src/superio/nsc/pc87417/pc87417.h Fri Apr 30 22:44:30 2010 (r5520) @@ -110,3 +110,9 @@ #define PC87417_HAP1 0x14 #define PC87417_XSCNF 0x15 #define PC87417_XWBCNF 0x16 + +#if defined(__PRE_RAM__) && !defined(__ROMCC__) +void pc87417_enable_serial(device_t dev, unsigned iobase); +void pc87417_enable_dev(device_t dev); +#endif + Modified: trunk/src/superio/nsc/pc87417/pc87417_early_serial.c ============================================================================== --- trunk/src/superio/nsc/pc87417/pc87417_early_serial.c Fri Apr 30 22:36:02 2010 (r5519) +++ trunk/src/superio/nsc/pc87417/pc87417_early_serial.c Fri Apr 30 22:44:30 2010 (r5520) @@ -23,7 +23,7 @@ #include <arch/romcc_io.h> #include "pc87417.h" -static void pc87417_enable_serial(device_t dev, unsigned iobase) +void pc87417_enable_serial(device_t dev, unsigned iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); @@ -31,7 +31,7 @@ pnp_set_enable(dev, 1); } -static void pc87417_enable_dev(device_t dev) +void pc87417_enable_dev(device_t dev) { pnp_set_logical_device(dev); pnp_set_enable(dev, 1); Modified: trunk/src/superio/winbond/w83627ehg/w83627ehg.h ============================================================================== --- trunk/src/superio/winbond/w83627ehg/w83627ehg.h Fri Apr 30 22:36:02 2010 (r5519) +++ trunk/src/superio/winbond/w83627ehg/w83627ehg.h Fri Apr 30 22:44:30 2010 (r5520) @@ -44,3 +44,9 @@ #define W83627EHG_GPIO3 ((1 << 8) | 9) #define W83627EHG_GPIO4 ((2 << 8) | 9) #define W83627EHG_GPIO5 ((3 << 8) | 9) + +#if defined(__PRE_RAM__) && !defined(__ROMCC__) +void w83627ehg_enable_dev(device_t dev, unsigned iobase); +void w83627ehg_disable_dev(device_t dev); +void w83627ehg_enable_serial(device_t dev, unsigned iobase); +#endif Modified: trunk/src/superio/winbond/w83627ehg/w83627ehg_early_init.c ============================================================================== --- trunk/src/superio/winbond/w83627ehg/w83627ehg_early_init.c Fri Apr 30 22:36:02 2010 (r5519) +++ trunk/src/superio/winbond/w83627ehg/w83627ehg_early_init.c Fri Apr 30 22:44:30 2010 (r5520) @@ -22,13 +22,13 @@ #include <arch/romcc_io.h> #include "w83627ehg.h" -static void w83627ehg_disable_dev(device_t dev) +void w83627ehg_disable_dev(device_t dev) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); } -static void w83627ehg_enable_dev(device_t dev, unsigned iobase) +void w83627ehg_enable_dev(device_t dev, unsigned iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); Modified: trunk/src/superio/winbond/w83627ehg/w83627ehg_early_serial.c ============================================================================== --- trunk/src/superio/winbond/w83627ehg/w83627ehg_early_serial.c Fri Apr 30 22:36:02 2010 (r5519) +++ trunk/src/superio/winbond/w83627ehg/w83627ehg_early_serial.c Fri Apr 30 22:44:30 2010 (r5520) @@ -35,7 +35,7 @@ outb(0xaa, port); } -static void w83627ehg_enable_serial(device_t dev, unsigned iobase) +void w83627ehg_enable_serial(device_t dev, unsigned iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); Modified: trunk/src/superio/winbond/w83627hf/w83627hf.h ============================================================================== --- trunk/src/superio/winbond/w83627hf/w83627hf.h Fri Apr 30 22:36:02 2010 (r5519) +++ trunk/src/superio/winbond/w83627hf/w83627hf.h Fri Apr 30 22:44:30 2010 (r5520) @@ -113,5 +113,7 @@ #if defined(__PRE_RAM__) && !defined(__ROMCC__) void w83627hf_disable_dev(device_t dev); void w83627hf_enable_dev(device_t dev, unsigned iobase); +void w83627hf_enable_serial(device_t dev, unsigned iobase); +void w83627hf_set_clksel_48(device_t dev); #endif Modified: trunk/src/superio/winbond/w83627hf/w83627hf_early_serial.c ============================================================================== --- trunk/src/superio/winbond/w83627hf/w83627hf_early_serial.c Fri Apr 30 22:36:02 2010 (r5519) +++ trunk/src/superio/winbond/w83627hf/w83627hf_early_serial.c Fri Apr 30 22:44:30 2010 (r5520) @@ -37,7 +37,7 @@ outb(0xaa, port); } -static void w83627hf_enable_serial(device_t dev, unsigned iobase) +void w83627hf_enable_serial(device_t dev, unsigned iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); @@ -47,7 +47,7 @@ pnp_exit_ext_func_mode(dev); } -static inline void w83627hf_set_clksel_48(device_t dev) +void w83627hf_set_clksel_48(device_t dev) { unsigned port = dev >> 8; pnp_enter_ext_func_mode(dev);

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[commit] r5519 - trunk/src/northbridge/amd/lx
by repository service 30 Apr '10

30 Apr '10

Author: myles Date: Fri Apr 30 22:36:02 2010 New Revision: 5519 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5519 Log: Factor out casmap calculation. Gets rid of a warning. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/amd/lx/raminit.c Modified: trunk/src/northbridge/amd/lx/raminit.c ============================================================================== --- trunk/src/northbridge/amd/lx/raminit.c Fri Apr 30 22:30:47 2010 (r5518) +++ trunk/src/northbridge/amd/lx/raminit.c Fri Apr 30 22:36:02 2010 (r5519) @@ -238,46 +238,23 @@ const uint8_t CASDDR[] = { 5, 5, 2, 6, 3, 7, 4, 0 }; /* 1(1.5), 1.5, 2, 2.5, 3, 3.5, 4, 0 */ -static void setCAS(void) +static u8 getcasmap(u32 dimm, u16 glspeed) { -/*;***************************************************************************** -;* -;* setCAS -;* EEPROM byte usage: (18) SDRAM device attributes - CAS latency -;* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5 -;* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1 -;* -;* The CAS setting is based on the information provided in each DIMMs SPD. -;* The speed at which a DIMM can run is described relative to the slowest -;* CAS the DIMM supports. Each speed for the relative CAS settings is -;* checked that it is within the GeodeLink speed. If it isn't within the GeodeLink -;* speed, the CAS setting is removed from the list of good settings for -;* the DIMM. This is done for both DIMMs and the lists are compared to -;* find the lowest common CAS latency setting. If there are no CAS settings -;* in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt. -;* -;* Entry: -;* Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information. -;* Destroys: We really use everything ! -;*****************************************************************************/ - uint16_t glspeed, dimm_speed; - uint8_t spd_byte, casmap0, casmap1, casmap_shift; - msr_t msr; - - glspeed = GeodeLinkSpeed(); + u16 dimm_speed; + u8 spd_byte, casmap, casmap_shift=0; /************************** DIMM0 **********************************/ - casmap0 = spd_read_byte(DIMM0, SPD_ACCEPTABLE_CAS_LATENCIES); - if (casmap0 != 0xFF) { + casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES); + if (casmap != 0xFF) { /* IF -.5 timing is supported, check -.5 timing > GeodeLink */ - spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND); + spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_2ND); if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); if (dimm_speed >= glspeed) { casmap_shift = 1; /* -.5 is a shift of 1 */ /* IF -1 timing is supported, check -1 timing > GeodeLink */ - spd_byte = spd_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD); + spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_3RD); if (spd_byte != 0) { /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); @@ -290,52 +267,53 @@ } } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */ /* set the casmap based on the shift to limit possible CAS settings */ - spd_byte = 31 - __builtin_clz((uint32_t) casmap0); + spd_byte = 31 - __builtin_clz((uint32_t) casmap); /* just want bits in the lower byte since we have to cast to a 32 */ - casmap0 &= 0xFF << (spd_byte - casmap_shift); + casmap &= 0xFF << (spd_byte - casmap_shift); } else { /* No DIMM */ - casmap0 = 0; + casmap = 0; } + return casmap; +} - /************************** DIMM1 **********************************/ - casmap1 = spd_read_byte(DIMM1, SPD_ACCEPTABLE_CAS_LATENCIES); - if (casmap1 != 0xFF) { - /* IF -.5 timing is supported, check -.5 timing > GeodeLink */ - spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_2ND); - if (spd_byte != 0) { - /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); - if (dimm_speed >= glspeed) { - casmap_shift = 1; /* -.5 is a shift of 1 */ - /* IF -1 timing is supported, check -1 timing > GeodeLink */ - spd_byte = spd_read_byte(DIMM1, SPD_SDRAM_CYCLE_TIME_3RD); - if (spd_byte != 0) { - /* Turn SPD ns time into MHZ. Check what the asm does to this math. */ - dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F)); - if (dimm_speed >= glspeed) { - casmap_shift = 2; /* -1 is a shift of 2 */ - } - /* note that the -1 result doesn't need to change the available CAS map */ - } /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */ - } else { - casmap_shift = 0; - } - } /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */ - /* set the casmap based on the shift to limit possible CAS settings */ - spd_byte = 31 - __builtin_clz((uint32_t) casmap1); - /* just want bits in the lower byte since we have to cast to a 32 */ - casmap1 &= 0xFF << (spd_byte - casmap_shift); - } else { /* No DIMM */ - casmap1 = 0; - } +static void setCAS(void) +{ +/*;***************************************************************************** +;* +;* setCAS +;* EEPROM byte usage: (18) SDRAM device attributes - CAS latency +;* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5 +;* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1 +;* +;* The CAS setting is based on the information provided in each DIMMs SPD. +;* The speed at which a DIMM can run is described relative to the slowest +;* CAS the DIMM supports. Each speed for the relative CAS settings is +;* checked that it is within the GeodeLink speed. If it isn't within the GeodeLink +;* speed, the CAS setting is removed from the list of good settings for +;* the DIMM. This is done for both DIMMs and the lists are compared to +;* find the lowest common CAS latency setting. If there are no CAS settings +;* in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt. +;* +;* Entry: +;* Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information. +;* Destroys: We really use everything ! +;*****************************************************************************/ + uint16_t glspeed; + uint8_t spd_byte, casmap0, casmap1; + msr_t msr; + + glspeed = GeodeLinkSpeed(); + + casmap0 = getcasmap(DIMM0, glspeed); + casmap1 = getcasmap(DIMM1, glspeed); /********************* CAS_LAT MAP COMPARE ***************************/ if (casmap0 == 0) { - spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap1)]; + spd_byte = CASDDR[__builtin_ctz(casmap1)]; } else if (casmap1 == 0) { - spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)]; + spd_byte = CASDDR[__builtin_ctz(casmap0)]; } else if ((casmap0 &= casmap1)) { - spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)]; + spd_byte = CASDDR[__builtin_ctz(casmap0)]; } else { print_emerg("DIMM CAS Latencies not compatible\n"); post_code(ERROR_DIFF_DIMMS);

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coreboot April 2010