I'm having difficulty building coreboot with SeaBIOS for use with the development version of QEMU. Two of the bios.bin files (0.5.1 and 0.6.0) downloaded from http://linuxtogo.org/~kevin/SeaBIOS/ work, but when I try to build from source, I get problems. I tried to follow the instructions from http://www.coreboot.org/QEMU_Build_Tutorial and http://www.coreboot.org/SeaBIOS but they make references to coreboot-v2 which doesn't seem to exist and targets/..../Config.lb which doesn't exist in coreboot-v3. I haven't applied the QEMU patches since they don't apply to qemu-0.12 and weren't needed for the downloaded bios.bin files.
I'm using vgabios-cirrus.bin from the coreboot website and pxe-e1000.bin contains 64k of zeros (just to keep QEMU happy). I'd like to be able to compile coreboot from source and boot from the hard disk as normal, not necessarily using SeaBIOS but that seemed like a sensible option.
I ran the following commands:
dd if=/dev/zero of=pxe-e1000.bin bs=64k count=1 wget http://www.coreboot.org/images/0/0d/Vgabios-cirrus.zip unzip Vgabios-cirrus.zip svn co svn://coreboot.org/repository/coreboot-v3 wget 'http://linuxtogo.org/~kevin/SeaBIOS/bios.bin.elf-0.6.0' cd coreboot-v3 make menuconfig # Set ROM size to 128k # Add an ELF payload (payload.elf) cp ../bios.bin.elf-0.6.0 payload.elf make cp -f build/coreboot.rom ../bios.bin qemu -no-reboot -m 256 -L .. -serial /dev/tty
I got lots of output from qemu (below) and it hangs with the VGA BIOS output on the screen.
Any help would be appreciated.
Cheers, Neil.
coreboot-3.0.1177 Wed Apr 28 16:16:49 BST 2010 starting... (console_loglevel=8) Choosing fallback boot. LAR: Attempting to open 'fallback/initram/segment0'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table@0xfffe0000, size 932 LAR: seen member normal/initram/segment0@0xfffe0400, size 440 LAR: seen member normal/stage2/segment0@0xfffe0610, size 1 LAR: seen member normal/stage2/segment1@0xfffe0670, size 19549 LAR: seen member normal/stage2/segment2@0xfffe5320, size 379 LAR: seen member normal/payload/segment0@0xfffe54f0, size 40387 LAR: seen member bootblock@0xffffafc0, size 20480 LAR: File not found! LAR: Run file fallback/initram/segment0 failed: No such file. Fallback failed. Try normal boot LAR: Attempting to open 'normal/initram/segment0'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table@0xfffe0000, size 932 LAR: seen member normal/initram/segment0@0xfffe0400, size 440 LAR: CHECK normal/initram/segment0 @ 0xfffe0400 start 0xfffe0450 len 440 reallen 440 compression 0 entry 0x00000020 loadaddress 0x00000000 Entry point is 0xfffe0470 RAM init code started. Nothing to do. printktest1: If the immediately preceding line does not say "Nothing to do.", then execution did not start at main() Trying absolute call from non-_MAINOBJECT XIP code. Absolute call successful. Done. run_file returns with 0 Done RAM init code Done printk() buffer move LAR: Attempting to open 'normal/stage2/segment0'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table@0xfffe0000, size 932 LAR: seen member normal/initram/segment0@0xfffe0400, size 440 LAR: seen member normal/stage2/segment0@0xfffe0610, size 1 LAR: CHECK normal/stage2/segment0 @ 0xfffe0610 start 0xfffe0660 len 1 reallen 194784 compression 3 entry 0x00002048 loadaddress 0x0000db80 LAR: Compression algorithm #3 (zeroes) used LAR: Attempting to open 'normal/stage2/segment1'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table@0xfffe0000, size 932 LAR: seen member normal/initram/segment0@0xfffe0400, size 440 LAR: seen member normal/stage2/segment0@0xfffe0610, size 1 LAR: seen member normal/stage2/segment1@0xfffe0670, size 19549 LAR: CHECK normal/stage2/segment1 @ 0xfffe0670 start 0xfffe06c0 len 19549 reallen 37740 compression 1 entry 0x00002048 loadaddress 0x00002000 LAR: Compression algorithm #1 (lzma) used LAR: Attempting to open 'normal/stage2/segment2'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table@0xfffe0000, size 932 LAR: seen member normal/initram/segment0@0xfffe0400, size 440 LAR: seen member normal/stage2/segment0@0xfffe0610, size 1 LAR: seen member normal/stage2/segment1@0xfffe0670, size 19549 LAR: seen member normal/stage2/segment2@0xfffe5320, size 379 LAR: CHECK normal/stage2/segment2 @ 0xfffe5320 start 0xfffe5370 len 379 reallen 6164 compression 1 entry 0x00002048 loadaddress 0x0000c36c LAR: Compression algorithm #1 (lzma) used LAR: Attempting to open 'normal/stage2/segment3'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table@0xfffe0000, size 932 LAR: seen member normal/initram/segment0@0xfffe0400, size 440 LAR: seen member normal/stage2/segment0@0xfffe0610, size 1 LAR: seen member normal/stage2/segment1@0xfffe0670, size 19549 LAR: seen member normal/stage2/segment2@0xfffe5320, size 379 LAR: seen member normal/payload/segment0@0xfffe54f0, size 40387 LAR: seen member bootblock@0xffffafc0, size 20480 LAR: File not found! LAR: load_file: No such file 'normal/stage2/segment3' LAR: load_file_segments: All loaded, entry 0x00002048 cpu_phase1: Coldboot: nothing to do. Phase 1: Very early setup... Phase 1: done Show all devs...After phase 1. root(Root Device): enabled 1, 0 resources cpus(CPU: 00): enabled 1, 0 resources domain_0_pci_0_0(PCI: 00:00.0): enabled 1, 0 resources domain_0_pci_1_0(PCI: 00:01.0): enabled 1, 0 resources domain_0_pci_1_1(PCI: 00:01.1): enabled 1, 0 resources domain_0_pci_1_3(PCI: 00:01.3): enabled 1, 0 resources domain_0(PCI_DOMAIN: 0000): enabled 1, 0 resources Phase 2: Early setup... Phase 2: Done. Show all devs...After phase 2. root(Root Device): enabled 1, 0 resources cpus(CPU: 00): enabled 1, 0 resources domain_0_pci_0_0(PCI: 00:00.0): enabled 1, 0 resources domain_0_pci_1_0(PCI: 00:01.0): enabled 1, 0 resources domain_0_pci_1_1(PCI: 00:01.1): enabled 1, 0 resources domain_0_pci_1_3(PCI: 00:01.3): enabled 1, 0 resources domain_0(PCI_DOMAIN: 0000): enabled 1, 0 resources Phase 3: Enumerating buses... dev_phase3_scan: scanning root(Root Device) scan_static_bus for root (Root Device) cpus(CPU: 00) enabled domain_0(PCI_DOMAIN: 0000) enabled domain_0(PCI_DOMAIN: 0000) scanning... dev_phase3_scan: scanning domain_0(PCI_DOMAIN: 0000) pci_domain_scan_bus: calling pci_scan_bus pci_scan_bus start bus->dev domain_0 bus 0 ERROR: pci_scan_bus called with incorrect bus->dev->path.type, path is PCI_DOMAIN: 0000 PCI: pci_scan_bus for bus 00 pci_scan_bus: old_devices domain_0_pci_0_0, dev for this bus domain_0 PCI: scan devfn 0x0 to 0xff PCI: devfn 0x0 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_pci_0_0 pci_get_dev: check dev domain_0_pci_0_0 it has devfn 0x00 PCI: pci_scan_bus pci_get_dev returns dev domain_0_pci_0_0 set_pci_ops: dev domain_0_pci_0_0 already has ops of type 20504349 PCI: 00:00.0 [PCI: 8086:1237] enabled PCI: pci_scan_bus pci_probe_dev returns dev domain_0_pci_0_0 Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x8 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_pci_1_0 pci_get_dev: check dev domain_0_pci_1_0 it has devfn 0x08 PCI: pci_scan_bus pci_get_dev returns dev domain_0_pci_1_0 set_pci_ops: dev domain_0_pci_1_0 already has ops of type 20504349 PCI: 00:01.0 [PCI: 8086:7000] enabled PCI: pci_scan_bus pci_probe_dev returns dev domain_0_pci_1_0 PCI: devfn 0x9 pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_pci_1_1 pci_get_dev: check dev domain_0_pci_1_1 it has devfn 0x09 PCI: pci_scan_bus pci_get_dev returns dev domain_0_pci_1_1 set_pci_ops: dev domain_0_pci_1_1 already has ops of type 20504349 PCI: 00:01.1 [PCI: 8086:7010] enabled PCI: pci_scan_bus pci_probe_dev returns dev domain_0_pci_1_1 PCI: devfn 0xa pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_pci_1_3 pci_get_dev: check dev domain_0_pci_1_3 it has devfn 0x0b PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xa, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) PCI: devfn 0xb pci_get_dev: list is NOT NULL, *list is NOT NULL pci_get_dev: check dev domain_0_pci_1_3 pci_get_dev: check dev domain_0_pci_1_3 it has devfn 0x0b PCI: pci_scan_bus pci_get_dev returns dev domain_0_pci_1_3 set_pci_ops: dev domain_0_pci_1_3 already has ops of type 20504349 PCI: 00:01.3 [PCI: 8086:7113] enabled PCI: pci_scan_bus pci_probe_dev returns dev domain_0_pci_1_3 PCI: devfn 0xc pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xc, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) PCI: devfn 0xd pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xd, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) PCI: devfn 0xe pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xe, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) PCI: devfn 0xf pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xf, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) PCI: devfn 0x10 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) new_device: devcnt 1 find_device_operations: check all_device_operations[0] find_device_operations: cons id PCI: 1013:00b8 find_device_operations: match PCI: 1013:00b8 constructor: constructor has ID PCI: 1013:00b8 default device constructor called set_pci_ops: dev dynamic PCI: 00:02.0 already has ops of type 20504349 PCI: 00:02.0 [PCI: 1013:00b8] enabled PCI: pci_scan_bus pci_probe_dev returns dev dynamic PCI: 00:02.0 Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x18 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) new_device: devcnt 2 find_device_operations: check all_device_operations[0] find_device_operations: cons id PCI: 1013:00b8 find_device_operations: check all_device_operations[1] find_device_operations: cons id PCI_DOMAIN: 8086:7190 find_device_operations: check all_device_operations[2] find_device_operations: cons id PCI: 8086:1237 find_device_operations: check all_device_operations[3] find_device_operations: cons id PCI: 8086:7000 find_device_operations: check all_device_operations[4] find_device_operations: cons id PCI: 8086:7010 find_device_operations: check all_device_operations[5] find_device_operations: cons id PCI: 8086:7113 No ops found and no constructor called for PCI: 8086:100e. find_device_operations: check all_device_operations[0] find_device_operations: cons id PCI: 1013:00b8 find_device_operations: check all_device_operations[1] find_device_operations: cons id PCI_DOMAIN: 8086:7190 find_device_operations: check all_device_operations[2] find_device_operations: cons id PCI: 8086:1237 find_device_operations: check all_device_operations[3] find_device_operations: cons id PCI: 8086:7000 find_device_operations: check all_device_operations[4] find_device_operations: cons id PCI: 8086:7010 find_device_operations: check all_device_operations[5] find_device_operations: cons id PCI: 8086:7113 set_pci_ops: dev dynamic PCI: 00:03.0 set ops to type 0 PCI: 00:03.0 [PCI: 8086:100e] enabled PCI: pci_scan_bus pci_probe_dev returns dev dynamic PCI: 00:03.0 Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x20 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x20, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x28 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x28, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x30 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x30, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x38 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x38, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x40 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x40, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x48 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x48, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x50 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x50, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x58 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x58, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x60 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x60, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x68 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x68, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x70 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x70, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x78 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x78, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x80 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x80, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x88 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x88, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x90 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x90, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0x98 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0x98, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xa0 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xa0, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xa8 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xa8, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xb0 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xb0, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xb8 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xb8, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xc0 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xc0, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xc8 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xc8, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xd0 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xd0, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xd8 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xd8, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xe0 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xe0, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xe8 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xe8, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xf0 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xf0, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: devfn 0xf8 pci_get_dev: list is NOT NULL, *list is NULL PCI: pci_scan_bus pci_get_dev returns dev None (no dev in tree yet) PCI: devfn 0xf8, bad id 0xffffffff PCI: pci_scan_bus pci_probe_dev returns dev None (no response) Not a multi function device, or the device is not present. Skip to next device. PCI: Done for loop dev_phase3_scan: busdevice domain_0_pci_0_0: enabled 1 ops NOT NULL dev_phase3_scan: can not scan from here, returning 0 dev_phase3_scan: busdevice domain_0_pci_1_0: enabled 1 ops NOT NULL dev_phase3_scan: can not scan from here, returning 0 dev_phase3_scan: busdevice domain_0_pci_1_1: enabled 1 ops NOT NULL dev_phase3_scan: can not scan from here, returning 0 dev_phase3_scan: busdevice domain_0_pci_1_3: enabled 1 ops NOT NULL dev_phase3_scan: can not scan from here, returning 0 dev_phase3_scan: busdevice dynamic PCI: 00:02.0: enabled 1 ops NOT NULL dev_phase3_scan: can not scan from here, returning 0 dev_phase3_scan: busdevice dynamic PCI: 00:03.0: enabled 1 ops NOT NULL dev_phase3_scan: can not scan from here, returning 0 PCI: pci_scan_bus returning with curr_bus=000 dev_phase3_scan: returning 0 scan_static_bus for root(Root Device) done dev_phase3_scan: returning 0 Phase 3: Done. Show all devs in tree form...After phase 3. root(Root Device): enabled 1, 0 resources cpus(CPU: 00): enabled 1, 0 resources domain_0(PCI_DOMAIN: 0000): enabled 1, 0 resources domain_0_pci_0_0(PCI: 00:00.0): enabled 1, 0 resources domain_0_pci_1_0(PCI: 00:01.0): enabled 1, 0 resources domain_0_pci_1_1(PCI: 00:01.1): enabled 1, 0 resources domain_0_pci_1_3(PCI: 00:01.3): enabled 1, 0 resources dynamic PCI: 00:02.0(PCI: 00:02.0): enabled 1, 0 resources dynamic PCI: 00:03.0(PCI: 00:03.0): enabled 1, 0 resources Phase 4: Allocating resources... Phase 4: Reading resources... read_resources: root(Root Device) read_resources bus 0 link: 0 read_resources: root(Root Device) dtsname cpus enabled 1 read_resources: cpus(CPU: 00) missing phase4_read_resources read_resources: root(Root Device) dtsname domain_0 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) read_resources bus 0 link: 0 read_resources: domain_0(PCI_DOMAIN: 0000) dtsname domain_0_pci_0_0 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) dtsname domain_0_pci_1_0 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) dtsname domain_0_pci_1_1 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) dtsname domain_0_pci_1_3 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) dtsname dynamic PCI: 00:02.0 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) dtsname dynamic PCI: 00:03.0 enabled 1 read_resources: domain_0(PCI_DOMAIN: 0000) read_resources bus 0 link: 0 done read_resources: root(Root Device) read_resources bus 0 link: 0 done Phase 4: Done reading resources. Phase 4: Constrain resources. Show resources in subtree (root)...Original. Root Device links 1 child on link 0 cpus CPU: 00 links 0 child on link 0 NULL PCI_DOMAIN: 0000 links 1 child on link 0 domain_0_pci_0_0 PCI_DOMAIN: 0000 resource base 1000 size 0 align 0 gran 0 limit ffff flags 400c0100 index 10000000 PCI_DOMAIN: 0000 resource base c0000 size 0 align 0 gran 0 limit febfffff flags 400c0200 index 10000100 PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI: 00:00.0 links 0 child on link 0 NULL PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit bfff flags c0040200 index 1 PCI: 00:01.0 links 0 child on link 0 NULL PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags e0000100 index 0 PCI: 00:01.1 links 0 child on link 0 NULL PCI: 00:01.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:01.3 links 0 child on link 0 NULL PCI: 00:02.0 links 0 child on link 0 NULL PCI: 00:02.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffff flags 1200 index 10 PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:02.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:03.0 links 0 child on link 0 NULL PCI: 00:03.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 PCI: 00:03.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 14 PCI: 00:03.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI_DOMAIN: 0000 compute_resource_needs_io: base: 1000 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:03.0 14 * [0x1000 - 0x103f] io PCI: 00:01.1 20 * [0x1040 - 0x104f] io PCI_DOMAIN: 0000 compute_resource_needs_io: base: 1050 size: 50 align: 6 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resource_needs_mem: base: c0000 size: 0 align: 0 gran: 0 limit: febfffff PCI: 00:02.0 10 * [0x2000000 - 0x3ffffff] prefmem PCI: 00:03.0 10 * [0x4000000 - 0x401ffff] mem PCI: 00:02.0 30 * [0x4020000 - 0x402ffff] mem PCI: 00:03.0 30 * [0x4030000 - 0x403ffff] mem PCI: 00:02.0 14 * [0x4040000 - 0x4040fff] mem PCI_DOMAIN: 0000 compute_resource_needs_mem: base: 4041000 size: 2041000 align: 25 gran: 0 limit: febfffff done Show resources in subtree (root)...After summations. Root Device links 1 child on link 0 cpus CPU: 00 links 0 child on link 0 NULL PCI_DOMAIN: 0000 links 1 child on link 0 domain_0_pci_0_0 PCI_DOMAIN: 0000 resource base 1000 size 50 align 6 gran 0 limit ffff flags 400c0100 index 10000000 PCI_DOMAIN: 0000 resource base c0000 size 2041000 align 25 gran 0 limit febfffff flags 400c0200 index 10000100 PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI: 00:00.0 links 0 child on link 0 NULL PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit bfff flags c0040200 index 1 PCI: 00:01.0 links 0 child on link 0 NULL PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags e0000100 index 0 PCI: 00:01.1 links 0 child on link 0 NULL PCI: 00:01.1 resource base 1040 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:01.3 links 0 child on link 0 NULL PCI: 00:02.0 links 0 child on link 0 NULL PCI: 00:02.0 resource base 2000000 size 2000000 align 25 gran 25 limit ffffffff flags 1200 index 10 PCI: 00:02.0 resource base 4040000 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:02.0 resource base 4020000 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:03.0 links 0 child on link 0 NULL PCI: 00:03.0 resource base 4000000 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 PCI: 00:03.0 resource base 1000 size 40 align 6 gran 6 limit ffff flags 100 index 14 PCI: 00:03.0 resource base 4030000 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 Allocating VGA resource PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Show resources in subtree (root)...After VGA. Root Device links 1 child on link 0 cpus CPU: 00 links 0 child on link 0 NULL PCI_DOMAIN: 0000 links 1 child on link 0 domain_0_pci_0_0 PCI_DOMAIN: 0000 resource base 1000 size 50 align 6 gran 0 limit ffff flags 400c0100 index 10000000 PCI_DOMAIN: 0000 resource base fc000000 size 2041000 align 25 gran 0 limit febfffff flags 400c0200 index 10000100 PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI: 00:00.0 links 0 child on link 0 NULL PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit bfff flags c0040200 index 1 PCI: 00:01.0 links 0 child on link 0 NULL PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags e0000100 index 0 PCI: 00:01.1 links 0 child on link 0 NULL PCI: 00:01.1 resource base 1040 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:01.3 links 0 child on link 0 NULL PCI: 00:02.0 links 0 child on link 0 NULL PCI: 00:02.0 resource base 2000000 size 2000000 align 25 gran 25 limit ffffffff flags 1200 index 10 PCI: 00:02.0 resource base 4040000 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:02.0 resource base 4020000 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:03.0 links 0 child on link 0 NULL PCI: 00:03.0 resource base 4000000 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 PCI: 00:03.0 resource base 1000 size 40 align 6 gran 6 limit ffff flags 100 index 14 PCI: 00:03.0 resource base 4030000 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI_DOMAIN: 0000 assign_resource_values_io: base:1000 size:50 align:6 gran:0 limit:ffff Assigned: PCI: 00:03.0 14 * [0x1000 - 0x103f] io Assigned: PCI: 00:01.1 20 * [0x1040 - 0x104f] io PCI_DOMAIN: 0000 assign_resource_values_io: next_base: 1050 size: 50 align: 6 gran: 0 done PCI_DOMAIN: 0000 assign_resource_values_mem: base:fc000000 size:2041000 align:25 gran:0 limit:febfffff Assigned: PCI: 00:02.0 10 * [0xfc000000 - 0xfdffffff] prefmem Assigned: PCI: 00:03.0 10 * [0xfe000000 - 0xfe01ffff] mem Assigned: PCI: 00:02.0 30 * [0xfe020000 - 0xfe02ffff] mem Assigned: PCI: 00:03.0 30 * [0xfe030000 - 0xfe03ffff] mem Assigned: PCI: 00:02.0 14 * [0xfe040000 - 0xfe040fff] mem PCI_DOMAIN: 0000 assign_resource_values_mem: next_base: fe041000 size: 2041000 align: 25 gran: 0 done Show resources in subtree (root)...After assigning values. Root Device links 1 child on link 0 cpus CPU: 00 links 0 child on link 0 NULL PCI_DOMAIN: 0000 links 1 child on link 0 domain_0_pci_0_0 PCI_DOMAIN: 0000 resource base 1000 size 50 align 6 gran 0 limit ffff flags 400c0100 index 10000000 PCI_DOMAIN: 0000 resource base fc000000 size 2041000 align 25 gran 0 limit febfffff flags 400c0200 index 10000100 PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI: 00:00.0 links 0 child on link 0 NULL PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit bfff flags c0040200 index 1 PCI: 00:01.0 links 0 child on link 0 NULL PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags e0000100 index 0 PCI: 00:01.1 links 0 child on link 0 NULL PCI: 00:01.1 resource base 1040 size 10 align 4 gran 4 limit ffff flags 40000100 index 20 PCI: 00:01.3 links 0 child on link 0 NULL PCI: 00:02.0 links 0 child on link 0 NULL PCI: 00:02.0 resource base fc000000 size 2000000 align 25 gran 25 limit ffffffff flags 40001200 index 10 PCI: 00:02.0 resource base fe040000 size 1000 align 12 gran 12 limit ffffffff flags 40000200 index 14 PCI: 00:02.0 resource base fe020000 size 10000 align 16 gran 16 limit ffffffff flags 40002200 index 30 PCI: 00:03.0 links 0 child on link 0 NULL PCI: 00:03.0 resource base fe000000 size 20000 align 17 gran 17 limit ffffffff flags 40000200 index 10 PCI: 00:03.0 resource base 1000 size 40 align 6 gran 6 limit ffff flags 40000100 index 14 PCI: 00:03.0 resource base fe030000 size 10000 align 16 gran 16 limit ffffffff flags 40002200 index 30 Phase 4: Setting resources... phase4_set_resources(root) Root Device, bus 0 link: 0 phase4_set_resources(domain_0) PCI_DOMAIN: 0000, bus 0 link: 0 Using CMOS settings of 245760 kB RAM. Adding RAM resource (655360 bytes) Adding RAM resource (250871808 bytes) PCI: 00:01.1 20 <- [0x0000001040 - 0x000000104f] size 0x00000010 gran 0x04 io pci_set_resource PCI: 00:02.0 10 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran 0x19 prefmem pci_set_resource PCI: 00:02.0 14 <- [0x00fe040000 - 0x00fe040fff] size 0x00001000 gran 0x0c mem pci_set_resource PCI: 00:02.0 30 <- [0x00fe020000 - 0x00fe02ffff] size 0x00010000 gran 0x10 romem pci_set_resource PCI: 00:03.0 10 <- [0x00fe000000 - 0x00fe01ffff] size 0x00020000 gran 0x11 mem pci_set_resource PCI: 00:03.0 14 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io pci_set_resource PCI: 00:03.0 30 <- [0x00fe030000 - 0x00fe03ffff] size 0x00010000 gran 0x10 romem pci_set_resource phase4_set_resources(domain_0) PCI_DOMAIN: 0000 done, bus 0 link: 0 phase4_set_resources(root) Root Device done, bus 0 link: 0 Show resources in subtree (root)...After setting resources. Root Device links 1 child on link 0 cpus CPU: 00 links 0 child on link 0 NULL PCI_DOMAIN: 0000 links 1 child on link 0 domain_0_pci_0_0 PCI_DOMAIN: 0000 resource base 1000 size 50 align 6 gran 0 limit ffff flags 400c0100 index 10000000 PCI_DOMAIN: 0000 resource base fc000000 size 2041000 align 25 gran 0 limit febfffff flags 400c0200 index 10000100 PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI: 00:00.0 links 0 child on link 0 NULL PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit bfff flags c0040200 index 1 PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a PCI: 00:00.0 resource base c0000 size ef40000 align 0 gran 0 limit 0 flags e0004200 index b PCI: 00:01.0 links 0 child on link 0 NULL PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit 0 flags e0000100 index 0 PCI: 00:01.1 links 0 child on link 0 NULL PCI: 00:01.1 resource base 1040 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:01.3 links 0 child on link 0 NULL PCI: 00:02.0 links 0 child on link 0 NULL PCI: 00:02.0 resource base fc000000 size 2000000 align 25 gran 25 limit ffffffff flags 60001200 index 10 PCI: 00:02.0 resource base fe040000 size 1000 align 12 gran 12 limit ffffffff flags 60000200 index 14 PCI: 00:02.0 resource base fe020000 size 10000 align 16 gran 16 limit ffffffff flags 60002200 index 30 PCI: 00:03.0 links 0 child on link 0 NULL PCI: 00:03.0 resource base fe000000 size 20000 align 17 gran 17 limit ffffffff flags 60000200 index 10 PCI: 00:03.0 resource base 1000 size 40 align 6 gran 6 limit ffff flags 60000100 index 14 PCI: 00:03.0 resource base fe030000 size 10000 align 16 gran 16 limit ffffffff flags 60002200 index 30 Phase 4: Done allocating resources. Show all devs...After phase 4. root(Root Device): enabled 1, 0 resources cpus(CPU: 00): enabled 1, 0 resources domain_0_pci_0_0(PCI: 00:00.0): enabled 1, 3 resources domain_0_pci_1_0(PCI: 00:01.0): enabled 1, 1 resources domain_0_pci_1_1(PCI: 00:01.1): enabled 1, 1 resources domain_0_pci_1_3(PCI: 00:01.3): enabled 1, 0 resources domain_0(PCI_DOMAIN: 0000): enabled 1, 4 resources dynamic PCI: 00:02.0(PCI: 00:02.0): enabled 1, 3 resources dynamic PCI: 00:03.0(PCI: 00:03.0): enabled 1, 3 resources Phase 5: Enabling resources... dev_phase5: cpus(CPU: 00) missing ops PCI: 00:01.0: Setting subsystem VID/DID to 1af4/1100 pci_dev_enable_resources: domain_0_pci_1_0 (PCI: 00:01.0) cmd <- 147 PCI: 00:01.1: Setting subsystem VID/DID to 1af4/1100 pci_dev_enable_resources: domain_0_pci_1_1 (PCI: 00:01.1) cmd <- 141 PCI: 00:01.3: Setting subsystem VID/DID to 1af4/1100 pci_dev_enable_resources: domain_0_pci_1_3 (PCI: 00:01.3) cmd <- 140 PCI: 00:02.0: Device not on_mainboard pci_dev_enable_resources: dynamic PCI: 00:02.0 (PCI: 00:02.0) cmd <- 143 PCI: 00:03.0: Device not on_mainboard pci_dev_enable_resources: dynamic PCI: 00:03.0 (PCI: 00:03.0) cmd <- 143 Phase 5: Done. Show all devs...After phase 5. root(Root Device): enabled 1, 0 resources cpus(CPU: 00): enabled 1, 0 resources domain_0_pci_0_0(PCI: 00:00.0): enabled 1, 3 resources domain_0_pci_1_0(PCI: 00:01.0): enabled 1, 1 resources domain_0_pci_1_1(PCI: 00:01.1): enabled 1, 1 resources domain_0_pci_1_3(PCI: 00:01.3): enabled 1, 0 resources domain_0(PCI_DOMAIN: 0000): enabled 1, 4 resources dynamic PCI: 00:02.0(PCI: 00:02.0): enabled 1, 3 resources dynamic PCI: 00:03.0(PCI: 00:03.0): enabled 1, 3 resources Phase 6: Initializing devices... Phase 6: Root Device init. Phase 6: PCI_DOMAIN: 0000 init. Phase 6: PCI: 00:00.0 init. Phase 6: PCI: 00:01.0 init. Initializing realtime clock. RTC: Checksum invalid zeroing cmos Invalid coreboot CMOS checksum. Phase 6: PCI: 00:01.1 init. Enabling IDE channel 1 Enabling IDE channel 2 Enabling Legacy IDE Phase 6: PCI: 00:01.3 init. Enabling SMBus. Enable Power Management Functions Phase 6: PCI: 00:02.0 init. Init VGA device PCI: pci_dev_init dynamic PCI: 00:02.0 Probing for option ROM ROM address for PCI: 00:02.0 = c0000 PCI Expansion ROM, signature 0xaa55, INIT size 0x8c00, data ptr 0x0038 PCI ROM Image, @0x000c003c, Vendor 1013, Device 00b8, PCI ROM Image, Class Code 030000, Code Type 00 Phase 6: PCI: 00:03.0 init. PCI: pci_dev_init dynamic PCI: 00:03.0 Probing for option ROM ROM address for PCI: 00:03.0 = fe030000 PCI Expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000 Incorrect Expansion ROM Header Signature 0000 Phase 6: Devices initialized. Show all devs...After phase 6. root(Root Device): enabled 1, 0 resources cpus(CPU: 00): enabled 1, 0 resources domain_0_pci_0_0(PCI: 00:00.0): enabled 1, 3 resources domain_0_pci_1_0(PCI: 00:01.0): enabled 1, 1 resources domain_0_pci_1_1(PCI: 00:01.1): enabled 1, 1 resources domain_0_pci_1_3(PCI: 00:01.3): enabled 1, 0 resources domain_0(PCI_DOMAIN: 0000): enabled 1, 4 resources dynamic PCI: 00:02.0(PCI: 00:02.0): enabled 1, 3 resources dynamic PCI: 00:03.0(PCI: 00:03.0): enabled 1, 3 resources cpu_phase2: Coldboot: nothing to do. search_global_resources: mask 4200 type 4200 search_global_resources: dev root, #resources 0 search_global_resources: dev cpus, #resources 0 search_global_resources: dev domain_0_pci_0_0, #resources 3 search_global_resources: dev domain_0_pci_0_0, resource 0, flags c0040200 base 0xa0000 size 0x20000 search_global_resources: dev domain_0_pci_0_0, resource 1, flags e0004200 base 0x0 size 0xa0000 search_global_resources: dev domain_0_pci_0_0, resource 2, flags e0004200 base 0xc0000 size 0xef40000 search_global_resources: dev domain_0_pci_1_0, #resources 1 search_global_resources: dev domain_0_pci_1_0, resource 0, flags e0000100 base 0x0 size 0x1000 search_global_resources: dev domain_0_pci_1_1, #resources 1 search_global_resources: dev domain_0_pci_1_1, resource 0, flags 60000100 base 0x1040 size 0x10 search_global_resources: dev domain_0_pci_1_3, #resources 0 search_global_resources: dev domain_0, #resources 4 search_global_resources: dev domain_0, resource 0, flags 400c0100 base 0x1000 size 0x50 search_global_resources: dev domain_0, resource 1, flags 400c0200 base 0xfc000000 size 0x2041000 search_global_resources: dev domain_0, resource 2, flags e0000200 base 0xfec00000 size 0x100000 search_global_resources: dev domain_0, resource 3, flags e0000200 base 0xfee00000 size 0x10000 search_global_resources: dev dynamic PCI: 00:02.0, #resources 3 search_global_resources: dev dynamic PCI: 00:02.0, resource 0, flags 60001200 base 0xfc000000 size 0x2000000 search_global_resources: dev dynamic PCI: 00:02.0, resource 1, flags 60000200 base 0xfe040000 size 0x1000 search_global_resources: dev dynamic PCI: 00:02.0, resource 2, flags 60002200 base 0xfe020000 size 0x10000 search_global_resources: dev dynamic PCI: 00:03.0, #resources 3 search_global_resources: dev dynamic PCI: 00:03.0, resource 0, flags 60000200 base 0xfe000000 size 0x20000 search_global_resources: dev dynamic PCI: 00:03.0, resource 1, flags 60000100 base 0x1000 size 0x40 search_global_resources: dev dynamic PCI: 00:03.0, resource 2, flags 60002200 base 0xfe030000 size 0x10000 Multiboot Information structure has been written. LAR: Attempting to open 'normal/option_table'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table@0xfffe0000, size 932 LAR: CHECK normal/option_table @ 0xfffe0000 start 0xfffe0050 len 932 reallen 932 compression 0 entry 0x00000000 loadaddress 0x00000000 search_global_resources: mask 4200 type 4200 search_global_resources: dev root, #resources 0 search_global_resources: dev cpus, #resources 0 search_global_resources: dev domain_0_pci_0_0, #resources 3 search_global_resources: dev domain_0_pci_0_0, resource 0, flags c0040200 base 0xa0000 size 0x20000 search_global_resources: dev domain_0_pci_0_0, resource 1, flags e0004200 base 0x0 size 0xa0000 lb_memory_range: start 0x0 size 0xa0000 search_global_resources: dev domain_0_pci_0_0, resource 2, flags e0004200 base 0xc0000 size 0xef40000 lb_memory_range: start 0xc0000 size 0xef40000 search_global_resources: dev domain_0_pci_1_0, #resources 1 search_global_resources: dev domain_0_pci_1_0, resource 0, flags e0000100 base 0x0 size 0x1000 search_global_resources: dev domain_0_pci_1_1, #resources 1 search_global_resources: dev domain_0_pci_1_1, resource 0, flags 60000100 base 0x1040 size 0x10 search_global_resources: dev domain_0_pci_1_3, #resources 0 search_global_resources: dev domain_0, #resources 4 search_global_resources: dev domain_0, resource 0, flags 400c0100 base 0x1000 size 0x50 search_global_resources: dev domain_0, resource 1, flags 400c0200 base 0xfc000000 size 0x2041000 search_global_resources: dev domain_0, resource 2, flags e0000200 base 0xfec00000 size 0x100000 search_global_resources: dev domain_0, resource 3, flags e0000200 base 0xfee00000 size 0x10000 search_global_resources: dev dynamic PCI: 00:02.0, #resources 3 search_global_resources: dev dynamic PCI: 00:02.0, resource 0, flags 60001200 base 0xfc000000 size 0x2000000 search_global_resources: dev dynamic PCI: 00:02.0, resource 1, flags 60000200 base 0xfe040000 size 0x1000 search_global_resources: dev dynamic PCI: 00:02.0, resource 2, flags 60002200 base 0xfe020000 size 0x10000 search_global_resources: dev dynamic PCI: 00:03.0, #resources 3 search_global_resources: dev dynamic PCI: 00:03.0, resource 0, flags 60000200 base 0xfe000000 size 0x20000 search_global_resources: dev dynamic PCI: 00:03.0, resource 1, flags 60000100 base 0x1000 size 0x40 search_global_resources: dev dynamic PCI: 00:03.0, resource 2, flags 60002200 base 0xfe030000 size 0x10000 lb_cleanup_memory_ranges: # entries 2 #0: base 0x00000000 size 0xa0000 #1: base 0x000c0000 size 0xef40000 lb_memory_range: start 0x0 size 0x500 lb_cleanup_memory_ranges: # entries 3 #0: base 0x00000500 size 0x9fb00 #1: base 0x000c0000 size 0xef40000 #2: base 0x00000000 size 0x500 lb_memory_range: start 0xf0000 size 0xd0 lb_cleanup_memory_ranges: # entries 5 #0: base 0x00000000 size 0x500 #1: base 0x00000500 size 0x9fb00 #2: base 0x000c0000 size 0x30000 #3: base 0x000f00d0 size 0xef0ff30 #4: base 0x000f0000 size 0xd0 Wrote coreboot table at: 0x00000500 - 0x00000ad4 checksum 7cf4 Show all devs...After writing tables. root(Root Device): enabled 1, 0 resources cpus(CPU: 00): enabled 1, 0 resources domain_0_pci_0_0(PCI: 00:00.0): enabled 1, 3 resources domain_0_pci_1_0(PCI: 00:01.0): enabled 1, 1 resources domain_0_pci_1_1(PCI: 00:01.1): enabled 1, 1 resources domain_0_pci_1_3(PCI: 00:01.3): enabled 1, 0 resources domain_0(PCI_DOMAIN: 0000): enabled 1, 4 resources dynamic PCI: 00:02.0(PCI: 00:02.0): enabled 1, 3 resources dynamic PCI: 00:03.0(PCI: 00:03.0): enabled 1, 3 resources Stage2 code done. LAR: Attempting to open 'normal/payload/segment0'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table@0xfffe0000, size 932 LAR: seen member normal/initram/segment0@0xfffe0400, size 440 LAR: seen member normal/stage2/segment0@0xfffe0610, size 1 LAR: seen member normal/stage2/segment1@0xfffe0670, size 19549 LAR: seen member normal/stage2/segment2@0xfffe5320, size 379 LAR: seen member normal/payload/segment0@0xfffe54f0, size 40387 LAR: CHECK normal/payload/segment0 @ 0xfffe54f0 start 0xfffe5540 len 40387 reallen 80896 compression 1 entry 0x000fdf82 loadaddress 0x000ec400 LAR: Compression algorithm #1 (lzma) used Decoding error = 1 LAR: Attempting to open 'normal/payload/segment1'. LAR: Start 0xfffe0000 len 0x20000 LAR: seen member normal/option_table@0xfffe0000, size 932 LAR: seen member normal/initram/segment0@0xfffe0400, size 440 LAR: seen member normal/stage2/segment0@0xfffe0610, size 1 LAR: seen member normal/stage2/segment1@0xfffe0670, size 19549 LAR: seen member normal/stage2/segment2@0xfffe5320, size 379 LAR: seen member normal/payload/segment0@0xfffe54f0, size 40387 LAR: seen member bootblock@0xffffafc0, size 20480 LAR: File not found! LAR: load_file: No such file 'normal/payload/segment1' LAR: load_file_segments: All loaded, entry 0x000fdf82
On Wed, Apr 28, 2010 at 10:05 AM, Neil Turton nturton@solarflare.com wrote:
I'm having difficulty building coreboot with SeaBIOS for use with the development version of QEMU.
I'm using vgabios-cirrus.bin from the coreboot website and pxe-e1000.bin contains 64k of zeros (just to keep QEMU happy). I'd like to be able to compile coreboot from source and boot from the hard disk as normal, not necessarily using SeaBIOS but that seemed like a sensible option.
Yes. SeaBIOS or FILO would work fine.
1. svn co svn://coreboot.org/coreboot/trunk coreboot 2. make menuconfig select mainboard emulation qemu select payload (Add a payload) 3. copy FILO or SeaBIOS to coreboot/payload.elf 4. make
The build tutorials are hard to keep up to date. If these steps work for you, let us know. If you have questions, I'll try to help.
Thanks, Myles
Coreboot v2 is what is now known as v4.
ons, 28 04 2010 kl. 10:43 -0600, skrev Myles Watson:
On Wed, Apr 28, 2010 at 10:05 AM, Neil Turton nturton@solarflare.com wrote:
I'm having difficulty building coreboot with SeaBIOS for use with the development version of QEMU.
I'm using vgabios-cirrus.bin from the coreboot website and pxe-e1000.bin contains 64k of zeros (just to keep QEMU happy). I'd like to be able to compile coreboot from source and boot from the hard disk as normal, not necessarily using SeaBIOS but that seemed like a sensible option.
Yes. SeaBIOS or FILO would work fine.
- svn co svn://coreboot.org/coreboot/trunk coreboot
- make menuconfig select mainboard emulation qemu select payload (Add a payload)
- copy FILO or SeaBIOS to coreboot/payload.elf
- make
The build tutorials are hard to keep up to date. If these steps work for you, let us know. If you have questions, I'll try to help.
Thanks, Myles
On Wed, Apr 28, 2010 at 11:11 AM, Anders Jenbo anders@jenbo.dk wrote:
Coreboot v2 is what is now known as v4.
My preference would be to refer to the branches as v1, v2, v3 ... and call the current, supported project coreboot. I think it eliminates confusion.
Thanks, Myles
On Wed, Apr 28, 2010 at 11:11 AM, Anders Jenbo anders@jenbo.dk wrote:
Coreboot v2 is what is now known as v4.
My preference would be to refer to the branches as v1, v2, v3 ... and call the current, supported project coreboot. I think it eliminates confusion.
I meant "reduces confusion". Sorry for the confusion :)
Myles
Hi Myles,
Thanks for the reply. I understand about it being hard to keep the tutorials up to date.
You wrote:
- svn co svn://coreboot.org/coreboot/trunk coreboot
- make menuconfig select mainboard emulation qemu select payload (Add a payload)
- copy FILO or SeaBIOS to coreboot/payload.elf
- make
I've just tried that and I see the VGA BIOS screen before qemu quits. The end of the build phase is below, followed by the serial output. If I omit -no-reboot, it gets stuck in an endless reboot loops. This is using bios.bin.elf-0.6.0 as the payload.
I tried with FILO and got to the boot prompt. I've not worked out how to boot the MBR though. What are the commands to do this?
Cheers, Neil.
[...] CBFSPRINT coreboot.rom
coreboot.rom: 256 kB, bootblocksize 658, romsize 262144, offset 0x0 Alignment: 64 bytes
Name Offset Type Size fallback/romstage 0x0 stage 8117 fallback/coreboot_ram 0x2000 stage 27540 fallback/payload 0x8c00 payload 40443 (empty) 0x12a40 null 185062
coreboot-4.0-r5511 Thu Apr 29 10:30:17 BST 2010 starting... Loading stage image. Check CBFS header at fffffd4e magic is 4f524243 Found CBFS header at fffffd4e Check fallback/romstage CBFS: follow chain: fffc0000 + 38 + 1fb5 + align -> fffc2000 Check fallback/coreboot_ram Stage: loading fallback/coreboot_ram @ 0x100000 (114688 bytes), entry @ 0x100000 Stage: done loading. Jumping to image. coreboot-4.0-r5511 Thu Apr 29 10:30:17 BST 2010 booting... Enumerating buses... Show all devs...Before Device Enumeration. Root Device: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PCI: 00:01.1: enabled 1, 0 resources Compare with tree... Root Device: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 0 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 0 resources PCI: 00:01.1: enabled 1, 0 resources scan_static_bus for Root Device Finding PCI configuration type. PCI: Using configuration type 1 PCI_DOMAIN: 0000 enabled PCI_DOMAIN: 0000 scanning... PCI: pci_scan_bus for bus 00 PCI: 00:00.0 [8086/1237] enabled PCI: 00:01.0 [8086/7000] bus ops PCI: 00:01.0 [8086/7000] enabled PCI: 00:01.1 [8086/7010] ops PCI: 00:01.1 [8086/7010] enabled malloc Enter, size 1092, free_mem_ptr 00118000 malloc 00118000 PCI: 00:01.3 [8086/7113] bus ops PCI: 00:01.3 [8086/7113] enabled malloc Enter, size 1092, free_mem_ptr 00118444 malloc 00118444 PCI: 00:02.0 [1013/00b8] ops PCI: 00:02.0 [1013/00b8] enabled malloc Enter, size 1092, free_mem_ptr 00118888 malloc 00118888 PCI: 00:03.0 [8086/100e] enabled scan_static_bus for PCI: 00:01.0 scan_static_bus for PCI: 00:01.0 done scan_static_bus for PCI: 00:01.3 scan_static_bus for PCI: 00:01.3 done PCI: pci_scan_bus returning with max=000 scan_static_bus for Root Device done done Setting up VGA for PCI: 00:02.0 Setting PCI_BRIDGE_CTL_VGA for bridge PCI_DOMAIN: 0000 Setting PCI_BRIDGE_CTL_VGA for bridge Root Device Allocating resources... Reading resources... Root Device read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 PCI_DOMAIN: 0000 read_resources bus 0 link: 0 done Root Device read_resources bus 0 link: 0 done Done reading resources. Show resources in subtree (Root Device)...After reading. Root Device links 1 child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base 0 size 0 align 0 gran 0 limit ffffffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI: 00:00.0 links 0 child on link 0 NULL PCI: 00:01.0 links 0 child on link 0 NULL PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0000200 index 2 PCI: 00:01.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:01.1 links 0 child on link 0 NULL PCI: 00:01.1 resource base 0 size 10 align 4 gran 4 limit ffff flags 100 index 20 PCI: 00:01.3 links 0 child on link 0 NULL PCI: 00:02.0 links 0 child on link 0 NULL PCI: 00:02.0 resource base 0 size 2000000 align 25 gran 25 limit ffffffff flags 1200 index 10 PCI: 00:02.0 resource base 0 size 1000 align 12 gran 12 limit ffffffff flags 200 index 14 PCI: 00:02.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI: 00:03.0 links 0 child on link 0 NULL PCI: 00:03.0 resource base 0 size 20000 align 17 gran 17 limit ffffffff flags 200 index 10 PCI: 00:03.0 resource base 0 size 40 align 6 gran 6 limit ffff flags 100 index 14 PCI: 00:03.0 resource base 0 size 10000 align 16 gran 16 limit ffffffff flags 2200 index 30 PCI_DOMAIN: 0000 compute_resources_io: base: 0 size: 0 align: 0 gran: 0 limit: ffff PCI: 00:03.0 14 * [0x0 - 0x3f] io PCI: 00:01.1 20 * [0x40 - 0x4f] io PCI_DOMAIN: 0000 compute_resources_io: base: 50 size: 50 align: 6 gran: 0 limit: ffff done PCI_DOMAIN: 0000 compute_resources_mem: base: 0 size: 0 align: 0 gran: 0 limit: ffffffff PCI: 00:02.0 10 * [0x0 - 0x1ffffff] prefmem PCI: 00:03.0 10 * [0x2000000 - 0x201ffff] mem PCI: 00:02.0 30 * [0x2020000 - 0x202ffff] mem PCI: 00:03.0 30 * [0x2030000 - 0x203ffff] mem PCI: 00:02.0 14 * [0x2040000 - 0x2040fff] mem PCI_DOMAIN: 0000 compute_resources_mem: base: 2041000 size: 2041000 align: 25 gran: 0 limit: ffffffff done avoid_fixed_resources: PCI_DOMAIN: 0000 avoid_fixed_resources:@PCI_DOMAIN: 0000 10000000 limit 0000ffff avoid_fixed_resources:@PCI_DOMAIN: 0000 10000100 limit ffffffff constrain_resources: PCI_DOMAIN: 0000 constrain_resources: PCI: 00:00.0 constrain_resources: PCI: 00:01.0 constrain_resources: PCI: 00:01.1 constrain_resources: PCI: 00:01.3 constrain_resources: PCI: 00:02.0 constrain_resources: PCI: 00:03.0 avoid_fixed_resources2: PCI_DOMAIN: 0000@10000000 limit 0000ffff lim->base 00001000 lim->limit 0000ffff avoid_fixed_resources2: PCI_DOMAIN: 0000@10000100 limit ffffffff lim->base 00000000 lim->limit febfffff Setting resources... PCI_DOMAIN: 0000 allocate_resources_io: base:1000 size:50 align:6 gran:0 limit:ffff Assigned: PCI: 00:03.0 14 * [0x1000 - 0x103f] io Assigned: PCI: 00:01.1 20 * [0x1040 - 0x104f] io PCI_DOMAIN: 0000 allocate_resources_io: next_base: 1050 size: 50 align: 6 gran: 0 done PCI_DOMAIN: 0000 allocate_resources_mem: base:fc000000 size:2041000 align:25 gran:0 limit:febfffff Assigned: PCI: 00:02.0 10 * [0xfc000000 - 0xfdffffff] prefmem Assigned: PCI: 00:03.0 10 * [0xfe000000 - 0xfe01ffff] mem Assigned: PCI: 00:02.0 30 * [0xfe020000 - 0xfe02ffff] mem Assigned: PCI: 00:03.0 30 * [0xfe030000 - 0xfe03ffff] mem Assigned: PCI: 00:02.0 14 * [0xfe040000 - 0xfe040fff] mem PCI_DOMAIN: 0000 allocate_resources_mem: next_base: fe041000 size: 2041000 align: 25 gran: 0 done Root Device assign_resources, bus 0 link: 0 RAM size config registers are empty; defaulting to 64 MBytes I would set ram size to 0x10000 Kbytes PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 PCI: 00:01.1 20 <- [0x0000001040 - 0x000000104f] size 0x00000010 gran 0x04 io PCI: 00:02.0 10 <- [0x00fc000000 - 0x00fdffffff] size 0x02000000 gran 0x19 prefmem PCI: 00:02.0 14 <- [0x00fe040000 - 0x00fe040fff] size 0x00001000 gran 0x0c mem PCI: 00:02.0 30 <- [0x00fe020000 - 0x00fe02ffff] size 0x00010000 gran 0x10 romem PCI: 00:03.0 10 <- [0x00fe000000 - 0x00fe01ffff] size 0x00020000 gran 0x11 mem PCI: 00:03.0 14 <- [0x0000001000 - 0x000000103f] size 0x00000040 gran 0x06 io PCI: 00:03.0 30 <- [0x00fe030000 - 0x00fe03ffff] size 0x00010000 gran 0x10 romem PCI_DOMAIN: 0000 assign_resources, bus 0 link: 0 Root Device assign_resources, bus 0 link: 0 Done setting resources. Show resources in subtree (Root Device)...After assigning values. Root Device links 1 child on link 0 PCI_DOMAIN: 0000 PCI_DOMAIN: 0000 links 1 child on link 0 PCI: 00:00.0 PCI_DOMAIN: 0000 resource base 1000 size 50 align 6 gran 0 limit ffff flags 40040100 index 10000000 PCI_DOMAIN: 0000 resource base fc000000 size 2041000 align 25 gran 0 limit febfffff flags 40040200 index 10000100 PCI_DOMAIN: 0000 resource base fec00000 size 100000 align 0 gran 0 limit ffffffff flags e0000200 index 2 PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit ffffffff flags e0000200 index 3 PCI_DOMAIN: 0000 resource base 0 size a0000 align 0 gran 0 limit 0 flags e0004200 index a PCI_DOMAIN: 0000 resource base c0000 size 3f40000 align 0 gran 0 limit 0 flags e0004200 index b PCI: 00:00.0 links 0 child on link 0 NULL PCI: 00:01.0 links 0 child on link 0 NULL PCI: 00:01.0 resource base 0 size 1000 align 0 gran 0 limit ffff flags c0000100 index 1 PCI: 00:01.0 resource base ff800000 size 800000 align 0 gran 0 limit 0 flags c0000200 index 2 PCI: 00:01.0 resource base fec00000 size 1000 align 0 gran 0 limit 0 flags c0000200 index 3 PCI: 00:01.1 links 0 child on link 0 NULL PCI: 00:01.1 resource base 1040 size 10 align 4 gran 4 limit ffff flags 60000100 index 20 PCI: 00:01.3 links 0 child on link 0 NULL PCI: 00:02.0 links 0 child on link 0 NULL PCI: 00:02.0 resource base fc000000 size 2000000 align 25 gran 25 limit febfffff flags 60001200 index 10 PCI: 00:02.0 resource base fe040000 size 1000 align 12 gran 12 limit febfffff flags 60000200 index 14 PCI: 00:02.0 resource base fe020000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30 PCI: 00:03.0 links 0 child on link 0 NULL PCI: 00:03.0 resource base fe000000 size 20000 align 17 gran 17 limit febfffff flags 60000200 index 10 PCI: 00:03.0 resource base 1000 size 40 align 6 gran 6 limit ffff flags 60000100 index 14 PCI: 00:03.0 resource base fe030000 size 10000 align 16 gran 16 limit febfffff flags 60002200 index 30 Done allocating resources. Enabling resources... PCI: 00:00.0 subsystem <- 00/00 PCI: 00:00.0 cmd <- 00 PCI: 00:01.0 cmd <- 07 PCI: 00:01.1 cmd <- 01 PCI: 00:01.3 cmd <- 00 PCI: 00:02.0 cmd <- 03 PCI: 00:03.0 cmd <- 03 done. Initializing devices... Root Device init PCI: 00:00.0 init Check CBFS header at fffffd4e magic is 4f524243 Found CBFS header at fffffd4e Check fallback/romstage CBFS: follow chain: fffc0000 + 38 + 1fb5 + align -> fffc2000 Check fallback/coreboot_ram CBFS: follow chain: fffc2000 + 38 + 6b94 + align -> fffc8c00 Check fallback/payload CBFS: follow chain: fffc8c00 + 38 + 9dfb + align -> fffd2a40 Check CBFS: follow chain: fffd2a40 + 28 + 2d2e6 + align -> fffffd80 CBFS: Could not find file pci8086,1237.rom PCI: 00:01.0 init RTC Init RTC: Checksum invalid zeroing cmos Invalid CMOS LB checksum PCI: 00:01.1 init IDE: Primary IDE interface: on IDE: Secondary IDE interface: on IDE: Access to legacy IDE ports: off PCI: 00:02.0 init Check CBFS header at fffffd4e magic is 4f524243 Found CBFS header at fffffd4e Check fallback/romstage CBFS: follow chain: fffc0000 + 38 + 1fb5 + align -> fffc2000 Check fallback/coreboot_ram CBFS: follow chain: fffc2000 + 38 + 6b94 + align -> fffc8c00 Check fallback/payload CBFS: follow chain: fffc8c00 + 38 + 9dfb + align -> fffd2a40 Check CBFS: follow chain: fffd2a40 + 28 + 2d2e6 + align -> fffffd80 CBFS: Could not find file pci1013,00b8.rom On card, rom address for PCI: 00:02.0 = fe020000 PCI Expansion ROM, signature 0xaa55, INIT size 0x8c00, data ptr 0x0038 PCI ROM Image, Vendor 1013, Device 00b8, PCI ROM Image, Class Code 030000, Code Type 00 copying VGA ROM Image from fe020000 to 0xc0000, 0x8c00 bytes Real mode stub @00000600: 422 bytes Calling Option ROM... ... Option ROM returned. Keyboard init... Keyboard controller output buffer result timeout setting ethernet Assigning IRQ 11 to 0:3.0 i8259_configure_irq_trigger: current interrupts are 0x0 i8259_configure_irq_trigger: try to set interrupts 0x800 PCI: 00:03.0 init Check CBFS header at fffffd4e magic is 4f524243 Found CBFS header at fffffd4e Check fallback/romstage CBFS: follow chain: fffc0000 + 38 + 1fb5 + align -> fffc2000 Check fallback/coreboot_ram CBFS: follow chain: fffc2000 + 38 + 6b94 + align -> fffc8c00 Check fallback/payload CBFS: follow chain: fffc8c00 + 38 + 9dfb + align -> fffd2a40 Check CBFS: follow chain: fffd2a40 + 28 + 2d2e6 + align -> fffffd80 CBFS: Could not find file pci8086,100e.rom On card, rom address for PCI: 00:03.0 = fe030000 PCI Expansion ROM, signature 0x0000, INIT size 0x0000, data ptr 0x0000 Incorrect Expansion ROM Header Signature 0000 Devices initialized Show all devs...After init. Root Device: enabled 1, 0 resources PCI_DOMAIN: 0000: enabled 1, 6 resources PCI: 00:00.0: enabled 1, 0 resources PCI: 00:01.0: enabled 1, 3 resources PCI: 00:01.1: enabled 1, 1 resources PCI: 00:01.3: enabled 1, 0 resources PCI: 00:02.0: enabled 1, 3 resources PCI: 00:03.0: enabled 1, 3 resources Initializing CBMEM area to 0x3ff0000 (65536 bytes) Adding CBMEM entry as no. 1 Moving GDT to 03ff0200...ok High Tables Base is 3ff0000. Copying Interrupt Routing Table to 0x000f0000... done. Adding CBMEM entry as no. 2 Copying Interrupt Routing Table to 0x03ff0400... done. PIRQ table: 128 bytes. Multiboot Information structure has been written. Adding CBMEM entry as no. 3 Writing high table forward entry at 0x00000500 Wrote coreboot table at: 00000500 - 00000518 checksum e7df New low_table_end: 0x00000518 Now going to write high coreboot table at 0x03ff1400 rom_table_end = 0x03ff1400 Adjust low_table_end from 0x00000518 to 0x00001000 Adjust rom_table_end from 0x03ff1400 to 0x04000000 Adding high table area coreboot memory table: 0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES 1. 0000000000001000-000000000009ffff: RAM 2. 00000000000c0000-0000000003feffff: RAM 3. 0000000003ff0000-0000000003ffffff: CONFIGURATION TABLES Wrote coreboot table at: 03ff1400 - 03ff1a4c checksum 6ba1 coreboot table: 1612 bytes. 0. FREE SPACE 03ff3400 0000cc00 1. GDT 03ff0200 00000200 2. IRQ TABLE 03ff0400 00001000 3. COREBOOT 03ff1400 00002000 Check CBFS header at fffffd4e magic is 4f524243 Found CBFS header at fffffd4e Check fallback/romstage CBFS: follow chain: fffc0000 + 38 + 1fb5 + align -> fffc2000 Check fallback/coreboot_ram CBFS: follow chain: fffc2000 + 38 + 6b94 + align -> fffc8c00 Check fallback/payload Got a payload Loading segment from rom address 0xfffc8c38 data (compression=1) malloc Enter, size 36, free_mem_ptr 00118ccc malloc 00118ccc New segment dstaddr 0xec400 memsize 0x13c00 srcaddr 0xfffc8c70 filesize 0x9dc3 (cleaned up) New segment addr 0xec400 size 0x13c00 offset 0xfffc8c70 filesize 0x9dc3 Loading segment from rom address 0xfffc8c54 Entry Point 0x000fdf82 Loading Segment: addr: 0x00000000000ec400 memsz: 0x0000000000013c00 filesz: 0x0000000000009dc3 lb: [0x0000000000100000, 0x000000000011c000) Post relocation: addr: 0x00000000000ec400 memsz: 0x0000000000013c00 filesz: 0x0000000000009dc3 using LZMA lzma: Decoding error = 1 [ 0x00000000000ec400, 00000000000ec400, 0x0000000000100000) <- 00000000fffc8c70 Clearing Segment: addr: 0x00000000000ec400 memsz: 0x0000000000013c00 dest 000ec400, end 00100000, bouncebuffer 3fb8000 Loaded segments Jumping to boot code at fdf82 entry = 0x000fdf82 lb_start = 0x00100000 lb_size = 0x0001c000 adjust = 0x03ed4000 buffer = 0x03fb8000 elf_boot_notes = 0x0010c854 adjusted_boot_notes = 0x03fe0854
Neil Turton wrote:
I tried with FILO and got to the boot prompt. I've not worked out how to boot the MBR though.
FILO is used to boot a kernel from a known partition on local storage. FILO with the GRUB-like interface accepts the same commands as GRUB, except that disk devices are named hda1 and so on. Note never sda. Note this device naming is different than in Linux. Disk devices are assigned names in PCI bus order.
We really do need a command in FILO to print a list of devices. :)
MBR is a BIOS thingy so for that you need SeaBIOS.
//Peter
Check fallback/payload Got a payload Loading segment from rom address 0xfffc8c38 data (compression=1) malloc Enter, size 36, free_mem_ptr 00118ccc malloc 00118ccc New segment dstaddr 0xec400 memsize 0x13c00 srcaddr 0xfffc8c70 filesize 0x9dc3 (cleaned up) New segment addr 0xec400 size 0x13c00 offset 0xfffc8c70 filesize 0x9dc3 Loading segment from rom address 0xfffc8c54 Entry Point 0x000fdf82 Loading Segment: addr: 0x00000000000ec400 memsz: 0x0000000000013c00 filesz: 0x0000000000009dc3 lb: [0x0000000000100000, 0x000000000011c000) Post relocation: addr: 0x00000000000ec400 memsz: 0x0000000000013c00 filesz: 0x0000000000009dc3 using LZMA lzma: Decoding error = 1
I wonder why you get an lzma decoding error. Have you tried not compressing the payload (Kconfig setting)?
Does your version of qemu write protect the BIOS area so that SeaBIOS can't live there? It seems like I had that problem once.
[ 0x00000000000ec400, 00000000000ec400, 0x0000000000100000) <- 00000000fffc8c70 Clearing Segment: addr: 0x00000000000ec400 memsz: 0x0000000000013c00 dest 000ec400, end 00100000, bouncebuffer 3fb8000 Loaded segments Jumping to boot code at fdf82
That's odd. After a decoding error I'm surprised we try to continue.
Good luck, Myles
Hi Peter and Myles,
Thanks for the info about FILO.
Myles Watson wrote:
Does your version of qemu write protect the BIOS area so that SeaBIOS can't live there? It seems like I had that problem once.
That seems to be the problem. I changed IO_MEM_ROM to IO_MEM_RAM for the ISA mapping in the QEMU source code and SeaBIOS booted my hard disk. At least it did once I remembered to put the -hda parameter back onto the qemu command line. ;-)
Thanks for the help.
Cheers, Neil.
-
Anders Jenbo -
Myles Watson -
Neil Turton -
Peter Stuge