coreboot April 2010

coreboot@coreboot.org

64 participants
402 discussions

Dualbios on GA-MA770-UD3
by Vadim Girlin 27 Apr '10

27 Apr '10

Hello, Sorry for my bad english. I'm going to try coreboot on Gigabyte GA-MA770-UD3. It's AMD 770 (RX780 / SB700). I've prepared the image for it based on code for mahogany fam10 with some modifications. I've tried it with simnow using the configuration close to mine as much as possible - it even boots with my native BIOS. And it boots with coreboot image. My motherboard supports hardware dual bios - with two chips on it. I'm going to try flashing backup chip and boot from it. It seems to be possible - I've tested it (flashing at least). Chips on this board could be switched by changing bit 0 at undocumented register EF on LDN 7 of IT8720. I can use slightly patched flashrom for accessing any chip I want without any problems. And this is tested many times. My idea is to use backup chip for debugging - that always keeps my chance to reboot from main bios chip. And removes the need for desoldering etc. But the problems are when I'm trying to boot - and I expected them. It seems that after warm reboot it is trying to boot from selected chip as I want, but reboots againg in a second. AFAIK there is some hardware watchdog on these dualbios motherboards. There are many possibilities - northbridge, southbridge, superio. My main question is - is anybody working on it or may be have some info on it. I definitely will find the way to turn the watchdog off but may be somebody already did that? And second problem is that original bios is checking second chip - and trying to recover it by flashing the bios from main chip on reboot? rewriting coreboot. AFAICS this could be solved by including some signatures etc. It seems to be easy to find out. May be someone is working on this? BTW I can send the patch for flashrom - but I think that with information I mentioned above somebody could make it much better than my ugly hack. I hope the regs should be the same for all latest Gigabyte MBs using IT8720/18 Please, post any info you have that can help me. -- Best regards, Vadim Girlin

9 22

[Coreboot] clean up white space in 440BX raminit.c
by Anders Jenbo 27 Apr '10

27 Apr '10

Remove some additional white space to make it look nicer in nano Signed-off-by: Anders Jenbo <anders(a)jenbo.dk> --- -Anders

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[commit] r5503 - trunk
by repository service 26 Apr '10

26 Apr '10

Author: stepan Date: Mon Apr 26 14:27:18 2010 New Revision: 5503 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5503 Log: For the mainboard with AMD Family 10, if we make clean and make again, it will fail. why? After make clean, .c files created by iasl are still left in the build folder, it will match the rule of $(obj)/%.o: $(obj)/%.c $(obj)/config.h @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -c -o $@ $< it will miss the rule which should be applied. define objs_asl_template .... So we move the .c file back to .hex (or other suffix? or delete?). This patch will work after make distclean, otherwise nobody will rename the .c. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/Makefile Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Mon Apr 26 14:08:51 2010 (r5502) +++ trunk/Makefile Mon Apr 26 14:27:18 2010 (r5503) @@ -226,6 +226,8 @@ iasl -p $$(basename $$@) -tc $$(basename $$(a)).asl mv $$(basename $$(a)).hex $$(basename $$(a)).c $(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $$@))), -DAmlCode=AmlCode_$$(basename $$(notdir $$@))) -c -o $$@ $$(basename $$(a)).c + # keep %.o: %.c rule from catching the temporary .c file after a make clean + mv $$(basename $$(a)).c $$(basename $$(a)).hex endef # macro to define template macros that are used by use_template macro

3 2

Trac reminder: list of new ticket(s)
by coreboot tracker 26 Apr '10

26 Apr '10

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build service results for r5505
by coreboot information 26 Apr '10

26 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 5505 to the coreboot repository. This caused the following changes: Change Log: I meant SSE. Reported by Dustin Harrison. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of amd:serengeti_cheetah_fam10 has been fixed If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r5504
by coreboot information 26 Apr '10

26 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "myles" checked in revision 5504 to the coreboot repository. This caused the following changes: Change Log: Enable SSE2 for ep80579. Reported by Dustin Harrison. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Build Log: Compilation of amd:serengeti_cheetah_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5504&device=serengeti_chee… If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5505 - trunk/src/cpu/intel/ep80579
by repository service 26 Apr '10

26 Apr '10

Author: myles Date: Mon Apr 26 15:33:23 2010 New Revision: 5505 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5505 Log: I meant SSE. Reported by Dustin Harrison. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/cpu/intel/ep80579/Kconfig Modified: trunk/src/cpu/intel/ep80579/Kconfig ============================================================================== --- trunk/src/cpu/intel/ep80579/Kconfig Mon Apr 26 15:27:35 2010 (r5504) +++ trunk/src/cpu/intel/ep80579/Kconfig Mon Apr 26 15:33:23 2010 (r5505) @@ -1,3 +1,3 @@ config CPU_INTEL_EP80579 bool - select SSE2 + select SSE

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[commit] r5504 - trunk/src/cpu/intel/ep80579
by repository service 26 Apr '10

26 Apr '10

Author: myles Date: Mon Apr 26 15:27:35 2010 New Revision: 5504 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5504 Log: Enable SSE2 for ep80579. Reported by Dustin Harrison. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: trunk/src/cpu/intel/ep80579/Kconfig Modified: trunk/src/cpu/intel/ep80579/Kconfig ============================================================================== --- trunk/src/cpu/intel/ep80579/Kconfig Mon Apr 26 14:27:18 2010 (r5503) +++ trunk/src/cpu/intel/ep80579/Kconfig Mon Apr 26 15:27:35 2010 (r5504) @@ -1,2 +1,3 @@ config CPU_INTEL_EP80579 bool + select SSE2

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Patch for enableing 440BX NB to use large memory modules
by Anders Jenbo 26 Apr '10

26 Apr '10

440BX can partially use memory larger then what is supported by seeing them as being a max size supported module. Single sided 512MB (what I used to test), becomes a 128MB. A asymmetric 384MB double sided modules, with 256MB on one side and 128MB on the other. Becomes two sides with 128MB (a 256MB module). This is also enabled in at least some BIOSs (GA-BXC). The patch also cleans up some whitespace. Signed-off-by: Anders Jenbo <anders(a)jenbo.dk> --- Forgot to attach the actual patch... Anders Jenbo

3 2

[commit] r5502 - in trunk/src: arch/i386/lib devices/oprom
by repository service 26 Apr '10

26 Apr '10

Author: stepan Date: Mon Apr 26 14:08:51 2010 New Revision: 5502 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5502 Log: fix a bug in pcibios check. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/arch/i386/lib/c_start.S trunk/src/devices/oprom/x86_asm.S trunk/src/devices/oprom/x86_interrupts.c Modified: trunk/src/arch/i386/lib/c_start.S ============================================================================== --- trunk/src/arch/i386/lib/c_start.S Mon Apr 26 08:59:07 2010 (r5501) +++ trunk/src/arch/i386/lib/c_start.S Mon Apr 26 14:08:51 2010 (r5502) @@ -21,7 +21,7 @@ leal _stack, %edi movl $_estack, %ecx subl %edi, %ecx - shrl $2, %ecx /* it is 32 bit align, right? */ + shrl $2, %ecx /* it is 32 bit aligned, right? */ xorl %eax, %eax rep stosl @@ -31,7 +31,7 @@ movl $_ebss, %ecx subl %edi, %ecx jz .Lnobss - shrl $2, %ecx /* it is 32 bit align, right? */ + shrl $2, %ecx /* it is 32 bit aligned, right? */ xorl %eax, %eax rep stosl @@ -72,20 +72,20 @@ * Now we are finished. Memory is up, data is copied and * bss is cleared. Now we call the main routine and * let it do the rest. - */ + */ post_code(0xfe) /* post fe */ /* Restore the stack location */ movl %ebp, %esp - + /* The boot_complete flag has already been pushed */ call hardwaremain - /*NOTREACHED*/ + /* NOTREACHED */ .Lhlt: post_code(0xee) /* post ee */ hlt jmp .Lhlt - + vec0: pushl $0 /* error code */ pushl $0 /* vector */ @@ -94,103 +94,104 @@ pushl $0 /* error code */ pushl $1 /* vector */ jmp int_hand - + vec2: pushl $0 /* error code */ pushl $2 /* vector */ jmp int_hand - + vec3: pushl $0 /* error code */ pushl $3 /* vector */ jmp int_hand - + vec4: pushl $0 /* error code */ pushl $4 /* vector */ jmp int_hand - + vec5: pushl $0 /* error code */ pushl $5 /* vector */ jmp int_hand - + vec6: pushl $0 /* error code */ pushl $6 /* vector */ jmp int_hand - + vec7: pushl $0 /* error code */ pushl $7 /* vector */ jmp int_hand - + vec8: /* error code */ pushl $8 /* vector */ jmp int_hand .word 0x9090 - + vec9: pushl $0 /* error code */ pushl $9 /* vector */ jmp int_hand - + vec10: /* error code */ pushl $10 /* vector */ jmp int_hand .word 0x9090 - + vec11: /* error code */ pushl $11 /* vector */ jmp int_hand .word 0x9090 - + vec12: /* error code */ pushl $12 /* vector */ jmp int_hand .word 0x9090 - + vec13: /* error code */ pushl $13 /* vector */ jmp int_hand .word 0x9090 - + vec14: /* error code */ pushl $14 /* vector */ jmp int_hand .word 0x9090 - + vec15: pushl $0 /* error code */ pushl $15 /* vector */ jmp int_hand - + vec16: pushl $0 /* error code */ pushl $16 /* vector */ jmp int_hand - + vec17: /* error code */ pushl $17 /* vector */ jmp int_hand .word 0x9090 - + vec18: pushl $0 /* error code */ pushl $18 /* vector */ jmp int_hand - + vec19: pushl $0 /* error code */ pushl $19 /* vector */ jmp int_hand + int_hand: /* At this point on the stack there is: * 0(%esp) vector @@ -232,7 +233,7 @@ .globl gdb_stub_breakpoint gdb_stub_breakpoint: popl %eax /* Return address */ - pushfl + pushfl pushl %cs pushl %eax /* Return address */ pushl $0 /* No error code */ @@ -260,7 +261,7 @@ * * When we're executing code from RAM, we want to do more complex * stuff, like initializing PCI option roms in real mode, or doing - * a resume from a suspend to ram. + * a resume from a suspend to ram. */ gdt: /* selgdt 0, unused */ @@ -271,13 +272,13 @@ .word 0x0000, 0x0000 /* dummy */ .byte 0x00, 0x00, 0x00, 0x00 - /* selgdt 0x10, flat code segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */ + /* selgdt 0x10, flat code segment */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */ /* selgdt 0x18, flat data segment */ - .word 0xffff, 0x0000 - .byte 0x00, 0x93, 0xcf, 0x00 + .word 0xffff, 0x0000 + .byte 0x00, 0x93, 0xcf, 0x00 /* selgdt 0x20, unused */ .word 0x0000, 0x0000 /* dummy */ @@ -285,31 +286,31 @@ /* The next two entries are used for executing VGA option ROMs */ - /* selgdt 0x28 16-bit 64k code at 0x00000000 */ + /* selgdt 0x28 16 bit 64k code at 0x00000000 */ .word 0xffff, 0x0000 .byte 0, 0x9a, 0, 0 - /* selgdt 0x30 16-bit 64k data at 0x00000000 */ + /* selgdt 0x30 16 bit 64k data at 0x00000000 */ .word 0xffff, 0x0000 .byte 0, 0x92, 0, 0 /* The next two entries are used for ACPI S3 RESUME */ - /* selgdt 0x38, flat data segment 16bit */ + /* selgdt 0x38, flat data segment 16 bit */ .word 0x0000, 0x0000 /* dummy */ - .byte 0x00, 0x93, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */ + .byte 0x00, 0x93, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */ - /* selgdt 0x40, flat code segment 16bit */ - .word 0xffff, 0x0000 - .byte 0x00, 0x9b, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */ + /* selgdt 0x40, flat code segment 16 bit */ + .word 0xffff, 0x0000 + .byte 0x00, 0x9b, 0x8f, 0x00 /* G=1 and 0x0f, So we get 4Gbytes for limit */ gdt_end: idtarg: .word _idt_end - _idt - 1 /* limit */ .long _idt - .word 0 + .word 0 _idt: - .fill 20, 8, 0 # idt is unitiailzed + .fill 20, 8, 0 # idt is uninitialized _idt_end: .previous Modified: trunk/src/devices/oprom/x86_asm.S ============================================================================== --- trunk/src/devices/oprom/x86_asm.S Mon Apr 26 08:59:07 2010 (r5501) +++ trunk/src/devices/oprom/x86_asm.S Mon Apr 26 14:08:51 2010 (r5502) @@ -49,8 +49,8 @@ /* Realmode IDT pointer structure. */ .globl __realmode_idt __realmode_idt = RELOCATED(.) - .word 1023 /* 16-bit limit */ - .long 0 /* 24-bit base */ + .word 1023 /* 16 bit limit */ + .long 0 /* 24 bit base */ .word 0 /* Preserve old stack */ @@ -101,14 +101,14 @@ 1: /* Setup a stack: Put the stack at the end of page zero. * That way we can easily share it between real and - * protected, since the 16-bit ESP at segment 0 will + * protected, since the 16 bit ESP at segment 0 will * work for any case. */ mov $0x0, %ax mov %ax, %ss movl $0x1000, %eax movl %eax, %esp - /* Load our 16 bit idt */ + /* Load 16 bit IDT */ xor %ax, %ax mov %ax, %ds lidt __realmode_idt @@ -119,9 +119,9 @@ mov %ax, %gs mov $0x40, %ax mov %ax, %ds - mov %cx, %ax // restore ax /* ************************************ */ + mov %cx, %ax // restore ax // TODO this will not work for non-VGA option ROMs /* run VGA BIOS at 0xc000:0003 */ lcall $0xc000, $0x0003 @@ -201,7 +201,7 @@ 1: /* Setup a stack: Put the stack at the end of page zero. * That way we can easily share it between real and - * protected, since the 16-bit ESP at segment 0 will + * protected, since the 16 bit ESP at segment 0 will * work for any case. */ mov $0x0, %ax mov %ax, %ss @@ -415,12 +415,12 @@ mov $0x0, %ax mov %ax, %ss - /* Restore 16-bit IDT */ + /* Restore 16 bit IDT */ xor %ax, %ax mov %ax, %ds lidt __realmode_idt - /* Set up our segment registers to segment 0x0000 */ + /* Set up segment registers to segment 0x0000 */ mov %ax, %es mov %ax, %fs mov %ax, %gs Modified: trunk/src/devices/oprom/x86_interrupts.c ============================================================================== --- trunk/src/devices/oprom/x86_interrupts.c Mon Apr 26 08:59:07 2010 (r5501) +++ trunk/src/devices/oprom/x86_interrupts.c Mon Apr 26 14:08:51 2010 (r5502) @@ -58,6 +58,11 @@ return 0; } +#define PCI_CONFIG_SPACE_TYPE1 (1 << 0) +#define PCI_CONFIG_SPACE_TYPE2 (1 << 1) +#define PCI_SPECIAL_CYCLE_TYPE1 (1 << 4) +#define PCI_SPECIAL_CYCLE_TYPE2 (1 << 5) + int int1a_handler(struct eregs *regs) { unsigned short func = (unsigned short)regs->eax; @@ -74,6 +79,11 @@ switch (func) { case PCIBIOS_CHECK: regs->edx = 0x20494350; /* ' ICP' */ + regs->eax &= 0xffff0000; /* Clear AH / AL */ + regs->eax |= PCI_CONFIG_SPACE_TYPE1 | PCI_SPECIAL_CYCLE_TYPE1; + // last bus in the system. Hard code to 255 for now. + // dev_enumerate() does not seem to tell us (publically) + regs->ecx = 0xff; regs->edi = 0x00000000; /* protected mode entry */ retval = 0; break; @@ -114,7 +124,7 @@ dev = dev_find_slot(bus, devfn); if (!dev) { printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n", func, bus, devfn); - // idiots. the pcibios guys assumed you'd never pass a bad bus/devfn! + // Or are we supposed to return PCIBIOS_NODEV? regs->eax = PCIBIOS_BADREG; retval = -1; return retval; @@ -164,38 +174,12 @@ { int res = -1; - /* This int15 handler is VIA Tech. specific. Other chipsets need other + /* This int15 handler is Intel IGD. specific. Other chipsets need other * handlers. The right way to do this is to move this handler code into * the mainboard or northbridge code. + * TODO: completely move to mainboards / chipsets. */ switch (regs->eax & 0xffff) { - case 0x5f19: - break; - case 0x5f18: - regs->eax = 0x5f; - // MCLK = 133, 32M frame buffer, 256 M main memory - regs->ebx = 0x545; - regs->ecx = 0x060; - res = 0; - break; - case 0x5f00: - regs->eax = 0x8600; - break; - case 0x5f01: - regs->eax = 0x5f; - regs->ecx = (regs->ecx & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768 - res = 0; - break; - case 0x5f02: - regs->eax = 0x5f; - regs->ebx = (regs->ebx & 0xffff0000) | 2; - regs->ecx = (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only - regs->edx = (regs->edx & 0xffff0000) | 0; // TV Layout - default - res = 0; - break; - case 0x5f0f: - regs->eax = 0x860f; - break; /* And now Intel IGD code */ #define BOOT_DISPLAY_DEFAULT 0 #define BOOT_DISPLAY_CRT (1 << 0) @@ -206,7 +190,6 @@ #define BOOT_DISPLAY_TV2 (1 << 5) #define BOOT_DISPLAY_EFP2 (1 << 6) #define BOOT_DISPLAY_LCD2 (1 << 7) - case 0x5f35: regs->eax = 0x5f; regs->ecx = BOOT_DISPLAY_DEFAULT;

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coreboot April 2010