coreboot April 2010

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[commit] r5497 - in trunk/src: mainboard/asus/a8v-e_se mainboard/asus/m2v-mx_se southbridge/via southbridge/via/k8t890
by repository service 25 Apr '10

25 Apr '10

Author: ruik Date: Sun Apr 25 22:24:09 2010 New Revision: 5497 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5497 Log: Fix the the build of r5494 on Asus A8V-E SE. The K8M890 and K8T890 were not treated separately until now. Fix it. Hope self ack is OK, compiled tested locally. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Modified: trunk/src/mainboard/asus/a8v-e_se/Kconfig trunk/src/mainboard/asus/m2v-mx_se/Kconfig trunk/src/southbridge/via/Makefile.inc trunk/src/southbridge/via/k8t890/Kconfig trunk/src/southbridge/via/k8t890/k8t890_dram.c Modified: trunk/src/mainboard/asus/a8v-e_se/Kconfig ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/Kconfig Sun Apr 25 20:06:32 2010 (r5496) +++ trunk/src/mainboard/asus/a8v-e_se/Kconfig Sun Apr 25 22:24:09 2010 (r5497) @@ -83,4 +83,3 @@ hex default 0x1043 depends on BOARD_ASUS_A8V_E_SE - Modified: trunk/src/mainboard/asus/m2v-mx_se/Kconfig ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/Kconfig Sun Apr 25 20:06:32 2010 (r5496) +++ trunk/src/mainboard/asus/m2v-mx_se/Kconfig Sun Apr 25 22:24:09 2010 (r5497) @@ -25,7 +25,7 @@ select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_VIA_VT8237R - select SOUTHBRIDGE_VIA_K8T890 + select SOUTHBRIDGE_VIA_K8M890 select SUPERIO_ITE_IT8712F select USE_PRINTK_IN_CAR select USE_DCACHE_RAM Modified: trunk/src/southbridge/via/Makefile.inc ============================================================================== --- trunk/src/southbridge/via/Makefile.inc Sun Apr 25 20:06:32 2010 (r5496) +++ trunk/src/southbridge/via/Makefile.inc Sun Apr 25 22:24:09 2010 (r5497) @@ -1,4 +1,5 @@ subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8T890) += k8t890 +subdirs-$(CONFIG_SOUTHBRIDGE_VIA_K8M890) += k8t890 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8231) += vt8231 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8235) += vt8235 subdirs-$(CONFIG_SOUTHBRIDGE_VIA_VT8237R) += vt8237r Modified: trunk/src/southbridge/via/k8t890/Kconfig ============================================================================== --- trunk/src/southbridge/via/k8t890/Kconfig Sun Apr 25 20:06:32 2010 (r5496) +++ trunk/src/southbridge/via/k8t890/Kconfig Sun Apr 25 22:24:09 2010 (r5497) @@ -1,17 +1,20 @@ +config SOUTHBRIDGE_VIA_K8M890 + bool + config SOUTHBRIDGE_VIA_K8T890 bool -config SOUTHBRIDGE_VIA_K8T890_VGA_EN +config SOUTHBRIDGE_VIA_K8M890_VGA_EN bool "Enable onboard K8M890 graphics" default y - depends on SOUTHBRIDGE_VIA_K8T890 + depends on SOUTHBRIDGE_VIA_K8M890 select VGA select GFXUMA choice prompt "Framebuffer size" default K8M890_VIDEO_MB_32MB - depends on SOUTHBRIDGE_VIA_K8T890_VGA_EN + depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN config K8M890_VIDEO_MB_32MB bool "32MB" @@ -33,4 +36,4 @@ default 128 if K8M890_VIDEO_MB_128MB default 256 if K8M890_VIDEO_MB_256MB default -1 if K8M890_VIDEO_MB_CMOS - depends on SOUTHBRIDGE_VIA_K8T890_VGA_EN + depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN Modified: trunk/src/southbridge/via/k8t890/k8t890_dram.c ============================================================================== --- trunk/src/southbridge/via/k8t890/k8t890_dram.c Sun Apr 25 20:06:32 2010 (r5496) +++ trunk/src/southbridge/via/k8t890/k8t890_dram.c Sun Apr 25 22:24:09 2010 (r5497) @@ -98,7 +98,8 @@ msr = rdmsr(TOP_MEM); uma_memory_base = msr.lo - uma_memory_size; - printk(BIOS_INFO, "K8M890: UMA base is %llx size is %d (MB)\n", uma_memory_base, uma_memory_size / 1024 / 1024); + printk(BIOS_INFO, "K8M890: UMA base is %llx size is %u (MB)\n", uma_memory_base, + (u32) (uma_memory_size / 1024 / 1024)); /* enable VGA, so the bridges gets VGA_EN and resources are set */ pci_write_config8(dev, 0xa1, 0x80); #endif @@ -131,7 +132,6 @@ */ unsigned int fbbits = 0; u8 tmp; - int ret; fbbits = ((log2(uma_memory_size >> 20) - 2) << 4); printk(BIOS_INFO, "K8M890: Using a %dMB framebuffer.\n", (unsigned int) (uma_memory_size >> 20));

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build service results for r5496
by coreboot information 25 Apr '10

25 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5496 to the coreboot repository. This caused the following changes: Change Log: try to unify timing initialization across those boards that need it... Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of asus:a8v-e_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5496&device=a8v-e_se&vendo… Compilation of gigabyte:m57sli has been fixed Compilation of msi:ms7260 has been fixed Compilation of msi:ms9282 has been fixed Compilation of nvidia:l1_2pvv has been fixed Compilation of supermicro:h8dme has been fixed Compilation of supermicro:h8dmr has been fixed Compilation of supermicro:h8dmr_fam10 has been fixed Compilation of supermicro:h8qme_fam10 has been fixed Compilation of supermicro:x6dai_g has been fixed Compilation of supermicro:x6dhe_g has been fixed Compilation of tyan:s2912 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

build service results for r5495
by coreboot information 25 Apr '10

25 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 5495 to the coreboot repository. This caused the following changes: Change Log: Only do complete VGA init if a VGABIOS was found and installed. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of asus:a8v-e_se is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5495&device=a8v-e_se&vendo… Compilation of gigabyte:m57sli is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5495&device=m57sli&vendor=… Compilation of msi:ms7260 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5495&device=ms7260&vendor=… Compilation of msi:ms9282 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5495&device=ms9282&vendor=… Compilation of nvidia:l1_2pvv is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5495&device=l1_2pvv&vendor… Compilation of supermicro:h8dme is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5495&device=h8dme&vendor=s… Compilation of supermicro:h8dmr is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5495&device=h8dmr&vendor=s… Compilation of supermicro:h8dmr_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5495&device=h8dmr_fam10&ve… Compilation of supermicro:h8qme_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5495&device=h8qme_fam10&ve… Compilation of supermicro:x6dai_g is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5495&device=x6dai_g&vendor… Compilation of supermicro:x6dhe_g is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5495&device=x6dhe_g&vendor… Compilation of tyan:s2912 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5495&device=s2912&vendor=t… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5496 - in trunk/src: mainboard/asus/a8n_e mainboard/gigabyte/m57sli mainboard/msi/ms7260 mainboard/msi/ms9282 mainboard/msi/ms9652_fam10 mainboard/nvidia/l1_2pvv mainboard/supermicro/h8dm...
by repository service 25 Apr '10

25 Apr '10

Author: stepan Date: Sun Apr 25 20:06:32 2010 New Revision: 5496 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5496 Log: try to unify timing initialization across those boards that need it... Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/asus/a8n_e/romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/supermicro/x6dai_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g/romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/southbridge/intel/esb6300/esb6300_smbus.c trunk/src/southbridge/intel/esb6300/esb6300_smbus.h trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Modified: trunk/src/mainboard/asus/a8n_e/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/romstage.c Sun Apr 25 20:05:42 2010 (r5495) +++ trunk/src/mainboard/asus/a8n_e/romstage.c Sun Apr 25 20:06:32 2010 (r5496) @@ -63,11 +63,6 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "cpu/amd/dualcore/dualcore.c" -static void memreset_setup(void) -{ - /* Nothing to do. */ -} - static void memreset(int controllers, const struct mem_controller *ctrl) { /* Nothing to do. */ @@ -181,7 +176,6 @@ dump_smbus_registers(); #endif - memreset_setup(); sdram_initialize(nodes, ctrl); #if 0 Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Sun Apr 25 20:05:42 2010 (r5495) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Sun Apr 25 20:06:32 2010 (r5496) @@ -265,6 +265,8 @@ } #endif + init_timer(); // Need to use TMICT to synconize FID/VID + needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= mcp55_early_setup_x(); @@ -281,9 +283,7 @@ enable_smbus(); - //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Sun Apr 25 20:05:42 2010 (r5495) +++ trunk/src/mainboard/msi/ms7260/romstage.c Sun Apr 25 20:06:32 2010 (r5496) @@ -237,6 +237,8 @@ } #endif + init_timer(); /* Need to use TMICT to synconize FID/VID. */ + needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= mcp55_early_setup_x(); @@ -253,9 +255,7 @@ enable_smbus(); - /* Do we need apci timer, tsc...., only debug need it for better output */ /* All AP stopped? */ - // init_timer(); /* Need to use TMICT to synconize FID/VID. */ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Sun Apr 25 20:05:42 2010 (r5495) +++ trunk/src/mainboard/msi/ms9282/romstage.c Sun Apr 25 20:06:32 2010 (r5496) @@ -199,16 +199,16 @@ #endif ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn - needs_reset = optimize_link_coherent_ht(); + init_timer(); /* Need to use TMICT to synconize FID/VID. */ - needs_reset |= optimize_link_incoherent_ht(sysinfo); - - needs_reset |= mcp55_early_setup_x(); - - if (needs_reset) { - print_info("ht reset -\n"); - soft_reset(); - } + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + needs_reset |= mcp55_early_setup_x(); + + if (needs_reset) { + print_info("ht reset -\n"); + soft_reset(); + } //It's the time to set ctrl now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); @@ -226,6 +226,5 @@ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); post_cache_as_ram(); - } Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Sun Apr 25 20:05:42 2010 (r5495) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Sun Apr 25 20:06:32 2010 (r5496) @@ -58,6 +58,8 @@ #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" @@ -262,6 +264,7 @@ msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif + init_timer(); /* Need to use TMICT to synconize FID/VID. */ wants_reset = mcp55_early_setup_x(); Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Sun Apr 25 20:05:42 2010 (r5495) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Sun Apr 25 20:06:32 2010 (r5496) @@ -250,6 +250,7 @@ } #endif + init_timer(); /* Need to use TMICT to synconize FID/VID. */ needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); @@ -267,9 +268,7 @@ enable_smbus(); - //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Sun Apr 25 20:05:42 2010 (r5495) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Sun Apr 25 20:06:32 2010 (r5496) @@ -46,16 +46,14 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -// for enable the FAN -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" - #include "pc80/serial.c" #include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> -// #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" +// for enable the FAN +#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -313,7 +311,8 @@ } #endif -#if 1 + init_timer(); /* Need to use TMICT to synconize FID/VID. */ + needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= mcp55_early_setup_x(); @@ -323,7 +322,7 @@ print_info("ht reset -\n"); soft_reset(); } -#endif + allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl in sysinfo now; @@ -331,9 +330,7 @@ enable_smbus(); /* enable in sio_setup */ - //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Sun Apr 25 20:05:42 2010 (r5495) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Sun Apr 25 20:06:32 2010 (r5496) @@ -49,16 +49,14 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -// for enable the FAN -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" - #include "pc80/serial.c" #include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_fxx_rev.h> -//#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" +// for enable the FAN +#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -213,12 +211,10 @@ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if SET_FIDVID == 1 - { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - + printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo); } enable_fid_change(); @@ -231,12 +227,12 @@ { msr_t msr; msr=rdmsr(0xc0010042); - print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - + printk(BIOS_DEBUG, "end msr fid, vid %08x, %08x\n", msr.hi, msr.lo); } #endif -#if 1 + init_timer(); // Need to use TMICT to synconize FID/VID + needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= mcp55_early_setup_x(); @@ -246,7 +242,7 @@ print_info("ht reset -\n"); soft_reset(); } -#endif + allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl in sysinfo now; @@ -254,9 +250,7 @@ // enable_smbus(); /* enable in sio_setup */ - //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Sun Apr 25 20:05:42 2010 (r5495) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Sun Apr 25 20:06:32 2010 (r5496) @@ -44,18 +44,18 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -// for enable the FAN -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "pc80/serial.c" #include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> -//#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" +// for enable the FAN +#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" - +#include "cpu/amd/model_10xxx/apic_timer.c" +#include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" @@ -90,7 +90,7 @@ #include "northbridge/amd/amdfam10/raminit_amdmct.c" #include "northbridge/amd/amdfam10/amdfam10_pci.c" -#include "resourcemap.c" +#include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" @@ -103,8 +103,6 @@ #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" - - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/microcode/microcode.c" @@ -118,23 +116,25 @@ static void sio_setup(void) { - uint32_t dword; - uint8_t byte; - enable_smbus(); -// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ - smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ - - byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b); - byte |= 0x20; - pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0x7b, byte); - - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0); - dword |= (1<<0); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); - - dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4); - dword |= (1<<16); - pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); + uint32_t dword; + uint8_t byte; + + enable_smbus(); + // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ + /* set FAN ctrl to DC mode */ + smbusx_write_byte(1, (0x58 >> 1), 0xb1, 0xff); + + byte = pci_read_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b); + byte |= 0x20; + pci_write_config8(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0x7b, byte); + + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0); + dword |= (1 << 0); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa0, dword); + + dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4); + dword |= (1 << 16); + pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword); } @@ -142,14 +142,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); u32 bsp_apicid = 0; u32 val; u32 wants_reset; msr_t msr; - if (!cpu_init_detectedx && boot_cpu()) { + if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ @@ -160,126 +161,129 @@ /* Setup the mcp55 */ mcp55_enable_rom(); - } + } + + post_code(0x30); - post_code(0x30); - - if (bist == 0) { + if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - } + } - post_code(0x32); + post_code(0x32); pnp_enter_ext_func_mode(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); - w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); - uart_init(); - console_init(); - printk(BIOS_DEBUG, "\n"); + uart_init(); + console_init(); + printk(BIOS_DEBUG, "\n"); /* Halt if there was a built in self test failure */ report_bist_failure(bist); - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); - - /* Setup sysinfo defaults */ - set_sysinfo_in_ram(0); - - update_microcode(val); - post_code(0x33); - - cpuSetAMDMSR(); - post_code(0x34); - - amd_ht_init(sysinfo); - post_code(0x35); - - /* Setup nodes PCI space and start core 0 AP init. */ - finalize_node_setup(sysinfo); - - /* Setup any mainboard PCI settings etc. */ - setup_mb_resource_map(); - post_code(0x36); - - /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: A bunch of cores are going to start output to serial at once. - * It would be nice to fixup prink spinlocks for ROM XIP mode. - * I think it could be done by putting the spinlock flag in the cache - * of the BSP located right after sysinfo. - */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n", sysinfo, sysinfo + 1); + printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); - wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS==1 - /* Core0 on each node is configured. Now setup any additional cores. */ - printk(BIOS_DEBUG, "start_other_cores()\n"); - start_other_cores(); - post_code(0x37); - wait_all_other_cores_started(bsp_apicid); -#endif + /* Setup sysinfo defaults */ + set_sysinfo_in_ram(0); - post_code(0x38); + update_microcode(val); + post_code(0x33); -#if SET_FIDVID == 1 - msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + cpuSetAMDMSR(); + post_code(0x34); + + amd_ht_init(sysinfo); + post_code(0x35); + + /* Setup nodes PCI space and start core 0 AP init. */ + finalize_node_setup(sysinfo); + + /* Setup any mainboard PCI settings etc. */ + setup_mb_resource_map(); + post_code(0x36); + + /* wait for all the APs core0 started by finalize_node_setup. */ - /* FIXME: The sb fid change may survive the warm reset and only - * need to be done once.*/ + /* FIXME: A bunch of cores are going to start output to serial at once. + * It would be nice to fixup prink spinlocks for ROM XIP mode. + * I think it could be done by putting the spinlock flag in the cache + * of the BSP located right after sysinfo. + */ - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - post_code(0x39); + wait_all_core0_started(); +#if CONFIG_LOGICAL_CPUS==1 + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); + start_other_cores(); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); +#endif + + post_code(0x38); - if (!warm_reset_detect(0)) { // BSP is node 0 - init_fidvid_bsp(bsp_apicid, sysinfo->nodes); - } else { - init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 - } - - post_code(0x3A); - - /* show final fid and vid */ - msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); +#if SET_FIDVID == 1 + msr = rdmsr(0xc0010071); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", + msr.hi, msr.lo); + + /* FIXME: The sb fid change may survive the warm reset and only + * need to be done once.*/ + + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + post_code(0x39); + + if (!warm_reset_detect(0)) { // BSP is node 0 + init_fidvid_bsp(bsp_apicid, sysinfo->nodes); + } else { + init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + } + + post_code(0x3A); + + /* show final fid and vid */ + msr = rdmsr(0xc0010071); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", + msr.hi, msr.lo); #endif - wants_reset = mcp55_early_setup_x(); + init_timer(); // Need to use TMICT to synconize FID/VID - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ - if (!warm_reset_detect(0)) { - print_info("...WARM RESET...\n\n\n"); - soft_reset(); - die("After soft_reset_x - shouldn't see this message!!!\n"); - } + wants_reset = mcp55_early_setup_x(); - if (wants_reset) - printk(BIOS_DEBUG, "mcp55_early_setup_x wanted additional reset!\n"); + /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ + if (!warm_reset_detect(0)) { + print_info("...WARM RESET...\n\n\n"); + soft_reset(); + die("After soft_reset_x - shouldn't see this message!!!\n"); + } - post_code(0x3B); + if (wants_reset) + printk(BIOS_DEBUG, "mcp55_early_setup_x wants additional reset!\n"); -/* It's the time to set ctrl in sysinfo now; */ -printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); -fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + post_code(0x3B); -post_code(0x3D); + /* It's the time to set ctrl in sysinfo now; */ + printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); -//printk(BIOS_DEBUG, "enable_smbus()\n"); -// enable_smbus(); /* enable in sio_setup */ + post_code(0x3D); -post_code(0x40); + // printk(BIOS_DEBUG, "enable_smbus()\n"); + // enable_smbus(); /* enable in sio_setup */ - printk(BIOS_DEBUG, "raminit_amdmct()\n"); - raminit_amdmct(sysinfo); - post_code(0x41); + post_code(0x40); -// printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); - post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. - post_code(0x42); // Should never see this post code. + printk(BIOS_DEBUG, "raminit_amdmct()\n"); + raminit_amdmct(sysinfo); + post_code(0x41); + // printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n"); + post_cache_as_ram(); // BSP switch stack to ram, copy + execute stage 2 + post_code(0x42); // Should never see this post code. } - Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Sun Apr 25 20:05:42 2010 (r5495) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Sun Apr 25 20:06:32 2010 (r5496) @@ -44,19 +44,18 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" -// for enable the FAN -#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" - #include "pc80/serial.c" #include "console/console.c" #include "lib/ramtest.c" #include <cpu/amd/model_10xxx_rev.h> -//#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" +// for enable the FAN +#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" - +#include "cpu/amd/model_10xxx/apic_timer.c" +#include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" @@ -293,6 +292,8 @@ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); #endif + init_timer(); // Need to use TMICT to synconize FID/VID + wants_reset = mcp55_early_setup_x(); /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/romstage.c Sun Apr 25 20:05:42 2010 (r5495) +++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c Sun Apr 25 20:06:32 2010 (r5496) @@ -10,6 +10,8 @@ #include "pc80/serial.c" #include "console/console.c" #include "lib/ramtest.c" +#include "pc80/udelay_io.c" +#include "lib/delay.c" #include "southbridge/intel/esb6300/esb6300_early_smbus.c" #include "northbridge/intel/e7525/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Sun Apr 25 20:05:42 2010 (r5495) +++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Sun Apr 25 20:06:32 2010 (r5496) @@ -10,6 +10,8 @@ #include "pc80/serial.c" #include "console/console.c" #include "lib/ramtest.c" +#include "pc80/udelay_io.c" +#include "lib/delay.c" #include "southbridge/intel/esb6300/esb6300_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Sun Apr 25 20:05:42 2010 (r5495) +++ trunk/src/mainboard/tyan/s2912/romstage.c Sun Apr 25 20:06:32 2010 (r5496) @@ -245,6 +245,8 @@ } #endif + init_timer(); // Need to use TMICT to synconize FID/VID + needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= mcp55_early_setup_x(); @@ -262,9 +264,7 @@ enable_smbus(); - //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ -// init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Sun Apr 25 20:05:42 2010 (r5495) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Sun Apr 25 20:06:32 2010 (r5496) @@ -59,6 +59,8 @@ #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" +#include "cpu/amd/model_10xxx/apic_timer.c" +#include "lib/delay.c" #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" @@ -254,6 +256,8 @@ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif + init_timer(); // Need to use TMICT to synconize FID/VID + wants_reset = mcp55_early_setup_x(); /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ Modified: trunk/src/southbridge/intel/esb6300/esb6300_smbus.c ============================================================================== --- trunk/src/southbridge/intel/esb6300/esb6300_smbus.c Sun Apr 25 20:05:42 2010 (r5495) +++ trunk/src/southbridge/intel/esb6300/esb6300_smbus.c Sun Apr 25 20:06:32 2010 (r5496) @@ -8,11 +8,16 @@ #include "esb6300.h" #include "esb6300_smbus.h" -static int lsmbus_read_byte(device_t dev, uint8_t address) +static int lsmbus_read_byte(device_t dev, u8 address) { + u16 device; struct resource *res; - res = find_resource(dev, 0x20); - + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + res = find_resource(pbus->dev, 0x20); + return do_smbus_read_byte(res->base, device, address); } Modified: trunk/src/southbridge/intel/esb6300/esb6300_smbus.h ============================================================================== --- trunk/src/southbridge/intel/esb6300/esb6300_smbus.h Sun Apr 25 20:05:42 2010 (r5495) +++ trunk/src/southbridge/intel/esb6300/esb6300_smbus.h Sun Apr 25 20:06:32 2010 (r5496) @@ -40,8 +40,7 @@ return loops?0:-1; } -#ifdef UNUSED_CODE -static int smbus_wait_until_blk_done(unsigned smbus_io_base) +static inline int smbus_wait_until_blk_done(unsigned smbus_io_base) { unsigned loops = SMBUS_TIMEOUT; unsigned char byte; @@ -53,7 +52,6 @@ } while((byte&(1<<7)) == 0); return loops?0:-1; } -#endif static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) { Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Sun Apr 25 20:05:42 2010 (r5495) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Sun Apr 25 20:06:32 2010 (r5496) @@ -134,9 +134,6 @@ } -#include "src/pc80/udelay_io.c" -#include "src/lib/delay.c" - static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x) { uint32_t tgio_ctrl;

1 0

[commit] r5495 - trunk/src/northbridge/via/cx700
by repository service 25 Apr '10

25 Apr '10

Author: oxygene Date: Sun Apr 25 20:05:42 2010 New Revision: 5495 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5495 Log: Only do complete VGA init if a VGABIOS was found and installed. Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/via/cx700/cx700_vga.c Modified: trunk/src/northbridge/via/cx700/cx700_vga.c ============================================================================== --- trunk/src/northbridge/via/cx700/cx700_vga.c Sun Apr 25 17:21:18 2010 (r5494) +++ trunk/src/northbridge/via/cx700/cx700_vga.c Sun Apr 25 20:05:42 2010 (r5495) @@ -117,6 +117,8 @@ pci_dev_init(dev); + if (pci_read_config32(dev, PCI_ROM_ADDRESS) != 0xc0000) return; + printk(BIOS_DEBUG, "Enable VGA console\n"); // this is how it should look: // call_bios_interrupt(0x10,0x4f1f,0x8003,1,0);

1 0

build service results for r5494
by coreboot information 25 Apr '10

25 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "ruik" checked in revision 5494 to the coreboot repository. This caused the following changes: Change Log: Following patch changes the K8M890 VGA handling. It reverts the framebuffer size to option based (similar what Uwe did) and also it uses GFXUMA to handle the high_tables_start offset from memory top. To satisfy the CMOS option users (Hi, libv! ;) I added also a possibility to do that through CMOS. Fixed printks to match the new style. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of asus:a8v-e_se has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5494&device=a8v-e_se&vendo… Compilation of gigabyte:m57sli is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5494&device=m57sli&vendor=… Compilation of msi:ms7260 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5494&device=ms7260&vendor=… Compilation of msi:ms9282 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5494&device=ms9282&vendor=… Compilation of nvidia:l1_2pvv is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5494&device=l1_2pvv&vendor… Compilation of supermicro:h8dme is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5494&device=h8dme&vendor=s… Compilation of supermicro:h8dmr is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5494&device=h8dmr&vendor=s… Compilation of supermicro:h8dmr_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5494&device=h8dmr_fam10&ve… Compilation of supermicro:h8qme_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5494&device=h8qme_fam10&ve… Compilation of supermicro:x6dai_g is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5494&device=x6dai_g&vendor… Compilation of supermicro:x6dhe_g is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5494&device=x6dhe_g&vendor… Compilation of tyan:s2912 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5494&device=s2912&vendor=t… If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

build service results for r5493
by coreboot information 25 Apr '10

25 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5493 to the coreboot repository. This caused the following changes: Change Log: no warnings days. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of gigabyte:m57sli has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5493&device=m57sli&vendor=… Compilation of msi:ms7260 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5493&device=ms7260&vendor=… Compilation of msi:ms9282 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5493&device=ms9282&vendor=… Compilation of msi:ms9652_fam10 has been fixed Compilation of nvidia:l1_2pvv has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5493&device=l1_2pvv&vendor… Compilation of supermicro:h8dme is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5493&device=h8dme&vendor=s… Compilation of supermicro:h8dmr is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5493&device=h8dmr&vendor=s… Compilation of supermicro:h8dmr_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5493&device=h8dmr_fam10&ve… Compilation of supermicro:h8qme_fam10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5493&device=h8qme_fam10&ve… Compilation of supermicro:x6dai_g has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5493&device=x6dai_g&vendor… Compilation of supermicro:x6dhe_g has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5493&device=x6dhe_g&vendor… Compilation of tyan:s2912 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5493&device=s2912&vendor=t… Compilation of tyan:s2912_fam10 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5493 - in trunk/src: drivers/ati/ragexl mainboard/intel/jarrell mainboard/intel/xe7501devkit southbridge/amd/amd8111 southbridge/amd/cs5536 southbridge/broadcom/bcm5785 southbridge/intel/...
by repository service 25 Apr '10

25 Apr '10

Author: stepan Date: Sun Apr 25 16:37:18 2010 New Revision: 5493 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5493 Log: no warnings days. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/drivers/ati/ragexl/atyfb.h trunk/src/drivers/ati/ragexl/fbcon.h trunk/src/drivers/ati/ragexl/xlinit.c trunk/src/mainboard/intel/jarrell/jarrell_fixups.c trunk/src/mainboard/intel/jarrell/reset.c trunk/src/mainboard/intel/xe7501devkit/reset.c trunk/src/southbridge/amd/amd8111/amd8111_early_smbus.c trunk/src/southbridge/amd/cs5536/cs5536_smbus2.h trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c trunk/src/southbridge/intel/esb6300/esb6300_smbus.c trunk/src/southbridge/intel/esb6300/esb6300_smbus.h trunk/src/southbridge/intel/i82801cx/i82801cx.h trunk/src/southbridge/intel/i82801cx/i82801cx_reset.c trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Modified: trunk/src/drivers/ati/ragexl/atyfb.h ============================================================================== --- trunk/src/drivers/ati/ragexl/atyfb.h Sun Apr 25 15:54:30 2010 (r5492) +++ trunk/src/drivers/ati/ragexl/atyfb.h Sun Apr 25 16:37:18 2010 (r5493) @@ -1,24 +1,11 @@ - /* * ATI Frame Buffer Device Driver Core Definitions */ -#define u32 uint32_t -#define u16 uint16_t -#define u8 uint8_t - -#define u_int uint32_t + +#define PLL_CRTC_DECODE 0 #define EINVAL -1 -#define readb(addr) (*(volatile unsigned char *) (addr)) -#define readw(addr) (*(volatile unsigned short *) (addr)) -#define readl(addr) (*(volatile unsigned int *) (addr)) - -#define writeb(b,addr) (*(volatile unsigned char *) (addr) = (b)) -#define writew(b,addr) (*(volatile unsigned short *) (addr) = (b)) -#define writel(b,addr) (*(volatile unsigned int *) (addr) = (b)) - - #define max(x,y) (x>=y)?x:y #if CONFIG_CONSOLE_BTEXT==1 @@ -226,7 +213,7 @@ #ifdef ATARI return in_le32((volatile u32 *)(info->ati_regbase+regindex)); #else - return readl (info->ati_regbase + regindex); + return read32 (info->ati_regbase + regindex); #endif } @@ -240,7 +227,7 @@ #ifdef ATARI out_le32 (info->ati_regbase+regindex, val); #else - writel (val, info->ati_regbase + regindex); + write32 (info->ati_regbase + regindex, val); #endif } @@ -254,7 +241,7 @@ #if defined(__mc68000__) return le16_to_cpu(*((volatile u16 *)(info->ati_regbase+regindex))); #else - return readw (info->ati_regbase + regindex); + return read16 (info->ati_regbase + regindex); #endif } @@ -268,7 +255,7 @@ #if defined(__mc68000__) *((volatile u16 *)(info->ati_regbase+regindex)) = cpu_to_le16(val); #else - writew (val, info->ati_regbase + regindex); + write16 (info->ati_regbase + regindex, val); #endif } @@ -282,7 +269,7 @@ #ifdef ATARI return in_8 (info->ati_regbase + regindex); #else - return readb (info->ati_regbase + regindex); + return read8 (info->ati_regbase + regindex); #endif } @@ -296,7 +283,7 @@ #ifdef ATARI out_8 (info->ati_regbase + regindex, val); #else - writeb (val, info->ati_regbase + regindex); + write8 (info->ati_regbase + regindex, val); #endif } @@ -407,8 +394,8 @@ extern void aty_reset_engine(const struct fb_info_aty *info); extern void aty_init_engine(const struct atyfb_par *par, struct fb_info_aty *info); -extern void aty_rectfill(int dstx, int dsty, u_int width, u_int height, - u_int color, struct fb_info_aty *info); +extern void aty_rectfill(int dstx, int dsty, u32 width, u32 height, + u32 color, struct fb_info_aty *info); /* Modified: trunk/src/drivers/ati/ragexl/fbcon.h ============================================================================== --- trunk/src/drivers/ati/ragexl/fbcon.h Sun Apr 25 15:54:30 2010 (r5492) +++ trunk/src/drivers/ati/ragexl/fbcon.h Sun Apr 25 16:37:18 2010 (r5493) @@ -11,11 +11,8 @@ #ifndef _VIDEO_FBCON_H #define _VIDEO_FBCON_H - - struct display { /* Filled in by the frame buffer device */ - struct fb_var_screeninfo var; /* variable infos. yoffset and vmode */ /* are updated by fbcon.c */ struct fb_cmap cmap; /* colormap */ @@ -29,19 +26,10 @@ u32 line_length; /* length of a line in bytes */ u16 can_soft_blank; /* zero if no hardware blanking */ u16 inverse; /* != 0 text black on white as default */ -// struct display_switch *dispsw; /* low level operations */ -// void *dispsw_data; /* optional dispsw helper data */ - -#if 0 - struct fb_fix_cursorinfo fcrsr; - struct fb_var_cursorinfo *vcrsr; - struct fb_cursorstate crsrstate; -#endif /* Filled in by the low-level console driver */ struct vc_data *conp; /* pointer to console data */ -// struct fb_info *fb_info; /* frame buffer for this console */ int vrows; /* number of virtual rows */ unsigned short cursor_x; /* current cursor position */ unsigned short cursor_y; @@ -148,29 +136,4 @@ /* Namespace consistency */ #define SCROLL_YNOPARTIAL __SCROLL_YNOPARTIAL - -#if defined(__i386__) || defined(__alpha__) || \ - defined(__x86_64__) || defined(__hppa__) || \ - defined(__powerpc64__) - -#define fb_readb __raw_readb -#define fb_readw __raw_readw -#define fb_readl __raw_readl -#define fb_writeb __raw_writeb -#define fb_writew __raw_writew -#define fb_writel __raw_writel -#define fb_memset memset_io - -#else - -#define fb_readb(addr) (*(volatile u8 *) (addr)) -#define fb_readw(addr) (*(volatile u16 *) (addr)) -#define fb_readl(addr) (*(volatile u32 *) (addr)) -#define fb_writeb(b,addr) (*(volatile u8 *) (addr) = (b)) -#define fb_writew(b,addr) (*(volatile u16 *) (addr) = (b)) -#define fb_writel(b,addr) (*(volatile u32 *) (addr) = (b)) -#define fb_memset memset - -#endif - #endif /* _VIDEO_FBCON_H */ Modified: trunk/src/drivers/ati/ragexl/xlinit.c ============================================================================== --- trunk/src/drivers/ati/ragexl/xlinit.c Sun Apr 25 15:54:30 2010 (r5492) +++ trunk/src/drivers/ati/ragexl/xlinit.c Sun Apr 25 16:37:18 2010 (r5493) @@ -1429,10 +1429,10 @@ #else scale = (M64_HAS(INTEGRATED) && info->default_par.crtc.bpp == 16) ? 3 : 0; #endif - writeb(regno << scale, &info->aty_cmap_regs->windex); - writeb(red, &info->aty_cmap_regs->lut); - writeb(green, &info->aty_cmap_regs->lut); - writeb(blue, &info->aty_cmap_regs->lut); + write8(&info->aty_cmap_regs->windex, regno << scale) + write8(&info->aty_cmap_regs->lut, red); + write8(&info->aty_cmap_regs->lut, green); + write8(&info->aty_cmap_regs->lut, blue); return 0; } Modified: trunk/src/mainboard/intel/jarrell/jarrell_fixups.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/jarrell_fixups.c Sun Apr 25 15:54:30 2010 (r5492) +++ trunk/src/mainboard/intel/jarrell/jarrell_fixups.c Sun Apr 25 16:37:18 2010 (r5493) @@ -4,7 +4,7 @@ { device_t dev; unsigned long value, base; - dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); + dev = pci_locate_device_on_bus(PCI_ID(0x8086, 0x24d0), 0); if (dev != PCI_DEV_INVALID) { /* I/O space is always enables */ @@ -30,8 +30,6 @@ return; } - - static void mainboard_set_e7520_pll(unsigned bits) { uint16_t gpio_index; @@ -64,14 +62,13 @@ outb((data & 0xeb) | ((bits&2)?0:1)<<4 | ((bits&1)?0:1)<<2, gpio_index + PC87427_GPDO_4); /* reset */ print_debug("set_pllsel: settings adjusted, now resetting...\n"); - // hard_reset(); /* should activate a PCI_RST, which should reset MCH, but it doesn't seem to work ???? */ -// mch_reset(); + // hard_reset(); /* should activate a PCI_RST, which should reset MCH, but it doesn't seem to work ???? */ + // mch_reset(); full_reset(); } return; } - static void mainboard_set_e7520_leds(void) { uint8_t cnt; @@ -118,6 +115,3 @@ return; } - - - Modified: trunk/src/mainboard/intel/jarrell/reset.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/reset.c Sun Apr 25 15:54:30 2010 (r5492) +++ trunk/src/mainboard/intel/jarrell/reset.c Sun Apr 25 16:37:18 2010 (r5493) @@ -1,6 +1,6 @@ #include <arch/io.h> -#include <reset.h> #include <arch/romcc_io.h> +#include <reset.h> void soft_reset(void) { @@ -13,6 +13,11 @@ outb(0x06, 0xcf9); } +#ifndef __ROMCC__ +/* Used only board-internally by power_reset_check.c and jarell_fixups.c */ +void full_reset(void); +#endif + void full_reset(void) { /* Enable power on after power fail... */ @@ -20,7 +25,7 @@ byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa4); byte &= 0xfe; pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa4, byte); + outb(0x0e, 0xcf9); } - Modified: trunk/src/mainboard/intel/xe7501devkit/reset.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/reset.c Sun Apr 25 15:54:30 2010 (r5492) +++ trunk/src/mainboard/intel/xe7501devkit/reset.c Sun Apr 25 16:37:18 2010 (r5493) @@ -1,6 +1,6 @@ #include <reset.h> -void i82801cx_hard_reset(void); +#include "southbridge/intel/i82801cx/i82801cx.h" void hard_reset(void) { Modified: trunk/src/southbridge/amd/amd8111/amd8111_early_smbus.c ============================================================================== --- trunk/src/southbridge/amd/amd8111/amd8111_early_smbus.c Sun Apr 25 15:54:30 2010 (r5492) +++ trunk/src/southbridge/amd/amd8111/amd8111_early_smbus.c Sun Apr 25 16:37:18 2010 (r5493) @@ -26,22 +26,23 @@ print_spew("SMBus controller enabled\n"); } -static int smbus_recv_byte(unsigned device) +static inline int smbus_recv_byte(unsigned device) { return do_smbus_recv_byte(SMBUS_IO_BASE, device); } -static int smbus_send_byte(unsigned device, unsigned char val) +static inline int smbus_send_byte(unsigned device, unsigned char val) { return do_smbus_send_byte(SMBUS_IO_BASE, device, val); } -static int smbus_read_byte(unsigned device, unsigned address) +static inline int smbus_read_byte(unsigned device, unsigned address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -static int smbus_write_byte(unsigned device, unsigned address, unsigned char val) +static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val) { return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); } + Modified: trunk/src/southbridge/amd/cs5536/cs5536_smbus2.h ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536_smbus2.h Sun Apr 25 15:54:30 2010 (r5492) +++ trunk/src/southbridge/amd/cs5536/cs5536_smbus2.h Sun Apr 25 16:37:18 2010 (r5493) @@ -253,18 +253,16 @@ printk(BIOS_DEBUG, "SMBUS READ ERROR (%d): %d\n", index, ret); } -static unsigned char do_smbus_read_byte(unsigned smbus_io_base, - unsigned char device, - unsigned char address) +static inline unsigned char do_smbus_read_byte(unsigned smbus_io_base, + unsigned char device, unsigned char address) { unsigned char val = 0; _doread(smbus_io_base, device, address, &val, sizeof(val)); return val; } -static unsigned short do_smbus_read_word(unsigned smbus_io_base, - unsigned char device, - unsigned char address) +static inline unsigned short do_smbus_read_word(unsigned smbus_io_base, + unsigned char device, unsigned char address) { unsigned short val = 0; _doread(smbus_io_base, device, address, (unsigned char *)&val, @@ -304,15 +302,15 @@ return -1; } -static int do_smbus_write_byte(unsigned smbus_io_base, unsigned char device, - unsigned char address, unsigned char data) +static inline int do_smbus_write_byte(unsigned smbus_io_base, + unsigned char device, unsigned char address, unsigned char data) { return _dowrite(smbus_io_base, device, address, (unsigned char *)&data, 1); } -static int do_smbus_write_word(unsigned smbus_io_base, unsigned char device, - unsigned char address, unsigned short data) +static inline int do_smbus_write_word(unsigned smbus_io_base, + unsigned char device, unsigned char address, unsigned short data) { return _dowrite(smbus_io_base, device, address, (unsigned char *)&data, 2); Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c Sun Apr 25 15:54:30 2010 (r5492) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_early_smbus.c Sun Apr 25 16:37:18 2010 (r5493) @@ -25,21 +25,22 @@ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); } -static int smbus_recv_byte(unsigned device) +static inline int smbus_recv_byte(unsigned device) { return do_smbus_recv_byte(SMBUS_IO_BASE, device); } -static int smbus_send_byte(unsigned device, unsigned char val) +static inline int smbus_send_byte(unsigned device, unsigned char val) { return do_smbus_send_byte(SMBUS_IO_BASE, device, val); } -static int smbus_read_byte(unsigned device, unsigned address) +static inline int smbus_read_byte(unsigned device, unsigned address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -static int smbus_write_byte(unsigned device, unsigned address, unsigned char val) + +static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val) { return do_smbus_write_byte(SMBUS_IO_BASE, device, address, val); } Modified: trunk/src/southbridge/intel/esb6300/esb6300_smbus.c ============================================================================== --- trunk/src/southbridge/intel/esb6300/esb6300_smbus.c Sun Apr 25 15:54:30 2010 (r5492) +++ trunk/src/southbridge/intel/esb6300/esb6300_smbus.c Sun Apr 25 16:37:18 2010 (r5493) @@ -8,13 +8,10 @@ #include "esb6300.h" #include "esb6300_smbus.h" -static int lsmbus_read_byte(struct bus *bus, device_t dev, uint8_t address) +static int lsmbus_read_byte(device_t dev, uint8_t address) { - unsigned device; struct resource *res; - - device = dev->path.i2c.device; - res = find_resource(bus->dev, 0x20); + res = find_resource(dev, 0x20); return do_smbus_read_byte(res->base, device, address); } @@ -22,10 +19,12 @@ static struct smbus_bus_operations lops_smbus_bus = { .read_byte = lsmbus_read_byte, }; + static struct pci_operations lops_pci = { /* The subsystem id follows the ide controller */ .set_subsystem = 0, }; + static struct device_operations smbus_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, Modified: trunk/src/southbridge/intel/esb6300/esb6300_smbus.h ============================================================================== --- trunk/src/southbridge/intel/esb6300/esb6300_smbus.h Sun Apr 25 15:54:30 2010 (r5492) +++ trunk/src/southbridge/intel/esb6300/esb6300_smbus.h Sun Apr 25 16:37:18 2010 (r5493) @@ -14,18 +14,12 @@ #define SMBUS_TIMEOUT (100*1000*10) - -static void smbus_delay(void) -{ - outb(0x80, 0x80); -} - static int smbus_wait_until_ready(unsigned smbus_io_base) { unsigned loops = SMBUS_TIMEOUT; unsigned char byte; do { - smbus_delay(); + udelay(100); if (--loops == 0) break; byte = inb(smbus_io_base + SMBHSTSTAT); @@ -38,7 +32,7 @@ unsigned loops = SMBUS_TIMEOUT; unsigned char byte; do { - smbus_delay(); + udelay(100); if (--loops == 0) break; byte = inb(smbus_io_base + SMBHSTSTAT); @@ -46,18 +40,20 @@ return loops?0:-1; } +#ifdef UNUSED_CODE static int smbus_wait_until_blk_done(unsigned smbus_io_base) { unsigned loops = SMBUS_TIMEOUT; unsigned char byte; do { - smbus_delay(); + udelay(100); if (--loops == 0) break; byte = inb(smbus_io_base + SMBHSTSTAT); } while((byte&(1<<7)) == 0); return loops?0:-1; } +#endif static int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, unsigned address) { Modified: trunk/src/southbridge/intel/i82801cx/i82801cx.h ============================================================================== --- trunk/src/southbridge/intel/i82801cx/i82801cx.h Sun Apr 25 15:54:30 2010 (r5492) +++ trunk/src/southbridge/intel/i82801cx/i82801cx.h Sun Apr 25 16:37:18 2010 (r5493) @@ -2,8 +2,10 @@ #define I82801CX_H #if !defined(__PRE_RAM__) +#include <device/device.h> #include "chip.h" -extern void i82801cx_enable(device_t dev); +void i82801cx_enable(device_t dev); +void i82801cx_hard_reset(void); #endif Modified: trunk/src/southbridge/intel/i82801cx/i82801cx_reset.c ============================================================================== --- trunk/src/southbridge/intel/i82801cx/i82801cx_reset.c Sun Apr 25 15:54:30 2010 (r5492) +++ trunk/src/southbridge/intel/i82801cx/i82801cx_reset.c Sun Apr 25 16:37:18 2010 (r5493) @@ -1,4 +1,5 @@ #include <arch/io.h> +#include "i82801cx.h" void i82801cx_hard_reset(void) { Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Sun Apr 25 15:54:30 2010 (r5492) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Sun Apr 25 16:37:18 2010 (r5493) @@ -134,6 +134,9 @@ } +#include "src/pc80/udelay_io.c" +#include "src/lib/delay.c" + static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x) { uint32_t tgio_ctrl;

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build service results for r5492
by coreboot information 25 Apr '10

25 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5492 to the coreboot repository. This caused the following changes: Change Log: zero warnings days Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of msi:ms9652_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5492&device=ms9652_fam10&v… Compilation of supermicro:h8dme has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5492&device=h8dme&vendor=s… Compilation of supermicro:h8dmr has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5492&device=h8dmr&vendor=s… Compilation of supermicro:h8dmr_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5492&device=h8dmr_fam10&ve… Compilation of supermicro:h8qme_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5492&device=h8qme_fam10&ve… Compilation of tyan:s2912_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5492&device=s2912_fam10&ve… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r5492 - in trunk/src: mainboard/asus/a8v-e_se mainboard/gigabyte/m57sli northbridge/amd/amdk8 northbridge/via/cn400 northbridge/via/cx700 northbridge/via/vx800 southbridge/amd/rs780 southb...
by repository service 25 Apr '10

25 Apr '10

Author: stepan Date: Sun Apr 25 15:54:30 2010 New Revision: 5492 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5492 Log: zero warnings days Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/gigabyte/m57sli/fanctl.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/northbridge/amd/amdk8/exit_from_self.c trunk/src/northbridge/amd/amdk8/raminit.h trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c trunk/src/northbridge/via/cn400/vga.c trunk/src/northbridge/via/cx700/cx700_vga.c trunk/src/northbridge/via/cx700/northbridge.h trunk/src/northbridge/via/vx800/northbridge.h trunk/src/southbridge/amd/rs780/rs780_gfx.c trunk/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c trunk/src/superio/ite/it8716f/it8716f.h trunk/src/superio/ite/it8716f/it8716f_early_init.c trunk/src/superio/ite/it8716f/it8716f_early_serial.c trunk/src/superio/ite/it8716f/superio.c Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Sun Apr 25 13:57:21 2010 (r5491) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Sun Apr 25 15:54:30 2010 (r5492) @@ -80,7 +80,8 @@ { } -static void soft_reset(void) +#include <reset.h> +void soft_reset(void) { uint8_t tmp; @@ -98,6 +99,9 @@ } } +// defines S3_NVRAM_EARLY: +#include "southbridge/via/k8t890/k8t890_early_car.c" + #define K8_4RANK_DIMM_SUPPORT 1 #include "northbridge/amd/amdk8/amdk8.h" @@ -107,7 +111,6 @@ #include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" -#include "southbridge/via/k8t890/k8t890_early_car.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/gigabyte/m57sli/fanctl.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/fanctl.c Sun Apr 25 13:57:21 2010 (r5491) +++ trunk/src/mainboard/gigabyte/m57sli/fanctl.c Sun Apr 25 15:54:30 2010 (r5492) @@ -1,5 +1,6 @@ #include <arch/io.h> #include <stdlib.h> +#include <superio/ite/it8716f/it8716f.h> static void write_index(uint16_t port_base, uint8_t reg, uint8_t value) { Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Sun Apr 25 13:57:21 2010 (r5491) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Sun Apr 25 15:54:30 2010 (r5492) @@ -98,16 +98,6 @@ return smbus_read_byte(device, address); } -#include "northbridge/amd/amdk8/amdk8_f.h" -#include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" -#include "lib/generic_sdram.c" - -#include "resourcemap.c" - -#include "cpu/amd/dualcore/dualcore.c" - #define MCP55_NUM 1 #define MCP55_USE_NIC 1 #define MCP55_USE_AZA 1 @@ -125,6 +115,18 @@ #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h" #include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c" + + +#include "northbridge/amd/amdk8/amdk8_f.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit_f.c" +#include "lib/generic_sdram.c" + +#include "resourcemap.c" + +#include "cpu/amd/dualcore/dualcore.c" + #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/northbridge/amd/amdk8/exit_from_self.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/exit_from_self.c Sun Apr 25 13:57:21 2010 (r5491) +++ trunk/src/northbridge/amd/amdk8/exit_from_self.c Sun Apr 25 15:54:30 2010 (r5492) @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "raminit.h" + void exit_from_self(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo) { Modified: trunk/src/northbridge/amd/amdk8/raminit.h ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit.h Sun Apr 25 13:57:21 2010 (r5491) +++ trunk/src/northbridge/amd/amdk8/raminit.h Sun Apr 25 15:54:30 2010 (r5492) @@ -11,6 +11,9 @@ uint16_t channel1[DIMM_SOCKETS]; }; +struct sys_info; +void exit_from_self(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo); + #if defined(__PRE_RAM__) && defined(RAMINIT_SYSINFO) && RAMINIT_SYSINFO == 1 void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo); #else Modified: trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Sun Apr 25 13:57:21 2010 (r5491) +++ trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Sun Apr 25 15:54:30 2010 (r5492) @@ -1829,12 +1829,12 @@ //int s3_save_nvram_early(u32 dword, int size, int nvram_pos); //int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); #else -static int s3_save_nvram_early(u32 dword, int size, int nvram_pos) +static inline int s3_save_nvram_early(u32 dword, int size, int nvram_pos) { return nvram_pos; } -static int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) +static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) { die("No memory NVRAM loader for DQS data! Unable to restore memory state\n"); Modified: trunk/src/northbridge/via/cn400/vga.c ============================================================================== --- trunk/src/northbridge/via/cn400/vga.c Sun Apr 25 13:57:21 2010 (r5491) +++ trunk/src/northbridge/via/cn400/vga.c Sun Apr 25 15:54:30 2010 (r5492) @@ -80,12 +80,12 @@ static void vga_init(device_t dev) { u8 reg8; - u32 temp; mainboard_interrupt_handlers(0x15, &via_cn400_int15_handler); #undef OLD_BOCHS_METHOD #ifdef OLD_BOCHS_METHOD + u32 temp; // XXX We might need more bios hooks in the f segment, but // this way of copying the BOCHS BIOS does not work anymore. // As soon as someone verifies that CN400 can init VGA, the Modified: trunk/src/northbridge/via/cx700/cx700_vga.c ============================================================================== --- trunk/src/northbridge/via/cx700/cx700_vga.c Sun Apr 25 13:57:21 2010 (r5491) +++ trunk/src/northbridge/via/cx700/cx700_vga.c Sun Apr 25 15:54:30 2010 (r5492) @@ -81,7 +81,8 @@ return res; } -void write_protect_vgabios(void) +#ifdef UNUSED_CODE +static void write_protect_vgabios(void) { device_t dev; @@ -95,6 +96,7 @@ if (dev) pci_write_config8(dev, 0x61, 0xff); } +#endif static void vga_init(device_t dev) { Modified: trunk/src/northbridge/via/cx700/northbridge.h ============================================================================== --- trunk/src/northbridge/via/cx700/northbridge.h Sun Apr 25 13:57:21 2010 (r5491) +++ trunk/src/northbridge/via/cx700/northbridge.h Sun Apr 25 15:54:30 2010 (r5492) @@ -21,5 +21,6 @@ #define NORTHBRIDGE_VIA_CX700_H extern unsigned int cx700_scan_root_bus(device_t root, unsigned int max); +extern void (*vga_enable_console)(void) __attribute__((regparm(0))); #endif /* NORTHBRIDGE_VIA_CX700_H */ Modified: trunk/src/northbridge/via/vx800/northbridge.h ============================================================================== --- trunk/src/northbridge/via/vx800/northbridge.h Sun Apr 25 13:57:21 2010 (r5491) +++ trunk/src/northbridge/via/vx800/northbridge.h Sun Apr 25 15:54:30 2010 (r5492) @@ -21,5 +21,6 @@ #define NORTHBRIDGE_VIA_VX800_H extern unsigned int vx800_scan_root_bus(device_t root, unsigned int max); +extern void (*vga_enable_console)(void) __attribute__((regparm(0))); #endif /* NORTHBRIDGE_VIA_VX800_H */ Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_gfx.c Sun Apr 25 13:57:21 2010 (r5491) +++ trunk/src/southbridge/amd/rs780/rs780_gfx.c Sun Apr 25 15:54:30 2010 (r5492) @@ -122,6 +122,7 @@ #define MMIO_ATTRIB_BOTTOM_TO_TOP 1<<1 #define MMIO_ATTRIB_SKIP_ZERO 1<<2 +#ifdef DONT_TRUST_RESOURCE_ALLOCATION static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO) { int i; @@ -180,7 +181,6 @@ return n; } -#ifdef DONT_TRUST_RESOURCE_ALLOCATION static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO) { CIM_STATUS Status = CIM_UNSUPPORTED; Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c Sun Apr 25 13:57:21 2010 (r5491) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_ctrl.c Sun Apr 25 15:54:30 2010 (r5492) @@ -19,6 +19,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <reset.h> + static unsigned get_sbdn(unsigned bus) { device_t dev; @@ -33,7 +35,15 @@ } -static void hard_reset(void) +void soft_reset(void) +{ + set_bios_reset(); + /* link reset */ + outb(0x02, 0x0cf9); + outb(0x06, 0x0cf9); +} + +void hard_reset(void) { set_bios_reset(); @@ -41,20 +51,10 @@ outb(0x0a, 0x0cf9); outb(0x0e, 0x0cf9); } + static void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn) { -/* default value for mcp55 is good */ + /* default value for mcp55 is good */ /* set VFSMAF ( VID/FID System Management Action Field) to 2 */ - -} - -static void soft_reset(void) -{ - set_bios_reset(); -#if 1 - /* link reset */ - outb(0x02, 0x0cf9); - outb(0x06, 0x0cf9); -#endif } Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Sun Apr 25 13:57:21 2010 (r5491) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Sun Apr 25 15:54:30 2010 (r5492) @@ -21,6 +21,7 @@ static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val); +#ifdef UNUSED_CODE static int set_ht_link_mcp55(uint8_t ht_c_num) { unsigned vendorid = 0x10de; @@ -51,6 +52,7 @@ outl(val, control); } +#endif /* SIZE 0x100 */ #define ANACTRL_IO_BASE 0x2800 @@ -131,14 +133,6 @@ } -static void delayx(uint8_t value) { -#if 1 - int i; - for(i=0;i<0x8000;i++) { - outb(value, 0x80); - } -#endif -} static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx, unsigned anactrl_io_base, unsigned pci_e_x) { @@ -169,15 +163,15 @@ tgio_ctrl |= (pci_e_x<<4)|(1<<8); outl(tgio_ctrl, anactrl_io_base + 0xcc); -// wait 100us - delayx(1); + // wait 100us + udelay(100); dword = pci_read_config32(dev, 0xe4); dword &= ~(0x3f0); // enable pci_write_config32(dev, 0xe4, dword); -// need to wait 100ms - delayx(1000); + // need to wait 100ms + mdelay(100); } static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base, unsigned *pci_e_x) Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c Sun Apr 25 13:57:21 2010 (r5491) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c Sun Apr 25 15:54:30 2010 (r5492) @@ -31,13 +31,13 @@ { device_t dev; dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0); -#if 0 + if (dev == PCI_DEV_INVALID) { - die("SMBUS controller not found\n"); + printk(BIOS_WARNING, "SMBUS controller not found\n"); + } else { + printk(BIOS_DEBUG, "SMBus controller enabled\n"); } - print_debug("SMBus controller enabled\n"); -#endif /* set smbus iobase */ pci_write_config32(dev, 0x20, SMBUS0_IO_BASE | 1); pci_write_config32(dev, 0x24, SMBUS1_IO_BASE | 1); @@ -48,36 +48,42 @@ outb(inb(SMBUS1_IO_BASE + SMBHSTSTAT), SMBUS1_IO_BASE + SMBHSTSTAT); } -static int smbus_recv_byte(unsigned device) +static inline int smbus_recv_byte(unsigned device) { return do_smbus_recv_byte(SMBUS0_IO_BASE, device); } -static int smbus_send_byte(unsigned device, unsigned char val) + +static inline int smbus_send_byte(unsigned device, unsigned char val) { return do_smbus_send_byte(SMBUS0_IO_BASE, device, val); } -static int smbus_read_byte(unsigned device, unsigned address) + +static inline int smbus_read_byte(unsigned device, unsigned address) { return do_smbus_read_byte(SMBUS0_IO_BASE, device, address); } -static int smbus_write_byte(unsigned device, unsigned address, unsigned char val) + +static inline int smbus_write_byte(unsigned device, unsigned address, unsigned char val) { return do_smbus_write_byte(SMBUS0_IO_BASE, device, address, val); } -static int smbusx_recv_byte(unsigned smb_index, unsigned device) +static inline int smbusx_recv_byte(unsigned smb_index, unsigned device) { return do_smbus_recv_byte(SMBUS0_IO_BASE + (smb_index<<8), device); } -static int smbusx_send_byte(unsigned smb_index, unsigned device, unsigned char val) + +static inline int smbusx_send_byte(unsigned smb_index, unsigned device, unsigned char val) { return do_smbus_send_byte(SMBUS0_IO_BASE + (smb_index<<8), device, val); } -static int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address) + +static inline int smbusx_read_byte(unsigned smb_index, unsigned device, unsigned address) { return do_smbus_read_byte(SMBUS0_IO_BASE + (smb_index<<8), device, address); } -static int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address, unsigned char val) + +static inline int smbusx_write_byte(unsigned smb_index, unsigned device, unsigned address, unsigned char val) { return do_smbus_write_byte(SMBUS0_IO_BASE + (smb_index<<8), device, address, val); } Modified: trunk/src/superio/ite/it8716f/it8716f.h ============================================================================== --- trunk/src/superio/ite/it8716f/it8716f.h Sun Apr 25 13:57:21 2010 (r5491) +++ trunk/src/superio/ite/it8716f/it8716f.h Sun Apr 25 15:54:30 2010 (r5492) @@ -21,6 +21,9 @@ /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */ /* Status: Untested on real hardware, but it compiles. */ +#ifndef SUPERIO_ITE_IT8716F_IT8716F_H +#define SUPERIO_ITE_IT8716F_IT8716F_H + #define IT8716F_FDC 0x00 /* Floppy */ #define IT8716F_SP1 0x01 /* Com1 */ #define IT8716F_SP2 0x02 /* Com2 */ @@ -32,3 +35,16 @@ #define IT8716F_MIDI 0x08 /* MIDI port */ #define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_IR 0x0a /* Consumer IR */ + +#if defined(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) && CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL +/* provided by mainboard, called by it8716f superio.c */ +void init_ec(uint16_t base); +#endif + +#if defined(__PRE_RAM__) && !defined(__ROMCC__) +void it8716f_disable_dev(device_t dev); +void it8716f_enable_dev(device_t dev, unsigned iobase); +void it8716f_enable_serial(device_t dev, unsigned iobase); +#endif + +#endif Modified: trunk/src/superio/ite/it8716f/it8716f_early_init.c ============================================================================== --- trunk/src/superio/ite/it8716f/it8716f_early_init.c Sun Apr 25 13:57:21 2010 (r5491) +++ trunk/src/superio/ite/it8716f/it8716f_early_init.c Sun Apr 25 15:54:30 2010 (r5492) @@ -22,13 +22,13 @@ #include <arch/romcc_io.h> #include "it8716f.h" -static void it8716f_disable_dev(device_t dev) +void it8716f_disable_dev(device_t dev) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); } -static void it8716f_enable_dev(device_t dev, unsigned iobase) +void it8716f_enable_dev(device_t dev, unsigned iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); Modified: trunk/src/superio/ite/it8716f/it8716f_early_serial.c ============================================================================== --- trunk/src/superio/ite/it8716f/it8716f_early_serial.c Sun Apr 25 13:57:21 2010 (r5491) +++ trunk/src/superio/ite/it8716f/it8716f_early_serial.c Sun Apr 25 15:54:30 2010 (r5492) @@ -59,7 +59,7 @@ pnp_write_config(dev, 0x02, 0x02); } -static void it8716f_enable_serial(device_t dev, unsigned iobase) +void it8716f_enable_serial(device_t dev, unsigned iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); Modified: trunk/src/superio/ite/it8716f/superio.c ============================================================================== --- trunk/src/superio/ite/it8716f/superio.c Sun Apr 25 13:57:21 2010 (r5491) +++ trunk/src/superio/ite/it8716f/superio.c Sun Apr 25 15:54:30 2010 (r5492) @@ -51,9 +51,7 @@ pnp_write_config(dev, 0x02, 0x02); } -#if CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL -extern void init_ec(uint16_t base); -#else +#if !defined(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) || !CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL static void pnp_write_index(uint16_t port_base, uint8_t reg, uint8_t value) { outb(reg, port_base);

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coreboot April 2010