coreboot April 2010

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[buildrom] r279 - buildrom-devel
by repository service 22 Apr '10

22 Apr '10

Author: myles Date: Thu Apr 22 20:16:02 2010 New Revision: 279 URL: http://tracker.coreboot.org/trac/buildrom/changeset/279 Log: Make a payload only option for buildrom. Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Myles Watson <mylesgw(a)gmail.com> Modified: buildrom-devel/Config.in buildrom-devel/Makefile Modified: buildrom-devel/Config.in ============================================================================== --- buildrom-devel/Config.in Sun Apr 18 10:31:32 2010 (r278) +++ buildrom-devel/Config.in Thu Apr 22 20:16:02 2010 (r279) @@ -67,7 +67,13 @@ choice prompt "coreboot version" - default COREBOOT_V2 + default PAYLOAD_ONLY + +config PAYLOAD_ONLY + bool "payload only" + help + Coreboot is a lot easier to build for v4. Copy the payload from + deploy/ to coreboot/svn/payload.elf and build it. config COREBOOT_V2 bool "coreboot v2" Modified: buildrom-devel/Makefile ============================================================================== --- buildrom-devel/Makefile Sun Apr 18 10:31:32 2010 (r278) +++ buildrom-devel/Makefile Thu Apr 22 20:16:02 2010 (r279) @@ -107,7 +107,19 @@ ifeq ($(CONFIG_COREBOOT_V2),y) rom: payload $(COREBOOT-y) -else +endif + +ifeq ($(CONFIG_PAYLOAD_ONLY),y) +rom: payload + @ echo "" + @ echo "CONFIG_PAYLOAD_ONLY was set" + @ echo "" + @ echo "1. cp deploy/your_payload.elf coreboot/svn/payload.elf" + @ echo "2. configure the payload to be payload.elf and build it." + @ echo "" +endif + +ifeq ($(CONFIG_COREBOOT_V3),y) # If compressing the payload in v3, parse the elf and tell lar to compress it. # Parsing the elf without compression bloats the ROM with bss zeroes. @@ -154,7 +166,9 @@ ifeq ($(CONFIG_COREBOOT_V2),y) INCMK += $(PACKAGE_DIR)/coreboot-v2/coreboot-v2.mk -else +endif + +ifeq ($(CONFIG_COREBOOT_V3),y) INCMK += $(PACKAGE_DIR)/coreboot-v3/coreboot-v3.mk endif

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[commit] r5478 - in trunk/src: devices/oprom mainboard/via/epia-m northbridge/via/vt8623
by repository service 22 Apr '10

22 Apr '10

Author: stepan Date: Thu Apr 22 20:15:32 2010 New Revision: 5478 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5478 Log: via epia-m now works with default x86.c instead of its own copy of vgabios.c. Allows to drop quite a bunch of nasty code Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/src/northbridge/via/vt8623/vga.c Deleted: trunk/src/mainboard/via/epia-m/Makefile.inc trunk/src/mainboard/via/epia-m/vgabios.c trunk/src/mainboard/via/epia-m/vgachip.h Modified: trunk/src/devices/oprom/x86.c trunk/src/devices/oprom/x86_asm.S trunk/src/mainboard/via/epia-m/Kconfig trunk/src/mainboard/via/epia-m/devicetree.cb trunk/src/mainboard/via/epia-m/mainboard.c trunk/src/mainboard/via/epia-m/romstage.c trunk/src/northbridge/via/vt8623/Makefile.inc trunk/src/northbridge/via/vt8623/northbridge.c trunk/src/northbridge/via/vt8623/northbridge.h Modified: trunk/src/devices/oprom/x86.c ============================================================================== --- trunk/src/devices/oprom/x86.c Thu Apr 22 15:18:09 2010 (r5477) +++ trunk/src/devices/oprom/x86.c Thu Apr 22 20:15:32 2010 (r5478) @@ -318,7 +318,7 @@ /* Pass errors back to our caller via the CARRY flag */ if (ret) { - printk(BIOS_DEBUG,"error!\n"); + printk(BIOS_DEBUG,"int%02x call returned error.\n", intnumber); flags |= 1; // error: set carry }else{ flags &= ~1; // no error: clear carry Modified: trunk/src/devices/oprom/x86_asm.S ============================================================================== --- trunk/src/devices/oprom/x86_asm.S Thu Apr 22 15:18:09 2010 (r5477) +++ trunk/src/devices/oprom/x86_asm.S Thu Apr 22 20:15:32 2010 (r5478) @@ -257,8 +257,6 @@ .globl __run_interrupt __run_interrupt = RELOCATED(.) - /* paranoia -- does ecx get saved? not sure. This is - * the easiest safe thing to do. */ pushal /* save the stack */ mov %esp, __stack Modified: trunk/src/mainboard/via/epia-m/Kconfig ============================================================================== --- trunk/src/mainboard/via/epia-m/Kconfig Thu Apr 22 15:18:09 2010 (r5477) +++ trunk/src/mainboard/via/epia-m/Kconfig Thu Apr 22 20:15:32 2010 (r5478) @@ -22,24 +22,8 @@ default "EPIA-M" depends on BOARD_VIA_EPIA_M -config RAMBASE - hex - default 0x4000 - depends on BOARD_VIA_EPIA_M - config IRQ_SLOT_COUNT int default 5 depends on BOARD_VIA_EPIA_M -# this is done by this board's vgabios.c already -config VGA_ROM_RUN - bool - default n - depends on BOARD_VIA_EPIA_M - -config PCI_ROM_RUN - bool - default n - depends on BOARD_VIA_EPIA_M - Modified: trunk/src/mainboard/via/epia-m/devicetree.cb ============================================================================== --- trunk/src/mainboard/via/epia-m/devicetree.cb Thu Apr 22 15:18:09 2010 (r5477) +++ trunk/src/mainboard/via/epia-m/devicetree.cb Thu Apr 22 20:15:32 2010 (r5478) @@ -7,6 +7,10 @@ end device pci_domain 0 on + + device pci 0.0 on end + device pci 1.0 on end + chip southbridge/via/vt8235 device pci 10.0 on end # USB 1.1 Modified: trunk/src/mainboard/via/epia-m/mainboard.c ============================================================================== --- trunk/src/mainboard/via/epia-m/mainboard.c Thu Apr 22 15:18:09 2010 (r5477) +++ trunk/src/mainboard/via/epia-m/mainboard.c Thu Apr 22 20:15:32 2010 (r5478) @@ -1,40 +1,5 @@ -#include <console/console.h> #include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <device/pci_ops.h> -#include <arch/io.h> #include "chip.h" -#include "vgachip.h" - -static void vga_fixup(void) { - // we do this right here because: - // - all the hardware is working, and some VGA bioses seem to need - // that - // - we need page 0 below for coreboot tables. - - printk(BIOS_DEBUG, "INSTALL REAL-MODE IDT\n"); - setup_realmode_idt(); - printk(BIOS_DEBUG, "DO THE VGA BIOS\n"); - do_vgabios(); - post_code(0x93); - vga_enable_console(); -} - -void write_protect_vgabios(void) -{ - device_t dev; - - printk(BIOS_INFO, "write_protect_vgabios\n"); - /* there are two possible devices. Just do both. */ - dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3122, 0); - if(dev) - pci_write_config8(dev, 0x61, 0xaa); - - dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3123, 0); - if(dev) - pci_write_config8(dev, 0x61, 0xaa); -} struct chip_operations mainboard_ops = { CHIP_NAME("VIA EPIA-M Mainboard") Modified: trunk/src/mainboard/via/epia-m/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m/romstage.c Thu Apr 22 15:18:09 2010 (r5477) +++ trunk/src/mainboard/via/epia-m/romstage.c Thu Apr 22 20:15:32 2010 (r5478) @@ -30,7 +30,7 @@ { device_t dev; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235), 0); if (dev == PCI_DEV_INVALID) { @@ -82,7 +82,7 @@ * Disable the firewire stuff, which apparently steps on IO 0+ on * reset. Doh! */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_6305), 0); if (dev != PCI_DEV_INVALID) { pci_write_config8(dev, 0x15, 0x1c); @@ -94,14 +94,12 @@ enable_smbus(); - print_spew("In romstage.c:main()\n"); - /* Halt if there was a built in self test failure */ report_bist_failure(bist); // init_timer(); - outb(5, 0x80); + post_code(0x05); print_debug(" Enabling mainboard devices\n"); enable_mainboard_devices(); @@ -113,18 +111,11 @@ /* Check all of memory */ #if 0 - ram_check(0x00000000, msr.lo); -#endif -#if 0 static const struct { unsigned long lo, hi; } check_addrs[] = { /* Check 16MB of memory @ 0*/ { 0x00000000, 0x01000000 }, -#if TOTAL_CPUS > 1 - /* Check 16MB of memory @ 2GB */ - { 0x80000000, 0x81000000 }, -#endif }; int i; for(i = 0; i < ARRAY_SIZE(check_addrs); i++) { Modified: trunk/src/northbridge/via/vt8623/Makefile.inc ============================================================================== --- trunk/src/northbridge/via/vt8623/Makefile.inc Thu Apr 22 15:18:09 2010 (r5477) +++ trunk/src/northbridge/via/vt8623/Makefile.inc Thu Apr 22 20:15:32 2010 (r5478) @@ -19,4 +19,5 @@ ## driver-y += northbridge.o +driver-y += vga.o Modified: trunk/src/northbridge/via/vt8623/northbridge.c ============================================================================== --- trunk/src/northbridge/via/vt8623/northbridge.c Thu Apr 22 15:18:09 2010 (r5477) +++ trunk/src/northbridge/via/vt8623/northbridge.c Thu Apr 22 20:15:32 2010 (r5478) @@ -105,82 +105,6 @@ .device = PCI_DEVICE_ID_VIA_8633_1, }; -static void vga_init(device_t dev) -{ - //unsigned long fb; - //msr_t clocks1,clocks2,instructions,setup; - - printk(BIOS_DEBUG, "VGA random fixup ...\n"); - pci_write_config8(dev, 0x04, 0x07); - pci_write_config8(dev, 0x0d, 0x20); - pci_write_config32(dev,0x10,0xd8000008); - pci_write_config32(dev,0x14,0xdc000000); - - // set up performnce counters for debugging vga init sequence - //setup.lo = 0x1c0; // count instructions - //wrmsr(0x187,setup); - //instructions.hi = 0; - //instructions.lo = 0; - //wrmsr(0xc2,instructions); - //clocks1 = rdmsr(0x10); - - -#if 0 - /* code to make vga init go through the emulator - as of yet this does not workfor the epia-m */ - pci_dev_init(dev); - - call_bios_interrupt(0x10,0x4f1f,0x8003,1,0); - - //clocks2 = rdmsr(0x10); - //instructions = rdmsr(0xc2); - - printk(BIOS_DEBUG, "Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo); - printk(BIOS_DEBUG, "Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo); - printk(BIOS_DEBUG, "Instructions = %08x:%08x\n",instructions.hi,instructions.lo); - -#else - - /* code to make vga init run in real mode - does work but against the current coreboot philosophy */ - printk(BIOS_DEBUG, "INSTALL REAL-MODE IDT\n"); - setup_realmode_idt(); - printk(BIOS_DEBUG, "DO THE VGA BIOS\n"); - do_vgabios(); - - //clocks2 = rdmsr(0x10); - //instructions = rdmsr(0xc2); - - //printk(BIOS_DEBUG, "Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo); - //printk(BIOS_DEBUG, "Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo); - //printk(BIOS_DEBUG, "Instructions = %08x:%08x\n",instructions.hi,instructions.lo); - - vga_enable_console(); - -#endif - - pci_write_config32(dev,0x30,0); - - /* Set the vga mtrrs - disable for the moment as the add_var_mtrr function has vapourised */ -#if 0 - add_var_mtrr( 0xd0000000 >> 10, 0x08000000>>10, MTRR_TYPE_WRCOMB); - fb = pci_read_config32(dev,0x10); // get the fb address - add_var_mtrr( fb>>10, 8192, MTRR_TYPE_WRCOMB); -#endif -} - -static struct device_operations vga_operations = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = vga_init, - .ops_pci = 0, -}; - -static const struct pci_driver vga_driver __pci_driver = { - .ops = &vga_operations, - .vendor = PCI_VENDOR_ID_VIA, - .device = 0x3122, -}; - static void ram_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek) { Modified: trunk/src/northbridge/via/vt8623/northbridge.h ============================================================================== --- trunk/src/northbridge/via/vt8623/northbridge.h Thu Apr 22 15:18:09 2010 (r5477) +++ trunk/src/northbridge/via/vt8623/northbridge.h Thu Apr 22 20:15:32 2010 (r5478) @@ -2,11 +2,7 @@ #define NORTHBRIDGE_VIA_VT8623_H unsigned int vt8623_scan_root_bus(device_t root, unsigned int max); - -void vga_enable_console(void); -void do_vgabios(void); -void setup_realmode_idt(void); +extern void (*vga_enable_console)(void) __attribute__((regparm(0))); void write_protect_vgabios(void); - #endif /* NORTHBRIDGE_VIA_VT8623_H */ Added: trunk/src/northbridge/via/vt8623/vga.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/northbridge/via/vt8623/vga.c Thu Apr 22 20:15:32 2010 (r5478) @@ -0,0 +1,158 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <arch/io.h> +#include <stdint.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <stdlib.h> +#include <string.h> +#include <bitops.h> +#include <cpu/cpu.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <arch/interrupt.h> +#include "chip.h" +#include "northbridge.h" + +static int via_vt8623_int15_handler(struct eregs *regs) +{ + int res=-1; + printk(BIOS_DEBUG, "via_vt8623_int15_handler\n"); + switch(regs->eax & 0xffff) { + case 0x5f19: + break; + case 0x5f18: + regs->eax=0x5f; + regs->ebx=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory + regs->ecx=0x060; + res=0; + break; + case 0x5f00: + regs->eax = 0x8600; + break; + case 0x5f01: + regs->eax = 0x5f; + regs->ecx = (regs->ecx & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768 + res = 0; + break; + case 0x5f02: + regs->eax=0x5f; + regs->ebx= (regs->ebx & 0xffff0000) | 2; + regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only + regs->edx= (regs->edx & 0xffff0000) | 0; // TV Layout - default + res=0; + break; + case 0x5f0f: + regs->eax=0x860f; + break; + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + regs->eax & 0xffff); + break; + } + return res; +} + +void write_protect_vgabios(void) +{ + device_t dev; + + printk(BIOS_DEBUG, "write_protect_vgabios\n"); + + dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3122, 0); + if (dev) + pci_write_config8(dev, 0x61, 0xaa); + + dev = dev_find_device(PCI_VENDOR_ID_VIA, 0x3123, 0); + if (dev) + pci_write_config8(dev, 0x61, 0xaa); +} + +static void vga_random_fixup(device_t dev) +{ + printk(BIOS_DEBUG, "VGA random fixup ...\n"); + pci_write_config8(dev, 0x04, 0x07); + pci_write_config8(dev, 0x0d, 0x20); + pci_write_config32(dev,0x10,0xd8000008); + pci_write_config32(dev,0x14,0xdc000000); +} + +static void vga_init(device_t dev) +{ + vga_random_fixup(dev); + + mainboard_interrupt_handlers(0x15, &via_vt8623_int15_handler); + +#ifdef MEASURE_VGA_INIT_TIME + msr_t clocks1, clocks2, instructions, setup; + + // set up performnce counters for debugging vga init sequence + setup.lo = 0x1c0; // count instructions + wrmsr(0x187,setup); + instructions.hi = 0; + instructions.lo = 0; + wrmsr(0xc2,instructions); + clocks1 = rdmsr(0x10); +#endif + printk(BIOS_DEBUG, "Initializing VGA...\n"); + + pci_dev_init(dev); + + printk(BIOS_DEBUG, "Enable VGA console\n"); + // this is how it should look: + // call_bios_interrupt(0x10,0x4f1f,0x8003,1,0); + // this is how it looks: + vga_enable_console(); + +#ifdef MEASURE_VGA_INIT_TIME + clocks2 = rdmsr(0x10); + instructions = rdmsr(0xc2); + + printk(BIOS_DEBUG, "Clocks 1 = %08x:%08x\n",clocks1.hi,clocks1.lo); + printk(BIOS_DEBUG, "Clocks 2 = %08x:%08x\n",clocks2.hi,clocks2.lo); + printk(BIOS_DEBUG, "Instructions = %08x:%08x\n",instructions.hi,instructions.lo); +#endif + + pci_write_config32(dev, 0x30, 0); + +#if 0 + /* Set the vga mtrrs - disable for the moment as the add_var_mtrr function has vapourised */ + unsigned long fb; + add_var_mtrr( 0xd0000000 >> 10, 0x08000000>>10, MTRR_TYPE_WRCOMB); + fb = pci_read_config32(dev,0x10); // get the fb address + add_var_mtrr( fb>>10, 8192, MTRR_TYPE_WRCOMB); +#endif +} + +static struct device_operations vga_operations = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = vga_init, + .ops_pci = 0, +}; + +static const struct pci_driver vga_driver __pci_driver = { + .ops = &vga_operations, + .vendor = PCI_VENDOR_ID_VIA, + .device = 0x3122, +};

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[commit] r5477 - in trunk/src: mainboard/asus/m2v-mx_se mainboard/bcom/winnetp680 mainboard/jetway/j7f24 mainboard/via/epia-cn mainboard/via/pc2500e northbridge/amd/amdk8 southbridge/via/k8t890 sou...
by repository service 22 Apr '10

22 Apr '10

Author: stepan Date: Thu Apr 22 15:18:09 2010 New Revision: 5477 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5477 Log: zero warnings days... Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c trunk/src/mainboard/bcom/winnetp680/romstage.c trunk/src/mainboard/jetway/j7f24/romstage.c trunk/src/mainboard/via/epia-cn/romstage.c trunk/src/mainboard/via/pc2500e/romstage.c trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c trunk/src/southbridge/via/k8t890/k8t890.h trunk/src/southbridge/via/k8t890/k8t890_early_car.c trunk/src/southbridge/via/vt8237r/vt8237r.h Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Thu Apr 22 12:44:08 2010 (r5476) +++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Thu Apr 22 15:18:09 2010 (r5477) @@ -57,7 +57,6 @@ #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" -#include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/early_ht.c" @@ -83,10 +82,11 @@ { } -#define K8_4RANK_DIMM_SUPPORT 1 - +// defines S3_NVRAM_EARLY: #include "southbridge/via/k8t890/k8t890_early_car.c" +#define K8_4RANK_DIMM_SUPPORT 1 + #include "northbridge/amd/amdk8/amdk8.h" #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" @@ -164,7 +164,7 @@ console_init(); enable_rom_decode(); - print_info("now booting... real_main\n"); + printk(BIOS_INFO, "now booting... \n"); if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); @@ -175,7 +175,7 @@ setup_coherent_ht_domain(); wait_all_core0_started(); - print_info("now booting... Core0 started\n"); + printk(BIOS_INFO, "now booting... All core 0 started\n"); #if CONFIG_LOGICAL_CPUS==1 /* It is said that we should start core1 after all core0 launched. */ @@ -196,12 +196,9 @@ vt8237_early_spi_init(); if (needs_reset) { - print_debug_hex8(needs_reset); - - print_debug("Xht reset -\n"); + printk(BIOS_DEBUG, "ht reset -\n"); soft_reset(); - print_debug("NO reset\n"); - + printk(BIOS_DEBUG, "FAILED!\n"); } /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ Modified: trunk/src/mainboard/bcom/winnetp680/romstage.c ============================================================================== --- trunk/src/mainboard/bcom/winnetp680/romstage.c Thu Apr 22 12:44:08 2010 (r5476) +++ trunk/src/mainboard/bcom/winnetp680/romstage.c Thu Apr 22 15:18:09 2010 (r5477) @@ -34,7 +34,6 @@ #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/lapic/boot_cpu.c" #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "superio/winbond/w83697hf/w83697hf_early_serial.c" #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) Modified: trunk/src/mainboard/jetway/j7f24/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/j7f24/romstage.c Thu Apr 22 12:44:08 2010 (r5476) +++ trunk/src/mainboard/jetway/j7f24/romstage.c Thu Apr 22 15:18:09 2010 (r5477) @@ -34,7 +34,6 @@ #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/lapic/boot_cpu.c" #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "superio/fintek/f71805f/f71805f_early_serial.c" Modified: trunk/src/mainboard/via/epia-cn/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-cn/romstage.c Thu Apr 22 12:44:08 2010 (r5476) +++ trunk/src/mainboard/via/epia-cn/romstage.c Thu Apr 22 15:18:09 2010 (r5477) @@ -34,7 +34,6 @@ #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/lapic/boot_cpu.c" #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "southbridge/via/vt8235/vt8235_early_serial.c" Modified: trunk/src/mainboard/via/pc2500e/romstage.c ============================================================================== --- trunk/src/mainboard/via/pc2500e/romstage.c Thu Apr 22 12:44:08 2010 (r5476) +++ trunk/src/mainboard/via/pc2500e/romstage.c Thu Apr 22 15:18:09 2010 (r5477) @@ -35,7 +35,6 @@ #include "cpu/x86/bist.h" #include "pc80/udelay_io.c" #include "lib/delay.c" -#include "cpu/x86/lapic/boot_cpu.c" #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "superio/ite/it8716f/it8716f_early_serial.c" Modified: trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Thu Apr 22 12:44:08 2010 (r5476) +++ trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Thu Apr 22 15:18:09 2010 (r5477) @@ -1823,8 +1823,11 @@ } #ifdef S3_NVRAM_EARLY -int s3_save_nvram_early(u32 dword, int size, int nvram_pos); -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); +// Don't define these prototypes as the real functions are already included +// at this point. +// +//int s3_save_nvram_early(u32 dword, int size, int nvram_pos); +//int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); #else static int s3_save_nvram_early(u32 dword, int size, int nvram_pos) { Modified: trunk/src/southbridge/via/k8t890/k8t890.h ============================================================================== --- trunk/src/southbridge/via/k8t890/k8t890.h Thu Apr 22 12:44:08 2010 (r5476) +++ trunk/src/southbridge/via/k8t890/k8t890.h Thu Apr 22 15:18:09 2010 (r5477) @@ -38,14 +38,17 @@ /* the FB size in MB (min is 8MB max is 512MB) */ #define K8M890_FBSIZEMB 64 +#ifdef __PRE_RAM__ +u8 k8t890_early_setup_ht(void); +#else #include <device/device.h> - #if 0 extern void writeback(struct device *dev, u16 where, u8 what); extern void dump_south(device_t dev); #endif -#include <southbridge/via/vt8237r/vt8237r.h> +#endif +#include <southbridge/via/vt8237r/vt8237r.h> int k8m890_host_fb_size_get(void); //void k8m890_host_fb_direct_set(uint32_t fb_address); Modified: trunk/src/southbridge/via/k8t890/k8t890_early_car.c ============================================================================== --- trunk/src/southbridge/via/k8t890/k8t890_early_car.c Thu Apr 22 12:44:08 2010 (r5476) +++ trunk/src/southbridge/via/k8t890/k8t890_early_car.c Thu Apr 22 15:18:09 2010 (r5477) @@ -23,12 +23,12 @@ */ #include <stdlib.h> -//include "k8t890.h" -#warning hack the right header here +#include "k8t890.h" /* The 256 bytes of NVRAM for S3 storage, 256B aligned */ #define K8T890_NVRAM_IO_BASE 0xf00 #define K8T890_MULTIPLE_FN_EN 0x4f + /* we provide S3 NVRAM to system */ #define S3_NVRAM_EARLY 1 @@ -113,7 +113,7 @@ return 1; } -int s3_save_nvram_early(u32 dword, int size, int nvram_pos) +static int s3_save_nvram_early(u32 dword, int size, int nvram_pos) { printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); @@ -134,7 +134,7 @@ return nvram_pos; } -int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) +static int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) { switch (size) { case 1: Modified: trunk/src/southbridge/via/vt8237r/vt8237r.h ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r.h Thu Apr 22 12:44:08 2010 (r5476) +++ trunk/src/southbridge/via/vt8237r/vt8237r.h Thu Apr 22 15:18:09 2010 (r5477) @@ -103,7 +103,18 @@ #endif ; -#ifndef __PRE_RAM__ +#ifdef __PRE_RAM__ +#ifndef __ROMCC__ +u8 smbus_read_byte(u8 dimm, u8 offset); +void enable_smbus(void); +void smbus_fixup(const struct mem_controller *ctrl); +// these are in vt8237_early_smbus.c - do they really belong there? +void vt8237_sb_enable_fid_vid(void); +void enable_rom_decode(void); +void vt8237_early_spi_init(void); +int vt8237_early_network_init(struct vt8237_network_rom *rom); +#endif +#else #include <device/device.h> void writeback(struct device *dev, u16 where, u8 what); void dump_south(device_t dev);

1 0

[commit] r5476 - in trunk/src: include/cpu/amd southbridge/amd/cs5536
by repository service 22 Apr '10

22 Apr '10

Author: stepan Date: Thu Apr 22 12:44:08 2010 New Revision: 5476 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5476 Log: None of the cs5536 settings in devicetree.cb were ever used and nobody noticed. Fix it! Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/include/cpu/amd/gx2def.h trunk/src/southbridge/amd/cs5536/cs5536.c Modified: trunk/src/include/cpu/amd/gx2def.h ============================================================================== --- trunk/src/include/cpu/amd/gx2def.h Thu Apr 22 11:22:15 2010 (r5475) +++ trunk/src/include/cpu/amd/gx2def.h Thu Apr 22 12:44:08 2010 (r5476) @@ -693,4 +693,11 @@ #define PMLogic_BASE ( 0x9D00) +#if !defined(__ROMCC__) && !defined(ASSEMBLY) +#if defined(__PRE_RAM__) +#else +void cpubug(void); +#endif +#endif + #endif /* CPU_AMD_GX2DEF_H */ Modified: trunk/src/southbridge/amd/cs5536/cs5536.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536.c Thu Apr 22 11:22:15 2010 (r5475) +++ trunk/src/southbridge/amd/cs5536/cs5536.c Thu Apr 22 12:44:08 2010 (r5476) @@ -527,10 +527,24 @@ device_t dev; msr_t msr; u32 msrnum; - struct southbridge_amd_cs5536_config *sb = - (struct southbridge_amd_cs5536_config *)dev->chip_info; + struct southbridge_amd_cs5536_config *sb; struct msrinit *csi; + dev = dev_find_device(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_CS5536_ISA, 0); + + if (!dev) { + printk(BIOS_ERR, "CS5536 not found.\n"); + return; + } + + sb = (struct southbridge_amd_cs5536_config *)dev->chip_info; + + if (!sb) { + printk(BIOS_ERR, "CS5536 configuration not found.\n"); + return; + } + post_code(P80_CHIPSET_INIT); /* we hope NEVER to be in coreboot when S3 resumes @@ -599,6 +613,12 @@ */ printk(BIOS_ERR, "cs5536: %s\n", __func__); + + if (!sb) { + printk(BIOS_ERR, "CS5536 configuration not found.\n"); + return; + } + setup_i8259(); lpc_init(sb); uarts_init(sb);

1 0

build service results for r5475
by coreboot information 22 Apr '10

22 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5475 to the coreboot repository. This caused the following changes: Change Log: fix compilation remaining geode boards Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:rumba has been fixed Compilation of lippert:frontrunner has been fixed Compilation of olpc:btest has been fixed Compilation of olpc:rev_a has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5475 - in trunk/src: mainboard/amd/rumba mainboard/lippert/frontrunner northbridge/amd/gx2 southbridge/amd/cs5536
by repository service 22 Apr '10

22 Apr '10

Author: stepan Date: Thu Apr 22 11:22:15 2010 New Revision: 5475 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5475 Log: fix compilation remaining geode boards Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/amd/rumba/devicetree.cb trunk/src/mainboard/lippert/frontrunner/devicetree.cb trunk/src/northbridge/amd/gx2/chipsetinit.c trunk/src/northbridge/amd/gx2/grphinit.c trunk/src/northbridge/amd/gx2/northbridge.c trunk/src/northbridge/amd/gx2/northbridge.h trunk/src/northbridge/amd/gx2/northbridgeinit.c trunk/src/southbridge/amd/cs5536/chip.h trunk/src/southbridge/amd/cs5536/cs5536.c Modified: trunk/src/mainboard/amd/rumba/devicetree.cb ============================================================================== --- trunk/src/mainboard/amd/rumba/devicetree.cb Thu Apr 22 02:52:42 2010 (r5474) +++ trunk/src/mainboard/amd/rumba/devicetree.cb Thu Apr 22 11:22:15 2010 (r5475) @@ -1,4 +1,6 @@ chip northbridge/amd/gx2 + register "setupflash" = "0" + #register "irqmap" = "0xaa5b" device apic_cluster 0 on chip cpu/amd/model_gx2 device apic 0 on end Modified: trunk/src/mainboard/lippert/frontrunner/devicetree.cb ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/devicetree.cb Thu Apr 22 02:52:42 2010 (r5474) +++ trunk/src/mainboard/lippert/frontrunner/devicetree.cb Thu Apr 22 11:22:15 2010 (r5475) @@ -1,4 +1,6 @@ chip northbridge/amd/gx2 + register "setupflash" = "0" + #register "irqmap" = "0xaa5b" device pci_domain 0 on device pci 0.0 on end chip southbridge/amd/cs5535 Modified: trunk/src/northbridge/amd/gx2/chipsetinit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/chipsetinit.c Thu Apr 22 02:52:42 2010 (r5474) +++ trunk/src/northbridge/amd/gx2/chipsetinit.c Thu Apr 22 11:22:15 2010 (r5475) @@ -12,9 +12,8 @@ #include <cpu/amd/gx2def.h> #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> -#include "../../../southbridge/amd/cs5536/cs5536.h" +#include "southbridge/amd/cs5536/cs5536.h" -extern int sizeram(void); /* the structs in this file only set msr.lo. But ... that may not always be true */ struct msrinit { @@ -22,13 +21,13 @@ msr_t msr; }; -/* Master Configuration Register for Bus Masters.*/ -struct msrinit SB_MASTER_CONF_TABLE[] = { - {USB1_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000}}, /* NOTE: Must be 1st entry in table*/ - {USB2_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000}}, - {ATA_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00048f000}}, - {AC97_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000}}, - {MDD_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00000f000}}, +/* Master Configuration Register for Bus Masters. */ +static struct msrinit SB_MASTER_CONF_TABLE[] = { + { USB1_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000} }, /* NOTE: Must be 1st entry in table */ + { USB2_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000} }, + { ATA_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00048f000} }, + { AC97_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00008f000} }, + { MDD_SB_GLD_MSR_CONF, {.hi=0,.lo=0x00000f000} }, /* GLPCI_SB_GLD_MSR_CONF, 0x0FFFFFFFF*/ /* GLCP_SB_GLD_MSR_CONF, 0x0FFFFFFFF*/ /* GLIU_SB_GLD_MSR_CONF, 0x0*/ @@ -36,37 +35,38 @@ }; /* 5535_A3 Clock Gating*/ -struct msrinit CS5535_CLOCK_GATING_TABLE[] = { - { USB1_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - { USB2_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - { GLIU_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000004}}, - { GLPCI_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - { GLCP_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000004}}, - { MDD_SB_GLD_MSR_PM, {.hi=0,.lo=0x050554111}}, - { ATA_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - { AC97_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - {0,{0,0}} +static struct msrinit CS5535_CLOCK_GATING_TABLE[] = { + { USB1_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, + { USB2_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, + { GLIU_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000004} }, + { GLPCI_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, + { GLCP_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000004} }, + { MDD_SB_GLD_MSR_PM, {.hi=0, .lo=0x050554111} }, + { ATA_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, + { AC97_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, + { 0, {.hi=0, .lo=0x000000000} } }; /* 5536 Clock Gating*/ -struct msrinit CS5536_CLOCK_GATING_TABLE[] = { +static struct msrinit CS5536_CLOCK_GATING_TABLE[] = { /* MSR Setting*/ - { GLIU_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000004}}, - { GLPCI_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - { GLCP_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000004}}, - { MDD_SB_GLD_MSR_PM, {.hi=0,.lo=0x050554111}}, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977)*/ - { ATA_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - { AC97_SB_GLD_MSR_PM, {.hi=0,.lo=0x000000005}}, - {0,{0,0}} + { GLIU_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000004} }, + { GLPCI_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, + { GLCP_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000004} }, + { MDD_SB_GLD_MSR_PM, {.hi=0, .lo=0x050554111} }, /* SMBus clock gating errata (PBZ 2226 & SiBZ 3977) */ + { ATA_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, + { AC97_SB_GLD_MSR_PM, {.hi=0, .lo=0x000000005} }, + { 0, {.hi=0, .lo=0x000000000} } }; +#ifdef UNUSED_CODE struct acpiinit { unsigned short ioreg; unsigned long regdata; unsigned short iolen; }; -struct acpiinit acpi_init_table[] = { +static struct acpiinit acpi_init_table[] = { {ACPI_BASE+0x00, 0x01000000, 4}, {ACPI_BASE+0x08, 0, 4}, {ACPI_BASE+0x0C, 0, 4}, @@ -81,34 +81,28 @@ {PM_WKXD, 0x0000000A0, 4}, {0,0,0} }; +#endif /* return 1 if we are a 5536-based system */ -static int is_5536(void){ +static int is_5536(void) +{ msr_t msr; msr = rdmsr(GLIU_SB_GLD_MSR_CAP); msr.lo >>= 20; printk(BIOS_DEBUG, "is_5536: msr.lo is 0x%x(==5 means 5536)\n", msr.lo&0xf); return ((msr.lo&0xf) == 5); } -/* ***************************************************************************/ -/* **/ -/* * pmChipsetInit*/ -/* **/ -/* * Program ACPI LBAR and initialize ACPI registers.*/ -/* * */ -/* **/ -/* * Entry:*/ -/* * None*/ -/* **/ -/* * Exit:*/ -/* * None*/ -/* **/ -/* * Destroys:*/ -/* * None*/ -/* **/ -/* ***************************************************************************/ -static void -pmChipsetInit(void) { + +#ifdef UNUSED_CODE +/***************************************************************************** + * + * pmChipsetInit + * + * Program ACPI LBAR and initialize ACPI registers. + * + *****************************************************************************/ +static void pmChipsetInit(void) +{ unsigned long val = 0; unsigned short port; @@ -129,40 +123,43 @@ /* PM_SED*/ port = (PMLogic_BASE + 0x014); -/* mov eax, 0x057642 ; 100ms, works*/ val = 0x04601 ; /* 5ms*/ outl(val, port); /* PM_SIDD*/ port = (PMLogic_BASE + 0x020); -/* mov eax, 0x0AEC84 ; 200ms, works*/ val = 0x08C02 ; /* 10ms*/ outl(val, port); - /* GPIO24 OUT_AUX1 function is the external signal for 5535's vsb_working_aux*/ - /* which is de-asserted when 5535 enters Standby(S3 or S5) state.*/ - /* On Hawk, GPIO24 controls all voltage rails except Vmem and Vstandby. This means*/ - /* GX2 will be fully de-powered if this control de-asserts in S3/S5.*/ - /* */ - /* GPIO24 is setup in preChipsetInit for two reasons*/ - /* 1. GPIO24 at reset defaults to disabled, since this signal is vsb_work_aux on*/ - /* Hawk it controls the FET's for all voltage rails except Vstanby & Vmem.*/ - /* BIOS needs to enable GPIO24 as OUT_AUX1 & OUTPUT_EN early so it is driven*/ - /* by 5535.*/ - /* 2. Non-PM builds will require GPIO24 enabled for instant-off power button*/ - /* */ - - /* GPIO11 OUT_AUX1 function is the external signal for 5535's slp_clk_n which is asserted*/ - /* when 5535 enters Sleep(S1) state.*/ - /* On Hawk, GPIO11 is connected to control input of external clock generator*/ - /* for 14MHz, PCI, USB & LPC clocks.*/ - /* Programming of GPIO11 will be done by VSA PM code. During VSA Init. BIOS writes*/ - /* PM Core Virual Register indicating if S1 Clocks should be On or Off. This is based*/ - /* on a Setup item. We do not want to leave GPIO11 enabled because of a Hawk board*/ - /* problem. With GPIO11 enabled in S3, something is back-driving GPIO11 causing it to*/ - /* float to 1.6-1.7V.*/ - + /* GPIO24 OUT_AUX1 function is the external signal for 5535's + * vsb_working_aux which is de-asserted when 5535 enters Standby (S3 or + * S5) state. On Hawk, GPIO24 controls all voltage rails except Vmem + * and Vstandby. This means GX2 will be fully de-powered if this + * control de-asserts in S3/S5. + */ + + /* GPIO24 is setup in preChipsetInit for two reasons + * 1. GPIO24 at reset defaults to disabled, since this signal is + * vsb_work_aux on Hawk it controls the FET's for all voltage + * rails except Vstanby & Vmem. BIOS needs to enable GPIO24 as + * OUT_AUX1 & OUTPUT_EN early so it is driven by 5535. + * 2. Non-PM builds will require GPIO24 enabled for instant-off power + * button + */ + + /* GPIO11 OUT_AUX1 function is the external signal for 5535's + * slp_clk_n which is asserted when 5535 enters Sleep(S1) state. + * On Hawk, GPIO11 is connected to control input of external clock + * generator for 14MHz, PCI, USB & LPC clocks. + * Programming of GPIO11 will be done by VSA PM code. During VSA + * Init. BIOS writes PM Core Virual Register indicating if S1 Clocks + * should be On or Off. This is based on a Setup item. We do not want + * to leave GPIO11 enabled because of a Hawk board problem. With + * GPIO11 enabled in S3, something is back-driving GPIO11 causing it + * to float to 1.6-1.7V. + */ } +#endif struct FLASH_DEVICE { unsigned char fType; /* Flash type: NOR or NAND */ @@ -170,7 +167,7 @@ unsigned long fMask; /* Flash size/mask */ }; -struct FLASH_DEVICE FlashInitTable[] = { +static struct FLASH_DEVICE FlashInitTable[] = { { FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K }, /* CS0, or Flash Device 0 */ { FLASH_TYPE_NONE, 0, 0 }, /* CS1, or Flash Device 1 */ { FLASH_TYPE_NONE, 0, 0 }, /* CS2, or Flash Device 2 */ @@ -179,12 +176,12 @@ #define FlashInitTableLen (ARRAY_SIZE(FlashInitTable)) -uint32_t FlashPort[] = { +static uint32_t FlashPort[] = { MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LBAR_FLSH2, MDD_LBAR_FLSH3 - }; +}; /*************************************************************************** * @@ -194,10 +191,6 @@ * correct size info. Call this routine only if flash needs to be * configured (don't call it if you want IDE). * - * Entry: - * Exit: - * Destroys: - * **************************************************************************/ static void ChipsetFlashSetup(void) { @@ -242,34 +235,34 @@ printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", MDD_PIN_OPT, msr.hi, msr.lo); wrmsr(MDD_PIN_OPT, msr); } - printk(BIOS_DEBUG, "ChipsetFlashSetup--\n"); + printk(BIOS_DEBUG, "ChipsetFlashSetup--\n"); } -/* ***************************************************************************/ -/* **/ -/* * ChipsetGeodeLinkInit*/ -/* * Handle chipset specific GeodeLink settings here. */ -/* * Called from GeodeLink init code.*/ -/* **/ -/* * Entry:*/ -/* * Exit:*/ -/* * Destroys: GS*/ -/* **/ -/* ***************************************************************************/ +/**************************************************************************** + * + * ChipsetGeodeLinkInit + * + * Handle chipset specific GeodeLink settings here. + * Called from GeodeLink init code. + * + ****************************************************************************/ static void -ChipsetGeodeLinkInit(void){ +ChipsetGeodeLinkInit(void) +{ msr_t msr; unsigned long msrnum; unsigned long totalmem; if (is_5536()) return; + /* SWASIF for A1 DMA */ - /* Set all memory to "just above systop" PCI so DMA will work*/ - /* check A1*/ + /* Set all memory to "just above systop" PCI so DMA will work */ + + /* check A1 */ msrnum = MSR_SB_GLCP + 0x17; msr = rdmsr(msrnum); if ((msr.lo&0xff) == 0x11) @@ -280,13 +273,14 @@ totalmem = ~totalmem; totalmem &= 0xfffff; msr.lo = totalmem; - msr.hi = 0x20000000; /* Port 1 (PCI)*/ - msrnum = MSR_SB_GLIU + 0x20; /* */; + msr.hi = 0x20000000; /* Port 1 (PCI) */ + msrnum = MSR_SB_GLIU + 0x20; wrmsr(msrnum, msr); } void -chipsetinit (struct northbridge_amd_gx2_config *nb){ +gx2_chipsetinit (struct northbridge_amd_gx2_config *nb) +{ msr_t msr; struct msrinit *csi; int i; @@ -294,7 +288,10 @@ outb( P80_CHIPSET_INIT, 0x80); ChipsetGeodeLinkInit(); -#if 0 + + printk(BIOS_DEBUG, "Companion is a %s\n", is_5536()?"CS5536":"CS5535"); + +#ifdef UNUSED_CODE /* we hope NEVER to be in coreboot when S3 resumes if (! IsS3Resume()) */ { @@ -313,9 +310,8 @@ } #endif - if (!is_5536()) { - /* Setup USB. Need more details. #118.18*/ + /* Setup USB. Need more details. #118.18 */ msrnum = MSR_SB_USB1 + 8; msr.lo = 0x00012090; msr.hi = 0; @@ -328,24 +324,23 @@ outl (GPIOL_2_SET, GPIOL_INPUT_ENABLE); outl (GPIOL_2_SET, GPIOL_IN_AUX1_SELECT); - /* Allow IO read and writes during a ATA DMA operation.*/ - /* This could be done in the HD rom but do it here for easier debugging.*/ + /* Allow IO read and writes during a ATA DMA operation. */ + /* This could be done in the HD rom but do it here for easier debugging. */ msrnum = ATA_SB_GLD_MSR_ERR; msr = rdmsr(msrnum); msr.lo &= ~0x100; wrmsr(msrnum, msr); - /* Enable Post Primary IDE.*/ + /* Enable Post Primary IDE. */ msrnum = GLPCI_SB_CTRL; msr = rdmsr(msrnum); msr.lo |= GLPCI_CRTL_PPIDE_SET; wrmsr(msrnum, msr); - - /* Set up Master Configuration Register*/ - /* If 5536, use same master config settings as 5535, except for OHCI MSRs*/ - if (is_5536()) + /* Set up Master Configuration Register */ + /* If 5536, use same master config settings as 5535, except for OHCI MSRs */ + if (is_5536()) i = 2; else i = 0; @@ -357,17 +352,15 @@ wrmsr(csi->msrnum, msr); // MSR - see table above } + /* Flash Setup */ + printk(BIOS_INFO, "%sDOING ChipsetFlashSetup()!\n", + nb->setupflash ? "" : "NOT "); - /* Flash Setup*/ - printk(BIOS_ERR, "%sDOING ChipsetFlashSetup()!!!!!!!!!!!!!!!!!!\n", nb->setupflash? " " : "NOT"); if (nb->setupflash) ChipsetFlashSetup(); + /* Set up Hardware Clock Gating */ - - /* */ - /* Set up Hardware Clock Gating*/ - /* */ /* if (getnvram(TOKEN_SB_CLK_GATE) != TVALUE_DISABLE) */ { if (is_5536()) @@ -381,5 +374,5 @@ wrmsr(csi->msrnum, msr); // MSR - see table above } } - } + Modified: trunk/src/northbridge/amd/gx2/grphinit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/grphinit.c Thu Apr 22 02:52:42 2010 (r5474) +++ trunk/src/northbridge/amd/gx2/grphinit.c Thu Apr 22 11:22:15 2010 (r5475) @@ -1,7 +1,11 @@ #include <arch/io.h> #include <stdint.h> #include <cpu/amd/vr.h> +#include <device/device.h> +#include "chip.h" +#include "northbridge.h" +// FIXME handle UMA properly. #define VIDEO_MB 8 // MB of video memory Modified: trunk/src/northbridge/amd/gx2/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridge.c Thu Apr 22 02:52:42 2010 (r5474) +++ trunk/src/northbridge/amd/gx2/northbridge.c Thu Apr 22 11:22:15 2010 (r5475) @@ -17,8 +17,6 @@ #include "../../../southbridge/amd/cs5536/cs5536.h" #define VIDEO_MB 8 -extern void graphics_init(void); - #define NORTHBRIDGE_FILE "northbridge.c" /* todo: add a resource record. We don't do this here because this may be called when @@ -190,7 +188,7 @@ } /* we have to do this here. We have not found a nicer way to do it */ -void +static void setup_gx2(void) { @@ -371,6 +369,7 @@ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } +#if 0 static void tolm_test(void *gp, struct device *dev, struct resource *new) { struct resource **best_p = gp; @@ -382,7 +381,6 @@ *best_p = best; } -#if 0 static u32 find_pci_tolm(struct bus *bus) { struct resource *min; @@ -396,6 +394,8 @@ return tolm; } #endif + +// FIXME handle UMA correctly. #define FRAMEBUFFERK 4096 static void pci_domain_set_resources(device_t dev) @@ -484,19 +484,17 @@ static void enable_dev(struct device *dev) { printk(BIOS_DEBUG, "gx2 north: enable_dev\n"); - void northbridgeinit(void); - void chipsetinit(struct northbridge_amd_gx2_config *nb); void do_vsmbios(void); + /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) { struct northbridge_amd_gx2_config *nb = (struct northbridge_amd_gx2_config *)dev->chip_info; - extern void cpubug(void); u32 tomk; printk(BIOS_DEBUG, "DEVICE_PATH_PCI_DOMAIN\n"); /* cpubug MUST be called before setup_gx2(), so we force the issue here */ northbridgeinit(); - cpubug(); - chipsetinit(nb); + cpubug(); + gx2_chipsetinit(nb); setup_gx2(); do_vsmbios(); graphics_init(); Modified: trunk/src/northbridge/amd/gx2/northbridge.h ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridge.h Thu Apr 22 02:52:42 2010 (r5474) +++ trunk/src/northbridge/amd/gx2/northbridge.h Thu Apr 22 11:22:15 2010 (r5475) @@ -1,6 +1,15 @@ #ifndef NORTHBRIDGE_AMD_GX2_H #define NORTHBRIDGE_AMD_GX2_H -extern unsigned int gx2_scan_root_bus(device_t root, unsigned int max); +#if !defined(__ROMCC__) && !defined(ASSEMBLY) +#if defined(__PRE_RAM__) +#else +unsigned int gx2_scan_root_bus(device_t root, unsigned int max); +int sizeram(void); +void gx2_chipsetinit (struct northbridge_amd_gx2_config *nb); +void graphics_init(void); +void northbridgeinit(void); +#endif +#endif #endif /* NORTHBRIDGE_AMD_GX2_H */ Modified: trunk/src/northbridge/amd/gx2/northbridgeinit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridgeinit.c Thu Apr 22 02:52:42 2010 (r5474) +++ trunk/src/northbridge/amd/gx2/northbridgeinit.c Thu Apr 22 11:22:15 2010 (r5475) @@ -135,7 +135,6 @@ */ /* yes, this duplicates later code, but it seems that is how they want it done. */ -extern int sizeram(void); static void SysmemInit(struct gliutable *gl) { Modified: trunk/src/southbridge/amd/cs5536/chip.h ============================================================================== --- trunk/src/southbridge/amd/cs5536/chip.h Thu Apr 22 02:52:42 2010 (r5474) +++ trunk/src/southbridge/amd/cs5536/chip.h Thu Apr 22 11:22:15 2010 (r5475) @@ -40,7 +40,6 @@ unsigned int com2_address; /* e.g. 0x2F8 */ unsigned int com2_irq; /* e.g. 3 */ unsigned int unwanted_vpci[MAX_UNWANTED_VPCI]; /* the following allow you to disable unwanted virtualized PCI devices */ - }; #endif /* _SOUTHBRIDGE_AMD_CS5536 */ Modified: trunk/src/southbridge/amd/cs5536/cs5536.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536.c Thu Apr 22 02:52:42 2010 (r5474) +++ trunk/src/southbridge/amd/cs5536/cs5536.c Thu Apr 22 11:22:15 2010 (r5475) @@ -40,7 +40,7 @@ }; /* Master Configuration Register for Bus Masters.*/ -struct msrinit SB_MASTER_CONF_TABLE[] = { +static struct msrinit SB_MASTER_CONF_TABLE[] = { {USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}}, {ATA_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00048f000}}, {AC97_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000}}, @@ -49,7 +49,7 @@ }; /* 5536 Clock Gating*/ -struct msrinit CS5536_CLOCK_GATING_TABLE[] = { +static struct msrinit CS5536_CLOCK_GATING_TABLE[] = { /* MSR Setting*/ {GLIU_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000004}}, {GLPCI_SB_GLD_MSR_PM, {.hi = 0,.lo = 0x000000005}}, @@ -65,7 +65,7 @@ u32 regdata; }; -struct acpiinit acpi_init_table[] = { +static struct acpiinit acpi_init_table[] = { {ACPI_IO_BASE + 0x00, 0x01000000}, {ACPI_IO_BASE + 0x08, 0}, {ACPI_IO_BASE + 0x0C, 0}, @@ -86,7 +86,7 @@ unsigned long fMask; /* Flash size/mask */ }; -struct FLASH_DEVICE FlashInitTable[] = { +static struct FLASH_DEVICE FlashInitTable[] = { {FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K}, /* CS0, or Flash Device 0 */ {FLASH_TYPE_NONE, 0, 0}, /* CS1, or Flash Device 1 */ {FLASH_TYPE_NONE, 0, 0}, /* CS2, or Flash Device 2 */ @@ -95,7 +95,7 @@ #define FlashInitTableLen (ARRAY_SIZE(FlashInitTable)) -u32 FlashPort[] = { +static u32 FlashPort[] = { MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, MDD_LBAR_FLSH2, @@ -512,12 +512,16 @@ } } -/* ***************************************************************************/ -/* **/ -/* * ChipsetInit */ -/* Called from northbridge init (Pre-VSA). */ -/* **/ -/* ***************************************************************************/ +/**************************************************************************** + * + * ChipsetInit + * + * Called from northbridge init (Pre-VSA). + * + * NOTE! This function is NOT called if the CS5536 is combined with + * an AMD Geode GX2. It's ONLY used on Geode LX based systems. + * + ****************************************************************************/ void chipsetinit(void) { device_t dev;

1 0

Five lines of bling, anyone?
by Peter Stuge 22 Apr '10

22 Apr '10

/| /| ___ ___ _ __ ___| |__ ___ ___ | |_ / __|/ _ \| '__/ _ \ '_ \/ _ \/ _ \| __| | (__| (_) | | | __/ |_)| (_)| (_) | |_ \___|\___/|_| \___|_.__/\___/\___/ \__| //Peter

5 4

build service results for r5474
by coreboot information 21 Apr '10

21 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5474 to the coreboot repository. This caused the following changes: Change Log: fix ARRAY_SIZE issue. the gx2+5536 issue is still open, and it reveils a serious problem with the code that was hidden under a bunch of warnings until now. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:norwich has been fixed Compilation of amd:rumba is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5474&device=rumba&vendor=a… Compilation of digitallogic:msm800sev has been fixed Compilation of iei:pcisa-lx-800-r10 has been fixed Compilation of lippert:frontrunner is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5474&device=frontrunner&ve… Compilation of olpc:btest is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5474&device=btest&vendor=o… Compilation of olpc:rev_a is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5474&device=rev_a&vendor=o… Compilation of pcengines:alix1c has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5474 - trunk/src/cpu/amd/model_lx
by repository service 21 Apr '10

21 Apr '10

Author: stepan Date: Thu Apr 22 02:52:42 2010 New Revision: 5474 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5474 Log: fix ARRAY_SIZE issue. the gx2+5536 issue is still open, and it reveils a serious problem with the code that was hidden under a bunch of warnings until now. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/amd/model_lx/msrinit.c Modified: trunk/src/cpu/amd/model_lx/msrinit.c ============================================================================== --- trunk/src/cpu/amd/model_lx/msrinit.c Wed Apr 21 22:55:38 2010 (r5473) +++ trunk/src/cpu/amd/model_lx/msrinit.c Thu Apr 22 02:52:42 2010 (r5474) @@ -17,6 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <stdlib.h> + struct msrinit { u32 msrnum; msr_t msr;

1 0

build service results for r5473
by coreboot information 21 Apr '10

21 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5473 to the coreboot repository. This caused the following changes: Change Log: oops, sorry for the last commit. This commit changes the code to distinguish between having VSA functionality in the code, and adding a VSA image to the ROM. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of amd:db800 has been fixed Compilation of amd:norwich is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5473&device=norwich&vendor… Compilation of amd:rumba is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5473&device=rumba&vendor=a… Compilation of artecgroup:dbe61 has been fixed Compilation of digitallogic:msm800sev is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5473&device=msm800sev&vend… Compilation of iei:pcisa-lx-800-r10 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5473&device=pcisa-lx-800-r… Compilation of lippert:frontrunner is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5473&device=frontrunner&ve… Compilation of lippert:roadrunner-lx has been fixed Compilation of lippert:spacerunner-lx has been fixed Compilation of olpc:btest is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5473&device=btest&vendor=o… Compilation of olpc:rev_a is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5473&device=rev_a&vendor=o… Compilation of pcengines:alix1c is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5473&device=alix1c&vendor=… Compilation of winent:pl6064 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot April 2010