coreboot April 2010

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[commit] r5491 - in trunk/src/mainboard/amd: mahogany mahogany_fam10 tilapia_fam10
by repository service 25 Apr '10

25 Apr '10

Author: zbao Date: Sun Apr 25 13:57:21 2010 New Revision: 5491 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5491 Log: Trivial. The comment also need to modify. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Modified: trunk/src/mainboard/amd/mahogany/dsdt.asl trunk/src/mainboard/amd/mahogany_fam10/dsdt.asl trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl Modified: trunk/src/mainboard/amd/mahogany/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/mahogany/dsdt.asl Sun Apr 25 13:53:09 2010 (r5490) +++ trunk/src/mainboard/amd/mahogany/dsdt.asl Sun Apr 25 13:57:21 2010 (r5491) @@ -271,7 +271,7 @@ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset * The 8 comes from 8 functions per device, and 4096 bytes per function config space */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ STB5, 32, Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ PT0D, 1, Modified: trunk/src/mainboard/amd/mahogany_fam10/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/dsdt.asl Sun Apr 25 13:53:09 2010 (r5490) +++ trunk/src/mainboard/amd/mahogany_fam10/dsdt.asl Sun Apr 25 13:57:21 2010 (r5491) @@ -313,7 +313,7 @@ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset * The 8 comes from 8 functions per device, and 4096 bytes per function config space */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ STB5, 32, Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ PT0D, 1, Modified: trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl Sun Apr 25 13:53:09 2010 (r5490) +++ trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl Sun Apr 25 13:57:21 2010 (r5491) @@ -313,7 +313,7 @@ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset * The 8 comes from 8 functions per device, and 4096 bytes per function config space */ - Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ STB5, 32, Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ PT0D, 1,

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[commit] r5490 - in trunk/src/mainboard/amd: mahogany mahogany/acpi mahogany_fam10 mahogany_fam10/acpi tilapia_fam10 tilapia_fam10/acpi
by repository service 25 Apr '10

25 Apr '10

Author: zbao Date: Sun Apr 25 13:53:09 2010 New Revision: 5490 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5490 Log: The device number of SATA SB700 is 0x11, while the one of SB600 is 0x12. We changed almost associated code when we ported but overlooked some. Some legacy of SB600 are also fixed. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/amd/mahogany/acpi/sata.asl trunk/src/mainboard/amd/mahogany/dsdt.asl trunk/src/mainboard/amd/mahogany_fam10/acpi/sata.asl trunk/src/mainboard/amd/mahogany_fam10/dsdt.asl trunk/src/mainboard/amd/tilapia_fam10/acpi/sata.asl trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl Modified: trunk/src/mainboard/amd/mahogany/acpi/sata.asl ============================================================================== --- trunk/src/mainboard/amd/mahogany/acpi/sata.asl Sun Apr 25 01:16:23 2010 (r5489) +++ trunk/src/mainboard/amd/mahogany/acpi/sata.asl Sun Apr 25 13:53:09 2010 (r5490) @@ -23,7 +23,7 @@ Scope (_SB) { Device(PCI0) { Device(SATA) { - Name(_ADR, 0x00120000) + Name(_ADR, 0x00110000) #include "sata.asl" } } Modified: trunk/src/mainboard/amd/mahogany/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/mahogany/dsdt.asl Sun Apr 25 01:16:23 2010 (r5489) +++ trunk/src/mainboard/amd/mahogany/dsdt.asl Sun Apr 25 13:53:09 2010 (r5490) @@ -271,7 +271,7 @@ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset * The 8 comes from 8 functions per device, and 4096 bytes per function config space */ - Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ STB5, 32, Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ PT0D, 1, @@ -1447,7 +1447,7 @@ Store (0x02, SIOD) } /* - * Keyboard PME is routed to SB600 Gevent3. We can wake + * Keyboard PME is routed to SB700 Gevent3. We can wake * up the system by pressing the key. */ Method (SIOS, 1) Modified: trunk/src/mainboard/amd/mahogany_fam10/acpi/sata.asl ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/acpi/sata.asl Sun Apr 25 01:16:23 2010 (r5489) +++ trunk/src/mainboard/amd/mahogany_fam10/acpi/sata.asl Sun Apr 25 13:53:09 2010 (r5490) @@ -23,7 +23,7 @@ Scope (_SB) { Device(PCI0) { Device(SATA) { - Name(_ADR, 0x00120000) + Name(_ADR, 0x00110000) #include "sata.asl" } } Modified: trunk/src/mainboard/amd/mahogany_fam10/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/dsdt.asl Sun Apr 25 01:16:23 2010 (r5489) +++ trunk/src/mainboard/amd/mahogany_fam10/dsdt.asl Sun Apr 25 13:53:09 2010 (r5490) @@ -313,7 +313,7 @@ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset * The 8 comes from 8 functions per device, and 4096 bytes per function config space */ - Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ STB5, 32, Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ PT0D, 1, @@ -1489,7 +1489,7 @@ Store (0x02, SIOD) } /* - * Keyboard PME is routed to SB600 Gevent3. We can wake + * Keyboard PME is routed to SB700 Gevent3. We can wake * up the system by pressing the key. */ Method (SIOS, 1) Modified: trunk/src/mainboard/amd/tilapia_fam10/acpi/sata.asl ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/acpi/sata.asl Sun Apr 25 01:16:23 2010 (r5489) +++ trunk/src/mainboard/amd/tilapia_fam10/acpi/sata.asl Sun Apr 25 13:53:09 2010 (r5490) @@ -23,7 +23,7 @@ Scope (_SB) { Device(PCI0) { Device(SATA) { - Name(_ADR, 0x00120000) + Name(_ADR, 0x00110000) #include "sata.asl" } } Modified: trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl Sun Apr 25 01:16:23 2010 (r5489) +++ trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl Sun Apr 25 13:53:09 2010 (r5490) @@ -313,7 +313,7 @@ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset * The 8 comes from 8 functions per device, and 4096 bytes per function config space */ - Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ STB5, 32, Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ PT0D, 1, @@ -1489,7 +1489,7 @@ Store (0x02, SIOD) } /* - * Keyboard PME is routed to SB600 Gevent3. We can wake + * Keyboard PME is routed to SB700 Gevent3. We can wake * up the system by pressing the key. */ Method (SIOS, 1)

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[patch]remove sb600 legacy code
by Zheng Bao 25 Apr '10

25 Apr '10

The device number of SATA SB700 is 0x11, while the one of SB600 is 0x12. We changed almost associated code when we ported but overlooked some. Some legacy of SB600 are also fixed. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: src/mainboard/amd/mahogany/dsdt.asl =================================================================== --- src/mainboard/amd/mahogany/dsdt.asl (revision 5485) +++ src/mainboard/amd/mahogany/dsdt.asl (working copy) @@ -271,7 +271,7 @@ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset * The 8 comes from 8 functions per device, and 4096 bytes per function config space */ - Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ STB5, 32, Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ PT0D, 1, @@ -1447,7 +1447,7 @@ Store (0x02, SIOD) } /* - * Keyboard PME is routed to SB600 Gevent3. We can wake + * Keyboard PME is routed to SB700 Gevent3. We can wake * up the system by pressing the key. */ Method (SIOS, 1) Index: src/mainboard/amd/mahogany/acpi/sata.asl =================================================================== --- src/mainboard/amd/mahogany/acpi/sata.asl (revision 5485) +++ src/mainboard/amd/mahogany/acpi/sata.asl (working copy) @@ -23,7 +23,7 @@ Scope (_SB) { Device(PCI0) { Device(SATA) { - Name(_ADR, 0x00120000) + Name(_ADR, 0x00110000) #include "sata.asl" } } Index: src/mainboard/amd/mahogany_fam10/dsdt.asl =================================================================== --- src/mainboard/amd/mahogany_fam10/dsdt.asl (revision 5485) +++ src/mainboard/amd/mahogany_fam10/dsdt.asl (working copy) @@ -313,7 +313,7 @@ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset * The 8 comes from 8 functions per device, and 4096 bytes per function config space */ - Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ STB5, 32, Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ PT0D, 1, @@ -1489,7 +1489,7 @@ Store (0x02, SIOD) } /* - * Keyboard PME is routed to SB600 Gevent3. We can wake + * Keyboard PME is routed to SB700 Gevent3. We can wake * up the system by pressing the key. */ Method (SIOS, 1) Index: src/mainboard/amd/mahogany_fam10/acpi/sata.asl =================================================================== --- src/mainboard/amd/mahogany_fam10/acpi/sata.asl (revision 5485) +++ src/mainboard/amd/mahogany_fam10/acpi/sata.asl (working copy) @@ -23,7 +23,7 @@ Scope (_SB) { Device(PCI0) { Device(SATA) { - Name(_ADR, 0x00120000) + Name(_ADR, 0x00110000) #include "sata.asl" } } Index: src/mainboard/amd/tilapia_fam10/acpi/sata.asl =================================================================== --- src/mainboard/amd/tilapia_fam10/acpi/sata.asl (revision 5485) +++ src/mainboard/amd/tilapia_fam10/acpi/sata.asl (working copy) @@ -23,7 +23,7 @@ Scope (_SB) { Device(PCI0) { Device(SATA) { - Name(_ADR, 0x00120000) + Name(_ADR, 0x00110000) #include "sata.asl" } } Index: src/mainboard/amd/tilapia_fam10/dsdt.asl =================================================================== --- src/mainboard/amd/tilapia_fam10/dsdt.asl (revision 5485) +++ src/mainboard/amd/tilapia_fam10/dsdt.asl (working copy) @@ -313,7 +313,7 @@ * ((bus number + 1) * ((device number * 8) * 4096)) + register offset * The 8 comes from 8 functions per device, and 4096 bytes per function config space */ - Offset(0x00090024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 18, Function 0 */ STB5, 32, Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ PT0D, 1, @@ -1489,7 +1489,7 @@ Store (0x02, SIOD) } /* - * Keyboard PME is routed to SB600 Gevent3. We can wake + * Keyboard PME is routed to SB700 Gevent3. We can wake * up the system by pressing the key. */ Method (SIOS, 1) _________________________________________________________________ Hotmail: Powerful Free email with security by Microsoft. https://signup.live.com/signup.aspx?id=60969

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[patch] Rename the intermediate file created by iasl
by Zheng Bao 25 Apr '10

25 Apr '10

For the mainboard with AMD Family 10, if we make clean and make again, it will fail. why? After make clean, .c files created by iasl are still left in the build folder, it will match the rule of $(obj)/%.o: $(obj)/%.c $(obj)/config.h @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -c -o $@ $< it will miss the rule which should be applied. define objs_asl_template .... So we move the .c file back to .hex (or other suffix? or delete?). This patch will work after make distclean, otherwise nobody will rename the .c. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: Makefile =================================================================== --- Makefile (revision 5489) +++ Makefile (working copy) @@ -226,6 +226,7 @@ iasl -p $$(basename $$@) -tc $$(basename $$(a)).asl mv $$(basename $$(a)).hex $$(basename $$(a)).c $(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $$@))), -DAmlCode=AmlCode_$$(basename $$(notdir $$@))) -c -o $$@ $$(basename $$(a)).c + mv $$(basename $$(a)).c $$(basename $$(a)).hex endef # macro to define template macros that are used by use_template macro _________________________________________________________________ Your E-mail and More On-the-Go. Get Windows Live Hotmail Free. https://signup.live.com/signup.aspx?id=60969

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[commit] r5489 - trunk/src/cpu/intel/model_6xx
by repository service 25 Apr '10

25 Apr '10

Author: stepan Date: Sun Apr 25 01:16:23 2010 New Revision: 5489 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5489 Log: these cpus are explicitly supported by model_6bx Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/cpu/intel/model_6xx/model_6xx_init.c Modified: trunk/src/cpu/intel/model_6xx/model_6xx_init.c ============================================================================== --- trunk/src/cpu/intel/model_6xx/model_6xx_init.c Sun Apr 25 01:15:23 2010 (r5488) +++ trunk/src/cpu/intel/model_6xx/model_6xx_init.c Sun Apr 25 01:16:23 2010 (r5489) @@ -57,9 +57,6 @@ { X86_VENDOR_INTEL, 0x06A0 }, { X86_VENDOR_INTEL, 0x06A1 }, { X86_VENDOR_INTEL, 0x06A4 }, - { X86_VENDOR_INTEL, 0x06B0 }, /* Mobile Celeron FCBGA */ - { X86_VENDOR_INTEL, 0x06B1 }, /* Celeron (Tualatin) */ - { X86_VENDOR_INTEL, 0x06B4 }, { 0, 0 }, };

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[commit] r5488 - in trunk/src: devices/oprom mainboard/artecgroup/dbe61/realmode northbridge/via/cn400 northbridge/via/cn700 northbridge/via/cx700 northbridge/via/vx800
by repository service 25 Apr '10

25 Apr '10

Author: stepan Date: Sun Apr 25 01:15:23 2010 New Revision: 5488 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5488 Log: drop all duplicate copies of vgabios.c in favor of devices/oprom/x86.c. We have some tests on hardware. Moving RAMBASE to 1MB needs to wait a bit until C7 cache_as_ram.inc has been adapted to cache that area or things will become incredibly slow (1.5s boot time instead of 0.5) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Deleted: trunk/src/mainboard/artecgroup/dbe61/realmode/ trunk/src/northbridge/via/cn400/vgabios.c trunk/src/northbridge/via/cn400/vgachip.h trunk/src/northbridge/via/cn700/vgabios.c trunk/src/northbridge/via/cn700/vgachip.h trunk/src/northbridge/via/cx700/vgabios.c trunk/src/northbridge/via/vx800/vgabios.c trunk/src/northbridge/via/vx800/vgachip.h Modified: trunk/src/devices/oprom/x86.c trunk/src/northbridge/via/cn400/Kconfig trunk/src/northbridge/via/cn400/Makefile.inc trunk/src/northbridge/via/cn400/vga.c trunk/src/northbridge/via/cn700/Kconfig trunk/src/northbridge/via/cn700/Makefile.inc trunk/src/northbridge/via/cn700/vga.c trunk/src/northbridge/via/cx700/Kconfig trunk/src/northbridge/via/cx700/Makefile.inc trunk/src/northbridge/via/cx700/cx700_vga.c trunk/src/northbridge/via/vx800/Kconfig trunk/src/northbridge/via/vx800/Makefile.inc trunk/src/northbridge/via/vx800/vga.c Modified: trunk/src/devices/oprom/x86.c ============================================================================== --- trunk/src/devices/oprom/x86.c Sat Apr 24 23:24:06 2010 (r5487) +++ trunk/src/devices/oprom/x86.c Sun Apr 25 01:15:23 2010 (r5488) @@ -134,11 +134,13 @@ /* Many option ROMs use the hard coded interrupt entry points in the * system bios. So install them at the known locations. - * Only need int10 so far. */ /* int42 is the relocated int10 */ - write_idt_stub((void *)0xff065, 0x42); + write_idt_stub((void *)0xff065, 0x42); + + /* VIA's VBIOS calls f000:f859 instead of int15 */ + write_idt_stub((void *)0xff859, 0x15); } void run_bios(struct device *dev, unsigned long addr) Modified: trunk/src/northbridge/via/cn400/Kconfig ============================================================================== --- trunk/src/northbridge/via/cn400/Kconfig Sat Apr 24 23:24:06 2010 (r5487) +++ trunk/src/northbridge/via/cn400/Kconfig Sun Apr 25 01:15:23 2010 (r5488) @@ -6,17 +6,6 @@ default 0 depends on NORTHBRIDGE_VIA_CN400 -# this is done by the northbridge's vgabios.c already -config VGA_ROM_RUN - bool - default n - depends on NORTHBRIDGE_VIA_CN400 - -config PCI_ROM_RUN - bool - default n - depends on NORTHBRIDGE_VIA_CN400 - # TODO: Values are from the CX700 datasheet, not sure if this matches CN400. # TODO: What should be the per-chipset default value here? choice Modified: trunk/src/northbridge/via/cn400/Makefile.inc ============================================================================== --- trunk/src/northbridge/via/cn400/Makefile.inc Sat Apr 24 23:24:06 2010 (r5487) +++ trunk/src/northbridge/via/cn400/Makefile.inc Sun Apr 25 01:15:23 2010 (r5488) @@ -18,8 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -obj-y += vgabios.o - driver-y += northbridge.o driver-y += agp.o driver-y += vga.o Modified: trunk/src/northbridge/via/cn400/vga.c ============================================================================== --- trunk/src/northbridge/via/cn400/vga.c Sat Apr 24 23:24:06 2010 (r5487) +++ trunk/src/northbridge/via/cn400/vga.c Sun Apr 25 01:15:23 2010 (r5488) @@ -33,24 +33,63 @@ #include <string.h> #include <bitops.h> #include <cpu/cpu.h> +#include <arch/interrupt.h> #include "chip.h" #include "northbridge.h" #include "cn400.h" -#include "vgachip.h" -void write_protect_vgabios(void) +static int via_cn400_int15_handler(struct eregs *regs) { - /* Don't bother for now. */ + int res=-1; + printk(BIOS_DEBUG, "via_cn400_int15_handler\n"); + switch(regs->eax & 0xffff) { + case 0x5f19: + break; + case 0x5f18: + regs->eax=0x5f; + regs->ebx=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory + regs->ecx=0x060; + res=0; + break; + case 0x5f00: + regs->eax = 0x8600; + break; + case 0x5f01: + regs->eax = 0x5f; + regs->ecx = (regs->ecx & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768 + res = 0; + break; + case 0x5f02: + regs->eax=0x5f; + regs->ebx= (regs->ebx & 0xffff0000) | 2; + regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only + regs->edx= (regs->edx & 0xffff0000) | 0; // TV Layout - default + res=0; + break; + case 0x5f0f: + regs->eax=0x860f; + break; + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + regs->eax & 0xffff); + break; + } + return res; } static void vga_init(device_t dev) { u8 reg8; u32 temp; -#ifdef DEBUG_CN400 - int i, j; -#endif + mainboard_interrupt_handlers(0x15, &via_cn400_int15_handler); + +#undef OLD_BOCHS_METHOD +#ifdef OLD_BOCHS_METHOD + // XXX We might need more bios hooks in the f segment, but + // this way of copying the BOCHS BIOS does not work anymore. + // As soon as someone verifies that CN400 can init VGA, the + // code should be removed. temp = (0xffffffff - CONFIG_FALLBACK_SIZE - 0xffff); printk(BIOS_DEBUG, "Copying BOCHS BIOS from 0x%08X to 0xf000\n", temp); /* @@ -59,7 +98,7 @@ */ //memcpy(0xf0000, (0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000); memcpy((void *)0xf0000, (void *)temp, 0x10000); - printk(BIOS_DEBUG, "Initializing VGA\n"); +#endif /* Set memory rate to 200 MHz. */ outb(0x3d, CRTM_INDEX); @@ -79,16 +118,13 @@ pci_write_config32(dev, 0x10, 0xf0000008); pci_write_config32(dev, 0x14, 0xf4000000); - printk(BIOS_DEBUG, "INSTALL REAL-MODE IDT\n"); - setup_realmode_idt(); - printk(BIOS_DEBUG, "DO THE VGA BIOS\n"); - do_vgabios(); - /* VGA seems to work without this, but crash & burn with it. */ - // printk(BIOS_DEBUG, "Enable VGA console\n"); - // vga_enable_console(); + printk(BIOS_DEBUG, "Initializing VGA...\n"); + + pci_dev_init(dev); /* It's not clear if these need to be programmed before or after * the VGA BIOS runs. Try both, clean up later. */ + /* Set memory rate to 200 MHz (again). */ outb(0x3d, CRTM_INDEX); reg8 = inb(CRTM_DATA); @@ -102,10 +138,14 @@ outb(0x39, SR_INDEX); outb(reg8, SR_DATA); +#ifdef OLD_BOCHS_METHOD /* Clear the BOCHS BIOS out of memory, so it doesn't confuse Linux. */ memset((void *)0xf0000, 0, 0x10000); +#endif #ifdef DEBUG_CN400 + int i, j; + printk(BIOS_SPEW, "%s PCI Header Regs::\n", dev_path(dev)); for (i = 0 ; i < 16; i++) Modified: trunk/src/northbridge/via/cn700/Kconfig ============================================================================== --- trunk/src/northbridge/via/cn700/Kconfig Sat Apr 24 23:24:06 2010 (r5487) +++ trunk/src/northbridge/via/cn700/Kconfig Sun Apr 25 01:15:23 2010 (r5488) @@ -7,17 +7,6 @@ default 0 depends on NORTHBRIDGE_VIA_CN700 -# this is done by the northbridge's vgabios.c already -config VGA_ROM_RUN - bool - default n - depends on NORTHBRIDGE_VIA_CN700 - -config PCI_ROM_RUN - bool - default n - depends on NORTHBRIDGE_VIA_CN700 - # TODO: Values are from the CX700 datasheet, not sure if this matches CN700. # TODO: What should be the per-chipset default value here? choice Modified: trunk/src/northbridge/via/cn700/Makefile.inc ============================================================================== --- trunk/src/northbridge/via/cn700/Makefile.inc Sat Apr 24 23:24:06 2010 (r5487) +++ trunk/src/northbridge/via/cn700/Makefile.inc Sun Apr 25 01:15:23 2010 (r5488) @@ -18,8 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -obj-y += vgabios.o - driver-y += northbridge.o driver-y += agp.o driver-y += vga.o Modified: trunk/src/northbridge/via/cn700/vga.c ============================================================================== --- trunk/src/northbridge/via/cn700/vga.c Sat Apr 24 23:24:06 2010 (r5487) +++ trunk/src/northbridge/via/cn700/vga.c Sun Apr 25 01:15:23 2010 (r5488) @@ -33,28 +33,65 @@ #include <string.h> #include <bitops.h> #include <cpu/cpu.h> +#include <arch/interrupt.h> #include "chip.h" #include "northbridge.h" #include "cn700.h" -#include "vgachip.h" -void write_protect_vgabios(void) +static int via_cn700_int15_handler(struct eregs *regs) { - /* Don't bother for now. */ + int res=-1; + printk(BIOS_DEBUG, "via_cn700_int15_handler\n"); + switch(regs->eax & 0xffff) { + case 0x5f19: + break; + case 0x5f18: + regs->eax=0x5f; + regs->ebx=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory + regs->ecx=0x060; + res=0; + break; + case 0x5f00: + regs->eax = 0x8600; + break; + case 0x5f01: + regs->eax = 0x5f; + regs->ecx = (regs->ecx & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768 + res = 0; + break; + case 0x5f02: + regs->eax=0x5f; + regs->ebx= (regs->ebx & 0xffff0000) | 2; + regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only + regs->edx= (regs->edx & 0xffff0000) | 0; // TV Layout - default + res=0; + break; + case 0x5f0f: + regs->eax=0x860f; + break; + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + regs->eax & 0xffff); + break; + } + return res; } static void vga_init(device_t dev) { u8 reg8; + mainboard_interrupt_handlers(0x15, &via_cn700_int15_handler); + +#undef OLD_BOCHS_METHOD +#ifdef OLD_BOCHS_METHOD print_debug("Copying BOCHS BIOS to 0xf000\n"); /* * Copy BOCHS BIOS from 4G-CONFIG_ROM_SIZE-64k (in flash) to 0xf0000 (in RAM) * This is for compatibility with the VGA ROM's BIOS callbacks. */ memcpy((void *)0xf0000, (const void *)(0xffffffff - CONFIG_ROM_SIZE - 0xffff), 0x10000); - - printk(BIOS_DEBUG, "Initializing VGA\n"); +#endif /* Set memory rate to 200 MHz. */ outb(0x3d, CRTM_INDEX); @@ -74,13 +111,9 @@ pci_write_config32(dev, 0x10, 0xf4000008); pci_write_config32(dev, 0x14, 0xfb000000); - printk(BIOS_DEBUG, "INSTALL REAL-MODE IDT\n"); - setup_realmode_idt(); - printk(BIOS_DEBUG, "DO THE VGA BIOS\n"); - do_vgabios(); - /* VGA seems to work without this, but crash & burn with it. */ - // printk(BIOS_DEBUG, "Enable VGA console\n"); - // vga_enable_console(); + printk(BIOS_DEBUG, "Initializing VGA...\n"); + + pci_dev_init(dev); /* It's not clear if these need to be programmed before or after * the VGA BIOS runs. Try both, clean up later. */ @@ -97,8 +130,10 @@ outb(0x39, SR_INDEX); outb(reg8, SR_DATA); +#ifdef OLD_BOCHS_METHOD /* Clear the BOCHS BIOS out of memory, so it doesn't confuse Linux. */ memset((void *)0xf0000, 0, 0x10000); +#endif } static const struct device_operations vga_operations = { Modified: trunk/src/northbridge/via/cx700/Kconfig ============================================================================== --- trunk/src/northbridge/via/cx700/Kconfig Sat Apr 24 23:24:06 2010 (r5487) +++ trunk/src/northbridge/via/cx700/Kconfig Sun Apr 25 01:15:23 2010 (r5488) @@ -5,14 +5,35 @@ select IOAPIC select SMP -# this is done by the northbridge's vgabios.c already -config VGA_ROM_RUN - bool - default n +# TODO: What should be the per-chipset default value here? +choice + prompt "Onboard graphics" + default CX700_VIDEO_MB_32MB depends on NORTHBRIDGE_VIA_CX700 -config PCI_ROM_RUN - bool - default n +# TODO: Setting the amount of gfx memory is not yet supported in the source code. +config CX700_VIDEO_MB_OFF + bool "Disabled, 0KB" +config CX700_VIDEO_MB_8MB + bool "Enabled, 8MB" +config CX700_VIDEO_MB_16MB + bool "Enabled, 16MB" +config CX700_VIDEO_MB_32MB + bool "Enabled, 32MB" +config CX700_VIDEO_MB_64MB + bool "Enabled, 64MB" +config CX700_VIDEO_MB_128MB + bool "Enabled, 128MB" + +endchoice + +config VIDEO_MB + int + default 0 if CX700_VIDEO_MB_OFF + default 8 if CX700_VIDEO_MB_8MB + default 16 if CX700_VIDEO_MB_16MB + default 32 if CX700_VIDEO_MB_32MB + default 64 if CX700_VIDEO_MB_64MB + default 128 if CX700_VIDEO_MB_128MB depends on NORTHBRIDGE_VIA_CX700 Modified: trunk/src/northbridge/via/cx700/Makefile.inc ============================================================================== --- trunk/src/northbridge/via/cx700/Makefile.inc Sat Apr 24 23:24:06 2010 (r5487) +++ trunk/src/northbridge/via/cx700/Makefile.inc Sun Apr 25 01:15:23 2010 (r5488) @@ -19,7 +19,6 @@ obj-y += cx700_reset.o obj-y += northbridge.o -obj-y += vgabios.o driver-y += cx700_agp.o driver-y += cx700_lpc.o Modified: trunk/src/northbridge/via/cx700/cx700_vga.c ============================================================================== --- trunk/src/northbridge/via/cx700/cx700_vga.c Sat Apr 24 23:24:06 2010 (r5487) +++ trunk/src/northbridge/via/cx700/cx700_vga.c Sun Apr 25 01:15:23 2010 (r5488) @@ -29,6 +29,7 @@ #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> +#include <arch/interrupt.h> #include "chip.h" #include "northbridge.h" @@ -41,9 +42,44 @@ #define CRTC_INDEX 0x3d4 #define CRTC_DATA 0x3d5 -void setup_realmode_idt(void); -void do_vgabios(void); -void vga_enable_console(void); +static int via_cx700_int15_handler(struct eregs *regs) +{ + int res=-1; + printk(BIOS_DEBUG, "via_cx700_int15_handler\n"); + switch(regs->eax & 0xffff) { + case 0x5f19: + break; + case 0x5f18: + regs->eax=0x5f; + regs->ebx=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory + regs->ecx=0x060; + res=0; + break; + case 0x5f00: + regs->eax = 0x8600; + break; + case 0x5f01: + regs->eax = 0x5f; + regs->ecx = (regs->ecx & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768 + res = 0; + break; + case 0x5f02: + regs->eax=0x5f; + regs->ebx= (regs->ebx & 0xffff0000) | 2; + regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only + regs->edx= (regs->edx & 0xffff0000) | 0; // TV Layout - default + res=0; + break; + case 0x5f0f: + regs->eax=0x860f; + break; + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + regs->eax & 0xffff); + break; + } + return res; +} void write_protect_vgabios(void) { @@ -64,7 +100,7 @@ { u8 reg8; - printk(BIOS_DEBUG, "Initializing VGA...\n"); + mainboard_interrupt_handlers(0x15, &via_cx700_int15_handler); //* pci_write_config8(dev, 0x04, 0x07); @@ -75,12 +111,16 @@ pci_write_config8(dev, 0x3c, 0x0b); //*/ - printk(BIOS_DEBUG, "Executing VGA option rom in real mode\n"); - setup_realmode_idt(); - do_vgabios(); + printk(BIOS_DEBUG, "Initializing VGA...\n"); + + pci_dev_init(dev); + printk(BIOS_DEBUG, "Enable VGA console\n"); + // this is how it should look: + // call_bios_interrupt(0x10,0x4f1f,0x8003,1,0); + // this is how it looks: vga_enable_console(); - + /* It's not clear if these need to be programmed before or after * the VGA bios runs. Try both, clean up later */ /* Set memory rate to 200MHz */ Modified: trunk/src/northbridge/via/vx800/Kconfig ============================================================================== --- trunk/src/northbridge/via/vx800/Kconfig Sat Apr 24 23:24:06 2010 (r5487) +++ trunk/src/northbridge/via/vx800/Kconfig Sun Apr 25 01:15:23 2010 (r5488) @@ -6,14 +6,3 @@ default 0 depends on NORTHBRIDGE_VIA_VX800 -# this is done by the northbridge's vgabios.c already -config VGA_ROM_RUN - bool - default n - depends on NORTHBRIDGE_VIA_VX800 - -config PCI_ROM_RUN - bool - default n - depends on NORTHBRIDGE_VIA_VX800 - Modified: trunk/src/northbridge/via/vx800/Makefile.inc ============================================================================== --- trunk/src/northbridge/via/vx800/Makefile.inc Sat Apr 24 23:24:06 2010 (r5487) +++ trunk/src/northbridge/via/vx800/Makefile.inc Sun Apr 25 01:15:23 2010 (r5488) @@ -18,8 +18,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -obj-y += vgabios.o - driver-y += northbridge.o driver-y += vga.o driver-y += vx800_lpc.o Modified: trunk/src/northbridge/via/vx800/vga.c ============================================================================== --- trunk/src/northbridge/via/vx800/vga.c Sat Apr 24 23:24:06 2010 (r5487) +++ trunk/src/northbridge/via/vx800/vga.c Sun Apr 25 01:15:23 2010 (r5488) @@ -32,9 +32,9 @@ #include <cpu/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> +#include <arch/interrupt.h> #include "chip.h" #include "northbridge.h" -#include "vgachip.h" /* PCI Domain 1 Device 0 Function 0 */ @@ -49,6 +49,83 @@ #define VIACONFIG_VGA_PCI_10 0xf8000008 #define VIACONFIG_VGA_PCI_14 0xfc000000 +static int via_vx800_int15_handler(struct eregs *regs) +{ + int res=-1; + printk(BIOS_DEBUG, "via_vx800_int15_handler\n"); + switch(regs->eax & 0xffff) { + case 0x5f19: + regs->eax=0x5f; + regs->ecx=0x03; + res=0; + break; + case 0x5f18: + { + /* + * BL Bit[7:4] + * Memory Data Rate + * 0000: 66MHz + * 0001: 100MHz + * 0010: 133MHz + * 0011: 200MHz ( DDR200 ) + * 0100: 266MHz ( DDR266 ) + * 0101: 333MHz ( DDR333 ) + * 0110: 400MHz ( DDR400 ) + * 0111: 533MHz ( DDR I/II 533 + * 1000: 667MHz ( DDR I/II 667) + * Bit[3:0] + * N: Frame Buffer Size 2^N MB + */ + u8 i; + device_t dev; + dev = dev_find_slot(0, PCI_DEVFN(0, 3)); + i = pci_read_config8(dev, 0xa1); + i = (i & 0x70); + i = i >> 4; + if (i == 0) { + regs->eax = 0x00; //not support 5f18 + break; + } + i = i + 2; + regs->ebx = (u32) i; + i = pci_read_config8(dev, 0x90); + i = (i & 0x07); + i = i + 3; + i = i << 4; + regs->ebx = regs->ebx + ((u32) i); + regs->eax = 0x5f; + res = 0; + break; + } + case 0x5f00: + regs->eax = 0x005f; + res = 0; + break; + case 0x5f01: + regs->eax = 0x5f; + regs->ecx = (regs->ecx & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768 + res = 0; + break; + case 0x5f02: + regs->eax=0x5f; + regs->ebx= (regs->ebx & 0xffff0000) | 2; + regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only + regs->edx= (regs->edx & 0xffff0000) | 0; // TV Layout - default + res=0; + break; + case 0x5f0f: + regs->eax = 0x005f; + res = 0; + break; + default: + printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", + regs->eax & 0xffff); + regs->eax = 0; + break; + } + return res; +} + void write_protect_vgabios(void) { device_t dev; @@ -70,12 +147,12 @@ { uint8_t reg8; - print_debug("Initiailizing VGA...\n"); - u8 tmp8; -//A20 OPEN - tmp8 = inb(0x92); - tmp8 = tmp8 | 2; - outb(tmp8, 0x92); + mainboard_interrupt_handlers(0x15, &via_vx800_int15_handler); + + //A20 OPEN + reg8 = inb(0x92); + reg8 = reg8 | 2; + outb(reg8, 0x92); //* //pci_write_config8(dev, 0x04, 0x07); @@ -85,27 +162,17 @@ pci_write_config32(dev, 0x14, VIACONFIG_VGA_PCI_14); pci_write_config8(dev, 0x3c, 0x0a); //same with vx855_lpc.c //*/ - printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); -#if 1 - printk(BIOS_DEBUG, "INSTALL REAL-MODE IDT\n"); - setup_realmode_idt(); - printk(BIOS_DEBUG, "DO THE VGA BIOS\n"); + printk(BIOS_DEBUG, "Initializing VGA...\n"); + + pci_dev_init(dev); + + printk(BIOS_DEBUG, "Enable VGA console\n"); + // this is how it should look: + // call_bios_interrupt(0x10,0x4f1f,0x8003,1,0); + // this is how it looks: + vga_enable_console(); - do_vgabios(); - if ((acpi_sleep_type == 3)/* || (PAYLOAD_IS_SEABIOS == 0)*/) { - printk(BIOS_DEBUG, "Enable VGA console\n"); - // remove this function since in cn700 it is said "VGA seems to work without this, but crash & burn with it" - //but the existense of vga_enable_console() seems do not hurt my coreboot. XP+ubuntu s3 can resume with and without this function. - //and remove it also do not help my s3 problem: desktop screen have some thin black line, after resuming back to win. - vga_enable_console(); - } -#else -/* Attempt to manually force the rom to load */ - printk(BIOS_DEBUG, "Forcing rom load\n"); - pci_rom_load(dev, 0xfff80000); - run_bios(dev, 0xc0000); -#endif if ((acpi_sleep_type == 3)/* || (PAYLOAD_IS_SEABIOS == 0)*/) { /* It's not clear if these need to be programmed before or after * the VGA bios runs. Try both, clean up later */ @@ -117,13 +184,13 @@ outb(0x3d, CRTM_INDEX); outb(reg8, CRTM_DATA); +#if 0 /* Set framebuffer size to CONFIG_VIDEO_MB mb */ - /*reg8 = (CONFIG_VIDEO_MB/4); - outb(0x39, SR_INDEX); - outb(reg8, SR_DATA); */ + reg8 = (CONFIG_VIDEO_MB/4); + outb(0x39, SR_INDEX); + outb(reg8, SR_DATA); +#endif } - printk(BIOS_EMERG, "file '%s', line %d\n\n", __FILE__, __LINE__); - } static struct device_operations vga_operations = {

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[commit] r5487 - trunk/util/cbfstool
by repository service 24 Apr '10

24 Apr '10

Author: stepan Date: Sat Apr 24 23:24:06 2010 New Revision: 5487 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5487 Log: print the known cbfs types in cbfstool "usage" Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/util/cbfstool/cbfstool.c trunk/util/cbfstool/common.c trunk/util/cbfstool/common.h Modified: trunk/util/cbfstool/cbfstool.c ============================================================================== --- trunk/util/cbfstool/cbfstool.c Sat Apr 24 09:56:32 2010 (r5486) +++ trunk/util/cbfstool/cbfstool.c Sat Apr 24 23:24:06 2010 (r5487) @@ -254,17 +254,20 @@ void usage(void) { printf - ("cbfstool: Management utility for CBFS formatted ROM images\n" - "USAGE:\n" "cbfstool [-h]\n" - "cbfstool FILE COMMAND [PARAMETERS]...\n\n" "OPTIONs:\n" - " -h Display this help message\n\n" + ("cbfstool: Management utility for CBFS formatted ROM images\n\n" + "USAGE:\n" " cbfstool [-h]\n" + " cbfstool FILE COMMAND [PARAMETERS]...\n\n" "OPTIONs:\n" + " -h Display this help message\n\n" "COMMANDs:\n" - "add FILE NAME TYPE [base address] Add a component\n" - "add-payload FILE NAME [COMP] [base] Add a payload to the ROM\n" - "add-stage FILE NAME [COMP] [base] Add a stage to the ROM\n" - "create SIZE BOOTBLOCK [ALIGN] Create a ROM file\n" - "locate FILE NAME ALIGN Find a place for a file of that size\n" - "print Show the contents of the ROM\n"); + " add FILE NAME TYPE [base address] Add a component\n" + " add-payload FILE NAME [COMP] [base] Add a payload to the ROM\n" + " add-stage FILE NAME [COMP] [base] Add a stage to the ROM\n" + " create SIZE BOOTBLOCK [ALIGN] Create a ROM file\n" + " locate FILE NAME ALIGN Find a place for a file of that size\n" + " print Show the contents of the ROM\n\n" + "TYPEs:\n" + ); + print_supported_filetypes(); } int main(int argc, char **argv) Modified: trunk/util/cbfstool/common.c ============================================================================== --- trunk/util/cbfstool/common.c Sat Apr 24 09:56:32 2010 (r5486) +++ trunk/util/cbfstool/common.c Sat Apr 24 23:24:06 2010 (r5487) @@ -137,6 +137,17 @@ {CBFS_COMPONENT_NULL, "null"} }; +void print_supported_filetypes(void) +{ + int i, number = ARRAY_SIZE(filetypes); + + for (i=0; i<number; i++) { + printf(" %s%c", filetypes[i].name, (i==(number-1))?'\n':','); + if ((i%8) == 7) + printf("\n"); + } +} + const char *strfiletype(uint32_t number) { int i; Modified: trunk/util/cbfstool/common.h ============================================================================== --- trunk/util/cbfstool/common.h Sat Apr 24 09:56:32 2010 (r5486) +++ trunk/util/cbfstool/common.h Sat Apr 24 23:24:06 2010 (r5487) @@ -72,4 +72,6 @@ uint32_t cbfs_find_location(const char *romfile, uint32_t filesize, const char *filename, uint32_t align); +void print_supported_filetypes(void); + #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))

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[PATCH] drop all copies of vgabios.c
by Stefan Reinauer 24 Apr '10

24 Apr '10

This patch cleans up the option rom code in coreboot significantly by dropping all extra copies of vgabios.c and instead changing the code to use oprom/x86.c with custom per-board int15 handlers. Corey, I can't test this on cn400/cn700 ... Can you? The code should go in as is, but it might require some extra fixing, as (like with vgabios.c before) the int15 handlers are all copies of the age-old epia-m code. (except vx800) Stefan

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[PATCH] Enable maximum decoded range for VT8237*
by Rudolf Marek 24 Apr '10

24 Apr '10

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, Attached patch adds support for tinybootblock on VT8237* to decode whole flash independent of strapping, making larger flashes work again (as it was in pre-tiny bootblock era) Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> I had a strange problem: #include <arch/io.h> #include <arch/romcc_io.h> #include <device/pci_ids.h> static void bootblock_southbridge_init(void) { device_t dev; /* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev == PCI_DEV_INVALID) { /* Power management controller */ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); if (dev == PCI_DEV_INVALID) return; } pci_write_config8(dev, 0x41, 0x7f); } did not reach the pci write for some reason. This code is a copy from enable_rom_decode() so it should work. Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkvOIO0ACgkQ3J9wPJqZRNVqFwCgz6+rJ6QmDVoFLHjZ3MS668jY uW4An2kWok6aukzhZGC1Fue5yJkN0Eef =LGC8 -----END PGP SIGNATURE-----

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[commit] r5486 - trunk/src/northbridge/amd/amdmct
by repository service 24 Apr '10

24 Apr '10

Author: zbao Date: Sat Apr 24 09:56:32 2010 New Revision: 5486 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5486 Log: Trivial. Fix a space to tab. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Modified: trunk/src/northbridge/amd/amdmct/amddefs.h Modified: trunk/src/northbridge/amd/amdmct/amddefs.h ============================================================================== --- trunk/src/northbridge/amd/amdmct/amddefs.h Fri Apr 23 22:58:13 2010 (r5485) +++ trunk/src/northbridge/amd/amdmct/amddefs.h Sat Apr 24 09:56:32 2010 (r5486) @@ -64,8 +64,8 @@ #define AMD_DR_ALL (AMD_DR_Bx) #define AMD_FAM10_ALL (AMD_DR_ALL | AMD_RB_C2 | AMD_HY_D0 | AMD_DA_C3 | AMD_DA_C2) #define AMD_FAM10_GT_B0 (AMD_FAM10_ALL & ~(AMD_DR_B0)) -#define AMD_DR_Cx (AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3) -#define AMD_DR_Dx (AMD_HY_D0) +#define AMD_DR_Cx (AMD_RB_C2 | AMD_DA_C2 | AMD_RB_C3 | AMD_DA_C3) +#define AMD_DR_Dx (AMD_HY_D0) /*

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coreboot April 2010