coreboot April 2010

coreboot@coreboot.org

64 participants
402 discussions

[commit] r5501 - trunk/src/northbridge/via/cx700
by repository service 26 Apr '10

26 Apr '10

Author: oxygene Date: Mon Apr 26 08:59:07 2010 New Revision: 5501 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5501 Log: Set success flag in cx700 int15 handler Signed-off-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Acked-by: Patrick Georgi <patrick.georgi(a)coresystems.de> Modified: trunk/src/northbridge/via/cx700/cx700_vga.c Modified: trunk/src/northbridge/via/cx700/cx700_vga.c ============================================================================== --- trunk/src/northbridge/via/cx700/cx700_vga.c Sun Apr 25 23:44:33 2010 (r5500) +++ trunk/src/northbridge/via/cx700/cx700_vga.c Mon Apr 26 08:59:07 2010 (r5501) @@ -114,7 +114,7 @@ if (mem_speed > 5) mem_speed = 5; - regs->ebx |= memory_mapping[mem_speed]; break; + regs->ebx |= memory_mapping[mem_speed]; res=0; break;

1 0

[patch] Rename the intermediate file created by iasl
by Bao, Zheng 26 Apr '10

26 Apr '10

For the mainboard with AMD Family 10, if we make clean and make again, it will fail. why? After make clean, .c files created by iasl are still left in the build folder, it will match the rule of $(obj)/%.o: $(obj)/%.c $(obj)/config.h @printf " CC $(subst $(obj)/,,$(@))\n" $(CC) -MMD $(CFLAGS) -c -o $@ $< it will miss the rule which should be applied. define objs_asl_template .... So we move the .c file back to .hex (or other suffix? or delete?). This patch will work after make distclean, otherwise nobody will rename the .c. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Index: Makefile =================================================================== --- Makefile (revision 5489) +++ Makefile (working copy) @@ -226,6 +226,7 @@ iasl -p $$(basename $$@) -tc $$(basename $$(a)).asl mv $$(basename $$(a)).hex $$(basename $$(a)).c $(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $$@))), -DAmlCode=AmlCode_$$(basename $$(notdir $$@))) -c -o $$@ $$(basename $$(a)).c + mv $$(basename $$(a)).c $$(basename $$(a)).hex endef # macro to define template macros that are used by use_template macro -- coreboot mailing list: coreboot(a)coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot

1 0

[commit] r5494 - in trunk/src: mainboard/asus/m2v-mx_se southbridge/via/k8t890
by repository service 26 Apr '10

26 Apr '10

Author: ruik Date: Sun Apr 25 17:21:18 2010 New Revision: 5494 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5494 Log: Following patch changes the K8M890 VGA handling. It reverts the framebuffer size to option based (similar what Uwe did) and also it uses GFXUMA to handle the high_tables_start offset from memory top. To satisfy the CMOS option users (Hi, libv! ;) I added also a possibility to do that through CMOS. Fixed printks to match the new style. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/mainboard/asus/m2v-mx_se/mainboard.c trunk/src/southbridge/via/k8t890/Kconfig trunk/src/southbridge/via/k8t890/k8t890_dram.c Modified: trunk/src/mainboard/asus/m2v-mx_se/mainboard.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/mainboard.c Sun Apr 25 16:37:18 2010 (r5493) +++ trunk/src/mainboard/asus/m2v-mx_se/mainboard.c Sun Apr 25 17:21:18 2010 (r5494) @@ -24,6 +24,10 @@ #include <southbridge/via/k8t890/k8t890.h> #include "chip.h" +#if CONFIG_GFXUMA +uint64_t uma_memory_base, uma_memory_size; +#endif + int add_mainboard_resources(struct lb_memory *mem) { device_t dev; @@ -38,6 +42,11 @@ res->size); } +#if (CONFIG_GFXUMA == 1) + lb_add_memory_range(mem, LB_MEM_RESERVED, + uma_memory_base, uma_memory_size); +#endif + #if CONFIG_HAVE_ACPI_RESUME == 1 lb_add_memory_range(mem, LB_MEM_RESERVED, CONFIG_RAMBASE, ((CONFIG_RAMTOP) - CONFIG_RAMBASE)); Modified: trunk/src/southbridge/via/k8t890/Kconfig ============================================================================== --- trunk/src/southbridge/via/k8t890/Kconfig Sun Apr 25 16:37:18 2010 (r5493) +++ trunk/src/southbridge/via/k8t890/Kconfig Sun Apr 25 17:21:18 2010 (r5494) @@ -1,3 +1,36 @@ config SOUTHBRIDGE_VIA_K8T890 bool +config SOUTHBRIDGE_VIA_K8T890_VGA_EN + bool "Enable onboard K8M890 graphics" + default y + depends on SOUTHBRIDGE_VIA_K8T890 + select VGA + select GFXUMA + +choice + prompt "Framebuffer size" + default K8M890_VIDEO_MB_32MB + depends on SOUTHBRIDGE_VIA_K8T890_VGA_EN + +config K8M890_VIDEO_MB_32MB + bool "32MB" +config K8M890_VIDEO_MB_64MB + bool "64MB" +config K8M890_VIDEO_MB_128MB + bool "128MB" +config K8M890_VIDEO_MB_256MB + bool "256MB" +config K8M890_VIDEO_MB_CMOS + bool "Use CMOS option" + +endchoice + +config VIDEO_MB + int + default 32 if K8M890_VIDEO_MB_32MB + default 64 if K8M890_VIDEO_MB_64MB + default 128 if K8M890_VIDEO_MB_128MB + default 256 if K8M890_VIDEO_MB_256MB + default -1 if K8M890_VIDEO_MB_CMOS + depends on SOUTHBRIDGE_VIA_K8T890_VGA_EN Modified: trunk/src/southbridge/via/k8t890/k8t890_dram.c ============================================================================== --- trunk/src/southbridge/via/k8t890/k8t890_dram.c Sun Apr 25 16:37:18 2010 (r5493) +++ trunk/src/southbridge/via/k8t890/k8t890_dram.c Sun Apr 25 17:21:18 2010 (r5494) @@ -67,47 +67,44 @@ } -static void dram_enable_k8m890(struct device *dev) -{ - dram_enable(dev); - - /* enable VGA, so the bridges gets VGA_EN and resources are set */ - pci_write_config8(dev, 0xa1, 0x80); -} - -static struct resource *resmax; +#if CONFIG_GFXUMA +extern uint64_t uma_memory_base, uma_memory_size; +#endif -static void get_memres(void *gp, struct device *dev, struct resource *res) +static void dram_enable_k8m890(struct device *dev) { - unsigned int *fbsize = (unsigned int *) gp; - uint64_t proposed_base = res->base + res->size - *fbsize; +#if CONFIG_GFXUMA + msr_t msr; + int ret; + unsigned int fbbits; - printk(BIOS_DEBUG, "get_memres: res->base=%llx res->size=%llx %d %d %d\n", - res->base, res->size, (res->size > *fbsize), - (!(proposed_base & (*fbsize - 1))), - (proposed_base < ((uint64_t) 0xffffffff))); - - /* if we fit and also align OK, and must be below 4GB */ - if ((res->size > *fbsize) && (!(proposed_base & (*fbsize - 1))) && - (proposed_base < ((uint64_t) 0xffffffff) )) { - resmax = res; + /* use CMOS */ + if (CONFIG_VIDEO_MB == -1) { + ret = get_option(&fbbits, "videoram_size"); + if (ret) { + printk(BIOS_WARNING, "Failed to get videoram size (error %d), using default.\n", ret); + fbbits = 5; + } + + if ((fbbits < 1) || (fbbits > 7)) { + printk(BIOS_WARNING, "Invalid videoram size (%d), using default.\n", + 4 << fbbits); + fbbits = 5; } -#if CONFIG_WRITE_HIGH_TABLES==1 -/* in arch/i386/boot/tables.c */ -extern uint64_t high_tables_base, high_tables_size; - - if ((high_tables_base) && ((high_tables_base > proposed_base) && - (high_tables_base < (res->base + res->size)))) { - high_tables_base = proposed_base - high_tables_size; - printk(BIOS_DEBUG, "Moving the high_tables_base pointer to " - "new base %llx\n", high_tables_base); + uma_memory_size = 4 << (fbbits + 20); + } else { + uma_memory_size = (CONFIG_VIDEO_MB << 20); } + + msr = rdmsr(TOP_MEM); + uma_memory_base = msr.lo - uma_memory_size; + printk(BIOS_INFO, "K8M890: UMA base is %llx size is %d (MB)\n", uma_memory_base, uma_memory_size / 1024 / 1024); + /* enable VGA, so the bridges gets VGA_EN and resources are set */ + pci_write_config8(dev, 0xa1, 0x80); #endif + dram_enable(dev); } -/* - * - */ int k8m890_host_fb_size_get(void) { @@ -125,57 +122,29 @@ static void dram_init_fb(struct device *dev) { +#if CONFIG_GFXUMA /* Important bits: * Enable the internal GFX bit 7 of reg 0xa1 plus in same reg: * bits 6:4 X fbuffer size will be 2^(X+2) or 100 = 64MB, 101 = 128MB * bits 3:0 BASE [31:28] * reg 0xa0 bits 7:1 BASE [27:21] bit0 enable CPU access */ - u8 tmp; - uint64_t proposed_base; unsigned int fbbits = 0; - unsigned int fbsize; + u8 tmp; int ret; - - ret = get_option(&fbbits, "videoram_size"); - if (ret) { - printk(BIOS_WARNING, "Failed to get videoram size (error %d), using default.\n", ret); - fbbits = 5; - } - - if ((fbbits < 1) || (fbbits > 7)) { - printk(BIOS_WARNING, "Invalid videoram size (%d), using default.\n", - 4 << fbbits); - fbbits = 5; - } - - fbsize = 4 << (fbbits + 20); - - resmax = NULL; - search_global_resources( - IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, - get_memres, (void *) &fbsize); - - /* no space for FB */ - if (!resmax) { - printk(BIOS_ERR, "VIA FB: no space for framebuffer in RAM\n"); - return; - } - - proposed_base = resmax->base + resmax->size - fbsize; - resmax->size -= fbsize; - - printk(BIOS_INFO, "K8M890: Using a %dMB framebuffer.\n", 4 << fbbits); + fbbits = ((log2(uma_memory_size >> 20) - 2) << 4); + printk(BIOS_INFO, "K8M890: Using a %dMB framebuffer.\n", (unsigned int) (uma_memory_size >> 20)); /* Step 1: enable UMA but no FB */ pci_write_config8(dev, 0xa1, 0x80); /* Step 2: enough is just the FB size, the CPU accessible address is not needed */ - tmp = (fbbits << 4) | 0x80; + tmp = fbbits | 0x80; pci_write_config8(dev, 0xa1, tmp); /* TODO K8 needs some UMA fine tuning too maybe call some generic routine here? */ +#endif } static const struct device_operations dram_ops_t = {

2 1

[PATCH] WIP - suspend/resume on AMD64 using CBMEM
by Rudolf Marek 26 Apr '10

26 Apr '10

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello, Attached patch implements again suspend/resume without reserved memory. The RAMBASE-RAMTOP is backuped to cbmem as ID_SUSPEND/RESUME and then before jumping to OS restore orig mem data again. I have a question regarding the size of HIGH tables memory and the size of CBMEM. Most NB have it hardcoded for high tables - perhaps it is time to fix it too? The problem with the CBMEM toc location was solved using the NVRAM for data pointer. I think when this patch is in good shape, one can try to get Suspend/Resume working on SB710/RS785. I tested Windows 7 (the build 7100?) and linux - both resumed from suspend ;) Any comments? Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkvUxRcACgkQ3J9wPJqZRNX5zwCeKIGdBWrmqzz+lrpFyNG0fELO 6O0AoOLwo9/rF17q6rji8K4ycs0hEW3S =Otx4 -----END PGP SIGNATURE-----

1 0

build service results for r5499
by coreboot information 25 Apr '10

25 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5499 to the coreboot repository. This caused the following changes: Change Log: a single place for the romstage stack for copy_and_run. geode lx and amd opteron don't use this yet. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of emulation:qemu-x86 has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5500 - trunk/src/northbridge/via/cx700
by repository service 25 Apr '10

25 Apr '10

Author: stepan Date: Sun Apr 25 23:44:33 2010 New Revision: 5500 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5500 Log: cx700 int15 handler rework. Int15 handler needs to provide the correct ram clock to the vga bios or there be dragons. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/northbridge/via/cx700/cx700_registers.h trunk/src/northbridge/via/cx700/cx700_vga.c trunk/src/northbridge/via/cx700/raminit.c Modified: trunk/src/northbridge/via/cx700/cx700_registers.h ============================================================================== --- trunk/src/northbridge/via/cx700/cx700_registers.h Sun Apr 25 23:43:29 2010 (r5499) +++ trunk/src/northbridge/via/cx700/cx700_registers.h Sun Apr 25 23:44:33 2010 (r5500) @@ -36,237 +36,11 @@ #define SCRATCH_DRAM_256M_BIT 0xee #define SCRATCH_FLAGS 0xef -static const u8 Reg_Val[] = { -/* REG, VALUE */ - 0x70, 0x33, - 0x71, 0x11, - 0x72, 0x33, - 0x73, 0x11, - 0x74, 0x20, - 0x75, 0x2e, - 0x76, 0x64, - 0x77, 0x00, - 0x78, 0x44, - 0x79, 0xaa, - 0x7a, 0x33, - 0x7b, 0xaa, - 0x7c, 0x00, - 0x7e, 0x33, - 0x7f, 0x33, - 0x80, 0x44, - 0x81, 0x44, - 0x82, 0x44, - 0x83, 0x02, - 0x50, 0x88, - 0x51, 0x7b, - 0x52, 0x6f, - 0x53, 0x88, - 0x54, 0x0e, - 0x55, 0x00, - 0x56, 0x00, - 0x59, 0x00, - 0x5d, 0x72, - 0x5e, 0x88, - 0x5f, 0xc7, - 0x68, 0x01, -}; +#define DDRII_666 0x5 +#define DDRII_533 0x4 +#define DDRII_400 0x3 +#define DDRII_333 0x2 +#define DDRII_266 0x1 +#define DDRII_200 0x0 -/* Host registers initial value */ -static const u8 Host_Reg_Val[] = { -/* REG, VALUE */ - 0x60, 0xff, - 0x61, 0xff, - 0x62, 0x0f, - 0x63, 0xff, - 0x64, 0xff, - 0x65, 0x0f, - 0x66, 0xff, - 0x67, 0x30, -}; -static const u8 Mem_Reg_Init[] = { -/* REG, AND, OR */ - 0x50, 0x11, 0x66, - 0x51, 0x11, 0x66, - 0x52, 0x00, 0x11, - 0x53, 0x00, 0x0f, - 0x54, 0x00, 0x00, - 0x55, 0x00, 0x00, - 0x56, 0x00, 0x00, - 0x57, 0x00, 0x00, - 0x60, 0x00, 0x00, - 0x62, 0xf7, 0x08, - 0x65, 0x00, 0xd9, - 0x66, 0x00, 0x80, - 0x67, 0x00, 0x50, /* OR 0x00 ?? */ - 0x69, 0xf0, 0x00, - 0x6a, 0x00, 0x00, - 0x6d, 0xcf, 0xc0, - 0x6e, 0xff, 0x80, - 0x75, 0x0f, 0x40, - 0x77, 0x00, 0x00, - 0x80, 0x00, 0x00, - 0x81, 0x00, 0x00, - 0x82, 0x00, 0x00, - 0x83, 0x00, 0x00, - 0x84, 0x00, 0x00, - 0x85, 0x00, 0x00, - 0x86, 0xff, 0x2c, /* OR 0x28 if we don't want enable top 1M SM memory */ - 0x40, 0x00, 0x00, - 0x7c, 0x00, 0x00, - 0x7e, 0x00, 0x00, - 0xa4, 0xfe, 0x00, - 0xb0, 0x7f, 0x80, - 0xb1, 0x00, 0xaa, - 0xb4, 0xfd, 0x02, - 0xb8, 0xfe, 0x00, -}; - -static const u8 Dram_Driving_ODT_CTRL[] = { -/* REG, VALUE */ - 0xd6, 0xa8, - 0xd4, 0x80, - 0xd0, 0x88, - 0xd3, 0x01, - 0xd8, 0x00, - 0xda, 0x80, -}; - -#define Rank0_ODT 0x00 -#define Rank1_ODT 0x01 -#define Rank2_ODT 0x02 -#define Rank3_ODT 0x03 -#define NA_ODT 0x00 -#define NB_ODT_75ohm 0x00 -#define NB_ODT_150ohm 0x01 -#define DDR2_ODT_75ohm 0x20 -#define DDR2_ODT_150ohm 0x40 - -static const u8 ODT_TBL[] = { -/* RankMap, ODT Control Bits, DRAM & NB ODT setting */ - 0x01, ((NA_ODT << 6) | (NA_ODT << 4) | (NA_ODT << 2) | Rank0_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm), - 0x03, ((NA_ODT << 6) | (NA_ODT << 4) | (Rank0_ODT << 2) | Rank1_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm), - 0x04, ((NA_ODT << 6) | (Rank2_ODT << 4) | (NA_ODT << 2) | NA_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm), - 0x05, ((NA_ODT << 6) | (Rank0_ODT << 4) | (NA_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm), - 0x07, ((NA_ODT << 6) | (Rank0_ODT << 4) | (Rank2_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm), - 0x0c, ((Rank2_ODT << 6) | (Rank3_ODT << 4) | (NA_ODT << 2) | NA_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm), - 0x0d, ((Rank0_ODT << 6) | (Rank0_ODT << 4) | (NA_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm), - 0x0f, ((Rank0_ODT << 6) | (Rank0_ODT << 4) | (Rank2_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm), -}; - -static const u8 DQS_DQ_TBL[] = { -/* RxE0: DRAM Timing DQS */ -/* RxE2: DRAM Timing DQ */ -/* RxE0, RxE2 */ - 0xee, 0xba, - 0xee, 0xba, - 0xcc, 0xba, - 0xcc, 0xba, -}; - -static const u8 Duty_Control_DDR2[] = { -/* RxEC, RxED, RxEE, RXEF */ - /* DDRII533 1~2 rank, DDRII400 */ - 0x84, 0x10, 0x00, 0x10, - /* DDRII533 3~4 rank */ - 0x44, 0x10, 0x00, 0x10, -}; - -static const u8 ChA_Clk_Phase_DDR2_Table[] = { -/* Rx91, Rx92, Rx93 */ - /* DDRII533 1 rank */ - 0x04, 0x05, 0x06, - /* DDRII533 2~4 rank */ - 0x04, 0x05, 0x05, - /* DDRII400 */ - 0x02, 0x04, 0x04, -}; - -static const u8 DQ_DQS_Table[] = { -/* REG, VALUE */ -/* DRAM DQ/DQS Output Delay Control */ - 0xdc, 0x65, - 0xdd, 0x01, - 0xde, 0xc0, -/* DRAM DQ/DQS input Capture Control */ - 0x78, 0x83, - 0x79, 0x83, - 0x7a, 0x00, -}; - -static const u8 DQSOChA_DDR2_Driving_Table[] = { -/* Rx70, Rx71 */ - /* DDRII533 1~2 rank */ - 0x00, 0x01, - /* DDRII533 3~4 rank */ - 0x03, 0x00, - /* DDRII400 1~2 rank */ - 0x00, 0x04, - /* DDRII400 3~4 rank */ - 0x00, 0x01, -}; - -/************************************************************************/ -/* Chipset Performance UP and other setting after DRAM Sizing Registers */ -/************************************************************************/ -static const u8 Dram_Table[] = { -/* REG, AND, OR */ - 0x60, 0xff, 0x03, - 0x66, 0xcf, 0x80, - 0x68, 0x00, 0x00, - 0x69, 0xfd, 0x03, - 0x6e, 0xff, 0x01, - 0x95, 0xff, 0x40, -}; - -static const u8 Host_Table[] = { -/* REG, AND, OR */ - 0x51, 0x81, 0x7a, - 0x55, 0xff, 0x06, - 0x5e, 0x00, 0x88, - 0x5d, 0xff, 0xb2, -}; - -static const u8 Init_Rank_Reg_Table[] = { - /* Rank Ending Address Registers */ - 0x40, 0x41, 0x42, 0x43, - /* Rank Beginning Address Registers */ - 0x48, 0x49, 0x4a, 0x4b, - /* Physical-to-Virtual Rank Mapping Registers */ - 0x54, 0x55, -}; - -static const u16 DDR2_MRS_table[] = { -/* CL: 2, 3, 4, 5 */ - 0x150, 0x1d0, 0x250, 0x2d0, /* BL=4 ;Use 1X-bandwidth MA table to init DRAM */ - 0x158, 0x1d8, 0x258, 0x2d8, /* BL=8 ;Use 1X-bandwidth MA table to init DRAM */ -}; - -#define MRS_DDR2_TWR2 ((0 << 15) | (0 << 20) | (1 << 12)) -#define MRS_DDR2_TWR3 ((0 << 15) | (1 << 20) | (0 << 12)) -#define MRS_DDR2_TWR4 ((0 << 15) | (1 << 20) | (1 << 12)) -#define MRS_DDR2_TWR5 ((1 << 15) | (0 << 20) | (0 << 12)) -static const u32 DDR2_Twr_table[] = { - MRS_DDR2_TWR2, - MRS_DDR2_TWR3, - MRS_DDR2_TWR4, - MRS_DDR2_TWR5, -}; - -static const u8 DQSI_Rate_Table[] = { - 8, /* DDRII 200 */ - 8, /* DDRII 266 */ - 8, /* DDRII 333 */ - 7, /* DDRII 400 */ - 8, /* DDRII 533 */ - 8, /* DDRII 666 */ -}; - -static const u8 REFC_Table[] = { - 0x65, 0x32, /* DDRII 100 */ - 0x86, 0x43, /* DDRII 266 */ - 0xa8, 0x54, /* DDRII 333 */ - 0xca, 0x65, /* DDRII 400 */ - 0xca, 0x86, /* DDRII 533 */ - 0xca, 0xa8, /* DDRII 666 */ -}; Modified: trunk/src/northbridge/via/cx700/cx700_vga.c ============================================================================== --- trunk/src/northbridge/via/cx700/cx700_vga.c Sun Apr 25 23:43:29 2010 (r5499) +++ trunk/src/northbridge/via/cx700/cx700_vga.c Sun Apr 25 23:44:33 2010 (r5500) @@ -30,6 +30,7 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <arch/interrupt.h> +#include "cx700_registers.h" #include "chip.h" #include "northbridge.h" @@ -45,34 +46,79 @@ static int via_cx700_int15_handler(struct eregs *regs) { int res=-1; + u8 mem_speed; + +#define MEMORY_SPEED_66MHZ (0 << 4) +#define MEMORY_SPEED_100MHZ (1 << 4) +#define MEMORY_SPEED_133MHZ (1 << 4) +#define MEMORY_SPEED_200MHZ (3 << 4) // DDR200 +#define MEMORY_SPEED_266MHZ (4 << 4) // DDR266 +#define MEMORY_SPEED_333MHZ (5 << 4) // DDR333 +#define MEMORY_SPEED_400MHZ (6 << 4) // DDR400 +#define MEMORY_SPEED_533MHZ (7 << 4) // DDR533 +#define MEMORY_SPEED_667MHZ (8 << 4) // DDR667 + + const u8 memory_mapping[6] = { + MEMORY_SPEED_200MHZ, MEMORY_SPEED_266MHZ, + MEMORY_SPEED_333MHZ, MEMORY_SPEED_400MHZ, + MEMORY_SPEED_533MHZ, MEMORY_SPEED_667MHZ + }; + printk(BIOS_DEBUG, "via_cx700_int15_handler\n"); + switch(regs->eax & 0xffff) { - case 0x5f19: + case 0x5f00: /* VGA POST Initialization Signal */ + regs->eax = (regs->eax & 0xffff0000 ) | 0x5f; + res = 0; break; - case 0x5f18: - regs->eax=0x5f; - regs->ebx=0x545; // MCLK = 133, 32M frame buffer, 256 M main memory - regs->ecx=0x060; - res=0; + + case 0x5f01: /* Software Panel Type Configuration */ + regs->eax = (regs->eax & 0xffff0000 ) | 0x5f; + // panel type = 2 = 1024 * 768 + regs->ecx = (regs->ecx & 0xffffff00 ) | 2; + res = 0; break; - case 0x5f00: - regs->eax = 0x8600; + + case 0x5f27: /* Boot Device Selection */ + regs->eax = (regs->eax & 0xffff0000 ) | 0x5f; + + regs->ebx = 0x00000000; // 0 -> default + regs->ecx = 0x00000000; // 0 -> default + // TV Layout - default + regs->edx = (regs->edx & 0xffffff00) | 0; + res=0; break; - case 0x5f01: - regs->eax = 0x5f; - regs->ecx = (regs->ecx & 0xffffff00 ) | 2; // panel type = 2 = 1024 * 768 - res = 0; + + case 0x5f0b: /* Get Expansion Setting */ + regs->eax = (regs->eax & 0xffff0000 ) | 0x5f; + + regs->ecx = regs->ecx & 0xffffff00; // non-expansion + // regs->ecx = regs->ecx & 0xffffff00 | 1; // expansion + res=0; break; - case 0x5f02: - regs->eax=0x5f; - regs->ebx= (regs->ebx & 0xffff0000) | 2; - regs->ecx= (regs->ecx & 0xffff0000) | 0x401; // PAL + crt only - regs->edx= (regs->edx & 0xffff0000) | 0; // TV Layout - default + + case 0x5f0f: /* VGA Post Completion */ + regs->eax = (regs->eax & 0xffff0000 ) | 0x5f; res=0; break; - case 0x5f0f: - regs->eax=0x860f; + + case 0x5f18: + regs->eax = (regs->eax & 0xffff0000 ) | 0x5f; +#define UMA_SIZE_8MB (3 << 0) +#define UMA_SIZE_16MB (4 << 0) +#define UMA_SIZE_32MB (5 << 0) + + regs->ebx = (regs->ebx & 0xffff0000 ) | MEMORY_SPEED_533MHZ | UMA_SIZE_32MB; + + mem_speed = pci_read_config8(dev_find_slot(0, PCI_DEVFN(0, 4)), SCRATCH_DRAM_FREQ); + if (mem_speed > 5) + mem_speed = 5; + + regs->ebx |= memory_mapping[mem_speed]; break; + + res=0; break; + default: printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", regs->eax & 0xffff); Modified: trunk/src/northbridge/via/cx700/raminit.c ============================================================================== --- trunk/src/northbridge/via/cx700/raminit.c Sun Apr 25 23:43:29 2010 (r5499) +++ trunk/src/northbridge/via/cx700/raminit.c Sun Apr 25 23:44:33 2010 (r5500) @@ -39,13 +39,6 @@ #define HOSTCTRL PCI_DEV(0, 0, 2) #define MEMCTRL PCI_DEV(0, 0, 3) -#define DDRII_666 0x5 -#define DDRII_533 0x4 -#define DDRII_400 0x3 -#define DDRII_333 0x2 -#define DDRII_266 0x1 -#define DDRII_200 0x0 - #define OHM_150 1 #ifdef MEM_WIDTH_32BIT_MODE @@ -114,6 +107,240 @@ } \ } +static const u8 Reg_Val[] = { +/* REG, VALUE */ + 0x70, 0x33, + 0x71, 0x11, + 0x72, 0x33, + 0x73, 0x11, + 0x74, 0x20, + 0x75, 0x2e, + 0x76, 0x64, + 0x77, 0x00, + 0x78, 0x44, + 0x79, 0xaa, + 0x7a, 0x33, + 0x7b, 0xaa, + 0x7c, 0x00, + 0x7e, 0x33, + 0x7f, 0x33, + 0x80, 0x44, + 0x81, 0x44, + 0x82, 0x44, + 0x83, 0x02, + 0x50, 0x88, + 0x51, 0x7b, + 0x52, 0x6f, + 0x53, 0x88, + 0x54, 0x0e, + 0x55, 0x00, + 0x56, 0x00, + 0x59, 0x00, + 0x5d, 0x72, + 0x5e, 0x88, + 0x5f, 0xc7, + 0x68, 0x01, +}; + +/* Host registers initial value */ +static const u8 Host_Reg_Val[] = { +/* REG, VALUE */ + 0x60, 0xff, + 0x61, 0xff, + 0x62, 0x0f, + 0x63, 0xff, + 0x64, 0xff, + 0x65, 0x0f, + 0x66, 0xff, + 0x67, 0x30, +}; + +static const u8 Mem_Reg_Init[] = { +/* REG, AND, OR */ + 0x50, 0x11, 0x66, + 0x51, 0x11, 0x66, + 0x52, 0x00, 0x11, + 0x53, 0x00, 0x0f, + 0x54, 0x00, 0x00, + 0x55, 0x00, 0x00, + 0x56, 0x00, 0x00, + 0x57, 0x00, 0x00, + 0x60, 0x00, 0x00, + 0x62, 0xf7, 0x08, + 0x65, 0x00, 0xd9, + 0x66, 0x00, 0x80, + 0x67, 0x00, 0x50, /* OR 0x00 ?? */ + 0x69, 0xf0, 0x00, + 0x6a, 0x00, 0x00, + 0x6d, 0xcf, 0xc0, + 0x6e, 0xff, 0x80, + 0x75, 0x0f, 0x40, + 0x77, 0x00, 0x00, + 0x80, 0x00, 0x00, + 0x81, 0x00, 0x00, + 0x82, 0x00, 0x00, + 0x83, 0x00, 0x00, + 0x84, 0x00, 0x00, + 0x85, 0x00, 0x00, + 0x86, 0xff, 0x2c, /* OR 0x28 if we don't want enable top 1M SM memory */ + 0x40, 0x00, 0x00, + 0x7c, 0x00, 0x00, + 0x7e, 0x00, 0x00, + 0xa4, 0xfe, 0x00, + 0xb0, 0x7f, 0x80, + 0xb1, 0x00, 0xaa, + 0xb4, 0xfd, 0x02, + 0xb8, 0xfe, 0x00, +}; + +static const u8 Dram_Driving_ODT_CTRL[] = { +/* REG, VALUE */ + 0xd6, 0xa8, + 0xd4, 0x80, + 0xd0, 0x88, + 0xd3, 0x01, + 0xd8, 0x00, + 0xda, 0x80, +}; + +#define Rank0_ODT 0x00 +#define Rank1_ODT 0x01 +#define Rank2_ODT 0x02 +#define Rank3_ODT 0x03 +#define NA_ODT 0x00 +#define NB_ODT_75ohm 0x00 +#define NB_ODT_150ohm 0x01 +#define DDR2_ODT_75ohm 0x20 +#define DDR2_ODT_150ohm 0x40 + +static const u8 ODT_TBL[] = { +/* RankMap, ODT Control Bits, DRAM & NB ODT setting */ + 0x01, ((NA_ODT << 6) | (NA_ODT << 4) | (NA_ODT << 2) | Rank0_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm), + 0x03, ((NA_ODT << 6) | (NA_ODT << 4) | (Rank0_ODT << 2) | Rank1_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm), + 0x04, ((NA_ODT << 6) | (Rank2_ODT << 4) | (NA_ODT << 2) | NA_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm), + 0x05, ((NA_ODT << 6) | (Rank0_ODT << 4) | (NA_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm), + 0x07, ((NA_ODT << 6) | (Rank0_ODT << 4) | (Rank2_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm), + 0x0c, ((Rank2_ODT << 6) | (Rank3_ODT << 4) | (NA_ODT << 2) | NA_ODT), (DDR2_ODT_150ohm | NB_ODT_75ohm), + 0x0d, ((Rank0_ODT << 6) | (Rank0_ODT << 4) | (NA_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm), + 0x0f, ((Rank0_ODT << 6) | (Rank0_ODT << 4) | (Rank2_ODT << 2) | Rank2_ODT), (DDR2_ODT_75ohm | NB_ODT_150ohm), +}; + +static const u8 DQS_DQ_TBL[] = { +/* RxE0: DRAM Timing DQS */ +/* RxE2: DRAM Timing DQ */ +/* RxE0, RxE2 */ + 0xee, 0xba, + 0xee, 0xba, + 0xcc, 0xba, + 0xcc, 0xba, +}; + +static const u8 Duty_Control_DDR2[] = { +/* RxEC, RxED, RxEE, RXEF */ + /* DDRII533 1~2 rank, DDRII400 */ + 0x84, 0x10, 0x00, 0x10, + /* DDRII533 3~4 rank */ + 0x44, 0x10, 0x00, 0x10, +}; + +static const u8 ChA_Clk_Phase_DDR2_Table[] = { +/* Rx91, Rx92, Rx93 */ + /* DDRII533 1 rank */ + 0x04, 0x05, 0x06, + /* DDRII533 2~4 rank */ + 0x04, 0x05, 0x05, + /* DDRII400 */ + 0x02, 0x04, 0x04, +}; + +static const u8 DQ_DQS_Table[] = { +/* REG, VALUE */ +/* DRAM DQ/DQS Output Delay Control */ + 0xdc, 0x65, + 0xdd, 0x01, + 0xde, 0xc0, +/* DRAM DQ/DQS input Capture Control */ + 0x78, 0x83, + 0x79, 0x83, + 0x7a, 0x00, +}; + +static const u8 DQSOChA_DDR2_Driving_Table[] = { +/* Rx70, Rx71 */ + /* DDRII533 1~2 rank */ + 0x00, 0x01, + /* DDRII533 3~4 rank */ + 0x03, 0x00, + /* DDRII400 1~2 rank */ + 0x00, 0x04, + /* DDRII400 3~4 rank */ + 0x00, 0x01, +}; + +/************************************************************************/ +/* Chipset Performance UP and other setting after DRAM Sizing Registers */ +/************************************************************************/ +static const u8 Dram_Table[] = { +/* REG, AND, OR */ + 0x60, 0xff, 0x03, + 0x66, 0xcf, 0x80, + 0x68, 0x00, 0x00, + 0x69, 0xfd, 0x03, + 0x6e, 0xff, 0x01, + 0x95, 0xff, 0x40, +}; + +static const u8 Host_Table[] = { +/* REG, AND, OR */ + 0x51, 0x81, 0x7a, + 0x55, 0xff, 0x06, + 0x5e, 0x00, 0x88, + 0x5d, 0xff, 0xb2, +}; + +static const u8 Init_Rank_Reg_Table[] = { + /* Rank Ending Address Registers */ + 0x40, 0x41, 0x42, 0x43, + /* Rank Beginning Address Registers */ + 0x48, 0x49, 0x4a, 0x4b, + /* Physical-to-Virtual Rank Mapping Registers */ + 0x54, 0x55, +}; + +static const u16 DDR2_MRS_table[] = { +/* CL: 2, 3, 4, 5 */ + 0x150, 0x1d0, 0x250, 0x2d0, /* BL=4 ;Use 1X-bandwidth MA table to init DRAM */ + 0x158, 0x1d8, 0x258, 0x2d8, /* BL=8 ;Use 1X-bandwidth MA table to init DRAM */ +}; + +#define MRS_DDR2_TWR2 ((0 << 15) | (0 << 20) | (1 << 12)) +#define MRS_DDR2_TWR3 ((0 << 15) | (1 << 20) | (0 << 12)) +#define MRS_DDR2_TWR4 ((0 << 15) | (1 << 20) | (1 << 12)) +#define MRS_DDR2_TWR5 ((1 << 15) | (0 << 20) | (0 << 12)) +static const u32 DDR2_Twr_table[] = { + MRS_DDR2_TWR2, + MRS_DDR2_TWR3, + MRS_DDR2_TWR4, + MRS_DDR2_TWR5, +}; + +static const u8 DQSI_Rate_Table[] = { + 8, /* DDRII 200 */ + 8, /* DDRII 266 */ + 8, /* DDRII 333 */ + 7, /* DDRII 400 */ + 8, /* DDRII 533 */ + 8, /* DDRII 666 */ +}; + +static const u8 REFC_Table[] = { + 0x65, 0x32, /* DDRII 100 */ + 0x86, 0x43, /* DDRII 266 */ + 0xa8, 0x54, /* DDRII 333 */ + 0xca, 0x65, /* DDRII 400 */ + 0xca, 0x86, /* DDRII 533 */ + 0xca, 0xa8, /* DDRII 666 */ +}; static void do_ram_command(const struct mem_controller *ctrl, u8 command) {

1 0

[commit] r5499 - in trunk/src: arch/i386/init cpu/intel/car cpu/intel/model_106cx cpu/intel/model_6ex cpu/intel/model_6fx cpu/via/car include/cpu/x86
by repository service 25 Apr '10

25 Apr '10

Author: stepan Date: Sun Apr 25 23:43:29 2010 New Revision: 5499 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5499 Log: a single place for the romstage stack for copy_and_run. geode lx and amd opteron don't use this yet. Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/src/include/cpu/x86/stack.h Modified: trunk/src/arch/i386/init/crt0_prologue.inc trunk/src/arch/i386/init/crt0_romcc_epilogue.inc trunk/src/cpu/intel/car/cache_as_ram.inc trunk/src/cpu/intel/model_106cx/cache_as_ram.inc trunk/src/cpu/intel/model_6ex/cache_as_ram.inc trunk/src/cpu/intel/model_6fx/cache_as_ram.inc trunk/src/cpu/via/car/cache_as_ram.inc Modified: trunk/src/arch/i386/init/crt0_prologue.inc ============================================================================== --- trunk/src/arch/i386/init/crt0_prologue.inc Sun Apr 25 22:42:02 2010 (r5498) +++ trunk/src/arch/i386/init/crt0_prologue.inc Sun Apr 25 23:43:29 2010 (r5499) @@ -18,6 +18,7 @@ */ #include <cpu/x86/post_code.h> +#include <cpu/x86/stack.h> .section ".rom.data", "a", @progbits .section ".rom.text", "ax", @progbits Modified: trunk/src/arch/i386/init/crt0_romcc_epilogue.inc ============================================================================== --- trunk/src/arch/i386/init/crt0_romcc_epilogue.inc Sun Apr 25 22:42:02 2010 (r5498) +++ trunk/src/arch/i386/init/crt0_romcc_epilogue.inc Sun Apr 25 23:43:29 2010 (r5499) @@ -14,16 +14,7 @@ movl %ebp, %esi - /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This - * makes sure that we stay completely within the 1M-64K of memory that we - * preserve for suspend/resume. - */ - -#ifndef HIGH_MEMORY_SAVE -#warning Need a central place for HIGH_MEMORY_SAVE -#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) -#endif - movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp + movl $ROMSTAGE_STACK, %esp movl %esp, %ebp pushl %esi call copy_and_run Modified: trunk/src/cpu/intel/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/car/cache_as_ram.inc Sun Apr 25 22:42:02 2010 (r5498) +++ trunk/src/cpu/intel/car/cache_as_ram.inc Sun Apr 25 23:43:29 2010 (r5499) @@ -30,6 +30,7 @@ #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase (0xd0000 - CacheSize) +#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> /* Save the BIST result */ @@ -398,16 +399,7 @@ movl %ebp, %esi - /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This - * makes sure that we stay completely within the 1M-64K of memory that we - * preserve for suspend/resume. - */ - -#ifndef HIGH_MEMORY_SAVE -#warning Need a central place for HIGH_MEMORY_SAVE -#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) -#endif - movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp + movl $ROMSTAGE_STACK, %esp movl %esp, %ebp pushl %esi call copy_and_run Modified: trunk/src/cpu/intel/model_106cx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Sun Apr 25 22:42:02 2010 (r5498) +++ trunk/src/cpu/intel/model_106cx/cache_as_ram.inc Sun Apr 25 23:43:29 2010 (r5499) @@ -21,6 +21,7 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE +#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> @@ -256,16 +257,7 @@ movl %ebp, %esi - /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This - * makes sure that we stay completely within the 1M-64K of memory that we - * preserve for suspend/resume. - */ - -#ifndef HIGH_MEMORY_SAVE -#warning Need a central place for HIGH_MEMORY_SAVE -#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) -#endif - movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp + movl $ROMSTAGE_STACK, %esp movl %esp, %ebp pushl %esi call copy_and_run Modified: trunk/src/cpu/intel/model_6ex/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Sun Apr 25 22:42:02 2010 (r5498) +++ trunk/src/cpu/intel/model_6ex/cache_as_ram.inc Sun Apr 25 23:43:29 2010 (r5499) @@ -21,6 +21,7 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE +#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> @@ -256,16 +257,7 @@ movl %ebp, %esi - /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This - * makes sure that we stay completely within the 1M-64K of memory that we - * preserve for suspend/resume. - */ - -#ifndef HIGH_MEMORY_SAVE -#warning Need a central place for HIGH_MEMORY_SAVE -#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) -#endif - movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp + movl $ROMSTAGE_STACK, %esp movl %esp, %ebp pushl %esi call copy_and_run Modified: trunk/src/cpu/intel/model_6fx/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Sun Apr 25 22:42:02 2010 (r5498) +++ trunk/src/cpu/intel/model_6fx/cache_as_ram.inc Sun Apr 25 23:43:29 2010 (r5499) @@ -21,6 +21,7 @@ #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE +#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> @@ -270,16 +271,7 @@ movl %ebp, %esi - /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This - * makes sure that we stay completely within the 1M-64K of memory that we - * preserve for suspend/resume. - */ - -#ifndef HIGH_MEMORY_SAVE -#warning Need a central place for HIGH_MEMORY_SAVE -#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) -#endif - movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp + movl $ROMSTAGE_STACK, %esp movl %esp, %ebp pushl %esi call copy_and_run Modified: trunk/src/cpu/via/car/cache_as_ram.inc ============================================================================== --- trunk/src/cpu/via/car/cache_as_ram.inc Sun Apr 25 22:42:02 2010 (r5498) +++ trunk/src/cpu/via/car/cache_as_ram.inc Sun Apr 25 23:43:29 2010 (r5499) @@ -28,7 +28,7 @@ #define CacheSize CONFIG_DCACHE_RAM_SIZE #define CacheBase CONFIG_DCACHE_RAM_BASE - +#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> /* Save the BIST result */ @@ -270,16 +270,7 @@ movl %ebp, %esi - /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This - * makes sure that we stay completely within the 1M-64K of memory that we - * preserve for suspend/resume. - */ - -#ifndef HIGH_MEMORY_SAVE -#warning Need a central place for HIGH_MEMORY_SAVE -#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 ) -#endif - movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp + movl $ROMSTAGE_STACK, %esp movl %esp, %ebp pushl %esi call copy_and_run Added: trunk/src/include/cpu/x86/stack.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/include/cpu/x86/stack.h Sun Apr 25 23:43:29 2010 (r5499) @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#ifndef __CPU_X86_STACK_H +#define __CPU_X86_STACK_H + +/* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This + * makes sure that we stay completely within the 1M-64K of memory that we + * preserve for suspend/resume. This is basically HIGH_MEMORY_SAFE (see + * cbmem.h) + */ + +#define ROMSTAGE_STACK_OFFSET ( (1024 - 64) * 1024 ) +#define ROMSTAGE_STACK (CONFIG_RAMBASE + ROMSTAGE_STACK_OFFSET) + +#endif

1 0

build service results for r5498
by coreboot information 25 Apr '10

25 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 5498 to the coreboot repository. This caused the following changes: Change Log: drop "arch/asm.h" and "arch/intel.h" and create "cpu/x86/post_code.h" (which could at some time hold global post code definitions, too) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of emulation:qemu-x86 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5498&device=qemu-x86&vendo… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r5498 - in trunk/src: arch/i386/include/arch arch/i386/init arch/i386/lib arch/i386/llshell cpu/x86/lapic cpu/x86/smm include/cpu/x86
by repository service 25 Apr '10

25 Apr '10

Author: stepan Date: Sun Apr 25 22:42:02 2010 New Revision: 5498 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5498 Log: drop "arch/asm.h" and "arch/intel.h" and create "cpu/x86/post_code.h" (which could at some time hold global post code definitions, too) Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Added: trunk/src/include/cpu/x86/post_code.h Deleted: trunk/src/arch/i386/include/arch/asm.h trunk/src/arch/i386/include/arch/intel.h Modified: trunk/src/arch/i386/include/arch/cpu.h trunk/src/arch/i386/init/bootblock_prologue.c trunk/src/arch/i386/init/crt0_prologue.inc trunk/src/arch/i386/lib/c_start.S trunk/src/arch/i386/lib/cpu.c trunk/src/arch/i386/llshell/console.inc trunk/src/arch/i386/llshell/llshell.inc trunk/src/cpu/x86/lapic/secondary.S trunk/src/cpu/x86/smm/smmhandler.S trunk/src/cpu/x86/smm/smmrelocate.S Modified: trunk/src/arch/i386/include/arch/cpu.h ============================================================================== --- trunk/src/arch/i386/include/arch/cpu.h Sun Apr 25 22:24:09 2010 (r5497) +++ trunk/src/arch/i386/include/arch/cpu.h Sun Apr 25 22:42:02 2010 (r5498) @@ -28,6 +28,7 @@ uint32_t ecx; uint32_t edx; }; + /* * Generic CPUID function */ @@ -44,7 +45,6 @@ return result; } - /* * CPUID functions returning a single datum */ @@ -58,6 +58,7 @@ : "ebx", "ecx", "edx"); return eax; } + static inline unsigned int cpuid_ebx(unsigned int op) { unsigned int eax, ebx; @@ -68,6 +69,7 @@ : "ecx", "edx" ); return ebx; } + static inline unsigned int cpuid_ecx(unsigned int op) { unsigned int eax, ecx; @@ -78,6 +80,7 @@ : "ebx", "edx" ); return ecx; } + static inline unsigned int cpuid_edx(unsigned int op) { unsigned int eax, edx; @@ -89,8 +92,6 @@ return edx; } - - #define X86_VENDOR_INVALID 0 #define X86_VENDOR_INTEL 1 #define X86_VENDOR_CYRIX 2 @@ -112,6 +113,7 @@ unsigned vendor; unsigned device; }; + struct cpu_driver { struct device_operations *ops; struct cpu_device_id *id_table; @@ -141,7 +143,6 @@ return ci->index; } - struct cpuinfo_x86 { uint8_t x86; /* CPU family */ uint8_t x86_vendor; /* CPU vendor */ Modified: trunk/src/arch/i386/init/bootblock_prologue.c ============================================================================== --- trunk/src/arch/i386/init/bootblock_prologue.c Sun Apr 25 22:24:09 2010 (r5497) +++ trunk/src/arch/i386/init/bootblock_prologue.c Sun Apr 25 22:42:02 2010 (r5498) @@ -1,37 +1,28 @@ -/* -*- asm -*- - * $ $ - * - */ - -/* - * Copyright (C) 1996-2002 Markus Franz Xaver Johannes Oberhumer +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2002 Eric Biederman * - * This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. * - * Originally this code was part of ucl the data compression library - * for upx the ``Ultimate Packer of eXecutables''. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. * - * - Converted to gas assembly, and refitted to work with etherboot. - * Eric Biederman 20 Aug 2002 - * - Merged the nrv2b decompressor into crt0.base of coreboot - * Eric Biederman 26 Sept 2002 + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <cpu/x86/post_code.h> -#include <arch/asm.h> -#include <arch/intel.h> -#include <console/loglevel.h> - -/* - * This is the entry code the code in .reset section - * jumps to this address. - * - */ .section ".rom.data", "a", @progbits .section ".rom.text", "ax", @progbits - post_code(0x01) /* delay for chipsets */ +/* This is the entry codde. The code in the .reset section jumps here. */ + + post_code(0x01) Modified: trunk/src/arch/i386/init/crt0_prologue.inc ============================================================================== --- trunk/src/arch/i386/init/crt0_prologue.inc Sun Apr 25 22:24:09 2010 (r5497) +++ trunk/src/arch/i386/init/crt0_prologue.inc Sun Apr 25 22:42:02 2010 (r5498) @@ -1,22 +1,28 @@ -/* - * Copyright 2002 Eric Biederman +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2002 Eric Biederman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. * - * This file is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of the License. + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#include <arch/asm.h> -#include <arch/intel.h> -#include <console/loglevel.h> +#include <cpu/x86/post_code.h> -/* - * This is the entry code. - * The code in the .reset section jumps to this address. - * - */ .section ".rom.data", "a", @progbits .section ".rom.text", "ax", @progbits - post_code(0x01) /* delay for chipsets */ +/* This is the entry code. The code in the .reset section jumps here. */ + + post_code(0x01) Modified: trunk/src/arch/i386/lib/c_start.S ============================================================================== --- trunk/src/arch/i386/lib/c_start.S Sun Apr 25 22:24:09 2010 (r5497) +++ trunk/src/arch/i386/lib/c_start.S Sun Apr 25 22:42:02 2010 (r5498) @@ -1,5 +1,4 @@ -#include <arch/asm.h> -#include <arch/intel.h> +#include <cpu/x86/post_code.h> .section ".text" .code32 Modified: trunk/src/arch/i386/lib/cpu.c ============================================================================== --- trunk/src/arch/i386/lib/cpu.c Sun Apr 25 22:24:09 2010 (r5497) +++ trunk/src/arch/i386/lib/cpu.c Sun Apr 25 22:42:02 2010 (r5498) @@ -238,7 +238,8 @@ get_fms(&c, cpu->device); - printk(BIOS_DEBUG, "CPU: family %02x, model %02x, stepping %02x\n", c.x86, c.x86_model, c.x86_mask); + printk(BIOS_DEBUG, "CPU: family %02x, model %02x, stepping %02x\n", + c.x86, c.x86_model, c.x86_mask); /* Lookup the cpu's operations */ set_cpu_ops(cpu); Modified: trunk/src/arch/i386/llshell/console.inc ============================================================================== --- trunk/src/arch/i386/llshell/console.inc Sun Apr 25 22:24:09 2010 (r5497) +++ trunk/src/arch/i386/llshell/console.inc Sun Apr 25 22:42:02 2010 (r5498) @@ -1,4 +1,3 @@ -// #include <loglevel.h> jmp console0 Modified: trunk/src/arch/i386/llshell/llshell.inc ============================================================================== --- trunk/src/arch/i386/llshell/llshell.inc Sun Apr 25 22:24:09 2010 (r5497) +++ trunk/src/arch/i386/llshell/llshell.inc Sun Apr 25 22:42:02 2010 (r5498) @@ -1,3 +1,20 @@ + +#define RET_LABEL(label) \ + jmp label##_done + +#define CALL_LABEL(label) \ + jmp label ;\ +label##_done: + +#define CALLSP(func) \ + lea 0f, %esp ; \ + jmp func ; \ +0: + +#define RETSP \ + jmp *%esp + + #include "console.inc" #include "pci.inc" #include "ramtest.inc" Modified: trunk/src/cpu/x86/lapic/secondary.S ============================================================================== --- trunk/src/cpu/x86/lapic/secondary.S Sun Apr 25 22:24:09 2010 (r5497) +++ trunk/src/cpu/x86/lapic/secondary.S Sun Apr 25 22:42:02 2010 (r5498) @@ -1,7 +1,6 @@ -#include <arch/asm.h> -#include <arch/intel.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/lapic_def.h> + .text .globl _secondary_start, _secondary_start_end .balign 4096 Modified: trunk/src/cpu/x86/smm/smmhandler.S ============================================================================== --- trunk/src/cpu/x86/smm/smmhandler.S Sun Apr 25 22:24:09 2010 (r5497) +++ trunk/src/cpu/x86/smm/smmhandler.S Sun Apr 25 22:42:02 2010 (r5498) @@ -52,8 +52,6 @@ * */ -#include <arch/asm.h> - #define LAPIC_ID 0xfee00020 /* SMM_HANDLER_OFFSET is the 16bit offset within the ASEG Modified: trunk/src/cpu/x86/smm/smmrelocate.S ============================================================================== --- trunk/src/cpu/x86/smm/smmrelocate.S Sun Apr 25 22:24:09 2010 (r5497) +++ trunk/src/cpu/x86/smm/smmrelocate.S Sun Apr 25 22:42:02 2010 (r5498) @@ -19,13 +19,13 @@ * MA 02110-1301 USA */ -#include <arch/asm.h> - // Make sure no stage 2 code is included: #define __PRE_RAM__ // FIXME: Is this piece of code southbridge specific, or // can it be cleaned up so this include is not required? +// It's needed right now because we get our PM_BASE from +// here. #include "../../../southbridge/intel/i82801gx/i82801gx.h" #undef DEBUG_SMM_RELOCATION Added: trunk/src/include/cpu/x86/post_code.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/include/cpu/x86/post_code.h Sun Apr 25 22:42:02 2010 (r5498) @@ -0,0 +1,6 @@ + + +#define post_code(value) \ + movb $value, %al; \ + outb %al, $0x80 +

1 0

build service results for r5497
by coreboot information 25 Apr '10

25 Apr '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "ruik" checked in revision 5497 to the coreboot repository. This caused the following changes: Change Log: Fix the the build of r5494 on Asus A8V-E SE. The K8M890 and K8T890 were not treated separately until now. Fix it. Hope self ack is OK, compiled tested locally. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Build Log: Compilation of asus:a8v-e_se has been fixed If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

← Newer
1
...
6
7
8
9
10
11
12
...
41
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot April 2010