coreboot November 2010

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[RFC]Dedefine DIMMx in romstage.c/spd_addr.h
by Patrick Georgi 18 Nov '10

18 Nov '10

Hi, two of the remaining defines that need to be eliminated from romstage.c are DIMM0 and DIMM1, as these are used in some northbridges. That got me thinking about moving all of DIMM0..DIMM7 to Kconfig, and how that could look like. The thing is, that we currently have lots of duplicate data (DIMM0..DIMMx) in _many_ board directories that looks essentially the same, there are maybe 5 or 6 different sets of values. Are these northbridge specific (with the option that some boards override them), or who is responsible for these values? Patrick

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[commit] r6089 - in trunk/src: mainboard/dell/s1850 mainboard/intel/jarrell northbridge/intel/e7520 northbridge/intel/e7525 northbridge/intel/i3100
by repository service 18 Nov '10

18 Nov '10

Author: oxygene Date: Thu Nov 18 12:36:16 2010 New Revision: 6089 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6089 Log: Move DIMM_MAP_LOGICAL to Kconfig. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/src/mainboard/dell/s1850/Kconfig trunk/src/mainboard/dell/s1850/romstage.c trunk/src/mainboard/intel/jarrell/Kconfig trunk/src/mainboard/intel/jarrell/romstage.c trunk/src/northbridge/intel/e7520/Kconfig trunk/src/northbridge/intel/e7520/raminit.c trunk/src/northbridge/intel/e7525/Kconfig trunk/src/northbridge/intel/e7525/raminit.c trunk/src/northbridge/intel/i3100/Kconfig trunk/src/northbridge/intel/i3100/raminit.c Modified: trunk/src/mainboard/dell/s1850/Kconfig ============================================================================== --- trunk/src/mainboard/dell/s1850/Kconfig Thu Nov 18 11:48:15 2010 (r6088) +++ trunk/src/mainboard/dell/s1850/Kconfig Thu Nov 18 12:36:16 2010 (r6089) @@ -46,4 +46,8 @@ int default 9 +config DIMM_MAP_LOGICAL + hex + default 0x2841 + endif # BOARD_DELL_S1850 Modified: trunk/src/mainboard/dell/s1850/romstage.c ============================================================================== --- trunk/src/mainboard/dell/s1850/romstage.c Thu Nov 18 11:48:15 2010 (r6088) +++ trunk/src/mainboard/dell/s1850/romstage.c Thu Nov 18 12:36:16 2010 (r6089) @@ -37,9 +37,6 @@ return smbus_read_byte(device, address); } -/* this is very highly mainboard dependent, related to wiring */ -/* from factory BIOS via lspci */ -#define DIMM_MAP_LOGICAL 0x2841 #include "northbridge/intel/e7520/raminit.c" #include "lib/generic_sdram.c" Modified: trunk/src/mainboard/intel/jarrell/Kconfig ============================================================================== --- trunk/src/mainboard/intel/jarrell/Kconfig Thu Nov 18 11:48:15 2010 (r6088) +++ trunk/src/mainboard/intel/jarrell/Kconfig Thu Nov 18 12:36:16 2010 (r6089) @@ -43,4 +43,8 @@ hex default 0x1079 +config DIMM_MAP_LOGICAL + hex + default 0x0124 + endif # BOARD_INTEL_JARRELL Modified: trunk/src/mainboard/intel/jarrell/romstage.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/romstage.c Thu Nov 18 11:48:15 2010 (r6088) +++ trunk/src/mainboard/intel/jarrell/romstage.c Thu Nov 18 12:36:16 2010 (r6089) @@ -29,8 +29,6 @@ #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D6F0) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) -#define DIMM_MAP_LOGICAL 0x0124 - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); Modified: trunk/src/northbridge/intel/e7520/Kconfig ============================================================================== --- trunk/src/northbridge/intel/e7520/Kconfig Thu Nov 18 11:48:15 2010 (r6088) +++ trunk/src/northbridge/intel/e7520/Kconfig Thu Nov 18 12:36:16 2010 (r6089) @@ -1,3 +1,9 @@ config NORTHBRIDGE_INTEL_E7520 bool +if NORTHBRIDGE_INTEL_E7520 +config DIMM_MAP_LOGICAL + hex + default 0x1248 + +endif Modified: trunk/src/northbridge/intel/e7520/raminit.c ============================================================================== --- trunk/src/northbridge/intel/e7520/raminit.c Thu Nov 18 11:48:15 2010 (r6088) +++ trunk/src/northbridge/intel/e7520/raminit.c Thu Nov 18 12:36:16 2010 (r6089) @@ -1078,12 +1078,8 @@ print_debug("Starting SDRAM Enable\n"); /* 0x80 */ -#ifdef DIMM_MAP_LOGICAL pci_write_config32(PCI_DEV(0, 0x00, 0), DRM, - 0x00210000 | DIMM_MAP_LOGICAL); -#else - pci_write_config32(PCI_DEV(0, 0x00, 0), DRM, 0x00211248); -#endif + 0x00210000 | CONFIG_DIMM_MAP_LOGICAL); /* set dram type and Front Side Bus freq. */ drc = spd_set_dram_controller_mode(ctrl, mask); if( drc == 0) { Modified: trunk/src/northbridge/intel/e7525/Kconfig ============================================================================== --- trunk/src/northbridge/intel/e7525/Kconfig Thu Nov 18 11:48:15 2010 (r6088) +++ trunk/src/northbridge/intel/e7525/Kconfig Thu Nov 18 12:36:16 2010 (r6089) @@ -1,3 +1,9 @@ config NORTHBRIDGE_INTEL_E7525 bool +if NORTHBRIDGE_INTEL_E7525 +config DIMM_MAP_LOGICAL + hex + default 0x1248 + +endif Modified: trunk/src/northbridge/intel/e7525/raminit.c ============================================================================== --- trunk/src/northbridge/intel/e7525/raminit.c Thu Nov 18 11:48:15 2010 (r6088) +++ trunk/src/northbridge/intel/e7525/raminit.c Thu Nov 18 12:36:16 2010 (r6089) @@ -1055,12 +1055,8 @@ print_debug("Starting SDRAM Enable\n"); /* 0x80 */ -#ifdef DIMM_MAP_LOGICAL pci_write_config32(ctrl->f0, DRM, - 0x00210000 | DIMM_MAP_LOGICAL); -#else - pci_write_config32(ctrl->f0, DRM, 0x00211248); -#endif + 0x00210000 | CONFIG_DIMM_MAP_LOGICAL); /* set dram type and Front Side Bus freq. */ drc = spd_set_dram_controller_mode(ctrl, mask); if( drc == 0) { Modified: trunk/src/northbridge/intel/i3100/Kconfig ============================================================================== --- trunk/src/northbridge/intel/i3100/Kconfig Thu Nov 18 11:48:15 2010 (r6088) +++ trunk/src/northbridge/intel/i3100/Kconfig Thu Nov 18 12:36:16 2010 (r6089) @@ -1,3 +1,9 @@ config NORTHBRIDGE_INTEL_I3100 bool +if NORTHBRIDGE_INTEL_I3100 +config DIMM_MAP_LOGICAL + hex + default 0x1248 + +endif Modified: trunk/src/northbridge/intel/i3100/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i3100/raminit.c Thu Nov 18 11:48:15 2010 (r6088) +++ trunk/src/northbridge/intel/i3100/raminit.c Thu Nov 18 12:36:16 2010 (r6089) @@ -973,12 +973,8 @@ print_debug("Starting SDRAM Enable\n"); /* 0x80 */ -#ifdef DIMM_MAP_LOGICAL pci_write_config32(ctrl->f0, DRM, - 0x00410000 | DIMM_MAP_LOGICAL); -#else - pci_write_config32(ctrl->f0, DRM, 0x00411248); -#endif + 0x00410000 | CONFIG_DIMM_MAP_LOGICAL); /* set dram type and Front Side Bus freq. */ drc = spd_set_dram_controller_mode(ctrl, mask); if( drc == 0) {

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[commit] r6088 - in trunk/src: mainboard/intel/eagleheights southbridge/intel/i3100
by repository service 18 Nov '10

18 Nov '10

Author: oxygene Date: Thu Nov 18 11:48:15 2010 New Revision: 6088 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6088 Log: Move register block definitions out of board code into chipset code (where it belongs) Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/src/mainboard/intel/eagleheights/romstage.c trunk/src/southbridge/intel/i3100/i3100.h trunk/src/southbridge/intel/i3100/i3100_sata.c Modified: trunk/src/mainboard/intel/eagleheights/romstage.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/romstage.c Thu Nov 18 01:46:53 2010 (r6087) +++ trunk/src/mainboard/intel/eagleheights/romstage.c Thu Nov 18 11:48:15 2010 (r6088) @@ -41,16 +41,11 @@ #include "superio/intel/i3100/i3100_early_serial.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" #include "northbridge/intel/i3100/i3100.h" +#include "southbridge/intel/i3100/i3100.h" #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) -/* SATA */ -#define SATA_MAP 0x90 - -#define SATA_MODE_IDE 0x00 -#define SATA_MODE_AHCI 0x01 - #define RCBA_RPC 0x0224 /* 32 bit */ #define RCBA_TCTL 0x3000 /* 8 bit */ Modified: trunk/src/southbridge/intel/i3100/i3100.h ============================================================================== --- trunk/src/southbridge/intel/i3100/i3100.h Thu Nov 18 01:46:53 2010 (r6087) +++ trunk/src/southbridge/intel/i3100/i3100.h Thu Nov 18 11:48:15 2010 (r6088) @@ -21,6 +21,25 @@ #define SOUTHBRIDGE_INTEL_I3100_I3100_H #include "chip.h" +#define SATA_CMD 0x04 +#define SATA_PI 0x09 +#define SATA_PTIM 0x40 +#define SATA_STIM 0x42 +#define SATA_D1TIM 0x44 +#define SATA_SYNCC 0x48 +#define SATA_SYNCTIM 0x4A +#define SATA_IIOC 0x54 +#define SATA_MAP 0x90 +#define SATA_PCS 0x91 +#define SATA_ACR0 0xA8 +#define SATA_ACR1 0xAC +#define SATA_ATC 0xC0 +#define SATA_ATS 0xC4 +#define SATA_SP 0xD0 + +#define SATA_MODE_IDE 0x00 +#define SATA_MODE_AHCI 0x01 + void i3100_enable(device_t dev); #endif Modified: trunk/src/southbridge/intel/i3100/i3100_sata.c ============================================================================== --- trunk/src/southbridge/intel/i3100/i3100_sata.c Thu Nov 18 01:46:53 2010 (r6087) +++ trunk/src/southbridge/intel/i3100/i3100_sata.c Thu Nov 18 11:48:15 2010 (r6088) @@ -27,22 +27,6 @@ #include <device/pci_ops.h> #include "i3100.h" -#define SATA_CMD 0x04 -#define SATA_PI 0x09 -#define SATA_PTIM 0x40 -#define SATA_STIM 0x42 -#define SATA_D1TIM 0x44 -#define SATA_SYNCC 0x48 -#define SATA_SYNCTIM 0x4A -#define SATA_IIOC 0x54 -#define SATA_MAP 0x90 -#define SATA_PCS 0x91 -#define SATA_ACR0 0xA8 -#define SATA_ACR1 0xAC -#define SATA_ATC 0xC0 -#define SATA_ATS 0xC4 -#define SATA_SP 0xD0 - typedef struct southbridge_intel_i3100_config config_t; static void sata_init(struct device *dev)

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[commit] r6087 - trunk/src/include/cpu/intel
by repository service 18 Nov '10

18 Nov '10

Author: oxygene Date: Thu Nov 18 01:46:53 2010 New Revision: 6087 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6087 Log: For completeness sake: License header. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/src/include/cpu/intel/acpi.h Modified: trunk/src/include/cpu/intel/acpi.h ============================================================================== --- trunk/src/include/cpu/intel/acpi.h Thu Nov 18 01:11:32 2010 (r6086) +++ trunk/src/include/cpu/intel/acpi.h Thu Nov 18 01:46:53 2010 (r6087) @@ -1,3 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Patrick Georgi <patrick(a)georgi-clan.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + #define IA32_PLATFORM_ID 0x017 #define IA32_PERF_STS 0x198 #define IA32_PERF_CTL 0x199

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[commit] r6083 - in trunk/src: mainboard/asus/m2v-mx_se southbridge/via/k8t890 southbridge/via/vt8237r
by repository service 18 Nov '10

18 Nov '10

Author: ruik Date: Wed Nov 17 12:30:50 2010 New Revision: 6083 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6083 Log: Linux also needs the MMCONF area to be reserved either in E820 or as an ACPI motherboard resource or it will not enable MMCONFIG and the extended pcie configuration area will be unaccessible: This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF resource flags to do this. I also added a new resource for the mapped bios rom area just below 4GB. I'm not sure if the choice for the index parameter of new_resource() is correct though. Note that the bios rom decode is enabled in src/southbridge/via/vt8237r/vt8237r_early_smbus.c for the whole 4MB area (even though the comment says 1MB). Ruik: I extended the flash range to 16MB (This is what VT8237S can decode) Remove the MMCONFIG region reserve in the mainboard file (this patch makes it obsolete) Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Modified: trunk/src/mainboard/asus/m2v-mx_se/mainboard.c trunk/src/southbridge/via/k8t890/k8t890_traf_ctrl.c trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c Modified: trunk/src/mainboard/asus/m2v-mx_se/mainboard.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/mainboard.c Wed Nov 17 12:02:05 2010 (r6082) +++ trunk/src/mainboard/asus/m2v-mx_se/mainboard.c Wed Nov 17 12:30:50 2010 (r6083) @@ -30,18 +30,6 @@ int add_mainboard_resources(struct lb_memory *mem) { - device_t dev; - - dev = dev_find_device(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_K8M890CE_5, 0); - if (dev) { - struct resource *res = - find_resource(dev, K8T890_MMCONFIG_MBAR); - if (res) - lb_add_memory_range(mem, LB_MEM_RESERVED, res->base, - res->size); - } - #if (CONFIG_GFXUMA == 1) lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); Modified: trunk/src/southbridge/via/k8t890/k8t890_traf_ctrl.c ============================================================================== --- trunk/src/southbridge/via/k8t890/k8t890_traf_ctrl.c Wed Nov 17 12:02:05 2010 (r6082) +++ trunk/src/southbridge/via/k8t890/k8t890_traf_ctrl.c Wed Nov 17 12:30:50 2010 (r6083) @@ -58,7 +58,7 @@ res->limit = res->base + res->size - 1; res->align = 8; res->gran = 8; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_STORED | IORESOURCE_ASSIGNED; /* Add an MMCONFIG resource. */ @@ -67,7 +67,7 @@ res->align = log2(res->size); res->gran = log2(res->size); res->limit = 0xffffffff; /* 4G */ - res->flags = IORESOURCE_MEM; + res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE; } static void traf_ctrl_enable_generic(struct device *dev) Modified: trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c Wed Nov 17 12:02:05 2010 (r6082) +++ trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c Wed Nov 17 12:30:50 2010 (r6083) @@ -521,7 +521,7 @@ res->base = VT8237R_ACPI_IO_BASE; res->size = 128; res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_STORED | IORESOURCE_ASSIGNED; /* Fixed EISA ECLR I/O Regs */ @@ -529,7 +529,7 @@ res->base = 0x4d0; res->size = 2; res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_STORED | IORESOURCE_ASSIGNED; /* Fixed System Management Bus I/O Resource */ @@ -537,7 +537,7 @@ res->base = VT8237R_SMBUS_IO_BASE; res->size = 16; res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_STORED | IORESOURCE_ASSIGNED; /* Fixed APIC resource */ @@ -547,7 +547,15 @@ res->limit = 0xffffffffUL; res->align = 8; res->gran = 8; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Fixed flashrom resource */ + res = new_resource(dev, 4); + res->base = 0xff000000UL; + res->size = 0x01000000UL; /* 16MB */ + res->limit = 0xffffffffUL; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_STORED | IORESOURCE_ASSIGNED; res = new_resource(dev, 1);

2 1

[commit] r6086 - in trunk/src: cpu/amd/dualcore cpu/amd/quadcore mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/serengeti_cheetah ma...
by repository service 18 Nov '10

18 Nov '10

Author: oxygene Date: Thu Nov 18 01:11:32 2010 New Revision: 6086 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6086 Log: Eliminate SET_NB_CFG_54 option. There was no board that deselected it, and very likely there won't ever be any hardware that requires it deselected. Keep the "selected" code path around, leading to no functional change. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Scott Duplichan <scott(a)notabs.org> Modified: trunk/src/cpu/amd/dualcore/dualcore.c trunk/src/cpu/amd/quadcore/quadcore.c trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/pistachio/romstage.c trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c trunk/src/mainboard/amd/serengeti_cheetah/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/amd/tilapia_fam10/romstage.c trunk/src/mainboard/arima/hdama/romstage.c trunk/src/mainboard/asrock/939a785gmh/romstage.c trunk/src/mainboard/asus/a8n_e/romstage.c trunk/src/mainboard/asus/m4a785-m/romstage.c trunk/src/mainboard/broadcom/blast/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/gigabyte/ma785gmt/romstage.c trunk/src/mainboard/gigabyte/ma78gm/romstage.c trunk/src/mainboard/hp/dl145_g1/romstage.c trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c trunk/src/mainboard/ibm/e325/romstage.c trunk/src/mainboard/ibm/e326/romstage.c trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/jetway/pa78vm5/romstage.c trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/msi/ms7135/romstage.c trunk/src/mainboard/msi/ms7260/ap_romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/newisys/khepri/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/sunw/ultra40/romstage.c trunk/src/mainboard/supermicro/h8dme/ap_romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/romstage.c trunk/src/mainboard/tyan/s2850/romstage.c trunk/src/mainboard/tyan/s2875/romstage.c trunk/src/mainboard/tyan/s2880/romstage.c trunk/src/mainboard/tyan/s2881/romstage.c trunk/src/mainboard/tyan/s2882/romstage.c trunk/src/mainboard/tyan/s2885/romstage.c trunk/src/mainboard/tyan/s2891/romstage.c trunk/src/mainboard/tyan/s2892/romstage.c trunk/src/mainboard/tyan/s2895/romstage.c trunk/src/mainboard/tyan/s2912/ap_romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/mainboard/tyan/s4880/romstage.c trunk/src/mainboard/tyan/s4882/romstage.c Modified: trunk/src/cpu/amd/dualcore/dualcore.c ============================================================================== --- trunk/src/cpu/amd/dualcore/dualcore.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/cpu/amd/dualcore/dualcore.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,10 +1,5 @@ /* 2004.12 yhlu add dual core support */ - -#ifndef SET_NB_CFG_54 - #define SET_NB_CFG_54 1 -#endif - #include "cpu/amd/dualcore/dualcore_id.c" #include <pc80/mc146818rtc.h> #if CONFIG_HAVE_OPTION_TABLE @@ -20,7 +15,6 @@ return dword; } -#if SET_NB_CFG_54 == 1 static inline uint8_t set_apicid_cpuid_lo(void) { #if CONFIG_K8_REV_F_SUPPORT == 0 @@ -35,11 +29,6 @@ return 1; } -#else - -static inline void set_apicid_cpuid_lo(void) { } - -#endif static inline void real_start_other_core(unsigned nodeid) { Modified: trunk/src/cpu/amd/quadcore/quadcore.c ============================================================================== --- trunk/src/cpu/amd/quadcore/quadcore.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/cpu/amd/quadcore/quadcore.c Thu Nov 18 01:11:32 2010 (r6086) @@ -24,10 +24,6 @@ #include "option_table.h" #endif -#ifndef SET_NB_CFG_54 - #define SET_NB_CFG_54 1 -#endif - #include "cpu/amd/quadcore/quadcore_id.c" static u32 get_core_num_in_bsp(u32 nodeid) @@ -43,7 +39,6 @@ return dword; } -#if SET_NB_CFG_54 == 1 static u8 set_apicid_cpuid_lo(void) { // set the NB_CFG[54]=1; why the OS will be happy with that ??? @@ -54,12 +49,6 @@ return 1; } -#else - -static void set_apicid_cpuid_lo(void) { } - -#endif - static void real_start_other_core(u32 nodeid, u32 cores) { Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -17,10 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #define RC0 (6<<8) #define RC1 (7<<8) Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/amd/mahogany/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -17,10 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #define RC0 (6<<8) #define RC1 (7<<8) Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -21,8 +21,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define SET_NB_CFG_54 1 - //used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 Modified: trunk/src/mainboard/amd/pistachio/romstage.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/amd/pistachio/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -17,10 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #define DIMM0 0x50 #define DIMM1 0x51 Modified: trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/amd/serengeti_cheetah/ap_romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,8 +1,6 @@ #define ASSEMBLY 1 #define __PRE_RAM__ -#define SET_NB_CFG_54 1 - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,5 +1,3 @@ -#define SET_NB_CFG_54 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -21,8 +21,6 @@ //#define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define SET_NB_CFG_54 1 - //used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -21,8 +21,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define SET_NB_CFG_54 1 - //used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 Modified: trunk/src/mainboard/arima/hdama/romstage.c ============================================================================== --- trunk/src/mainboard/arima/hdama/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/arima/hdama/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -73,9 +73,6 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -18,10 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #define RC0 (6<<8) #define RC1 (7<<8) Modified: trunk/src/mainboard/asus/a8n_e/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/asus/a8n_e/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -24,10 +24,6 @@ /* Used by it8712f_enable_serial(). */ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) -#if CONFIG_LOGICAL_CPUS == 1 -#define SET_NB_CFG_54 1 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/asus/m4a785-m/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -21,8 +21,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define SET_NB_CFG_54 1 - //used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 Modified: trunk/src/mainboard/broadcom/blast/romstage.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/broadcom/blast/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,8 +1,3 @@ - -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/ap_romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -24,8 +24,6 @@ #define ASSEMBLY 1 #define __PRE_RAM__ -#define SET_NB_CFG_54 1 - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -21,10 +21,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif Modified: trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/gigabyte/m57sli/ap_romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -22,8 +22,6 @@ #define ASSEMBLY 1 #define __PRE_RAM__ -#define SET_NB_CFG_54 1 - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -19,10 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -21,8 +21,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define SET_NB_CFG_54 1 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -21,8 +21,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define SET_NB_CFG_54 1 - //used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 Modified: trunk/src/mainboard/hp/dl145_g1/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g1/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/hp/dl145_g1/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,8 +1,3 @@ - -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -25,10 +25,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif Modified: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -28,11 +28,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 1 - -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/ibm/e325/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e325/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/ibm/e325/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,4 +1,3 @@ - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -70,9 +69,6 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/ibm/e326/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e326/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/ibm/e326/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,4 +1,3 @@ - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -70,9 +69,6 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -21,10 +21,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define SET_NB_CFG_54 1 - -//used by raminit - //used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,5 +1,3 @@ -#define SET_NB_CFG_54 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,5 +1,3 @@ -#define SET_NB_CFG_54 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,5 +1,3 @@ -#define SET_NB_CFG_54 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/jetway/pa78vm5/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -22,8 +22,6 @@ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ -#define SET_NB_CFG_54 1 - //used by incoherent_ht #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/kontron/kt690/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -18,10 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #define RC0 (6<<8) #define RC1 (7<<8) Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/msi/ms7135/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -24,10 +24,6 @@ #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) -#if CONFIG_LOGICAL_CPUS == 1 -#define SET_NB_CFG_54 1 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/msi/ms7260/ap_romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/ap_romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/msi/ms7260/ap_romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -23,7 +23,6 @@ #define __PRE_RAM__ -#define SET_NB_CFG_54 1 /* Used by RAM init. */ #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/msi/ms7260/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -20,10 +20,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_LOGICAL_CPUS == 1 -#define SET_NB_CFG_54 1 -#endif - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/msi/ms9185/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -23,8 +23,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SET_NB_CFG_54 1 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/msi/ms9282/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -22,8 +22,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SET_NB_CFG_54 1 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -22,11 +22,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 1 - -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/newisys/khepri/romstage.c ============================================================================== --- trunk/src/mainboard/newisys/khepri/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/newisys/khepri/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -4,7 +4,6 @@ * Additional (C) 2007 coresystems GmbH */ - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -80,9 +79,6 @@ /* newisys khepri does not want the default */ #include "resourcemap.c" -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif #include "cpu/amd/dualcore/dualcore.c" Modified: trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/nvidia/l1_2pvv/ap_romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -22,8 +22,6 @@ #define ASSEMBLY 1 #define __PRE_RAM__ -#define SET_NB_CFG_54 1 - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -19,10 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif Modified: trunk/src/mainboard/sunw/ultra40/romstage.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/sunw/ultra40/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,8 +1,3 @@ -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - - #include <stdint.h> #include <string.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/supermicro/h8dme/ap_romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/ap_romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/supermicro/h8dme/ap_romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -22,8 +22,6 @@ #define ASSEMBLY 1 #define __PRE_RAM__ -#define SET_NB_CFG_54 1 - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -16,10 +16,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif Modified: trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/supermicro/h8dmr/ap_romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -22,8 +22,6 @@ #define ASSEMBLY 1 #define __PRE_RAM__ -#define SET_NB_CFG_54 1 - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -19,10 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -22,11 +22,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 1 - -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -22,11 +22,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 1 - -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -17,10 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #define RC0 (6<<8) #define RC1 (7<<8) Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -17,10 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #define RC0 (6<<8) #define RC1 (7<<8) Modified: trunk/src/mainboard/tyan/s2850/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2850/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/tyan/s2850/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,4 +1,3 @@ - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -67,9 +66,6 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif #include "cpu/amd/dualcore/dualcore.c" Modified: trunk/src/mainboard/tyan/s2875/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2875/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/tyan/s2875/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,4 +1,3 @@ - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -68,9 +67,6 @@ #include "lib/generic_sdram.c" #include "northbridge/amd/amdk8/resourcemap.c" -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif #include "cpu/amd/dualcore/dualcore.c" Modified: trunk/src/mainboard/tyan/s2880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2880/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/tyan/s2880/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,4 +1,3 @@ - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -68,9 +67,6 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif #include "cpu/amd/dualcore/dualcore.c" Modified: trunk/src/mainboard/tyan/s2881/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2881/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/tyan/s2881/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,8 +1,3 @@ - -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/tyan/s2882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2882/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/tyan/s2882/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,4 +1,3 @@ - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -68,9 +67,6 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/tyan/s2885/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2885/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/tyan/s2885/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,4 +1,3 @@ - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -70,9 +69,6 @@ /* tyan does not want the default */ #include "resourcemap.c" -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif #include "cpu/amd/dualcore/dualcore.c" Modified: trunk/src/mainboard/tyan/s2891/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/tyan/s2891/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,7 +1,3 @@ -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/tyan/s2892/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/tyan/s2892/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,8 +1,3 @@ - -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/tyan/s2895/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/tyan/s2895/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,7 +1,3 @@ -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/tyan/s2912/ap_romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/ap_romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/tyan/s2912/ap_romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -22,8 +22,6 @@ #define ASSEMBLY 1 #define __PRE_RAM__ -#define SET_NB_CFG_54 1 - #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #include <stdint.h> Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/tyan/s2912/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -19,10 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -22,11 +22,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 1 - -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif - #include <stdint.h> #include <string.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/tyan/s4880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/tyan/s4880/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,4 +1,3 @@ - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -84,9 +83,6 @@ /* tyan does not want the default */ #include "resourcemap.c" -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif #include "cpu/amd/dualcore/dualcore.c" #define RC0 ((1<<2)<<8) Modified: trunk/src/mainboard/tyan/s4882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4882/romstage.c Wed Nov 17 22:52:15 2010 (r6085) +++ trunk/src/mainboard/tyan/s4882/romstage.c Thu Nov 18 01:11:32 2010 (r6086) @@ -1,4 +1,3 @@ - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -92,9 +91,6 @@ /* tyan does not want the default */ #include "resourcemap.c" -#if CONFIG_LOGICAL_CPUS==1 -#define SET_NB_CFG_54 1 -#endif #include "cpu/amd/dualcore/dualcore.c" #define RC0 ((1<<2)<<8)

1 0

Questions about more AMD related flags
by Patrick Georgi 18 Nov '10

18 Nov '10

Hi, while I opened that can of worms over with QRANK_DIMM_SUPPORT, and people are listening ;-), let me widen the debate some more: SET_NB_CFG_54: 1. It's used in two places (dualcore and quadcore AMD code) 2. There, it's set active if undeclared before 3. All other declarations set this active Any reason to keep this variable at all? If yes, I'll move it to Kconfig, otherwise I'll just drop it. and SET_FIDVID*: These have _very_ weird behaviour, being set to some defaults in the two init_cpus.c (and fidvid.c seems to expect to be included after that one?), and some other settings somewhere else. I tried to untangle that while moving to Kconfig, but didn't quite succeed, so is here anyone who knows which defaults (or dependencies) are correct for each of the following? So far I have: For K8: +config SET_FIDVID + bool + default y if K8_REV_F_SUPPORT + default n + +config SET_FIDVID_CORE0_ONLY + bool + default y + depends on SET_FIDVID + +config SET_FIDVID_CORE_RANGE + bool + default n + depends on SET_FIDVID + +config SET_FIDVID_ONE_BY_ONE + bool + default y + depends on SET_FIDVID + +config SET_FIDVID_DEBUG + bool + default n + depends on SET_FIDVID + +config SET_FIDVID_STORE_AP_APICID_AT_FIRST + bool + default y + depends on SET_FIDVID For Fam10h: +config SET_FIDVID + bool + default y + +config SET_FIDVID_CORE0_ONLY + bool + default n + depends on SET_FIDVID + +config SET_FIDVID_CORE_RANGE + bool + default n + depends on SET_FIDVID + +config SET_FIDVID_DEBUG + bool + default y + depends on SET_FIDVID + +config SET_FIDVID_STORE_AP_APICID_AT_FIRST + bool + default y + depends on SET_FIDVID Corrections welcome Thanks, Patrick

3 5

[commit] r6085 - in trunk/src: cpu/intel/speedstep include/cpu/intel mainboard/intel/eagleheights
by repository service 17 Nov '10

17 Nov '10

Author: oxygene Date: Wed Nov 17 22:52:15 2010 New Revision: 6085 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6085 Log: Move Intel power management related defines to some central location. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Added: trunk/src/include/cpu/intel/acpi.h Modified: trunk/src/cpu/intel/speedstep/acpi.c trunk/src/mainboard/intel/eagleheights/romstage.c Modified: trunk/src/cpu/intel/speedstep/acpi.c ============================================================================== --- trunk/src/cpu/intel/speedstep/acpi.c Wed Nov 17 17:27:06 2010 (r6084) +++ trunk/src/cpu/intel/speedstep/acpi.c Wed Nov 17 22:52:15 2010 (r6085) @@ -25,6 +25,7 @@ #include <arch/acpigen.h> #include <arch/cpu.h> #include <cpu/x86/msr.h> +#include <cpu/intel/acpi.h> #include <device/device.h> // XXX: PSS table values for power consumption are for Merom only @@ -83,8 +84,6 @@ int max_states=8; int busratio_step=2; -#define IA32_PLATFORM_ID 0x017 -#define IA32_PERF_STS 0x198 msr = rdmsr(IA32_PERF_STS); int busratio_min=(msr.lo >> 24) & 0x1f; int busratio_max=(msr.hi >> (40-32)) & 0x1f; Added: trunk/src/include/cpu/intel/acpi.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/include/cpu/intel/acpi.h Wed Nov 17 22:52:15 2010 (r6085) @@ -0,0 +1,5 @@ +#define IA32_PLATFORM_ID 0x017 +#define IA32_PERF_STS 0x198 +#define IA32_PERF_CTL 0x199 +#define MSR_THERM2_CTL 0x19D +#define IA32_MISC_ENABLES 0x1A0 Modified: trunk/src/mainboard/intel/eagleheights/romstage.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/romstage.c Wed Nov 17 17:27:06 2010 (r6084) +++ trunk/src/mainboard/intel/eagleheights/romstage.c Wed Nov 17 22:52:15 2010 (r6085) @@ -33,6 +33,7 @@ #include <console/console.h> #include <cpu/x86/bist.h> +#include <cpu/intel/acpi.h> #include "southbridge/intel/i3100/i3100_early_smbus.c" #include "southbridge/intel/i3100/i3100_early_lpc.c" @@ -44,11 +45,6 @@ #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) -#define IA32_PERF_STS 0x198 -#define IA32_PERF_CTL 0x199 -#define MSR_THERM2_CTL 0x19D -#define IA32_MISC_ENABLES 0x1A0 - /* SATA */ #define SATA_MAP 0x90

1 0

[patch] asus a8v-e (se|deluxe): Add _CRS method to a8v board dsdt PCI0 device definition
by Tobias Diedrich 17 Nov '10

17 Nov '10

Add _CRS method to a8v board dsdt PCI0 device definition swiftgeek noted on irc that his A8V-E Deluxe has trouble booting Linux using filo: 16:42 < SwiftGeek> filo managed to load kernel img + initramfs img from pata device 16:42 < SwiftGeek> but there is no pata device in linux |pci 0000:00:0b.0: no compatible bridge window for [mem 0xd2100000-0xd210ffff pref] |pci 0000:05:00.0: no compatible bridge window for [mem 0xd2000000-0xd201ffff pref] |[...] This is because the _CRS method for the PCI0 device is missing in the dsdt. It happens to work anyway with seabios, because seabios dmi data reports the bios production year as 2007 and Linux automatically disables the use of crs in the pci code then: arch/x86/pci/acpi.c:pci_acpi_crs_quirks(): | if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) && year < 2008) | pci_use_crs = false; But with filo there is no BIOS so it tries to use the non-existing crs data: |PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug |[Firmware Bug]: ACPI: no secondary bus range in _CRS In the end leading to a failed pata_via probe: |pata_via 0000:00:0f.1: device not available (can't reserve [io 0x0000-0x0007]) |pata_via: probe of 0000:00:0f.1 failed with error -22 Booting with the pci=nocrs kernel option works as a workaround, but the right thing to do is adding a _crs method. The simplistic _crs method below should work fine for both Linux and Windows XP. However, for correctness it is needed to exclude some reserved ranges: http://permalink.gmane.org/gmane.linux.bios/63267 (However, contrary to what I stated in that message, APIC space is already accounted for by both Linux and XP and doesn't have to be included in the PNP0C02 device resources, but it doesn't hurt to include it and makes the patch as simple as possible) Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- Index: src/mainboard/asus/a8v-e_se/acpi_tables.c =================================================================== --- src/mainboard/asus/a8v-e_se/acpi_tables.c.orig 2010-11-15 19:09:56.000000000 +0100 +++ src/mainboard/asus/a8v-e_se/acpi_tables.c 2010-11-15 19:11:03.000000000 +0100 @@ -31,6 +31,7 @@ #include <device/pci_ids.h> #include "southbridge/via/vt8237r/vt8237r.h" #include "southbridge/via/k8t890/k8t890.h" +#include "northbridge/amd/amdk8/amdk8_acpi.h" extern const unsigned char AmlCode[]; @@ -81,6 +82,12 @@ return current; } +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + k8acpi_write_vars(); + return (unsigned long) (acpigen_get_current()); +} + unsigned long write_acpi_tables(unsigned long start) { unsigned long current; @@ -91,6 +98,7 @@ acpi_mcfg_t *mcfg; acpi_fadt_t *fadt; acpi_facs_t *facs; + acpi_header_t *ssdt; acpi_header_t *dsdt; /* Align ACPI tables to 16 byte. */ @@ -151,6 +159,14 @@ current += srat->header.length; acpi_add_table(rsdp, srat); + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, "DYNADATA"); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + printk(BIOS_INFO, "ACPI: done.\n"); return current; } Index: src/mainboard/asus/a8v-e_se/dsdt.asl =================================================================== --- src/mainboard/asus/a8v-e_se/dsdt.asl.orig 2010-11-15 19:09:56.000000000 +0100 +++ src/mainboard/asus/a8v-e_se/dsdt.asl 2010-11-15 19:09:57.000000000 +0100 @@ -206,6 +206,58 @@ } } } + + External(TOM1) /* top of memory below 4GB */ + + Method(_CRS, 0) { + Name(TMP, ResourceTemplate() { + WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, + ) + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) + CreateDWordField(TMP, MMIO._BAS, MM1B) + CreateDWordField(TMP, MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) + + Return(TMP) + } } } } Index: src/mainboard/asus/a8v-e_deluxe/acpi_tables.c =================================================================== --- src/mainboard/asus/a8v-e_deluxe/acpi_tables.c.orig 2010-11-15 19:09:56.000000000 +0100 +++ src/mainboard/asus/a8v-e_deluxe/acpi_tables.c 2010-11-15 19:11:03.000000000 +0100 @@ -31,6 +31,7 @@ #include <device/pci_ids.h> #include "southbridge/via/vt8237r/vt8237r.h" #include "southbridge/via/k8t890/k8t890.h" +#include "northbridge/amd/amdk8/amdk8_acpi.h" extern const unsigned char AmlCode[]; @@ -81,6 +82,12 @@ return current; } +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + k8acpi_write_vars(); + return (unsigned long) (acpigen_get_current()); +} + unsigned long write_acpi_tables(unsigned long start) { unsigned long current; @@ -91,6 +98,7 @@ acpi_mcfg_t *mcfg; acpi_fadt_t *fadt; acpi_facs_t *facs; + acpi_header_t *ssdt; acpi_header_t *dsdt; /* Align ACPI tables to 16 byte. */ @@ -151,6 +159,14 @@ current += srat->header.length; acpi_add_table(rsdp, srat); + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, "DYNADATA"); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + printk(BIOS_INFO, "ACPI: done.\n"); return current; } Index: src/mainboard/asus/a8v-e_deluxe/dsdt.asl =================================================================== --- src/mainboard/asus/a8v-e_deluxe/dsdt.asl.orig 2010-11-15 19:09:56.000000000 +0100 +++ src/mainboard/asus/a8v-e_deluxe/dsdt.asl 2010-11-15 19:09:57.000000000 +0100 @@ -206,6 +206,58 @@ } } } + + External(TOM1) /* top of memory below 4GB */ + + Method(_CRS, 0) { + Name(TMP, ResourceTemplate() { + WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, + ) + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) + CreateDWordField(TMP, MMIO._BAS, MM1B) + CreateDWordField(TMP, MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) + + Return(TMP) + } } } }

2 1

[patch 0/7] ASUS M2V support (v4)
by Tobias Diedrich 17 Nov '10

17 Nov '10

Remainder of my ASUS M2V patchqueue, with the already applied parts removed. Rediffed against updated svn. -- Tobias PGP: http://8ef7ddba.uguu.de

4 16

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coreboot November 2010