coreboot November 2010

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[PATCH]Move MCP55 PCIe config from romstage to Kconfig
by Patrick Georgi 21 Nov '10

21 Nov '10

Hi, attached patch is another step towards getting rid of configuration in romstage.cs. Move MCP55_PCI_E_X_* to Kconfig. Any useless values in romstage.cs were not brought over to Kconfig (this applies to all #defines to 4, as that's the default anyway) Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>

2 1

[commit] r6103 - in trunk/src/mainboard: amd/db800 amd/norwich amd/rumba arima/hdama artecgroup/dbe61 asus/a8n_e asus/a8v-e_deluxe asus/a8v-e_se asus/m2v asus/m2v-mx_se bcom/winnetp680 dell/s1850 d...
by repository service 21 Nov '10

21 Nov '10

Author: uwe Date: Sun Nov 21 12:36:03 2010 New Revision: 6103 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6103 Log: Use DIMM0 et al in lots more places instead of hardocding values. The (0xa << 3) expression equals 0x50, i.e. DIMM0. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/amd/db800/romstage.c trunk/src/mainboard/amd/norwich/romstage.c trunk/src/mainboard/amd/rumba/romstage.c trunk/src/mainboard/arima/hdama/romstage.c trunk/src/mainboard/artecgroup/dbe61/romstage.c trunk/src/mainboard/asus/a8n_e/romstage.c trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/asus/m2v-mx_se/romstage.c trunk/src/mainboard/asus/m2v/romstage.c trunk/src/mainboard/bcom/winnetp680/romstage.c trunk/src/mainboard/dell/s1850/romstage.c trunk/src/mainboard/digitallogic/adl855pc/romstage.c trunk/src/mainboard/digitallogic/msm800sev/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/ibm/e325/romstage.c trunk/src/mainboard/ibm/e326/romstage.c trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c trunk/src/mainboard/intel/eagleheights/romstage.c trunk/src/mainboard/intel/jarrell/romstage.c trunk/src/mainboard/intel/mtarvon/romstage.c trunk/src/mainboard/intel/truxton/romstage.c trunk/src/mainboard/intel/xe7501devkit/romstage.c trunk/src/mainboard/jetway/j7f24/romstage.c trunk/src/mainboard/lanner/em8510/romstage.c trunk/src/mainboard/lippert/frontrunner/romstage.c trunk/src/mainboard/lippert/hurricane-lx/romstage.c trunk/src/mainboard/lippert/literunner-lx/romstage.c trunk/src/mainboard/lippert/roadrunner-lx/romstage.c trunk/src/mainboard/lippert/spacerunner-lx/romstage.c trunk/src/mainboard/msi/ms7135/romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/newisys/khepri/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/pcengines/alix1c/romstage.c trunk/src/mainboard/pcengines/alix2d/romstage.c trunk/src/mainboard/sunw/ultra40/romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/x6dai_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c trunk/src/mainboard/traverse/geos/romstage.c trunk/src/mainboard/tyan/s2735/romstage.c trunk/src/mainboard/tyan/s2850/romstage.c trunk/src/mainboard/tyan/s2875/romstage.c trunk/src/mainboard/tyan/s2880/romstage.c trunk/src/mainboard/tyan/s2881/romstage.c trunk/src/mainboard/tyan/s2882/romstage.c trunk/src/mainboard/tyan/s2885/romstage.c trunk/src/mainboard/tyan/s2891/romstage.c trunk/src/mainboard/tyan/s2892/romstage.c trunk/src/mainboard/tyan/s2895/romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/via/epia-cn/romstage.c trunk/src/mainboard/via/epia-n/romstage.c trunk/src/mainboard/via/pc2500e/romstage.c trunk/src/mainboard/via/vt8454c/romstage.c trunk/src/mainboard/winent/pl6064/romstage.c trunk/src/mainboard/wyse/s50/romstage.c Modified: trunk/src/mainboard/amd/db800/romstage.c ============================================================================== --- trunk/src/mainboard/amd/db800/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/amd/db800/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -65,7 +65,7 @@ post_code(0x01); static const struct mem_controller memctrl[] = { - {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} + {.channel0 = {DIMM0, DIMM1}} }; SystemPreInit(); Modified: trunk/src/mainboard/amd/norwich/romstage.c ============================================================================== --- trunk/src/mainboard/amd/norwich/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/amd/norwich/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -62,7 +62,7 @@ post_code(0x01); static const struct mem_controller memctrl[] = { - {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} + {.channel0 = {DIMM0, DIMM1}} }; SystemPreInit(); Modified: trunk/src/mainboard/amd/rumba/romstage.c ============================================================================== --- trunk/src/mainboard/amd/rumba/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/amd/rumba/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -35,7 +35,7 @@ void main(unsigned long bist) { static const struct mem_controller memctrl [] = { - {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} + {.channel0 = {DIMM0, DIMM1}} }; SystemPreInit(); Modified: trunk/src/mainboard/arima/hdama/romstage.c ============================================================================== --- trunk/src/mainboard/arima/hdama/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/arima/hdama/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -24,6 +24,7 @@ #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1) @@ -85,11 +86,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - (0xa<<3)|0, (0xa<<3)|2, 0, 0, - (0xa<<3)|1, (0xa<<3)|3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - (0xa<<3)|4, (0xa<<3)|6, 0, 0, - (0xa<<3)|5, (0xa<<3)|7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, #endif }; Modified: trunk/src/mainboard/artecgroup/dbe61/romstage.c ============================================================================== --- trunk/src/mainboard/artecgroup/dbe61/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/artecgroup/dbe61/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -78,7 +78,7 @@ msr_t msr; static const struct mem_controller memctrl[] = { - {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} + {.channel0 = {DIMM0, DIMM1}} }; SystemPreInit(); Modified: trunk/src/mainboard/asus/a8n_e/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/asus/a8n_e/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -48,6 +48,7 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "cpu/amd/dualcore/dualcore.c" +#include <spd.h> static void memreset(int controllers, const struct mem_controller *ctrl) { @@ -93,11 +94,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, - (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - (0xa << 3) | 4, (0xa << 3) | 6, 0, 0, - (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, #endif }; Modified: trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -46,6 +46,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED) @@ -154,11 +155,11 @@ { static const uint16_t spd_addr[] = { // Node 0 - (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, - (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, // Node 1 - (0xa << 3) | 4, (0xa << 3) | 6, 0, 0, - (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -46,6 +46,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED) @@ -154,11 +155,11 @@ { static const uint16_t spd_addr[] = { // Node 0 - (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, - (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, // Node 1 - (0xa << 3) | 4, (0xa << 3) | 6, 0, 0, - (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -49,6 +49,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO) @@ -128,11 +129,11 @@ { static const uint16_t spd_addr[] = { // Node 0 - (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, - (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, // Node 1 - (0xa << 3) | 4, (0xa << 3) | 6, 0, 0, - (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; Modified: trunk/src/mainboard/asus/m2v/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/asus/m2v/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -49,6 +49,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO) @@ -231,11 +232,11 @@ { static const uint16_t spd_addr[] = { // Node 0 - (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, - (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, // Node 1 - (0xa << 3) | 4, (0xa << 3) | 6, 0, 0, - (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, }; unsigned bsp_apicid = 0; int needs_reset = 0; Modified: trunk/src/mainboard/bcom/winnetp680/romstage.c ============================================================================== --- trunk/src/mainboard/bcom/winnetp680/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/bcom/winnetp680/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -32,6 +32,7 @@ #include "pc80/udelay_io.c" #include "lib/delay.c" #include <lib.h> +#include <spd.h> #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "superio/winbond/w83697hf/w83697hf_early_serial.c" #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) Modified: trunk/src/mainboard/dell/s1850/romstage.c ============================================================================== --- trunk/src/mainboard/dell/s1850/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/dell/s1850/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -19,6 +19,7 @@ #include "s1850_fixups.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" +#include <spd.h> #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC8374_SP1) @@ -149,10 +150,7 @@ u16 w; u32 l; int do_reset; - /* - * - * - */ + static const struct mem_controller mch[] = { { .node_id = 0, @@ -164,8 +162,8 @@ */ /* the wiring on this part is really messed up */ /* this is my best guess so far */ - .channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, }, - .channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, }, + .channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, }, + .channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, }, } }; Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -15,6 +15,7 @@ #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" +#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -32,7 +33,7 @@ static const struct mem_controller memctrl[] = { { .d0 = PCI_DEV(0, 0, 1), - .channel0 = { (0xa<<3)|0, 0 }, + .channel0 = { DIMM0, 0 }, }, }; Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm800sev/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -45,7 +45,7 @@ post_code(0x01); static const struct mem_controller memctrl [] = { - {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} + {.channel0 = {DIMM0, DIMM1}} }; SystemPreInit(); Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -37,6 +37,7 @@ #include <console/console.h> #include <usbdebug.h> +#include <spd.h> #include <cpu/amd/model_fxx_rev.h> @@ -134,11 +135,11 @@ { static const uint16_t spd_addr [] = { // Node 0 - (0xa<<3)|0, (0xa<<3)|2, 0, 0, - (0xa<<3)|1, (0xa<<3)|3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, // Node 1 - (0xa<<3)|4, (0xa<<3)|6, 0, 0, - (0xa<<3)|5, (0xa<<3)|7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -35,6 +35,7 @@ #include <console/console.h> #include <usbdebug.h> +#include <spd.h> #include <cpu/amd/model_fxx_rev.h> @@ -131,11 +132,11 @@ { static const uint16_t spd_addr [] = { // Node 0 - (0xa<<3)|0, (0xa<<3)|2, 0, 0, - (0xa<<3)|1, (0xa<<3)|3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, // Node 1 - (0xa<<3)|4, (0xa<<3)|6, 0, 0, - (0xa<<3)|5, (0xa<<3)|7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -146,8 +146,8 @@ { static const uint16_t spd_addr[] = { // first node - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, // second node DIMM4, DIMM6, 0, 0, Modified: trunk/src/mainboard/ibm/e325/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e325/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/ibm/e325/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -25,6 +25,7 @@ #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1) @@ -87,8 +88,8 @@ .f1 = PCI_DEV(0, 0x18, 1), .f2 = PCI_DEV(0, 0x18, 2), .f3 = PCI_DEV(0, 0x18, 3), - .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, - .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, + .channel0 = { DIMM0, DIMM2, 0, 0 }, + .channel1 = { DIMM1, DIMM3, 0, 0 }, }, #if CONFIG_MAX_PHYSICAL_CPUS > 1 { @@ -97,8 +98,8 @@ .f1 = PCI_DEV(0, 0x19, 1), .f2 = PCI_DEV(0, 0x19, 2), .f3 = PCI_DEV(0, 0x19, 3), - .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, - .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, + .channel0 = { DIMM4, DIMM6, 0, 0 }, + .channel1 = { DIMM5, DIMM7, 0, 0 }, }, #endif }; Modified: trunk/src/mainboard/ibm/e326/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e326/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/ibm/e326/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -29,6 +29,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1) #include "southbridge/amd/amd8111/amd8111_early_ctrl.c" +#include <spd.h> static void memreset_setup(void) { @@ -87,8 +88,8 @@ .f1 = PCI_DEV(0, 0x18, 1), .f2 = PCI_DEV(0, 0x18, 2), .f3 = PCI_DEV(0, 0x18, 3), - .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, - .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, + .channel0 = { DIMM0, DIMM2, 0, 0 }, + .channel1 = { DIMM1, DIMM3, 0, 0 }, }, #if CONFIG_MAX_PHYSICAL_CPUS > 1 { @@ -97,8 +98,8 @@ .f1 = PCI_DEV(0, 0x19, 1), .f2 = PCI_DEV(0, 0x19, 2), .f3 = PCI_DEV(0, 0x19, 3), - .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, - .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, + .channel0 = { DIMM4, DIMM6, 0, 0 }, + .channel1 = { DIMM5, DIMM7, 0, 0 }, }, #endif }; Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -69,7 +69,7 @@ post_code(0x01); static const struct mem_controller memctrl[] = { - {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} + {.channel0 = {DIMM0, DIMM1}} }; SystemPreInit(); Modified: trunk/src/mainboard/intel/eagleheights/romstage.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/intel/eagleheights/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -78,6 +78,7 @@ #include "lib/generic_sdram.c" #include "northbridge/intel/i3100/reset_test.c" #include "debug.c" +#include <spd.h> #define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1) @@ -136,8 +137,8 @@ .f1 = PCI_DEV(0, 0x00, 1), .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), - .channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 }, - .channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 }, + .channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 }, + .channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 }, } }; Modified: trunk/src/mainboard/intel/jarrell/romstage.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/intel/jarrell/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -19,6 +19,7 @@ #include "superio/nsc/pc87427/pc87427_early_init.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" +#include <spd.h> #define SIO_GPIO_BASE 0x680 #define SIO_XBUS_BASE 0x4880 @@ -41,10 +42,6 @@ static void main(unsigned long bist) { - /* - * - * - */ static const struct mem_controller mch[] = { { .node_id = 0, @@ -54,8 +51,8 @@ .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), */ - .channel0 = { (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, 0 }, - .channel1 = { (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, 0 }, + .channel0 = { DIMM2, DIMM1, DIMM0, 0 }, + .channel1 = { DIMM6, DIMM5, DIMM4, 0 }, } }; Modified: trunk/src/mainboard/intel/mtarvon/romstage.c ============================================================================== --- trunk/src/mainboard/intel/mtarvon/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/intel/mtarvon/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -36,6 +36,7 @@ #include "superio/intel/i3100/i3100_early_serial.c" #include "northbridge/intel/i3100/memory_initialized.c" #include "cpu/x86/bist.h" +#include <spd.h> #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) @@ -64,8 +65,8 @@ .f1 = PCI_DEV(0, 0x00, 1), .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), - .channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 }, - .channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 }, + .channel0 = { DIMM3, DIMM2, DIMM1, DIMM0 }, + .channel1 = { DIMM7, DIMM6, DIMM5, DIMM4 }, } }; Modified: trunk/src/mainboard/intel/truxton/romstage.c ============================================================================== --- trunk/src/mainboard/intel/truxton/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/intel/truxton/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -61,7 +61,7 @@ { .node_id = 0, .f0 = PCI_DEV(0, 0x00, 0), - .channel0 = { (0xa<<3)|2, (0xa<<3)|3 }, + .channel0 = { DIMM2, DIMM3 }, } }; Modified: trunk/src/mainboard/intel/xe7501devkit/romstage.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/intel/xe7501devkit/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -16,9 +16,9 @@ #include "superio/smsc/lpc47b272/lpc47b272_early_serial.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" +#include <spd.h> -#define SUPERIO_PORT 0x2e -#define SERIAL_DEV PNP_DEV(SUPERIO_PORT, LPC47B272_SP1) +#define SERIAL_DEV PNP_DEV(0x2e, LPC47B272_SP1) static void hard_reset(void) { @@ -41,8 +41,8 @@ { .d0 = PCI_DEV(0, 0, 0), .d0f1 = PCI_DEV(0, 0, 1), - .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 }, - .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 }, + .channel0 = { DIMM0, DIMM1, DIMM2, 0 }, + .channel1 = { DIMM4, DIMM5, DIMM6, 0 }, }, }; Modified: trunk/src/mainboard/jetway/j7f24/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/j7f24/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/jetway/j7f24/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -34,6 +34,7 @@ #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "superio/fintek/f71805f/f71805f_early_serial.c" #include <lib.h> +#include <spd.h> #if CONFIG_TTYS0_BASE == 0x2f8 #define SERIAL_DEV PNP_DEV(0x2e, F71805F_SP2) Modified: trunk/src/mainboard/lanner/em8510/romstage.c ============================================================================== --- trunk/src/mainboard/lanner/em8510/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/lanner/em8510/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -27,6 +27,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> +#include <spd.h> #include "pc80/udelay_io.c" #include <pc80/mc146818rtc.h> #include <console/console.h> @@ -54,7 +55,7 @@ static const struct mem_controller memctrl[] = { { .d0 = PCI_DEV(0, 0, 1), - .channel0 = { (0xa<<3)|0, 0 }, + .channel0 = { DIMM0, 0 }, }, }; Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/lippert/frontrunner/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -11,7 +11,6 @@ #include <cpu/amd/gx2def.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5535/cs5535.h" -#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -76,7 +75,7 @@ void main(unsigned long bist) { static const struct mem_controller memctrl [] = { - {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} + {.channel0 = {DIMM0, DIMM1}} }; unsigned char temp; SystemPreInit(); Modified: trunk/src/mainboard/lippert/hurricane-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/hurricane-lx/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/lippert/hurricane-lx/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -122,7 +122,7 @@ post_code(0x01); static const struct mem_controller memctrl[] = { - {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} + {.channel0 = {DIMM0, DIMM1}} }; SystemPreInit(); Modified: trunk/src/mainboard/lippert/literunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/literunner-lx/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/lippert/literunner-lx/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -34,7 +34,6 @@ #include <cpu/amd/lxdef.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" -#include <spd.h> #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" @@ -166,7 +165,7 @@ post_code(0x01); static const struct mem_controller memctrl[] = { - {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} + {.channel0 = {DIMM0, DIMM1}} }; SystemPreInit(); Modified: trunk/src/mainboard/lippert/roadrunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -97,7 +97,7 @@ post_code(0x01); static const struct mem_controller memctrl[] = { - {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} + {.channel0 = {DIMM0, DIMM1}} }; SystemPreInit(); Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -34,7 +34,6 @@ #include <cpu/amd/lxdef.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" -#include <spd.h> #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" @@ -163,7 +162,7 @@ post_code(0x01); static const struct mem_controller memctrl[] = { - {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} + {.channel0 = {DIMM0, DIMM1}} }; SystemPreInit(); Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/msi/ms7135/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -49,6 +49,7 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "cpu/amd/dualcore/dualcore.c" +#include <spd.h> static void memreset(int controllers, const struct mem_controller *ctrl) { @@ -95,7 +96,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - (0xa << 3) | 0, (0xa << 3) | 1, 0, 0, + DIMM0, DIMM1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/msi/ms7260/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -42,6 +42,7 @@ #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" #include <lib.h> +#include <spd.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" @@ -117,11 +118,11 @@ { static const uint16_t spd_addr[] = { // Node 0 - (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, - (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, // Node 1 - (0xa << 3) | 4, (0xa << 3) | 6, 0, 0, - (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/msi/ms9185/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -109,9 +109,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - //first node - RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, - RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7, + //first node + RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, + RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7, //second node RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/msi/ms9282/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -45,6 +45,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" +#include <spd.h> #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -132,11 +133,11 @@ { static const uint16_t spd_addr[] = { // Node 0 - RC0|(0xa<<3)|0, RC0|(0xa<<3)|2, RC0|(0xa<<3)|4, RC0|(0xa<<3)|6, - RC0|(0xa<<3)|1, RC0|(0xa<<3)|3, RC0|(0xa<<3)|5, RC0|(0xa<<3)|7, + RC0|DIMM0, RC0|DIMM2, RC0|DIMM4, RC0|DIMM6, + RC0|DIMM1, RC0|DIMM3, RC0|DIMM5, RC0|DIMM7, // node 1 - RC1|(0xa<<3)|0, RC1|(0xa<<3)|2, RC1|(0xa<<3)|4, RC1|(0xa<<3)|6, - RC1|(0xa<<3)|1, RC1|(0xa<<3)|3, RC1|(0xa<<3)|5, RC1|(0xa<<3)|7, + RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, + RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, }; unsigned bsp_apicid = 0; Modified: trunk/src/mainboard/newisys/khepri/romstage.c ============================================================================== --- trunk/src/mainboard/newisys/khepri/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/newisys/khepri/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -14,6 +14,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> +#include <spd.h> #include <cpu/amd/model_fxx_rev.h> @@ -93,11 +94,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - (0xa<<3)|0, (0xa<<3)|2, 0, 0, - (0xa<<3)|1, (0xa<<3)|3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - (0xa<<3)|4, (0xa<<3)|6, 0, 0, - (0xa<<3)|5, (0xa<<3)|7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, #endif }; Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -36,6 +36,7 @@ #include <console/console.h> #include <usbdebug.h> #include <lib.h> +#include <spd.h> #include <cpu/amd/model_fxx_rev.h> @@ -132,11 +133,11 @@ { static const uint16_t spd_addr [] = { // Node 0 - (0xa<<3)|0, (0xa<<3)|2, 0, 0, - (0xa<<3)|1, (0xa<<3)|3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, // Node 1 - (0xa<<3)|4, (0xa<<3)|6, 0, 0, - (0xa<<3)|5, (0xa<<3)|7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/pcengines/alix1c/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -32,7 +32,6 @@ #include <cpu/amd/lxdef.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" -#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) Modified: trunk/src/mainboard/pcengines/alix2d/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix2d/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/pcengines/alix2d/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -32,7 +32,6 @@ #include <cpu/amd/lxdef.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" -#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) Modified: trunk/src/mainboard/sunw/ultra40/romstage.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/sunw/ultra40/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -8,6 +8,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> +#include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -117,11 +118,11 @@ { static const uint16_t spd_addr [] = { // Node 0 - (0xa<<3)|0, (0xa<<3)|2, 0, 0, - (0xa<<3)|1, (0xa<<3)|3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, // Node 1 - (0xa<<3)|4, (0xa<<3)|6, 0, 0, - (0xa<<3)|5, (0xa<<3)|7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, }; int needs_reset; Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -32,6 +32,7 @@ #include <console/console.h> #include <lib.h> +#include <spd.h> #include <cpu/amd/model_fxx_rev.h> @@ -188,15 +189,15 @@ */ static const uint16_t spd_addr[] = { // Node 0 - RC0 | (0xa << 3) | 0, RC0 | (0xa << 3) | 2, - RC0 | (0xa << 3) | 4, RC0 | (0xa << 3) | 6, - RC0 | (0xa << 3) | 1, RC0 | (0xa << 3) | 3, - RC0 | (0xa << 3) | 5, RC0 | (0xa << 3) | 7, + RC0 | DIMM0, RC0 | DIMM2, + RC0 | DIMM4, RC0 | DIMM6, + RC0 | DIMM1, RC0 | DIMM3, + RC0 | DIMM5, RC0 | DIMM7, // Node 1 - RC1 | (0xa << 3) | 0, RC1 | (0xa << 3) | 2, - RC1 | (0xa << 3) | 4, RC1 | (0xa << 3) | 6, - RC1 | (0xa << 3) | 1, RC1 | (0xa << 3) | 3, - RC1 | (0xa << 3) | 5, RC1 | (0xa << 3) | 7, + RC1 | DIMM0, RC1 | DIMM2, + RC1 | DIMM4, RC1 | DIMM6, + RC1 | DIMM1, RC1 | DIMM3, + RC1 | DIMM5, RC1 | DIMM7, }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -35,6 +35,7 @@ #include <console/console.h> #include <lib.h> +#include <spd.h> #include <cpu/amd/model_fxx_rev.h> @@ -124,11 +125,11 @@ { static const uint16_t spd_addr [] = { // Node 0 - (0xa<<3)|0, (0xa<<3)|2, 0, 0, - (0xa<<3)|1, (0xa<<3)|3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, // Node 1 - (0xa<<3)|4, (0xa<<3)|6, 0, 0, - (0xa<<3)|5, (0xa<<3)|7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -20,6 +20,7 @@ #include "superio/winbond/w83627hf/w83627hf_early_init.c" #include "northbridge/intel/e7525/memory_initialized.c" #include "cpu/x86/bist.h" +#include <spd.h> #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) @@ -44,10 +45,6 @@ static void main(unsigned long bist) { - /* - * - * - */ static const struct mem_controller mch[] = { { .node_id = 0, @@ -55,8 +52,8 @@ .f1 = PCI_DEV(0, 0x00, 1), .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), - .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, }, - .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, }, + .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, }, + .channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, }, } }; Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -21,6 +21,7 @@ #include "superio/winbond/w83627hf/w83627hf_early_init.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" +#include <spd.h> #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) @@ -58,8 +59,8 @@ .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), */ - .channel0 = {(0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, (0xa<<3)|3, }, - .channel1 = {(0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, (0xa<<3)|7, }, + .channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, }, + .channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, }, } }; Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -19,6 +19,7 @@ #include "superio/nsc/pc87427/pc87427_early_init.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" +#include <spd.h> #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, PC87427_SP2) @@ -43,10 +44,6 @@ static void main(unsigned long bist) { - /* - * - * - */ static const struct mem_controller mch[] = { { .node_id = 0, @@ -56,8 +53,8 @@ .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), */ - .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, }, - .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, }, + .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, }, + .channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, }, } }; Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -19,6 +19,7 @@ #include "superio/winbond/w83627hf/w83627hf_early_init.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" +#include <spd.h> #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) @@ -57,8 +58,8 @@ .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), */ - .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, }, - .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, }, + .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, }, + .channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, }, } }; Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -19,6 +19,7 @@ #include "superio/winbond/w83627hf/w83627hf_early_init.c" #include "northbridge/intel/e7520/memory_initialized.c" #include "cpu/x86/bist.h" +#include <spd.h> #define CONSOLE_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define HIDDEN_SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP2) @@ -44,10 +45,6 @@ static void main(unsigned long bist) { - /* - * - * - */ static const struct mem_controller mch[] = { { .node_id = 0, @@ -57,8 +54,8 @@ .f2 = PCI_DEV(0, 0x00, 2), .f3 = PCI_DEV(0, 0x00, 3), */ - .channel0 = {(0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0, }, - .channel1 = {(0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4, }, + .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, }, + .channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, }, } }; Modified: trunk/src/mainboard/traverse/geos/romstage.c ============================================================================== --- trunk/src/mainboard/traverse/geos/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/traverse/geos/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -63,7 +63,7 @@ post_code(0x01); static const struct mem_controller memctrl[] = { - {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} + {.channel0 = {DIMM0, DIMM1}} }; SystemPreInit(); Modified: trunk/src/mainboard/tyan/s2735/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/tyan/s2735/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -9,6 +9,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> +#include <spd.h> #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7501/raminit.h" @@ -44,8 +45,8 @@ { .d0 = PCI_DEV(0, 0, 0), .d0f1 = PCI_DEV(0, 0, 1), - .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 }, - .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 }, + .channel0 = { DIMM0, DIMM1, DIMM2, 0 }, + .channel1 = { DIMM4, DIMM5, DIMM6, 0 }, }, }; Modified: trunk/src/mainboard/tyan/s2850/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2850/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/tyan/s2850/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -9,6 +9,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> +#include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -86,8 +87,8 @@ .f1 = PCI_DEV(0, 0x18, 1), .f2 = PCI_DEV(0, 0x18, 2), .f3 = PCI_DEV(0, 0x18, 3), - .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, - .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, + .channel0 = { DIMM0, DIMM2, 0, 0 }, + .channel1 = { DIMM1, DIMM3, 0, 0 }, }, }; Modified: trunk/src/mainboard/tyan/s2875/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2875/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/tyan/s2875/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -9,6 +9,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> +#include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -87,8 +88,8 @@ .f1 = PCI_DEV(0, 0x18, 1), .f2 = PCI_DEV(0, 0x18, 2), .f3 = PCI_DEV(0, 0x18, 3), - .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, - .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, + .channel0 = { DIMM0, DIMM2, 0, 0 }, + .channel1 = { DIMM1, DIMM3, 0, 0 }, }, #if CONFIG_MAX_PHYSICAL_CPUS > 1 { @@ -97,8 +98,8 @@ .f1 = PCI_DEV(0, 0x19, 1), .f2 = PCI_DEV(0, 0x19, 2), .f3 = PCI_DEV(0, 0x19, 3), - .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, - .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, + .channel0 = { DIMM4, DIMM6, 0, 0 }, + .channel1 = { DIMM5, DIMM7, 0, 0 }, }, #endif }; Modified: trunk/src/mainboard/tyan/s2880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2880/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/tyan/s2880/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -9,6 +9,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> +#include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -87,8 +88,8 @@ .f1 = PCI_DEV(0, 0x18, 1), .f2 = PCI_DEV(0, 0x18, 2), .f3 = PCI_DEV(0, 0x18, 3), - .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, - .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, + .channel0 = { DIMM0, DIMM2, 0, 0 }, + .channel1 = { DIMM1, DIMM3, 0, 0 }, }, #if CONFIG_MAX_PHYSICAL_CPUS > 1 { @@ -97,8 +98,8 @@ .f1 = PCI_DEV(0, 0x19, 1), .f2 = PCI_DEV(0, 0x19, 2), .f3 = PCI_DEV(0, 0x19, 3), - .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, - .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, + .channel0 = { DIMM4, DIMM6, 0, 0 }, + .channel1 = { DIMM5, DIMM7, 0, 0 }, }, #endif }; Modified: trunk/src/mainboard/tyan/s2881/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2881/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/tyan/s2881/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -8,6 +8,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> +#include <spd.h> #include <cpu/amd/model_fxx_rev.h> @@ -80,11 +81,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - (0xa<<3)|0, (0xa<<3)|2, 0, 0, - (0xa<<3)|1, (0xa<<3)|3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - (0xa<<3)|4, (0xa<<3)|6, 0, 0, - (0xa<<3)|5, (0xa<<3)|7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, #endif }; Modified: trunk/src/mainboard/tyan/s2882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2882/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/tyan/s2882/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -9,6 +9,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> +#include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -85,8 +86,8 @@ .f1 = PCI_DEV(0, 0x18, 1), .f2 = PCI_DEV(0, 0x18, 2), .f3 = PCI_DEV(0, 0x18, 3), - .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 }, - .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 }, + .channel0 = { DIMM0, DIMM2, 0, 0 }, + .channel1 = { DIMM1, DIMM3, 0, 0 }, }, #if CONFIG_MAX_PHYSICAL_CPUS > 1 { @@ -95,8 +96,8 @@ .f1 = PCI_DEV(0, 0x19, 1), .f2 = PCI_DEV(0, 0x19, 2), .f3 = PCI_DEV(0, 0x19, 3), - .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 }, - .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 }, + .channel0 = { DIMM4, DIMM6, 0, 0 }, + .channel1 = { DIMM5, DIMM7, 0, 0 }, }, #endif }; Modified: trunk/src/mainboard/tyan/s2885/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2885/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/tyan/s2885/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -8,6 +8,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> +#include <spd.h> #include <cpu/amd/model_fxx_rev.h> @@ -83,11 +84,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - (0xa<<3)|0, (0xa<<3)|2, 0, 0, - (0xa<<3)|1, (0xa<<3)|3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - (0xa<<3)|4, (0xa<<3)|6, 0, 0, - (0xa<<3)|5, (0xa<<3)|7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, #endif }; Modified: trunk/src/mainboard/tyan/s2891/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/tyan/s2891/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -8,6 +8,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> +#include <spd.h> #include <cpu/amd/model_fxx_rev.h> @@ -93,11 +94,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - (0xa<<3)|0, (0xa<<3)|2, 0, 0, - (0xa<<3)|1, (0xa<<3)|3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - (0xa<<3)|4, (0xa<<3)|6, 0, 0, - (0xa<<3)|5, (0xa<<3)|7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, #endif }; Modified: trunk/src/mainboard/tyan/s2892/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/tyan/s2892/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -9,6 +9,7 @@ #include <console/console.h> #include <lib.h> +#include <spd.h> #include <cpu/amd/model_fxx_rev.h> @@ -88,11 +89,11 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - (0xa<<3)|0, (0xa<<3)|2, 0, 0, - (0xa<<3)|1, (0xa<<3)|3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - (0xa<<3)|4, (0xa<<3)|6, 0, 0, - (0xa<<3)|5, (0xa<<3)|7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, #endif }; Modified: trunk/src/mainboard/tyan/s2895/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/tyan/s2895/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -8,6 +8,7 @@ #include <pc80/mc146818rtc.h> #include <console/console.h> #include <lib.h> +#include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/nvidia/ck804/ck804_early_smbus.h" @@ -112,10 +113,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const u16 spd_addr [] = { - (0xa<<3)|0, (0xa<<3)|2, 0, 0, - (0xa<<3)|1, (0xa<<3)|3, 0, 0, - (0xa<<3)|4, (0xa<<3)|6, 0, 0, - (0xa<<3)|5, (0xa<<3)|7, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, }; int needs_reset; Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/tyan/s2912/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -35,6 +35,7 @@ #include <console/console.h> #include <lib.h> +#include <spd.h> #include <usbdebug.h> #include <cpu/amd/model_fxx_rev.h> @@ -130,11 +131,11 @@ { static const uint16_t spd_addr [] = { // Node 0 - (0xa<<3)|0, (0xa<<3)|2, 0, 0, - (0xa<<3)|1, (0xa<<3)|3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, // Node 1 - (0xa<<3)|4, (0xa<<3)|6, 0, 0, - (0xa<<3)|5, (0xa<<3)|7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE Modified: trunk/src/mainboard/via/epia-cn/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-cn/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/via/epia-cn/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -34,6 +34,7 @@ #include "lib/delay.c" #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "southbridge/via/vt8235/vt8235_early_serial.c" +#include <spd.h> static inline int spd_read_byte(unsigned device, unsigned address) { Modified: trunk/src/mainboard/via/epia-n/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-n/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/via/epia-n/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -36,13 +36,10 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "superio/winbond/w83697hf/w83697hf_early_serial.c" +#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) -/* - * NOOB :: - * d0f0 - Device 0 Function 0 etc. - */ static const struct mem_controller ctrl = { .d0f0 = 0x0000, .d0f2 = 0x2000, Modified: trunk/src/mainboard/via/pc2500e/romstage.c ============================================================================== --- trunk/src/mainboard/via/pc2500e/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/via/pc2500e/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -34,6 +34,7 @@ #include "lib/delay.c" #include "southbridge/via/vt8237r/vt8237r_early_smbus.c" #include "superio/ite/it8716f/it8716f_early_serial.c" +#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) Modified: trunk/src/mainboard/via/vt8454c/romstage.c ============================================================================== --- trunk/src/mainboard/via/vt8454c/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/via/vt8454c/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -39,6 +39,7 @@ #include "northbridge/via/cx700/cx700_early_serial.c" #include "northbridge/via/cx700/raminit.c" +#include <spd.h> static void enable_mainboard_devices(void) { Modified: trunk/src/mainboard/winent/pl6064/romstage.c ============================================================================== --- trunk/src/mainboard/winent/pl6064/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/winent/pl6064/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -67,7 +67,7 @@ post_code(0x01); static const struct mem_controller memctrl[] = { - {.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}} + {.channel0 = {DIMM0, DIMM1}} }; SystemPreInit(); Modified: trunk/src/mainboard/wyse/s50/romstage.c ============================================================================== --- trunk/src/mainboard/wyse/s50/romstage.c Sun Nov 21 11:26:04 2010 (r6102) +++ trunk/src/mainboard/wyse/s50/romstage.c Sun Nov 21 12:36:03 2010 (r6103) @@ -54,7 +54,7 @@ void main(unsigned long bist) { static const struct mem_controller memctrl [] = { - {.channel0 = {(0xa<<3)|0, (0xa<<3)|1}} + {.channel0 = {DIMM0, DIMM1}} }; SystemPreInit();

1 0

build service results for r6102
by repository service 21 Nov '10

21 Nov '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 6102 to the coreboot repository. This caused the following changes: Change Log: Build fix. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of tyan:s2912_fam10 has been fixed If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r6102 - trunk/src/mainboard/tyan/s2912_fam10
by repository service 21 Nov '10

21 Nov '10

Author: uwe Date: Sun Nov 21 11:26:04 2010 New Revision: 6102 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6102 Log: Build fix. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Sat Nov 20 21:36:40 2010 (r6101) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Sun Nov 21 11:26:04 2010 (r6102) @@ -128,6 +128,7 @@ //second node RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, #endif +}; void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) {

1 0

build service results for r6101
by repository service 20 Nov '10

20 Nov '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 6101 to the coreboot repository. This caused the following changes: Change Log: Merge all spd_addr.h into the resp. romstage.c files. Except for one instance the spd_addr.h were now very tiny, there's not much point in keeping that stuff in an extra file. The only user of those files is the romstage.c file anyway. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of tyan:s2912_fam10 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6101&device=s2912_fam10&ve… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r6101 - in trunk/src/mainboard: amd/serengeti_cheetah_fam10 hp/dl165_g6_fam10 msi/ms9652_fam10 supermicro/h8dmr_fam10 supermicro/h8qme_fam10 tyan/s2912_fam10
by repository service 20 Nov '10

20 Nov '10

Author: uwe Date: Sat Nov 20 21:36:40 2010 New Revision: 6101 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6101 Log: Merge all spd_addr.h into the resp. romstage.c files. Except for one instance the spd_addr.h were now very tiny, there's not much point in keeping that stuff in an extra file. The only user of those files is the romstage.c file anyway. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Deleted: trunk/src/mainboard/amd/serengeti_cheetah_fam10/spd_addr.h trunk/src/mainboard/hp/dl165_g6_fam10/spd_addr.h trunk/src/mainboard/msi/ms9652_fam10/spd_addr.h trunk/src/mainboard/supermicro/h8dmr_fam10/spd_addr.h trunk/src/mainboard/supermicro/h8qme_fam10/spd_addr.h trunk/src/mainboard/tyan/s2912_fam10/spd_addr.h Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Sat Nov 20 21:23:08 2010 (r6100) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Sat Nov 20 21:36:40 2010 (r6101) @@ -39,6 +39,7 @@ #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" #include <lib.h> +#include <spd.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdfam10/reset_test.c" @@ -105,7 +106,98 @@ #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" -#include "spd_addr.h" +static const u8 spd_addr[] = { + //first node + RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + //second node + RC01, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, +#endif +#if CONFIG_MAX_PHYSICAL_CPUS > 2 + // third node + RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + // forth node + RC03, DIMM0, DIMM2, DIMM4, DIMM6, DIMM1, DIMM3, DIMM5, DIMM7, +#endif +#if CONFIG_MAX_PHYSICAL_CPUS > 4 + RC04, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC05, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#endif +#if CONFIG_MAX_PHYSICAL_CPUS > 6 + RC06, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC07, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#endif +#if CONFIG_MAX_PHYSICAL_CPUS > 8 + RC08, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC09, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC10, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC11, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#endif +#if CONFIG_MAX_PHYSICAL_CPUS > 12 + RC12, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC13, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC14, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC15, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#endif +#if CONFIG_MAX_PHYSICAL_CPUS > 16 + RC16, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC17, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC18, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC19, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#endif +#if CONFIG_MAX_PHYSICAL_CPUS > 20 + RC20, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC21, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC22, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC23, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#endif +#if CONFIG_MAX_PHYSICAL_CPUS > 24 + RC24, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC25, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC26, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC27, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC28, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC29, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC30, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC31, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#endif +#if CONFIG_MAX_PHYSICAL_CPUS > 32 + RC32, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC33, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC34, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC35, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC36, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC37, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC38, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC39, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC40, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC41, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC42, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC43, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC44, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC45, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC46, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC47, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#endif +#if CONFIG_MAX_PHYSICAL_CPUS > 48 + RC48, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC49, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC50, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC51, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC52, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC53, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC54, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC55, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC56, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC57, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC58, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC59, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC60, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC61, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC62, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#endif +}; void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Sat Nov 20 21:23:08 2010 (r6100) +++ trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Sat Nov 20 21:36:40 2010 (r6101) @@ -44,6 +44,7 @@ #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" #include <lib.h> +#include <spd.h> #include "cpu/amd/model_10xxx/apic_timer.c" #include "lib/delay.c" @@ -98,7 +99,15 @@ #include "northbridge/amd/amdfam10/early_ht.c" -#include "spd_addr.h" +static const u8 spd_addr[] = { + // switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr + //first node + RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + //second node + RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#endif +}; void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Sat Nov 20 21:23:08 2010 (r6100) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Sat Nov 20 21:36:40 2010 (r6101) @@ -33,6 +33,7 @@ #include <console/console.h> #include <usbdebug.h> #include <lib.h> +#include <spd.h> #include <cpu/amd/model_10xxx_rev.h> @@ -116,7 +117,14 @@ pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword); } -#include "spd_addr.h" +static const u8 spd_addr[] = { + //first node + RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + //second node + RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, +#endif +}; void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Sat Nov 20 21:23:08 2010 (r6100) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Sat Nov 20 21:36:40 2010 (r6101) @@ -33,6 +33,7 @@ #include <console/console.h> #include <lib.h> +#include <spd.h> #include <cpu/amd/model_10xxx_rev.h> @@ -117,7 +118,14 @@ } -#include "spd_addr.h" +static const u8 spd_addr[] = { + //first node + RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + //second node + RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, +#endif +}; void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Sat Nov 20 21:23:08 2010 (r6100) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Sat Nov 20 21:36:40 2010 (r6101) @@ -33,6 +33,7 @@ #include <console/console.h> #include <lib.h> +#include <spd.h> #include <cpu/amd/model_10xxx_rev.h> @@ -120,7 +121,20 @@ } -#include "spd_addr.h" +static const u8 spd_addr[] = { + //first node + RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + //second node + RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, +#endif +#if CONFIG_MAX_PHYSICAL_CPUS > 2 + //third node + RC02, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, + //forth node + RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0, +#endif +}; #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1) #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2) Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Sat Nov 20 21:23:08 2010 (r6100) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Sat Nov 20 21:36:40 2010 (r6101) @@ -33,6 +33,7 @@ #include <console/console.h> #include <usbdebug.h> #include <lib.h> +#include <spd.h> #include <cpu/amd/model_10xxx_rev.h> @@ -120,7 +121,13 @@ pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword); } -#include "spd_addr.h" +static const u8 spd_addr[] = { + //first node + RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + //second node + RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, +#endif void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) {

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[commit] r6100 - in trunk/src: include mainboard/amd/mahogany_fam10 mainboard/amd/serengeti_cheetah_fam10 mainboard/amd/tilapia_fam10 mainboard/asus/m4a785-m mainboard/bcom/winnetp680 mainboard/del...
by repository service 20 Nov '10

20 Nov '10

Author: uwe Date: Sat Nov 20 21:23:08 2010 New Revision: 6100 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6100 Log: Some more DIMM0 related cleanups and deduplication. - VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do. - spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of romstage.c files and lots of spd_addr.h files. Don't even bother for those spd_addr.h which aren't even actually used, drop them right away. - Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1, and 0xa0 with (DIMM0 << 1) where appropriate. - Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0, SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC. - VIA VX800: Drop unused SMBUS_ADDR_CH* #defines. - VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do. Then, replace 0xa0 (which now becomes 0x50) with DIMM0. - alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes. - Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Deleted: trunk/src/mainboard/amd/mahogany_fam10/spd_addr.h trunk/src/mainboard/amd/tilapia_fam10/spd_addr.h trunk/src/mainboard/asus/m4a785-m/spd_addr.h trunk/src/mainboard/iei/kino-780am2-fam10/spd_addr.h Modified: trunk/src/include/spd.h trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/spd_addr.h trunk/src/mainboard/amd/tilapia_fam10/romstage.c trunk/src/mainboard/asus/m4a785-m/romstage.c trunk/src/mainboard/bcom/winnetp680/romstage.c trunk/src/mainboard/dell/s1850/debug.c trunk/src/mainboard/gigabyte/ma785gmt/romstage.c trunk/src/mainboard/gigabyte/ma78gm/romstage.c trunk/src/mainboard/hp/dl165_g6_fam10/spd_addr.h trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c trunk/src/mainboard/intel/eagleheights/debug.c trunk/src/mainboard/intel/jarrell/debug.c trunk/src/mainboard/jetway/j7f24/romstage.c trunk/src/mainboard/jetway/pa78vm5/romstage.c trunk/src/mainboard/msi/ms9652_fam10/spd_addr.h trunk/src/mainboard/pcengines/alix1c/romstage.c trunk/src/mainboard/pcengines/alix2d/romstage.c trunk/src/mainboard/rca/rm4100/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/spd_addr.h trunk/src/mainboard/supermicro/h8qme_fam10/spd_addr.h trunk/src/mainboard/supermicro/x6dai_g/debug.c trunk/src/mainboard/supermicro/x6dhe_g/debug.c trunk/src/mainboard/supermicro/x6dhe_g2/debug.c trunk/src/mainboard/supermicro/x6dhr_ig/debug.c trunk/src/mainboard/supermicro/x6dhr_ig2/debug.c trunk/src/mainboard/thomson/ip1000/romstage.c trunk/src/mainboard/tyan/s2912_fam10/spd_addr.h trunk/src/mainboard/via/epia-cn/romstage.c trunk/src/mainboard/via/epia-n/romstage.c trunk/src/mainboard/via/pc2500e/romstage.c trunk/src/mainboard/via/vt8454c/romstage.c trunk/src/northbridge/amd/amdk8/raminit_test.c trunk/src/northbridge/intel/i440bx/debug.c trunk/src/northbridge/intel/i440bx/raminit.c trunk/src/northbridge/intel/i440bx/raminit.h trunk/src/northbridge/intel/i440lx/raminit.c trunk/src/northbridge/intel/i440lx/raminit.h trunk/src/northbridge/intel/i82810/debug.c trunk/src/northbridge/intel/i82810/raminit.c trunk/src/northbridge/intel/i82810/raminit.h trunk/src/northbridge/intel/i82830/raminit.c trunk/src/northbridge/intel/i82830/raminit.h trunk/src/northbridge/intel/i855/raminit.h trunk/src/northbridge/intel/i945/debug.c trunk/src/northbridge/intel/i945/raminit.c trunk/src/northbridge/intel/i945/raminit.h trunk/src/northbridge/via/cn400/raminit.c trunk/src/northbridge/via/vt8601/raminit.c trunk/src/northbridge/via/vt8623/raminit.c trunk/src/northbridge/via/vx800/detection.c trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c Modified: trunk/src/include/spd.h ============================================================================== --- trunk/src/include/spd.h Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/include/spd.h Sat Nov 20 21:23:08 2010 (r6100) @@ -166,5 +166,70 @@ #define DIMM6 0x56 #define DIMM7 0x57 -#endif /* _SPD_H_ */ +#define RC00 0 +#define RC01 1 +#define RC02 2 +#define RC03 3 +#define RC04 4 +#define RC05 5 +#define RC06 6 +#define RC07 7 +#define RC08 8 +#define RC09 9 +#define RC10 10 +#define RC11 11 +#define RC12 12 +#define RC13 13 +#define RC14 14 +#define RC15 15 +#define RC16 16 +#define RC17 17 +#define RC18 18 +#define RC19 19 +#define RC20 20 +#define RC21 21 +#define RC22 22 +#define RC23 23 +#define RC24 24 +#define RC25 25 +#define RC26 26 +#define RC27 27 +#define RC28 28 +#define RC29 29 +#define RC30 30 +#define RC31 31 +#define RC32 32 +#define RC33 33 +#define RC34 34 +#define RC35 35 +#define RC36 36 +#define RC37 37 +#define RC38 38 +#define RC39 39 +#define RC40 40 +#define RC41 41 +#define RC42 42 +#define RC43 43 +#define RC44 44 +#define RC45 45 +#define RC46 46 +#define RC47 47 +#define RC48 48 +#define RC49 49 +#define RC50 50 +#define RC51 51 +#define RC52 52 +#define RC53 53 +#define RC54 54 +#define RC55 55 +#define RC56 56 +#define RC57 57 +#define RC58 58 +#define RC59 59 +#define RC60 60 +#define RC61 61 +#define RC62 62 +#define RC63 63 + +#endif Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Sat Nov 20 21:23:08 2010 (r6100) @@ -86,11 +86,6 @@ #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" -//#include "spd_addr.h" - -#define RC00 0 -#define RC01 1 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/spd_addr.h ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/spd_addr.h Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/spd_addr.h Sat Nov 20 21:23:08 2010 (r6100) @@ -17,87 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/** - * This file defines the SPD addresses for the mainboard. Must be included in - * romstage.c - */ - -#define RC00 0 -#define RC01 1 -#define RC02 2 -#define RC03 3 -#define RC04 4 -#define RC05 5 -#define RC06 6 -#define RC07 7 -#define RC08 8 -#define RC09 9 -#define RC10 10 -#define RC11 11 -#define RC12 12 -#define RC13 13 -#define RC14 14 -#define RC15 15 -#define RC16 16 -#define RC17 17 -#define RC18 18 -#define RC19 19 -#define RC20 20 -#define RC21 21 -#define RC22 22 -#define RC23 23 -#define RC24 24 -#define RC25 25 -#define RC26 26 -#define RC27 27 -#define RC28 28 -#define RC29 29 -#define RC30 30 -#define RC31 31 - -#define RC32 32 -#define RC33 33 -#define RC34 34 -#define RC35 35 -#define RC36 36 -#define RC37 37 -#define RC38 38 -#define RC39 39 -#define RC40 40 -#define RC41 41 -#define RC42 42 -#define RC43 43 -#define RC44 44 -#define RC45 45 -#define RC46 46 -#define RC47 47 -#define RC48 48 -#define RC49 49 -#define RC50 50 -#define RC51 51 -#define RC52 52 -#define RC53 53 -#define RC54 54 -#define RC55 55 -#define RC56 56 -#define RC57 57 -#define RC58 58 -#define RC59 59 -#define RC60 60 -#define RC61 61 -#define RC62 62 -#define RC63 63 - - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 +/** This file defines the SPD addresses for the mainboard. */ +#include <spd.h> static const u8 spd_addr[] = { //first node @@ -191,4 +113,3 @@ RC63, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #endif }; - Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Sat Nov 20 21:23:08 2010 (r6100) @@ -86,11 +86,6 @@ #include "southbridge/amd/sb700/sb700_early_setup.c" #include <spd.h> -//#include "spd_addr.h" - -#define RC00 0 -#define RC01 1 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/romstage.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/asus/m4a785-m/romstage.c Sat Nov 20 21:23:08 2010 (r6100) @@ -86,11 +86,6 @@ #include "southbridge/amd/sb700/sb700_early_setup.c" #include <spd.h> -//#include "spd_addr.h" - -#define RC00 0 -#define RC01 1 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/bcom/winnetp680/romstage.c ============================================================================== --- trunk/src/mainboard/bcom/winnetp680/romstage.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/bcom/winnetp680/romstage.c Sat Nov 20 21:23:08 2010 (r6100) @@ -75,7 +75,7 @@ .d0f4 = 0x4000, .d0f7 = 0x7000, .d1f0 = 0x8000, - .channel0 = { 0x50 }, + .channel0 = { DIMM0 }, }; void main(unsigned long bist) Modified: trunk/src/mainboard/dell/s1850/debug.c ============================================================================== --- trunk/src/mainboard/dell/s1850/debug.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/dell/s1850/debug.c Sat Nov 20 21:23:08 2010 (r6100) @@ -1,6 +1,4 @@ -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x57 -#define SMBUS_MEM_DEVICE_INC 1 +#include <spd.h> static void print_reg(unsigned char index) { @@ -208,8 +206,8 @@ void dump_spd_registers(void) { unsigned device; - device = SMBUS_MEM_DEVICE_START; - while(device <= SMBUS_MEM_DEVICE_END) { + device = DIMM0; + while(device <= DIMM7) { int status = 0; int i; print_debug("\n"); @@ -233,7 +231,7 @@ print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } @@ -241,8 +239,8 @@ void show_dram_slots(void) { unsigned device; - device = SMBUS_MEM_DEVICE_START; - while(device <= SMBUS_MEM_DEVICE_END) { + device = DIMM0; + while(device <= DIMM7) { int status = 0; int i; print_debug("\n"); @@ -257,7 +255,7 @@ } print_debug_hex8(status); print_debug("\n"); - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } @@ -285,7 +283,7 @@ print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Sat Nov 20 21:23:08 2010 (r6100) @@ -82,10 +82,6 @@ #include "southbridge/amd/sb700/sb700_early_setup.c" #include <spd.h> - -#define RC00 0 -#define RC01 1 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/romstage.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c Sat Nov 20 21:23:08 2010 (r6100) @@ -86,10 +86,6 @@ #include "southbridge/amd/sb700/sb700_early_setup.c" #include <spd.h> - -#define RC00 0 -#define RC01 1 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/hp/dl165_g6_fam10/spd_addr.h ============================================================================== --- trunk/src/mainboard/hp/dl165_g6_fam10/spd_addr.h Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/hp/dl165_g6_fam10/spd_addr.h Sat Nov 20 21:23:08 2010 (r6100) @@ -17,87 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/** - * This file defines the SPD addresses for the mainboard. Must be included in - * romstage.c - */ - -#define RC00 0 -#define RC01 1 -#define RC02 2 -#define RC03 3 -#define RC04 4 -#define RC05 5 -#define RC06 6 -#define RC07 7 -#define RC08 8 -#define RC09 9 -#define RC10 10 -#define RC11 11 -#define RC12 12 -#define RC13 13 -#define RC14 14 -#define RC15 15 -#define RC16 16 -#define RC17 17 -#define RC18 18 -#define RC19 19 -#define RC20 20 -#define RC21 21 -#define RC22 22 -#define RC23 23 -#define RC24 24 -#define RC25 25 -#define RC26 26 -#define RC27 27 -#define RC28 28 -#define RC29 29 -#define RC30 30 -#define RC31 31 - -#define RC32 32 -#define RC33 33 -#define RC34 34 -#define RC35 35 -#define RC36 36 -#define RC37 37 -#define RC38 38 -#define RC39 39 -#define RC40 40 -#define RC41 41 -#define RC42 42 -#define RC43 43 -#define RC44 44 -#define RC45 45 -#define RC46 46 -#define RC47 47 -#define RC48 48 -#define RC49 49 -#define RC50 50 -#define RC51 51 -#define RC52 52 -#define RC53 53 -#define RC54 54 -#define RC55 55 -#define RC56 56 -#define RC57 57 -#define RC58 58 -#define RC59 59 -#define RC60 60 -#define RC61 61 -#define RC62 62 -#define RC63 63 - - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 +/** This file defines the SPD addresses for the mainboard. */ +#include <spd.h> static const u8 spd_addr[] = { // switch addr, 1A addr, 2A addr, 3A addr, 4A addr, 1B addr, 2B addr, 3B addr 4B addr @@ -108,4 +30,3 @@ RC01, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #endif }; - Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Sat Nov 20 21:23:08 2010 (r6100) @@ -89,11 +89,6 @@ #include "southbridge/amd/sb700/sb700_early_setup.c" #include <spd.h> -//#include "spd_addr.h" - -#define RC00 0 -#define RC01 1 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/intel/eagleheights/debug.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/debug.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/intel/eagleheights/debug.c Sat Nov 20 21:23:08 2010 (r6100) @@ -20,9 +20,7 @@ * MA 02110-1301 USA */ -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x57 -#define SMBUS_MEM_DEVICE_INC 1 +#include <spd.h> static void print_reg(unsigned char index) { @@ -230,8 +228,8 @@ static inline void dump_spd_registers(void) { unsigned device; - device = SMBUS_MEM_DEVICE_START; - while(device <= SMBUS_MEM_DEVICE_END) { + device = DIMM0; + while(device <= DIMM7) { int status = 0; int i; print_debug("\n"); @@ -254,7 +252,7 @@ print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } @@ -281,7 +279,7 @@ print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } Modified: trunk/src/mainboard/intel/jarrell/debug.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/debug.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/intel/jarrell/debug.c Sat Nov 20 21:23:08 2010 (r6100) @@ -1,6 +1,4 @@ -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x57 -#define SMBUS_MEM_DEVICE_INC 1 +#include <spd.h> static void print_reg(unsigned char index) { @@ -271,8 +269,8 @@ void dump_spd_registers(void) { unsigned device; - device = SMBUS_MEM_DEVICE_START; - while(device <= SMBUS_MEM_DEVICE_END) { + device = DIMM0; + while(device <= DIMM7) { int status = 0; int i; print_debug("\n"); @@ -296,7 +294,7 @@ print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } @@ -324,7 +322,7 @@ print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } Modified: trunk/src/mainboard/jetway/j7f24/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/j7f24/romstage.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/jetway/j7f24/romstage.c Sat Nov 20 21:23:08 2010 (r6100) @@ -81,7 +81,7 @@ .d0f4 = 0x4000, .d0f7 = 0x7000, .d1f0 = 0x8000, - .channel0 = { 0x50 }, + .channel0 = { DIMM0 }, }; void main(unsigned long bist) Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/romstage.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/jetway/pa78vm5/romstage.c Sat Nov 20 21:23:08 2010 (r6100) @@ -94,9 +94,6 @@ #include "southbridge/amd/sb700/sb700_early_setup.c" #include <spd.h> -#define RC00 0 -#define RC01 1 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/msi/ms9652_fam10/spd_addr.h ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/spd_addr.h Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/msi/ms9652_fam10/spd_addr.h Sat Nov 20 21:23:08 2010 (r6100) @@ -17,87 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/** - * This file defines the SPD addresses for the mainboard. Must be included in - * romstage.c - */ - -#define RC00 0 -#define RC01 1 -#define RC02 2 -#define RC03 3 -#define RC04 4 -#define RC05 5 -#define RC06 6 -#define RC07 7 -#define RC08 8 -#define RC09 9 -#define RC10 10 -#define RC11 11 -#define RC12 12 -#define RC13 13 -#define RC14 14 -#define RC15 15 -#define RC16 16 -#define RC17 17 -#define RC18 18 -#define RC19 19 -#define RC20 20 -#define RC21 21 -#define RC22 22 -#define RC23 23 -#define RC24 24 -#define RC25 25 -#define RC26 26 -#define RC27 27 -#define RC28 28 -#define RC29 29 -#define RC30 30 -#define RC31 31 - -#define RC32 32 -#define RC33 33 -#define RC34 34 -#define RC35 35 -#define RC36 36 -#define RC37 37 -#define RC38 38 -#define RC39 39 -#define RC40 40 -#define RC41 41 -#define RC42 42 -#define RC43 43 -#define RC44 44 -#define RC45 45 -#define RC46 46 -#define RC47 47 -#define RC48 48 -#define RC49 49 -#define RC50 50 -#define RC51 51 -#define RC52 52 -#define RC53 53 -#define RC54 54 -#define RC55 55 -#define RC56 56 -#define RC57 57 -#define RC58 58 -#define RC59 59 -#define RC60 60 -#define RC61 61 -#define RC62 62 -#define RC63 63 - - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 +/** This file defines the SPD addresses for the mainboard. */ +#include <spd.h> static const u8 spd_addr[] = { //first node @@ -107,4 +29,3 @@ RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, #endif }; - Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/romstage.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/pcengines/alix1c/romstage.c Sat Nov 20 21:23:08 2010 (r6100) @@ -89,7 +89,7 @@ print_debug("spd_read_byte dev "); print_debug_hex8(device); - if (device != (0x50 << 1)) { + if (device != DIMM0) { print_debug(" returns 0xff\n"); return 0xff; } @@ -123,7 +123,7 @@ void main(unsigned long bist) { static const struct mem_controller memctrl[] = { - {.channel0 = {0x50}}, + {.channel0 = {DIMM0}}, }; post_code(0x01); Modified: trunk/src/mainboard/pcengines/alix2d/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix2d/romstage.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/pcengines/alix2d/romstage.c Sat Nov 20 21:23:08 2010 (r6100) @@ -88,7 +88,7 @@ print_debug("spd_read_byte dev "); print_debug_hex8(device); - if (device != (0x50 << 1)) { + if (device != DIMM0) { print_debug(" returns 0xff\n"); return 0xff; } @@ -144,7 +144,7 @@ void main(unsigned long bist) { static const struct mem_controller memctrl[] = { - {.channel0 = {0x50}}, + {.channel0 = {DIMM0}}, }; post_code(0x01); Modified: trunk/src/mainboard/rca/rm4100/romstage.c ============================================================================== --- trunk/src/mainboard/rca/rm4100/romstage.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/rca/rm4100/romstage.c Sat Nov 20 21:23:08 2010 (r6100) @@ -45,15 +45,16 @@ /** * The onboard 64MB PC133 memory does not have a SPD EEPROM so the * values have to be set manually, the SO-DIMM socket is located in - * socket0 (0x50), and the onboard memory is located in socket1 (0x51). + * socket0 (0x50/DIMM0), and the onboard memory is located in socket1 + * (0x51/DIMM1). */ static inline int spd_read_byte(unsigned device, unsigned address) { int i; - if (device == 0x50) { + if (device == DIMM0) { return smbus_read_byte(device, address); - } else if (device == 0x51) { + } else if (device == DIMM1) { for (i = 0; i < ARRAY_SIZE(spd_table); i++) { if (spd_table[i].address == address) return spd_table[i].data; Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/spd_addr.h ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/spd_addr.h Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/spd_addr.h Sat Nov 20 21:23:08 2010 (r6100) @@ -17,87 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/** - * This file defines the SPD addresses for the mainboard. Must be included in - * romstage.c - */ - -#define RC00 0 -#define RC01 1 -#define RC02 2 -#define RC03 3 -#define RC04 4 -#define RC05 5 -#define RC06 6 -#define RC07 7 -#define RC08 8 -#define RC09 9 -#define RC10 10 -#define RC11 11 -#define RC12 12 -#define RC13 13 -#define RC14 14 -#define RC15 15 -#define RC16 16 -#define RC17 17 -#define RC18 18 -#define RC19 19 -#define RC20 20 -#define RC21 21 -#define RC22 22 -#define RC23 23 -#define RC24 24 -#define RC25 25 -#define RC26 26 -#define RC27 27 -#define RC28 28 -#define RC29 29 -#define RC30 30 -#define RC31 31 - -#define RC32 32 -#define RC33 33 -#define RC34 34 -#define RC35 35 -#define RC36 36 -#define RC37 37 -#define RC38 38 -#define RC39 39 -#define RC40 40 -#define RC41 41 -#define RC42 42 -#define RC43 43 -#define RC44 44 -#define RC45 45 -#define RC46 46 -#define RC47 47 -#define RC48 48 -#define RC49 49 -#define RC50 50 -#define RC51 51 -#define RC52 52 -#define RC53 53 -#define RC54 54 -#define RC55 55 -#define RC56 56 -#define RC57 57 -#define RC58 58 -#define RC59 59 -#define RC60 60 -#define RC61 61 -#define RC62 62 -#define RC63 63 - - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 +/** This file defines the SPD addresses for the mainboard. */ +#include <spd.h> static const u8 spd_addr[] = { //first node @@ -107,4 +29,3 @@ RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, #endif }; - Modified: trunk/src/mainboard/supermicro/h8qme_fam10/spd_addr.h ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/spd_addr.h Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/supermicro/h8qme_fam10/spd_addr.h Sat Nov 20 21:23:08 2010 (r6100) @@ -17,87 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/** - * This file defines the SPD addresses for the mainboard. Must be included in - * romstage.c - */ - -#define RC00 0 -#define RC01 1 -#define RC02 2 -#define RC03 3 -#define RC04 4 -#define RC05 5 -#define RC06 6 -#define RC07 7 -#define RC08 8 -#define RC09 9 -#define RC10 10 -#define RC11 11 -#define RC12 12 -#define RC13 13 -#define RC14 14 -#define RC15 15 -#define RC16 16 -#define RC17 17 -#define RC18 18 -#define RC19 19 -#define RC20 20 -#define RC21 21 -#define RC22 22 -#define RC23 23 -#define RC24 24 -#define RC25 25 -#define RC26 26 -#define RC27 27 -#define RC28 28 -#define RC29 29 -#define RC30 30 -#define RC31 31 - -#define RC32 32 -#define RC33 33 -#define RC34 34 -#define RC35 35 -#define RC36 36 -#define RC37 37 -#define RC38 38 -#define RC39 39 -#define RC40 40 -#define RC41 41 -#define RC42 42 -#define RC43 43 -#define RC44 44 -#define RC45 45 -#define RC46 46 -#define RC47 47 -#define RC48 48 -#define RC49 49 -#define RC50 50 -#define RC51 51 -#define RC52 52 -#define RC53 53 -#define RC54 54 -#define RC55 55 -#define RC56 56 -#define RC57 57 -#define RC58 58 -#define RC59 59 -#define RC60 60 -#define RC61 61 -#define RC62 62 -#define RC63 63 - - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 +/** This file defines the SPD addresses for the mainboard. */ +#include <spd.h> static const u8 spd_addr[] = { //first node @@ -113,4 +35,3 @@ RC03, DIMM4, DIMM6,0 , 0, DIMM5, DIMM7, 0, 0, #endif }; - Modified: trunk/src/mainboard/supermicro/x6dai_g/debug.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/debug.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/supermicro/x6dai_g/debug.c Sat Nov 20 21:23:08 2010 (r6100) @@ -1,6 +1,4 @@ -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x57 -#define SMBUS_MEM_DEVICE_INC 1 +#include <spd.h> static void print_reg(unsigned char index) { @@ -271,8 +269,8 @@ void dump_spd_registers(void) { unsigned device; - device = SMBUS_MEM_DEVICE_START; - while(device <= SMBUS_MEM_DEVICE_END) { + device = DIMM0; + while(device <= DIMM7) { int status = 0; int i; print_debug("\n"); @@ -296,7 +294,7 @@ print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } @@ -324,7 +322,7 @@ print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } Modified: trunk/src/mainboard/supermicro/x6dhe_g/debug.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/debug.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/supermicro/x6dhe_g/debug.c Sat Nov 20 21:23:08 2010 (r6100) @@ -1,6 +1,4 @@ -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x57 -#define SMBUS_MEM_DEVICE_INC 1 +#include <spd.h> static void print_reg(unsigned char index) { @@ -271,8 +269,8 @@ void dump_spd_registers(void) { unsigned device; - device = SMBUS_MEM_DEVICE_START; - while(device <= SMBUS_MEM_DEVICE_END) { + device = DIMM0; + while(device <= DIMM7) { int status = 0; int i; print_debug("\n"); @@ -296,7 +294,7 @@ print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } @@ -324,7 +322,7 @@ print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } Modified: trunk/src/mainboard/supermicro/x6dhe_g2/debug.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/debug.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/supermicro/x6dhe_g2/debug.c Sat Nov 20 21:23:08 2010 (r6100) @@ -1,6 +1,4 @@ -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x57 -#define SMBUS_MEM_DEVICE_INC 1 +#include <spd.h> static void print_reg(unsigned char index) { @@ -271,8 +269,8 @@ void dump_spd_registers(void) { unsigned device; - device = SMBUS_MEM_DEVICE_START; - while(device <= SMBUS_MEM_DEVICE_END) { + device = DIMM0; + while(device <= DIMM7) { int status = 0; int i; print_debug("\n"); @@ -296,7 +294,7 @@ print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } @@ -324,7 +322,7 @@ print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } Modified: trunk/src/mainboard/supermicro/x6dhr_ig/debug.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/debug.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/supermicro/x6dhr_ig/debug.c Sat Nov 20 21:23:08 2010 (r6100) @@ -1,6 +1,4 @@ -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x57 -#define SMBUS_MEM_DEVICE_INC 1 +#include <spd.h> static void print_reg(unsigned char index) { @@ -271,8 +269,8 @@ void dump_spd_registers(void) { unsigned device; - device = SMBUS_MEM_DEVICE_START; - while(device <= SMBUS_MEM_DEVICE_END) { + device = DIMM0; + while(device <= DIMM7) { int status = 0; int i; print_debug("\n"); @@ -296,7 +294,7 @@ print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } @@ -324,7 +322,7 @@ print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/debug.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/debug.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/debug.c Sat Nov 20 21:23:08 2010 (r6100) @@ -1,6 +1,4 @@ -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x57 -#define SMBUS_MEM_DEVICE_INC 1 +#include <spd.h> static void print_reg(unsigned char index) { @@ -271,8 +269,8 @@ void dump_spd_registers(void) { unsigned device; - device = SMBUS_MEM_DEVICE_START; - while(device <= SMBUS_MEM_DEVICE_END) { + device = DIMM0; + while(device <= DIMM7) { int status = 0; int i; print_debug("\n"); @@ -296,7 +294,7 @@ print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } @@ -324,7 +322,7 @@ print_debug_hex8(status); print_debug_char(' '); } - device += SMBUS_MEM_DEVICE_INC; + device++; print_debug("\n"); } } Modified: trunk/src/mainboard/thomson/ip1000/romstage.c ============================================================================== --- trunk/src/mainboard/thomson/ip1000/romstage.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/thomson/ip1000/romstage.c Sat Nov 20 21:23:08 2010 (r6100) @@ -46,15 +46,16 @@ /** * The onboard 64MB PC133 memory does not have a SPD EEPROM so the * values have to be set manually, the SO-DIMM socket is located in - * socket0 (0x50), and the onboard memory is located in socket1 (0x51). + * socket0 (0x50/DIMM0), and the onboard memory is located in socket1 + * (0x51/DIMM1). */ static inline int spd_read_byte(unsigned device, unsigned address) { int i; - if (device == 0x50) { + if (device == DIMM0) { return smbus_read_byte(device, address); - } else if (device == 0x51) { + } else if (device == DIMM1) { for (i = 0; i < ARRAY_SIZE(spd_table); i++) { if (spd_table[i].address == address) return spd_table[i].data; Modified: trunk/src/mainboard/tyan/s2912_fam10/spd_addr.h ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/spd_addr.h Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/tyan/s2912_fam10/spd_addr.h Sat Nov 20 21:23:08 2010 (r6100) @@ -17,87 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/** - * This file defines the SPD addresses for the mainboard. Must be included in - * romstage.c - */ - -#define RC00 0 -#define RC01 1 -#define RC02 2 -#define RC03 3 -#define RC04 4 -#define RC05 5 -#define RC06 6 -#define RC07 7 -#define RC08 8 -#define RC09 9 -#define RC10 10 -#define RC11 11 -#define RC12 12 -#define RC13 13 -#define RC14 14 -#define RC15 15 -#define RC16 16 -#define RC17 17 -#define RC18 18 -#define RC19 19 -#define RC20 20 -#define RC21 21 -#define RC22 22 -#define RC23 23 -#define RC24 24 -#define RC25 25 -#define RC26 26 -#define RC27 27 -#define RC28 28 -#define RC29 29 -#define RC30 30 -#define RC31 31 - -#define RC32 32 -#define RC33 33 -#define RC34 34 -#define RC35 35 -#define RC36 36 -#define RC37 37 -#define RC38 38 -#define RC39 39 -#define RC40 40 -#define RC41 41 -#define RC42 42 -#define RC43 43 -#define RC44 44 -#define RC45 45 -#define RC46 46 -#define RC47 47 -#define RC48 48 -#define RC49 49 -#define RC50 50 -#define RC51 51 -#define RC52 52 -#define RC53 53 -#define RC54 54 -#define RC55 55 -#define RC56 56 -#define RC57 57 -#define RC58 58 -#define RC59 59 -#define RC60 60 -#define RC61 61 -#define RC62 62 -#define RC63 63 - - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 +/** This file defines the SPD addresses for the mainboard. */ +#include <spd.h> static const u8 spd_addr[] = { //first node @@ -107,4 +29,3 @@ RC00, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, #endif }; - Modified: trunk/src/mainboard/via/epia-cn/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-cn/romstage.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/via/epia-cn/romstage.c Sat Nov 20 21:23:08 2010 (r6100) @@ -75,7 +75,7 @@ .d0f4 = 0x4000, .d0f7 = 0x7000, .d1f0 = 0x8000, - .channel0 = { 0x50 }, + .channel0 = { DIMM0 }, }; void main(unsigned long bist) Modified: trunk/src/mainboard/via/epia-n/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-n/romstage.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/via/epia-n/romstage.c Sat Nov 20 21:23:08 2010 (r6100) @@ -50,7 +50,7 @@ .d0f4 = 0x4000, .d0f7 = 0x7000, .d1f0 = 0x8000, - .channel0 = { 0x50 }, + .channel0 = { DIMM0 }, }; static inline int spd_read_byte(unsigned device, unsigned address) Modified: trunk/src/mainboard/via/pc2500e/romstage.c ============================================================================== --- trunk/src/mainboard/via/pc2500e/romstage.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/via/pc2500e/romstage.c Sat Nov 20 21:23:08 2010 (r6100) @@ -51,7 +51,7 @@ .d0f4 = 0x4000, .d0f7 = 0x7000, .d1f0 = 0x8000, - .channel0 = { 0x50 }, /* TODO: CN700 currently only supports 1 DIMM. */ + .channel0 = { DIMM0 }, /* TODO: CN700 currently only supports 1 DIMM. */ }; void main(unsigned long bist) Modified: trunk/src/mainboard/via/vt8454c/romstage.c ============================================================================== --- trunk/src/mainboard/via/vt8454c/romstage.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/mainboard/via/vt8454c/romstage.c Sat Nov 20 21:23:08 2010 (r6100) @@ -91,7 +91,7 @@ /* Set statically so it should work with cx700 as well */ static const struct mem_controller cx700[] = { { - .channel0 = {0x50, 0x51}, + .channel0 = {DIMM0, DIMM1}, }, }; Modified: trunk/src/northbridge/amd/amdk8/raminit_test.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_test.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/northbridge/amd/amdk8/raminit_test.c Sat Nov 20 21:23:08 2010 (r6100) @@ -268,11 +268,11 @@ { int result; spd_count++; - if ((device < 0x50) || (device >= (0x50 +MAX_DIMMS))) { + if ((device < DIMM0) || (device >= (DIMM0 + MAX_DIMMS))) { result = -1; } else { - device -= 0x50; + device -= DIMM0; /* 0x50 */ if (address > 256) { result = -1; @@ -324,8 +324,8 @@ .f1 = PCI_DEV(0, 0x18, 1), .f2 = PCI_DEV(0, 0x18, 2), .f3 = PCI_DEV(0, 0x18, 3), - .channel0 = { 0x50+0, 0x50+2, 0x50+4, 0x50+6 }, - .channel1 = { 0x50+1, 0x50+3, 0x50+5, 0x50+7 }, + .channel0 = { DIMM0+0, DIMM0+2, DIMM0+4, DIMM0+6 }, + .channel1 = { DIMM0+1, DIMM0+3, DIMM0+5, DIMM0+7 }, }, #endif #if SECOND_CPU @@ -335,8 +335,8 @@ .f1 = PCI_DEV(0, 0x19, 1), .f2 = PCI_DEV(0, 0x19, 2), .f3 = PCI_DEV(0, 0x19, 3), - .channel0 = { 0x50+8, 0x50+10, 0x50+12, 0x50+14 }, - .channel1 = { 0x50+9, 0x50+11, 0x50+13, 0x50+15 }, + .channel0 = { DIMM0+8, DIMM0+10, DIMM0+12, DIMM0+14 }, + .channel1 = { DIMM0+9, DIMM0+11, DIMM0+13, DIMM0+15 }, }, #endif }; Modified: trunk/src/northbridge/intel/i440bx/debug.c ============================================================================== --- trunk/src/northbridge/intel/i440bx/debug.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/northbridge/intel/i440bx/debug.c Sat Nov 20 21:23:08 2010 (r6100) @@ -7,7 +7,7 @@ print_debug("\n"); for(i = 0; i < DIMM_SOCKETS; i++) { unsigned device; - device = DIMM_SPD_BASE + i; + device = DIMM0 + i; if (device) { int j; print_debug("dimm: "); Modified: trunk/src/northbridge/intel/i440bx/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i440bx/raminit.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/northbridge/intel/i440bx/raminit.c Sat Nov 20 21:23:08 2010 (r6100) @@ -616,7 +616,7 @@ reg = pci_read_config8(NB, DRAMC); for (i = 0; i < DIMM_SOCKETS; i++) { - value = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH); + value = spd_read_byte(DIMM0 + i, SPD_REFRESH); if (value < 0) continue; reg = (reg & 0xf8) | refresh_rate_map[(value & 0x7f)]; @@ -750,7 +750,7 @@ for (i = 0; i < DIMM_SOCKETS; i++) { unsigned int device; - device = DIMM_SPD_BASE + i; + device = DIMM0 + i; bpr >>= 2; /* First check if a DIMM is actually present. */ Modified: trunk/src/northbridge/intel/i440bx/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i440bx/raminit.h Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/northbridge/intel/i440bx/raminit.h Sat Nov 20 21:23:08 2010 (r6100) @@ -24,9 +24,6 @@ /* The 440BX supports up to four (single- or double-sided) DIMMs. */ #define DIMM_SOCKETS 4 -/* DIMMs 1-4 are at 0x50, 0x51, 0x52, 0x53. */ -#define DIMM_SPD_BASE 0x50 - /* Function prototypes. */ int spd_read_byte(unsigned int device, unsigned int address); void sdram_set_registers(void); Modified: trunk/src/northbridge/intel/i440lx/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i440lx/raminit.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/northbridge/intel/i440lx/raminit.c Sat Nov 20 21:23:08 2010 (r6100) @@ -301,18 +301,18 @@ PRINT_DEBUG("DIMM"); PRINT_DEBUG_HEX8(i); PRINT_DEBUG(" rows: "); - PRINT_DEBUG_HEX8(spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS) & 0xFF); + PRINT_DEBUG_HEX8(spd_read_byte(DIMM0 + i, SPD_NUM_DIMM_BANKS) & 0xFF); PRINT_DEBUG(" rowsize: "); - PRINT_DEBUG_HEX8(spd_read_byte(DIMM_SPD_BASE + i, SPD_DENSITY_OF_EACH_ROW_ON_MODULE) & 0xFF); + PRINT_DEBUG_HEX8(spd_read_byte(DIMM0 + i, SPD_DENSITY_OF_EACH_ROW_ON_MODULE) & 0xFF); PRINT_DEBUG(" modulesize: "); - j = spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS); + j = spd_read_byte(DIMM0 + i, SPD_NUM_DIMM_BANKS); if (j < 0) j = 0; else ds = j; - j = spd_read_byte(DIMM_SPD_BASE + i, SPD_DENSITY_OF_EACH_ROW_ON_MODULE); + j = spd_read_byte(DIMM0 + i, SPD_DENSITY_OF_EACH_ROW_ON_MODULE); if (j < 0) j = 0; Modified: trunk/src/northbridge/intel/i440lx/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i440lx/raminit.h Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/northbridge/intel/i440lx/raminit.h Sat Nov 20 21:23:08 2010 (r6100) @@ -25,7 +25,4 @@ /* The 440LX supports up to four (single- or double-sided) DIMMs. */ #define DIMM_SOCKETS 4 -/* DIMMs 1-4 are at 0x50, 0x51, 0x52, 0x53. */ -#define DIMM_SPD_BASE 0x50 - #endif /* RAMINIT_H */ Modified: trunk/src/northbridge/intel/i82810/debug.c ============================================================================== --- trunk/src/northbridge/intel/i82810/debug.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/northbridge/intel/i82810/debug.c Sat Nov 20 21:23:08 2010 (r6100) @@ -7,7 +7,7 @@ print_debug("\n"); for(i = 0; i < DIMM_SOCKETS; i++) { unsigned device; - device = DIMM_SPD_BASE + i; + device = DIMM0 + i; if (device) { int j; print_debug("dimm: "); Modified: trunk/src/northbridge/intel/i82810/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i82810/raminit.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/northbridge/intel/i82810/raminit.c Sat Nov 20 21:23:08 2010 (r6100) @@ -255,12 +255,12 @@ for (i = 0; i < DIMM_SOCKETS; i++) { /* First check if a DIMM is actually present. */ - if (smbus_read_byte(DIMM_SPD_BASE + i, 2) == 4) { + if (smbus_read_byte(DIMM0 + i, 2) == 4) { print_debug("Found DIMM in slot "); print_debug_hex8(i); print_debug("\n"); - dimm_size = smbus_read_byte(DIMM_SPD_BASE + i, 31); + dimm_size = smbus_read_byte(DIMM0 + i, 31); /* WISHLIST: would be nice to display it as decimal? */ print_debug("DIMM is 0x"); @@ -293,7 +293,7 @@ /* If the DIMM is dual-sided, the DRP value is +2 */ /* TODO: Figure out asymetrical configurations. */ - if ((smbus_read_byte(DIMM_SPD_BASE + i, 127) | 0xf) == + if ((smbus_read_byte(DIMM0 + i, 127) | 0xf) == 0xff) { print_debug("DIMM is dual-sided\n"); dimm_size += 2; @@ -361,20 +361,18 @@ /* Check first slot. */ d0.size = d0.ds = d0.ss = 0; - if (smbus_read_byte(DIMM_SPD_BASE, SPD_MEMORY_TYPE) - == SPD_MEMORY_TYPE_SDRAM) { - d0.size = smbus_read_byte(DIMM_SPD_BASE, SPD_BANK_DENSITY); - d0.ds = smbus_read_byte(DIMM_SPD_BASE, SPD_NUM_DIMM_BANKS) > 1; + if (smbus_read_byte(DIMM0, SPD_MEMORY_TYPE) == SPD_MEMORY_TYPE_SDRAM) { + d0.size = smbus_read_byte(DIMM0, SPD_BANK_DENSITY); + d0.ds = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) > 1; d0.ss = !d0.ds; } /* Check second slot. */ d1.size = d1.ds = d1.ss = 0; - if (smbus_read_byte(DIMM_SPD_BASE + 1, SPD_MEMORY_TYPE) + if (smbus_read_byte(DIMM0 + 1, SPD_MEMORY_TYPE) == SPD_MEMORY_TYPE_SDRAM) { - d1.size = smbus_read_byte(DIMM_SPD_BASE + 1, SPD_BANK_DENSITY); - d1.ds = smbus_read_byte(DIMM_SPD_BASE + 1, - SPD_NUM_DIMM_BANKS) > 1; + d1.size = smbus_read_byte(DIMM0 + 1, SPD_BANK_DENSITY); + d1.ds = smbus_read_byte(DIMM0 + 1, SPD_NUM_DIMM_BANKS) > 1; d1.ss = !d1.ds; } Modified: trunk/src/northbridge/intel/i82810/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i82810/raminit.h Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/northbridge/intel/i82810/raminit.h Sat Nov 20 21:23:08 2010 (r6100) @@ -24,9 +24,6 @@ /* The 82810 supports max. 2 dual-sided DIMMs. */ #define DIMM_SOCKETS 2 -/* DIMM0 is at 0x50, DIMM1 is at 0x51. */ -#define DIMM_SPD_BASE 0x50 - /* Function prototypes. */ void sdram_set_registers(void); void sdram_set_spd_registers(void); Modified: trunk/src/northbridge/intel/i82830/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i82830/raminit.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/northbridge/intel/i82830/raminit.c Sat Nov 20 21:23:08 2010 (r6100) @@ -101,16 +101,16 @@ switch (row) { case 0: - device = DIMM_SPD_BASE; + device = DIMM0; break; case 1: - device = DIMM_SPD_BASE; + device = DIMM0; break; case 2: - device = DIMM_SPD_BASE + 1; + device = DIMM0 + 1; break; case 3: - device = DIMM_SPD_BASE + 1; + device = DIMM0 + 1; break; } @@ -224,7 +224,7 @@ for (i = 0; i < DIMM_SOCKETS; i++) { struct dimm_size sz; unsigned device; - device = DIMM_SPD_BASE + i; + device = DIMM0 + i; drb1 = 0; drb2 = 0; @@ -316,7 +316,7 @@ for (i = 0; i < DIMM_SOCKETS; i++) { unsigned device; - device = DIMM_SPD_BASE + i; + device = DIMM0 + i; /* First check if a DIMM is actually present. */ if (spd_read_byte(device, SPD_MEMORY_TYPE) == 0x4) { Modified: trunk/src/northbridge/intel/i82830/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i82830/raminit.h Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/northbridge/intel/i82830/raminit.h Sat Nov 20 21:23:08 2010 (r6100) @@ -27,7 +27,4 @@ /* The 82830 supports max. 2 dual-sided SO-DIMMs. */ #define DIMM_SOCKETS 2 -/* DIMM0 is at 0x50, DIMM1 is at 0x51. */ -#define DIMM_SPD_BASE 0x50 - #endif /* NORTHBRIDGE_INTEL_I82830_RAMINIT_H */ Modified: trunk/src/northbridge/intel/i855/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i855/raminit.h Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/northbridge/intel/i855/raminit.h Sat Nov 20 21:23:08 2010 (r6100) @@ -28,9 +28,6 @@ /* The i855 supports max. 2 dual-sided SO-DIMMs. */ #define DIMM_SOCKETS 2 -/* DIMM0 is at 0x50, DIMM1 is at 0x51. */ -#define DIMM_SPD_BASE 0x50 - struct mem_controller { device_t d0; uint16_t channel0[DIMM_SOCKETS]; @@ -38,5 +35,4 @@ void sdram_initialize(int controllers, const struct mem_controller *ctrl); - #endif /* NORTHBRIDGE_INTEL_I855_RAMINIT_H */ Modified: trunk/src/northbridge/intel/i945/debug.c ============================================================================== --- trunk/src/northbridge/intel/i945/debug.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/northbridge/intel/i945/debug.c Sat Nov 20 21:23:08 2010 (r6100) @@ -19,6 +19,7 @@ * MA 02110-1301 USA */ +#include <spd.h> #include <lib.h> #include <arch/io.h> #include <arch/romcc_io.h> @@ -26,10 +27,6 @@ #include <console/console.h> #include "i945.h" -#define SMBUS_MEM_DEVICE_START 0x50 -#define SMBUS_MEM_DEVICE_END 0x53 -#define SMBUS_MEM_DEVICE_INC 1 - void print_pci_devices(void) { device_t dev; @@ -88,8 +85,8 @@ void dump_spd_registers(void) { unsigned device; - device = SMBUS_MEM_DEVICE_START; - while(device <= SMBUS_MEM_DEVICE_END) { + device = DIMM0; + while(device <= DIMM3) { int status = 0; int i; printk(BIOS_DEBUG, "\ndimm %02x", device); @@ -105,7 +102,7 @@ } printk(BIOS_DEBUG, "%02x ", status); } - device += SMBUS_MEM_DEVICE_INC; + device++; printk(BIOS_DEBUG, "\n"); } } Modified: trunk/src/northbridge/intel/i945/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i945/raminit.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/northbridge/intel/i945/raminit.c Sat Nov 20 21:23:08 2010 (r6100) @@ -323,15 +323,14 @@ /** * i945 supports two DIMMs, in two configurations: * - * - single channel with two dimms - * - dual channel with one dimm per channel + * - single channel with two DIMMs + * - dual channel with one DIMM per channel * - * In practice dual channel mainboards have their spd at 0x50, 0x52 - * whereas single channel configurations have their spd at 0x50/x51 + * In practice dual channel mainboards have their SPD at 0x50/0x52 + * whereas single channel configurations have their SPD at 0x50/0x51. * * The capability register knows a lot about the channel configuration - * but for now we stick with the information we gather from the SPD - * ROMs + * but for now we stick with the information we gather via SPD. */ if (sdram_capabilities_dual_channel()) { @@ -362,7 +361,7 @@ */ for (i=0; i<(2 * DIMM_SOCKETS); i++) { - u8 reg8, device = DIMM_SPD_BASE + i; + u8 reg8, device = DIMM0 + i; /* Initialize the socket information with a sane value */ sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED; @@ -453,7 +452,7 @@ continue; /* Is the current DIMM a stacked DIMM? */ - if (spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_DIMM_BANKS) & (1 << 4)) + if (spd_read_byte(DIMM0 + i, SPD_NUM_DIMM_BANKS) & (1 << 4)) sysinfo->package = 1; } } @@ -470,7 +469,7 @@ for (i=0; i<2*DIMM_SOCKETS; i++) { if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED) - cas_mask &= spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES); + cas_mask &= spd_read_byte(DIMM0 + i, SPD_ACCEPTABLE_CAS_LATENCIES); } if(!cas_mask) { @@ -531,7 +530,7 @@ continue; } - current_cas_mask = spd_read_byte(DIMM_SPD_BASE + i, SPD_ACCEPTABLE_CAS_LATENCIES); + current_cas_mask = spd_read_byte(DIMM0 + i, SPD_ACCEPTABLE_CAS_LATENCIES); while (current_cas_mask) { int highest_supported_cas = 0, current_cas = 0; @@ -553,11 +552,11 @@ idx = highest_supported_cas - current_cas; PRINTK_DEBUG("idx=%d, ", idx); - PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx])); - PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1])); + PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(DIMM0 + i, spd_lookup_table[2*idx])); + PRINTK_DEBUG("tAC=%x", spd_read_byte(DIMM0 + i, spd_lookup_table[(2*idx)+1])); - if (spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] && - spd_read_byte(DIMM_SPD_BASE + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) { + if (spd_read_byte(DIMM0 + i, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] && + spd_read_byte(DIMM0 + i, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) { PRINTK_DEBUG(": OK\n"); break; } @@ -621,7 +620,7 @@ if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); + reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); if (!reg8) { die("Invalid tRAS value.\n"); } @@ -661,7 +660,7 @@ if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_ROW_PRECHARGE_TIME); + reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_ROW_PRECHARGE_TIME); if (!reg8) { die("Invalid tRP value.\n"); } @@ -702,7 +701,7 @@ if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_MIN_RAS_TO_CAS_DELAY); + reg8 = spd_read_byte(DIMM0 + i, SPD_MIN_RAS_TO_CAS_DELAY); if (!reg8) { die("Invalid tRCD value.\n"); } @@ -742,7 +741,7 @@ if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - reg8 = spd_read_byte(DIMM_SPD_BASE + i, SPD_WRITE_RECOVERY_TIME); + reg8 = spd_read_byte(DIMM0 + i, SPD_WRITE_RECOVERY_TIME); if (!reg8) { die("Invalid tWR value.\n"); } @@ -823,7 +822,7 @@ if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - refresh = spd_read_byte(DIMM_SPD_BASE + i, SPD_REFRESH) & ~(1 << 7); + refresh = spd_read_byte(DIMM0 + i, SPD_REFRESH) & ~(1 << 7); /* 15.6us */ if (!refresh) @@ -851,7 +850,7 @@ if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - if (!(spd_read_byte(DIMM_SPD_BASE + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8)) + if (!(spd_read_byte(DIMM0 + i, SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8)) die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n"); } } @@ -1471,9 +1470,9 @@ if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - sz = sdram_get_dimm_size(DIMM_SPD_BASE + i); + sz = sdram_get_dimm_size(DIMM0 + i); - sysinfo->banks[i] = spd_read_byte(DIMM_SPD_BASE + i, SPD_NUM_BANKS_PER_SDRAM); /* banks */ + sysinfo->banks[i] = spd_read_byte(DIMM0 + i, SPD_NUM_BANKS_PER_SDRAM); /* banks */ if (sz.side1 < 30) die("DDR-II rank size smaller than 128MB is not supported.\n"); @@ -1565,7 +1564,7 @@ continue; } - device = DIMM_SPD_BASE + i; + device = DIMM0 + i; value = spd_read_byte(device, SPD_NUM_ROWS); /* rows */ columnsrows = (value & 0x0f); Modified: trunk/src/northbridge/intel/i945/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i945/raminit.h Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/northbridge/intel/i945/raminit.h Sat Nov 20 21:23:08 2010 (r6100) @@ -22,7 +22,6 @@ #define DIMM_SOCKETS 2 -#define DIMM_SPD_BASE 0x50 #define DIMM_TCO_BASE 0x30 /* Burst length is always 8 */ Modified: trunk/src/northbridge/via/cn400/raminit.c ============================================================================== --- trunk/src/northbridge/via/cn400/raminit.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/northbridge/via/cn400/raminit.c Sat Nov 20 21:23:08 2010 (r6100) @@ -174,17 +174,15 @@ Read SPD byte 17, Number of banks on SDRAM device. */ c = 0; - b = smbus_read_byte(0x50, SPD_NUM_BANKS_PER_SDRAM); + b = smbus_read_byte(DIMM0, SPD_NUM_BANKS_PER_SDRAM); //print_val("Detecting Memory\nNumber of Banks ",b); // Only supporting 4 bank chips just now if( b == 4 ){ - /* - Read SPD byte 3, Number of row addresses. - */ + /* Read SPD byte 3, Number of row addresses. */ c = 0x01; bank = 0x40; - b = smbus_read_byte(0x50, SPD_NUM_ROWS); + b = smbus_read_byte(DIMM0, SPD_NUM_ROWS); //print_val("\nNumber of Rows ", b); if( b >= 0x0d ){ // 256/512Mb @@ -194,19 +192,15 @@ else bank = 0x44; - /* - Read SPD byte 13, Primary DRAM width. - */ - b = smbus_read_byte(0x50, SPD_PRIMARY_SDRAM_WIDTH); + /* Read SPD byte 13, Primary DRAM width. */ + b = smbus_read_byte(DIMM0, SPD_PRIMARY_SDRAM_WIDTH); //print_val("\nPrimary DRAM width", b); if( b != 4 ) // not 64/128Mb (x4) c = 0x81; // 256Mb } - /* - Read SPD byte 4, Number of column addresses. - */ - b = smbus_read_byte(0x50, SPD_NUM_COLUMNS); + /* Read SPD byte 4, Number of column addresses. */ + b = smbus_read_byte(DIMM0, SPD_NUM_COLUMNS); //print_val("\nNo Columns ",b); if( b == 10 || b == 11 || b == 12) c |= 0x60; // 10/11 bit col addr if( b == 9 ) c |= 0x40; // 9 bit col addr @@ -238,7 +232,7 @@ // Read SPD byte 31 Module bank density //c = 0; - b = smbus_read_byte(0x50, SPD_DENSITY_OF_EACH_ROW_ON_MODULE); + b = smbus_read_byte(DIMM0, SPD_DENSITY_OF_EACH_ROW_ON_MODULE); if( b & 0x02 ) { c = 0x40; // 2GB @@ -278,7 +272,7 @@ pci_write_config8(ctrl.d0f3, 0x40, c); // SPD byte 5 # of physical banks - b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS); + b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS); //print_val("\nNo Physical Banks ",b); if( b == 2) @@ -307,7 +301,7 @@ ma = bank; /* Read SPD byte 18 CAS Latency */ - b = smbus_read_byte(0x50, SPD_ACCEPTABLE_CAS_LATENCIES); + b = smbus_read_byte(DIMM0, SPD_ACCEPTABLE_CAS_LATENCIES); /* print_debug("\nCAS Supported "); if(b & 0x04) print_debug("2 "); @@ -316,30 +310,30 @@ if(b & 0x10) print_debug("3"); - c = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); + c = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); print_val("\nCycle time at CL X (nS)", c); - c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND); + c = smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND); print_val("\nCycle time at CL X-0.5 (nS)", c); - c = smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD); + c = smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD); print_val("\nCycle time at CL X-1 (nS)", c); */ /* Scaling of Cycle Time SPD data */ /* 7 4 3 0 */ /* ns x0.1ns */ - bank = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); + bank = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); if( b & 0x10 ){ // DDR offering optional CAS 3 //print_debug("\nStarting at CAS 3"); c = 0x30; /* see if we can better it */ if( b & 0x08 ){ // DDR mandatory CAS 2.5 - if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5 + if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank ){ // we can manage max MHz at CAS 2.5 //print_debug("\nWe can do CAS 2.5"); c = 0x20; } } if( b & 0x04 ){ // DDR mandatory CAS 2 - if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2 + if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_3RD) <= bank ){ // we can manage max Mhz at CAS 2 //print_debug("\nWe can do CAS 2"); c = 0x10; } @@ -348,7 +342,7 @@ //print_debug("\nStarting at CAS 2.5"); c = 0x20; // assume CAS 2.5 if( b & 0x04){ // Should always happen - if( smbus_read_byte(0x50, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2 + if( smbus_read_byte(DIMM0, SPD_SDRAM_CYCLE_TIME_2ND) <= bank){ // we can manage max Mhz at CAS 2 //print_debug("\nWe can do CAS 2"); c = 0x10; } @@ -383,7 +377,7 @@ Read SPD byte 27, min row pre-charge time. */ - b = smbus_read_byte(0x50, SPD_MIN_ROW_PRECHARGE_TIME); + b = smbus_read_byte(DIMM0, SPD_MIN_ROW_PRECHARGE_TIME); //print_val("\ntRP ",b); if ( b >= (5 * bank)) { @@ -402,7 +396,7 @@ Read SPD byte 29, min row pre-charge time. */ - b = smbus_read_byte(0x50, SPD_MIN_RAS_TO_CAS_DELAY); + b = smbus_read_byte(DIMM0, SPD_MIN_RAS_TO_CAS_DELAY); //print_val("\ntRCD ",b); if ( b >= (5 * bank)) c |= 0x0C; // set tRCD = 5T @@ -419,7 +413,7 @@ /* tRAS is in whole ns */ bank = bank >> 2; - b = smbus_read_byte(0x50, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); + b = smbus_read_byte(DIMM0, SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); //print_val("\ntRAS ",b); //print_val("\nBank ", bank); if ( b >= (9 * bank)) c |= 0xC0; // set tRAS = 9T @@ -438,7 +432,7 @@ /* DRAM Clock Device 0 Fn 3 Offset 68 */ - bank = smbus_read_byte(0x50, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); + bank = smbus_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX); /* Setup DRAM Cycle Time */ if ( bank <= 0x50 ) @@ -469,7 +463,7 @@ Read SPD byte 17, Number of banks on SDRAM device. */ c = 0x0F; - b = smbus_read_byte(0x50, SPD_NUM_BANKS_PER_SDRAM); + b = smbus_read_byte(DIMM0, SPD_NUM_BANKS_PER_SDRAM); if( b == 4) c |= 0x80; else if (b == 2) c |= 0x40; @@ -520,7 +514,7 @@ /* SPD byte 5 # of physical banks */ - b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS) -1; + b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) -1; c = b | 0x40; pci_write_config8(ctrl.d0f3, 0xb0, c); @@ -532,7 +526,7 @@ pci_write_config8(ctrl.d0f3, 0x48, ma); udelay(200); - c = smbus_read_byte(0x50, SPD_SUPPORTED_BURST_LENGTHS); + c = smbus_read_byte(DIMM0, SPD_SUPPORTED_BURST_LENGTHS); c &= 0x08; if ( c == 0x08 ) { @@ -673,7 +667,7 @@ pci_write_config8(ctrl.d0f3, 0xED, 0x11); /* SPD byte 5 # of physical banks */ - b = smbus_read_byte(0x50, SPD_NUM_DIMM_BANKS) -1; + b = smbus_read_byte(DIMM0, SPD_NUM_DIMM_BANKS) -1; /* determine low bond */ if( b == 2) @@ -795,7 +789,7 @@ */ //c = pci_read_config8(ctrl.d0f3, 0x68); //c &= 0x07; - //b = smbus_read_byte(0x50, SPD_REFRESH); + //b = smbus_read_byte(DIMM0, SPD_REFRESH); //print_val("SPD_REFRESH = ", b); pci_write_config8(ctrl.d0f3,0x6a,0x65); Modified: trunk/src/northbridge/via/vt8601/raminit.c ============================================================================== --- trunk/src/northbridge/via/vt8601/raminit.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/northbridge/via/vt8601/raminit.c Sat Nov 20 21:23:08 2010 (r6100) @@ -34,6 +34,8 @@ */ /* converted to C 9/2003 Ron Minnich */ +#include <spd.h> + /* Set to 1 if your DIMMs are PC133 Note that I'm assuming CPU's FSB * frequency is 133MHz. If your CPU runs at another bus speed, you * might need to change some of register values. @@ -178,8 +180,8 @@ /* we may run out of registers ... */ unsigned int banks, rows, cols; unsigned int value = 0; - /* unsigned int module = ((0x50 + slot) << 1) + 1; */ - unsigned int module = 0x50 + slot; + /* unsigned int module = ((DIMM0 + slot) << 1) + 1; */ + unsigned int module = DIMM0 + slot; /* is the module there? if byte 2 is not 4, then we'll assume it * is useless. @@ -220,7 +222,7 @@ #if 0 static int spd_num_chips(unsigned char slot) { - unsigned int module = 0x50 + slot; + unsigned int module = DIMM0 + slot; unsigned int width; width = smbus_read_byte(module, 13); @@ -236,13 +238,13 @@ unsigned char Trp = 1, Tras = 1, casl = 2, val; unsigned char timing = 0xe4; /* read Trp */ - val = smbus_read_byte(0x50, 27); + val = smbus_read_byte(DIMM0, 27); if (val < 2 * T133) Trp = 1; - val = smbus_read_byte(0x50, 30); + val = smbus_read_byte(DIMM0, 30); if (val < 5 * T133) Tras = 0; - val = smbus_read_byte(0x50, 18); + val = smbus_read_byte(DIMM0, 18); if (val < 8) casl = 1; if (val < 4) @@ -366,7 +368,7 @@ continue; /* Read the row densities */ - size = smbus_read_byte(0x50+slot, 0x1f); + size = smbus_read_byte(DIMM0 + slot, 0x1f); /* Set the MA map type. * Modified: trunk/src/northbridge/via/vt8623/raminit.c ============================================================================== --- trunk/src/northbridge/via/vt8623/raminit.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/northbridge/via/vt8623/raminit.c Sat Nov 20 21:23:08 2010 (r6100) @@ -30,6 +30,7 @@ */ /* ported and enhanced from assembler level code in coreboot v1 */ +#include <spd.h> #include <cpu/x86/mtrr.h> #include "raminit.h" @@ -101,7 +102,7 @@ Read SPD byte 17, Number of banks on SDRAM device. */ c = 0; - b = smbus_read_byte(0xa0,17); + b = smbus_read_byte(DIMM0,17); print_val("Detecting Memory\nNumber of Banks ",b); if( b != 2 ){ // not 16 Mb type @@ -109,14 +110,14 @@ /* Read SPD byte 3, Number of row addresses. */ - b = smbus_read_byte(0xa0,3); + b = smbus_read_byte(DIMM0,3); print_val("\nNumber of Rows ",b); if( b >= 0x0d ){ // not 64/128Mb (rows <=12) /* Read SPD byte 13, Primary DRAM width. */ - b = smbus_read_byte(0xa0,13); + b = smbus_read_byte(DIMM0,13); print_val("\nPriamry DRAM width",b); if( b != 4 ) // mot 64/128Mb (x4) c = 0x80; // 256Mb @@ -127,7 +128,7 @@ Read SPD byte 4, Number of column addresses. */ - b = smbus_read_byte(0xa0,4); + b = smbus_read_byte(DIMM0,4); print_val("\nNo Columns ",b); if( b == 10 || b == 11 ) c |= 0x60; // 10/11 bit col addr if( b == 9 ) c |= 0x40; // 9 bit col addr @@ -149,7 +150,7 @@ // Read SPD byte 31 Module bank density c = 0; - b = smbus_read_byte(0xa0,31); + b = smbus_read_byte(DIMM0,31); if( b & 0x02 ) c = 0x80; // 2GB else if( b & 0x01) c = 0x40; // 1GB else if( b & 0x80) c = 0x20; // 512Mb @@ -166,7 +167,7 @@ // set bank zero size pci_write_config8(north,0x5a,c); // SPD byte 5 # of physical banks - b = smbus_read_byte(0xa0,5); + b = smbus_read_byte(DIMM0,5); print_val("\nNo Physical Banks ",b); if( b == 2) @@ -180,7 +181,7 @@ /* Read SPD byte 18 CAS Latency */ - b = smbus_read_byte(0xa0,18); + b = smbus_read_byte(DIMM0,18); print_debug("\nCAS Supported "); if(b & 0x04) print_debug("2 "); @@ -188,9 +189,9 @@ print_debug("2.5 "); if(b & 0x10) print_debug("3"); - print_val("\nCycle time at CL X (nS)",smbus_read_byte(0xa0,9)); - print_val("\nCycle time at CL X-0.5 (nS)",smbus_read_byte(0xa0,23)); - print_val("\nCycle time at CL X-1 (nS)",smbus_read_byte(0xa0,25)); + print_val("\nCycle time at CL X (nS)",smbus_read_byte(DIMM0,9)); + print_val("\nCycle time at CL X-0.5 (nS)",smbus_read_byte(DIMM0,23)); + print_val("\nCycle time at CL X-1 (nS)",smbus_read_byte(DIMM0,25)); if( b & 0x10 ){ // DDR offering optional CAS 3 @@ -198,13 +199,13 @@ c = 0x30; /* see if we can better it */ if( b & 0x08 ){ // DDR mandatory CAS 2.5 - if( smbus_read_byte(0xa0,23) <= 0x75 ){ // we can manage 133Mhz at CAS 2.5 + if( smbus_read_byte(DIMM0,23) <= 0x75 ){ // we can manage 133Mhz at CAS 2.5 print_debug("\nWe can do CAS 2.5"); c = 0x20; } } if( b & 0x04 ){ // DDR mandatory CAS 2 - if( smbus_read_byte(0xa0,25) <= 0x75 ){ // we can manage 133Mhz at CAS 2 + if( smbus_read_byte(DIMM0,25) <= 0x75 ){ // we can manage 133Mhz at CAS 2 print_debug("\nWe can do CAS 2"); c = 0x10; } @@ -213,7 +214,7 @@ print_debug("\nStarting at CAS 2.5"); c = 0x20; // assume CAS 2.5 if( b & 0x04){ // Should always happen - if( smbus_read_byte(0xa0,23) <= 0x75){ // we can manage 133Mhz at CAS 2 + if( smbus_read_byte(DIMM0,23) <= 0x75){ // we can manage 133Mhz at CAS 2 print_debug("\nWe can do CAS 2"); c = 0x10; } @@ -253,7 +254,7 @@ Read SPD byte 27, min row pre-charge time. */ - b = smbus_read_byte(0xa0,27); + b = smbus_read_byte(DIMM0,27); print_val("\ntRP ",b); if( b > 0x3c ) // set tRP = 3T c |= 0x80; @@ -265,7 +266,7 @@ Read SPD byte 29, min row pre-charge time. */ - b = smbus_read_byte(0xa0,29); + b = smbus_read_byte(DIMM0,29); print_val("\ntRCD ",b); if( b > 0x3c ) // set tRCD = 3T c |= 0x04; @@ -277,7 +278,7 @@ Read SPD byte 30, device min active to pre-charge time. */ - b = smbus_read_byte(0xa0,30); + b = smbus_read_byte(DIMM0,30); print_val("\ntRAS ",b); if( b > 0x25 ) // set tRAS = 6T c |= 0x40; @@ -288,7 +289,7 @@ Read SPD byte 17, Number of banks on SDRAM device. */ - b = smbus_read_byte(0xa0,17); + b = smbus_read_byte(DIMM0,17); if( b == 4) c |= 0x02; else if (b == 2) c |= 0x01; @@ -342,7 +343,7 @@ pci_write_config8(north,0x6d,0x044); pci_write_config8(north,0x67,0x3a); - b = smbus_read_byte(0xa0,5); // SPD byte 5 # of physical banks + b = smbus_read_byte(DIMM0,5); // SPD byte 5 # of physical banks if( b > 1) { // Increase drive control when there is more than 1 physical bank pci_write_config8(north,0x6c,0x84); // Drive control: MA, DQS, MD/CKE Modified: trunk/src/northbridge/via/vx800/detection.c ============================================================================== --- trunk/src/northbridge/via/vx800/detection.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/northbridge/via/vx800/detection.c Sat Nov 20 21:23:08 2010 (r6100) @@ -19,14 +19,9 @@ /* FIXME this should go away */ static const struct mem_controller ctrl = { - .channel0 = {0x50, 0x51}, + .channel0 = {DIMM0, DIMM1}, }; -#define SMBUS_ADDR_CH_A_1 0xA0 /* Dimmx */ -#define SMBUS_ADDR_CH_A_2 0xA2 /* Dimmx */ -#define SMBUS_ADDR_CH_B_1 0xA4 /* Dimmx */ -#define SMBUS_ADDR_CH_B_2 0xA6 /* Dimmx */ - /* read data */ CB_STATUS GetSPDData(u8 Slot, u8 Length, u8 *Buf); void DRAMCmdRate(DRAM_SYS_ATTR *DramAttr); Modified: trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c ============================================================================== --- trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c Sat Nov 20 11:31:00 2010 (r6099) +++ trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c Sat Nov 20 21:23:08 2010 (r6100) @@ -174,7 +174,7 @@ outb(bIndex, SMBUS_IO_BASE+3); /* set slave address */ - outb(devAdr | 0x01, SMBUS_IO_BASE+4); + outb((devAdr << 1) | 0x01, SMBUS_IO_BASE+4); /* start */ outb(0x48, SMBUS_IO_BASE+2);

1 0

protected_start and __protected_start!
by ali hagigat 20 Nov '10

20 Nov '10

Would you please tell me how Coreboot jumps to the label, protected_start in src/cpu/x86/32bit? There is a jump instruction (jmp protected_start) in reset16.inc but it seems it will never be executed.

2 1

[commit] r6099 - in trunk/src: include mainboard/amd/db800 mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/norwich mainboard/amd/pistachio mainboard/amd/rumb...
by repository service 20 Nov '10

20 Nov '10

Author: oxygene Date: Sat Nov 20 11:31:00 2010 New Revision: 6099 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6099 Log: Unify DIMM SPD addressing. For Geode, change the addressing scheme to match the rest of the tree (0x50 instead of 0xa0). abuild tested. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/include/spd.h trunk/src/mainboard/amd/db800/romstage.c trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/norwich/romstage.c trunk/src/mainboard/amd/pistachio/romstage.c trunk/src/mainboard/amd/rumba/romstage.c trunk/src/mainboard/amd/serengeti_cheetah/romstage.c trunk/src/mainboard/amd/tilapia_fam10/romstage.c trunk/src/mainboard/artecgroup/dbe61/romstage.c trunk/src/mainboard/asrock/939a785gmh/romstage.c trunk/src/mainboard/asus/m4a785-m/romstage.c trunk/src/mainboard/broadcom/blast/romstage.c trunk/src/mainboard/digitallogic/msm800sev/romstage.c trunk/src/mainboard/gigabyte/ma785gmt/romstage.c trunk/src/mainboard/gigabyte/ma78gm/romstage.c trunk/src/mainboard/hp/dl145_g1/romstage.c trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c trunk/src/mainboard/intel/truxton/romstage.c trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/jetway/pa78vm5/romstage.c trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/lippert/frontrunner/romstage.c trunk/src/mainboard/lippert/hurricane-lx/romstage.c trunk/src/mainboard/lippert/literunner-lx/romstage.c trunk/src/mainboard/lippert/roadrunner-lx/romstage.c trunk/src/mainboard/lippert/spacerunner-lx/romstage.c trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/pcengines/alix1c/romstage.c trunk/src/mainboard/pcengines/alix2d/romstage.c trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/romstage.c trunk/src/mainboard/traverse/geos/romstage.c trunk/src/mainboard/tyan/s4880/romstage.c trunk/src/mainboard/tyan/s4882/romstage.c trunk/src/mainboard/winent/pl6064/romstage.c trunk/src/mainboard/wyse/s50/romstage.c trunk/src/northbridge/via/cx700/cx700_early_smbus.c trunk/src/northbridge/via/vx800/vx800_early_smbus.c trunk/src/southbridge/amd/cs5536/cs5536_early_smbus.c trunk/src/southbridge/via/vt8231/vt8231_early_smbus.c trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c Modified: trunk/src/include/spd.h ============================================================================== --- trunk/src/include/spd.h Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/include/spd.h Sat Nov 20 11:31:00 2010 (r6099) @@ -156,5 +156,15 @@ #define MODULE_BUFFERED 1 #define MODULE_REGISTERED 2 +/* DIMM SPD addresses */ +#define DIMM0 0x50 +#define DIMM1 0x51 +#define DIMM2 0x52 +#define DIMM3 0x53 +#define DIMM4 0x54 +#define DIMM5 0x55 +#define DIMM6 0x56 +#define DIMM7 0x57 + #endif /* _SPD_H_ */ Modified: trunk/src/mainboard/amd/db800/romstage.c ============================================================================== --- trunk/src/mainboard/amd/db800/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/amd/db800/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -30,6 +30,7 @@ #include <cpu/amd/lxdef.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" +#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -45,8 +46,6 @@ #define ManualConf 0 /* Do automatic strapped PLL config */ #define PLLMSRhi 0x000005DD /* Manual settings for the PLL */ #define PLLMSRlo 0x00DE60EE -#define DIMM0 0xA0 -#define DIMM1 0xA2 #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -20,9 +20,6 @@ #define RC0 (6<<8) #define RC1 (7<<8) -#define DIMM0 0x50 -#define DIMM1 0x51 - #define SMBUS_HUB 0x71 #include <stdint.h> @@ -43,6 +40,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" +#include <spd.h> #include <usbdebug.h> Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/amd/mahogany/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -20,9 +20,6 @@ #define RC0 (6<<8) #define RC1 (7<<8) -#define DIMM0 0x50 -#define DIMM1 0x51 - #define SMBUS_HUB 0x71 #include <stdint.h> @@ -34,6 +31,7 @@ #include <cpu/x86/lapic.h> #include <pc80/mc146818rtc.h> #include <console/console.h> +#include <spd.h> #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/raminit.h" Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -57,6 +57,7 @@ #include "southbridge/amd/rs780/rs780_early_setup.c" #include "southbridge/amd/sb700/sb700_early_setup.c" #include "northbridge/amd/amdfam10/debug.c" +#include <spd.h> static void activate_spd_rom(const struct mem_controller *ctrl) { @@ -90,11 +91,6 @@ #define RC00 0 #define RC01 1 -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/amd/norwich/romstage.c ============================================================================== --- trunk/src/mainboard/amd/norwich/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/amd/norwich/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -30,6 +30,7 @@ #include <cpu/amd/lxdef.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" +#include <spd.h> #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" @@ -42,8 +43,6 @@ #define ManualConf 0 /* Do automatic strapped PLL config */ #define PLLMSRhi 0x00001490 /* manual settings for the PLL */ #define PLLMSRlo 0x02000030 -#define DIMM0 0xA0 -#define DIMM1 0xA2 #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" Modified: trunk/src/mainboard/amd/pistachio/romstage.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/amd/pistachio/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -17,9 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define DIMM0 0x50 -#define DIMM1 0x51 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -39,6 +36,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" #include <usbdebug.h> +#include <spd.h> #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" Modified: trunk/src/mainboard/amd/rumba/romstage.c ============================================================================== --- trunk/src/mainboard/amd/rumba/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/amd/rumba/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -9,15 +9,13 @@ #include "cpu/x86/msr.h" #include <cpu/amd/gx2def.h> #include <cpu/amd/geode_post_code.h> +#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" -#define DIMM0 0xA0 -#define DIMM1 0xFF /* DIMM1 is not available/used on this board. */ - static inline int spd_read_byte(unsigned device, unsigned address) { if (device != DIMM0) Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -92,22 +92,13 @@ #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" +#include <spd.h> #define RC0 ((1<<0)<<8) #define RC1 ((1<<1)<<8) #define RC2 ((1<<2)<<8) #define RC3 ((1<<3)<<8) -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 - - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -84,17 +84,13 @@ #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" +#include <spd.h> //#include "spd_addr.h" #define RC00 0 #define RC01 1 -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/artecgroup/dbe61/romstage.c ============================================================================== --- trunk/src/mainboard/artecgroup/dbe61/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/artecgroup/dbe61/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -32,13 +32,11 @@ #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" #include "spd_table.h" +#include <spd.h> #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" -#define DIMM0 0xA0 -#define DIMM1 0xA2 - static int spd_read_byte(unsigned device, unsigned address) { int i; Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -21,9 +21,6 @@ #define RC0 (6<<8) #define RC1 (7<<8) -#define DIMM0 0x50 -#define DIMM1 0x51 - #define SMBUS_HUB 0x71 #include <stdint.h> @@ -40,6 +37,7 @@ #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" +#include <spd.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/asus/m4a785-m/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -84,17 +84,13 @@ #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" +#include <spd.h> //#include "spd_addr.h" #define RC00 0 #define RC01 1 -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/broadcom/blast/romstage.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/broadcom/blast/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -70,16 +70,11 @@ #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" +#include <spd.h> #define RC0 (6<<8) #define RC1 (7<<8) -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm800sev/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -11,6 +11,7 @@ #include <cpu/amd/lxdef.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" +#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -26,8 +27,6 @@ #define ManualConf 0 /* Do automatic strapped PLL config */ #define PLLMSRhi 0x00001490 /* manual settings for the PLL */ #define PLLMSRlo 0x02000030 -#define DIMM0 0xA0 -#define DIMM1 0xA2 #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -80,16 +80,12 @@ #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" +#include <spd.h> #define RC00 0 #define RC01 1 -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -84,16 +84,12 @@ #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" +#include <spd.h> #define RC00 0 #define RC01 1 -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/hp/dl145_g1/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g1/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/hp/dl145_g1/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -92,15 +92,11 @@ #include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" +#include <spd.h> #define RC0 ((1<<1)<<8) // Not sure about these values #define RC1 ((1<<2)<<8) // Not sure about these values -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -92,22 +92,10 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" +#include <spd.h> #include "cpu/amd/dualcore/dualcore.c" -//first node -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -//second node -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 - - - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -87,17 +87,13 @@ #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" +#include <spd.h> //#include "spd_addr.h" #define RC00 0 #define RC01 1 -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -30,6 +30,7 @@ #include <cpu/amd/lxdef.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" +#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -50,9 +51,6 @@ /* Hold Count - how long we will sit in reset */ #define PLLMSRlo 0x00DE6000 -#define DIMM0 0xA0 -#define DIMM1 0xA2 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" Modified: trunk/src/mainboard/intel/truxton/romstage.c ============================================================================== --- trunk/src/mainboard/intel/truxton/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/intel/truxton/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -37,7 +37,7 @@ #include "cpu/x86/mtrr/earlymtrr.c" #include "superio/intel/i3100/i3100_early_serial.c" #include "cpu/x86/bist.h" -#include "spd.h" +#include <spd.h> #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0) Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -81,15 +81,7 @@ #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 +#include <spd.h> #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -81,15 +81,7 @@ #include "northbridge/amd/amdk8/resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 +#include <spd.h> #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -81,15 +81,7 @@ #include "northbridge/amd/amdk8/resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" - -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 +#include <spd.h> #include "cpu/amd/car/post_cache_as_ram.c" Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/jetway/pa78vm5/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -92,17 +92,11 @@ #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" - - +#include <spd.h> #define RC00 0 #define RC01 1 -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/kontron/kt690/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -21,9 +21,6 @@ #define RC0 (6<<8) #define RC1 (7<<8) -#define DIMM0 0x50 -#define DIMM1 0x51 - #define SMBUS_HUB 0x71 #include <stdint.h> @@ -40,6 +37,7 @@ #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" +#include <spd.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/lippert/frontrunner/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -11,15 +11,13 @@ #include <cpu/amd/gx2def.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5535/cs5535.h" +#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #include "southbridge/amd/cs5535/cs5535_early_smbus.c" #include "southbridge/amd/cs5535/cs5535_early_setup.c" -#define DIMM0 0xA0 -#define DIMM1 0xFF /* DIMM1 is not available/used on this board. */ - static const unsigned char spdbytes[] = { /* 4x Qimonda HYB25DC512160CF-6 */ 0xFF, 0xFF, /* only values used by raminit.c are set */ [SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, /* (Fundamental) memory type */ Modified: trunk/src/mainboard/lippert/hurricane-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/hurricane-lx/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/lippert/hurricane-lx/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -33,6 +33,7 @@ #include <cpu/amd/lxdef.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" +#include <spd.h> #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" @@ -44,8 +45,6 @@ #define ManualConf 1 /* No automatic strapped PLL config */ #define PLLMSRhi 0x0000049C /* Manual settings for the PLL */ #define PLLMSRlo 0x00DE6001 -#define DIMM0 0xA0 -#define DIMM1 0xA2 static inline int spd_read_byte(unsigned int device, unsigned int address) { Modified: trunk/src/mainboard/lippert/literunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/literunner-lx/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/lippert/literunner-lx/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -34,6 +34,7 @@ #include <cpu/amd/lxdef.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" +#include <spd.h> #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" @@ -49,8 +50,6 @@ #define ManualConf 1 /* No automatic strapped PLL config */ #define PLLMSRhi 0x0000059C /* Manual settings for the PLL */ #define PLLMSRlo 0x00DE6001 -#define DIMM0 0xA0 -#define DIMM1 0xA2 static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I 0xFF, 0xFF, // only values used by Geode-LX raminit.c are set Modified: trunk/src/mainboard/lippert/roadrunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -33,6 +33,7 @@ #include <cpu/amd/lxdef.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" +#include <spd.h> #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" @@ -41,8 +42,6 @@ #define ManualConf 1 /* No automatic strapped PLL config */ #define PLLMSRhi 0x0000049C /* Manual settings for the PLL */ #define PLLMSRlo 0x00DE6001 -#define DIMM0 0xA0 -#define DIMM1 0xA2 static inline int spd_read_byte(unsigned int device, unsigned int address) { Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -34,6 +34,7 @@ #include <cpu/amd/lxdef.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" +#include <spd.h> #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" @@ -49,8 +50,6 @@ #define ManualConf 1 /* No automatic strapped PLL config */ #define PLLMSRhi 0x0000059C /* Manual settings for the PLL */ #define PLLMSRlo 0x00DE6001 -#define DIMM0 0xA0 -#define DIMM1 0xA2 static const unsigned char spdbytes[] = { // 4x Promos V58C2512164SA-J5I 0xFF, 0xFF, // only values used by Geode-LX raminit.c are set Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/msi/ms9185/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -93,19 +93,11 @@ #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" +#include <spd.h> #define RC0 (0x10<<8) #define RC1 (0x01<<8) -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/pcengines/alix1c/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -32,6 +32,7 @@ #include <cpu/amd/lxdef.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" +#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -106,9 +107,6 @@ #define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ #define PLLMSRlo 0x02000030 -#define DIMM0 0xa0 -#define DIMM1 0xa2 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" Modified: trunk/src/mainboard/pcengines/alix2d/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix2d/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/pcengines/alix2d/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -32,6 +32,7 @@ #include <cpu/amd/lxdef.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" +#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -105,9 +106,6 @@ #define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ #define PLLMSRlo 0x02000030 -#define DIMM0 0xa0 -#define DIMM1 0xa2 - #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" #include "northbridge/amd/lx/raminit.c" Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -20,9 +20,6 @@ #define RC0 (6<<8) #define RC1 (7<<8) -#define DIMM0 0x50 -#define DIMM1 0x51 - #define SMBUS_HUB 0x71 #include <stdint.h> @@ -39,6 +36,7 @@ #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" +#include <spd.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -20,9 +20,6 @@ #define RC0 (6<<8) #define RC1 (7<<8) -#define DIMM0 0x50 -#define DIMM1 0x51 - #define SMBUS_HUB 0x71 #include <stdint.h> @@ -39,6 +36,7 @@ #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" +#include <spd.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" Modified: trunk/src/mainboard/traverse/geos/romstage.c ============================================================================== --- trunk/src/mainboard/traverse/geos/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/traverse/geos/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -31,6 +31,7 @@ #include <cpu/amd/lxdef.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" +#include <spd.h> #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" @@ -43,8 +44,6 @@ #define ManualConf 1 /* Do automatic strapped PLL config */ #define PLLMSRhi 0x0000059C /* manual settings for the PLL */ #define PLLMSRlo 0x00DE602E -#define DIMM0 0xA0 -#define DIMM1 0xA2 #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" Modified: trunk/src/mainboard/tyan/s4880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/tyan/s4880/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -84,19 +84,13 @@ #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" +#include <spd.h> #define RC0 ((1<<2)<<8) #define RC1 ((1<<1)<<8) #define RC2 ((1<<4)<<8) #define RC3 ((1<<3)<<8) -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - - - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/tyan/s4882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4882/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/tyan/s4882/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -92,19 +92,13 @@ #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" +#include <spd.h> #define RC0 ((1<<2)<<8) #define RC1 ((1<<1)<<8) #define RC2 ((1<<4)<<8) #define RC3 ((1<<3)<<8) -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - - - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/winent/pl6064/romstage.c ============================================================================== --- trunk/src/mainboard/winent/pl6064/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/winent/pl6064/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -32,6 +32,7 @@ #include <cpu/amd/lxdef.h> #include <cpu/amd/geode_post_code.h> #include "southbridge/amd/cs5536/cs5536.h" +#include <spd.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -47,8 +48,6 @@ #define ManualConf 0 /* Do automatic strapped PLL config */ #define PLLMSRhi 0x00001490 /* Manual settings for the PLL */ #define PLLMSRlo 0x02000030 -#define DIMM0 0xA0 -#define DIMM1 0xA2 #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" Modified: trunk/src/mainboard/wyse/s50/romstage.c ============================================================================== --- trunk/src/mainboard/wyse/s50/romstage.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/mainboard/wyse/s50/romstage.c Sat Nov 20 11:31:00 2010 (r6099) @@ -30,13 +30,11 @@ #include "cpu/x86/msr.h" #include <cpu/amd/gx2def.h> #include <cpu/amd/geode_post_code.h> +#include <spd.h> #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" -#define DIMM0 0xA0 -#define DIMM1 0xFF /* DIMM1 is not available/used on this board. */ - static inline int spd_read_byte(unsigned int device, unsigned int address) { if (device != DIMM0) Modified: trunk/src/northbridge/via/cx700/cx700_early_smbus.c ============================================================================== --- trunk/src/northbridge/via/cx700/cx700_early_smbus.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/northbridge/via/cx700/cx700_early_smbus.c Sat Nov 20 11:31:00 2010 (r6099) @@ -37,7 +37,6 @@ /* Define register settings */ #define HOST_RESET 0xff -#define DIMM_BASE 0xa0 // 1010000 is base for DIMM in SMBus #define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ #define SMBUS_TIMEOUT (100*1000*10) Modified: trunk/src/northbridge/via/vx800/vx800_early_smbus.c ============================================================================== --- trunk/src/northbridge/via/vx800/vx800_early_smbus.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/northbridge/via/vx800/vx800_early_smbus.c Sat Nov 20 11:31:00 2010 (r6099) @@ -40,7 +40,6 @@ /* Define register settings */ #define HOST_RESET 0xff -#define DIMM_BASE 0xa0 // 1010000 is base for DIMM in SMBus #define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ #define SMBUS_TIMEOUT (100*1000*10) @@ -121,9 +120,7 @@ smbus_wait_until_ready(); /* Do some mathmatic magic */ - dimm = (dimm << 1); - dimm &= 0x0E; - dimm |= 0xA0; + dimm = (DIMM0 + dimm) << 1; outb(dimm | 0x1, SMBXMITADD); outb(offset, SMBHSTCMD); Modified: trunk/src/southbridge/amd/cs5536/cs5536_early_smbus.c ============================================================================== --- trunk/src/southbridge/amd/cs5536/cs5536_early_smbus.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/southbridge/amd/cs5536/cs5536_early_smbus.c Sat Nov 20 11:31:00 2010 (r6099) @@ -165,7 +165,7 @@ goto err; } - if ((smbus_send_slave_address(smbus_io_base, device))) { + if ((smbus_send_slave_address(smbus_io_base, device << 1))) { error = 3; goto err; } @@ -182,7 +182,7 @@ goto err; } - if ((smbus_send_slave_address(smbus_io_base, device | 0x01))) { + if ((smbus_send_slave_address(smbus_io_base, (device << 1) | 0x01))) { error = 6; goto err; } Modified: trunk/src/southbridge/via/vt8231/vt8231_early_smbus.c ============================================================================== --- trunk/src/southbridge/via/vt8231/vt8231_early_smbus.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/southbridge/via/vt8231/vt8231_early_smbus.c Sat Nov 20 11:31:00 2010 (r6099) @@ -16,7 +16,6 @@ /* Define register settings */ #define HOST_RESET 0xff -#define DIMM_BASE 0xa0 // 1010000 is base for DIMM in SMBus #define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ Modified: trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c ============================================================================== --- trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c Fri Nov 19 16:14:42 2010 (r6098) +++ trunk/src/southbridge/via/vt8235/vt8235_early_smbus.c Sat Nov 20 11:31:00 2010 (r6099) @@ -16,7 +16,6 @@ /* Define register settings */ #define HOST_RESET 0xff -#define DIMM_BASE 0xa0 // 1010000 is base for DIMM in SMBus #define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ

1 0

[PATCH]Refactor SPDROM access
by Patrick Georgi 20 Nov '10

20 Nov '10

Hi, attached patch cleans up SPDROM access and gets rid of the DIMMx definitions in romstage.cs (in favor of a single set of them in spd.h). Of special note is that amd/cs5535 and amd/cs5536 used different values for DIMMx: These were simply bitshifted. Their only use is in smbus_read_byte (pre-ram variant, which doesn't seem to be used for anything else), so I adapted their version to do the same bitshift the other implementations do. That way, they can reuse the same DIMMx defines, too. A later change would be to move the 90% of spd_read_byte implementations in the boards to a unified one (weak function) that can be overridden by boards that really behave differently (eg. those with fixed RAM without SPD ROMs). The single-DIMM special case could be accomodated with a Kconfig variable then. The patch is untested, so please review carefully. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>

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coreboot November 2010