[commit] r6108 - in trunk/src: mainboard/amd/db800 mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/norwich mainboard/amd/pistachio mainboard/amd/serengeti_ch...
by repository service 21 Nov '10
by repository service 21 Nov '10
21 Nov '10
Author: uwe
Date: Sun Nov 21 23:47:22 2010
New Revision: 6108
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6108
Log:
Simplify a few code chunks, fix whitespace and indentation.
Also, remove some less useful comments, some dead code / unused functions.
Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de>
Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de>
Modified:
trunk/src/mainboard/amd/db800/romstage.c
trunk/src/mainboard/amd/dbm690t/romstage.c
trunk/src/mainboard/amd/mahogany/romstage.c
trunk/src/mainboard/amd/mahogany_fam10/romstage.c
trunk/src/mainboard/amd/norwich/romstage.c
trunk/src/mainboard/amd/pistachio/romstage.c
trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
trunk/src/mainboard/amd/tilapia_fam10/romstage.c
trunk/src/mainboard/arima/hdama/romstage.c
trunk/src/mainboard/artecgroup/dbe61/romstage.c
trunk/src/mainboard/asi/mb_5blmp/romstage.c
trunk/src/mainboard/asrock/939a785gmh/romstage.c
trunk/src/mainboard/asus/a8n_e/romstage.c
trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c
trunk/src/mainboard/asus/a8v-e_se/romstage.c
trunk/src/mainboard/asus/m2v-mx_se/romstage.c
trunk/src/mainboard/asus/m2v/romstage.c
trunk/src/mainboard/asus/m4a785-m/romstage.c
trunk/src/mainboard/bcom/winnet100/romstage.c
trunk/src/mainboard/bcom/winnetp680/romstage.c
trunk/src/mainboard/broadcom/blast/romstage.c
trunk/src/mainboard/dell/s1850/romstage.c
trunk/src/mainboard/digitallogic/adl855pc/romstage.c
trunk/src/mainboard/digitallogic/msm586seg/romstage.c
trunk/src/mainboard/digitallogic/msm800sev/romstage.c
trunk/src/mainboard/eaglelion/5bcm/romstage.c
trunk/src/mainboard/emulation/qemu-x86/romstage.c
trunk/src/mainboard/getac/p470/romstage.c
trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
trunk/src/mainboard/gigabyte/m57sli/romstage.c
trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
trunk/src/mainboard/gigabyte/ma78gm/romstage.c
trunk/src/mainboard/hp/dl145_g1/romstage.c
trunk/src/mainboard/hp/dl145_g3/romstage.c
trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c
trunk/src/mainboard/ibase/mb899/romstage.c
trunk/src/mainboard/ibm/e325/romstage.c
trunk/src/mainboard/ibm/e326/romstage.c
trunk/src/mainboard/iei/juki-511p/romstage.c
trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
trunk/src/mainboard/iei/nova4899r/romstage.c
trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
trunk/src/mainboard/intel/d945gclf/romstage.c
trunk/src/mainboard/intel/eagleheights/romstage.c
trunk/src/mainboard/intel/jarrell/romstage.c
trunk/src/mainboard/intel/truxton/romstage.c
trunk/src/mainboard/intel/xe7501devkit/romstage.c
trunk/src/mainboard/iwill/dk8_htx/romstage.c
trunk/src/mainboard/iwill/dk8s2/romstage.c
trunk/src/mainboard/iwill/dk8x/romstage.c
trunk/src/mainboard/jetway/j7f24/romstage.c
trunk/src/mainboard/jetway/pa78vm5/romstage.c
trunk/src/mainboard/kontron/986lcd-m/romstage.c
trunk/src/mainboard/kontron/kt690/romstage.c
trunk/src/mainboard/lanner/em8510/romstage.c
trunk/src/mainboard/lippert/frontrunner/romstage.c
trunk/src/mainboard/msi/ms7135/romstage.c
trunk/src/mainboard/msi/ms7260/romstage.c
trunk/src/mainboard/msi/ms9185/romstage.c
trunk/src/mainboard/msi/ms9282/romstage.c
trunk/src/mainboard/msi/ms9652_fam10/romstage.c
trunk/src/mainboard/newisys/khepri/romstage.c
trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
trunk/src/mainboard/pcengines/alix1c/romstage.c
trunk/src/mainboard/pcengines/alix2d/romstage.c
trunk/src/mainboard/rca/rm4100/romstage.c
trunk/src/mainboard/roda/rk886ex/romstage.c
trunk/src/mainboard/sunw/ultra40/romstage.c
trunk/src/mainboard/supermicro/h8dme/romstage.c
trunk/src/mainboard/supermicro/h8dmr/romstage.c
trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
trunk/src/mainboard/supermicro/x6dai_g/romstage.c
trunk/src/mainboard/supermicro/x6dhe_g/romstage.c
trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c
trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c
trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c
trunk/src/mainboard/technexion/tim5690/romstage.c
trunk/src/mainboard/technexion/tim8690/romstage.c
trunk/src/mainboard/televideo/tc7020/romstage.c
trunk/src/mainboard/thomson/ip1000/romstage.c
trunk/src/mainboard/traverse/geos/romstage.c
trunk/src/mainboard/tyan/s2735/romstage.c
trunk/src/mainboard/tyan/s2850/romstage.c
trunk/src/mainboard/tyan/s2875/romstage.c
trunk/src/mainboard/tyan/s2880/romstage.c
trunk/src/mainboard/tyan/s2881/romstage.c
trunk/src/mainboard/tyan/s2882/romstage.c
trunk/src/mainboard/tyan/s2885/romstage.c
trunk/src/mainboard/tyan/s2891/romstage.c
trunk/src/mainboard/tyan/s2892/romstage.c
trunk/src/mainboard/tyan/s2895/romstage.c
trunk/src/mainboard/tyan/s2912/romstage.c
trunk/src/mainboard/tyan/s2912_fam10/romstage.c
trunk/src/mainboard/tyan/s4880/romstage.c
trunk/src/mainboard/tyan/s4882/romstage.c
trunk/src/mainboard/via/epia-cn/romstage.c
trunk/src/mainboard/via/epia-m/romstage.c
trunk/src/mainboard/via/epia-m700/romstage.c
trunk/src/mainboard/via/epia-n/romstage.c
trunk/src/mainboard/via/epia/romstage.c
trunk/src/mainboard/via/pc2500e/romstage.c
trunk/src/mainboard/winent/pl6064/romstage.c
trunk/src/mainboard/wyse/s50/romstage.c
trunk/src/northbridge/via/vx800/examples/romstage.c
Modified: trunk/src/mainboard/amd/db800/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/db800/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/amd/db800/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -54,11 +54,6 @@
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void)
-{
- /* Early mainboard specific GPIO setup. */
-}
-
void main(unsigned long bist)
{
post_code(0x01);
@@ -76,7 +71,6 @@
* early MSR setup for CS5536.
*/
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- mb_gpio_init();
uart_init();
console_init();
Modified: trunk/src/mainboard/amd/dbm690t/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/amd/dbm690t/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -47,17 +47,9 @@
#include "southbridge/amd/sb600/sb600_early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-/* called in raminit_f.c */
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@@ -88,14 +80,12 @@
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
-
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
enable_rs690_dev8();
sb600_lpc_init();
@@ -135,8 +125,7 @@
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
- if( (cpuid1.edx & 0x6) == 0x6 ) {
-
+ if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@@ -148,7 +137,6 @@
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
Modified: trunk/src/mainboard/amd/mahogany/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/amd/mahogany/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -47,17 +47,9 @@
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-/* called in raminit_f.c */
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@@ -88,14 +80,12 @@
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
-
/* sb700_lpc_port80(); */
sb700_pci_port80();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
enable_rs780_dev8();
sb700_lpc_init();
@@ -134,8 +124,7 @@
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
- if( (cpuid1.edx & 0x6) == 0x6 ) {
-
+ if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@@ -147,7 +136,6 @@
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -53,15 +53,11 @@
#include "northbridge/amd/amdfam10/debug.c"
#include <spd.h>
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- int result;
- result = smbus_read_byte(device, address);
- return result;
+ return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@ -78,11 +74,9 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@@ -91,7 +85,6 @@
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sb700_pci_port80();
}
Modified: trunk/src/mainboard/amd/norwich/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/norwich/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/amd/norwich/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -51,11 +51,6 @@
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void)
-{
- /* Early mainboard specific GPIO setup. */
-}
-
void main(unsigned long bist)
{
post_code(0x01);
@@ -77,7 +72,6 @@
*/
/* If debug. real setup done in chipset init via devicetree.cb. */
cs5536_setup_onchipuart(1);
- mb_gpio_init();
uart_init();
console_init();
Modified: trunk/src/mainboard/amd/pistachio/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/pistachio/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/amd/pistachio/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -42,17 +42,9 @@
#include "southbridge/amd/sb600/sb600_early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
-/* CAN'T BE REMOVED! memory bus reset hook for some broken amd k8 boards. */
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-/* called in raminit_f.c */
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@@ -85,14 +77,12 @@
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
-
sb600_lpc_port80();
/* sb600_pci_port80(); */
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
enable_rs690_dev8();
sb600_lpc_init();
@@ -138,8 +128,7 @@
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
- if( (cpuid1.edx & 0x6) == 0x6 ) {
-
+ if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@@ -151,7 +140,6 @@
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -33,13 +33,11 @@
static void memreset_setup(void)
{
//GPIO on amd8111 to enable MEMRST ????
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
@@ -54,6 +52,7 @@
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
+
#if 0
static inline void change_i2c_mux(unsigned device)
{
@@ -80,7 +79,7 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c" /* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@@ -117,7 +116,6 @@
};
struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset;
unsigned bsp_apicid = 0;
#if CONFIG_SET_FIDVID
@@ -127,18 +125,12 @@
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
- /* Setup the rom access for 4M */
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
-
-// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -188,20 +180,17 @@
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
- if( (cpuid1.edx & 0x6) == 0x6 ) {
+ if ((cpuid1.edx & 0x6) == 0x6) {
{
/* Read FIDVID_STATUS */
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
// show final fid and vid
@@ -209,13 +198,11 @@
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
} else {
print_debug("Changing FIDVID not supported\n");
}
-
#endif
#if 1
Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -55,8 +55,8 @@
static void memreset_setup(void)
{
//GPIO on amd8111 to enable MEMRST ????
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN=1
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void activate_spd_rom(const struct mem_controller *ctrl)
@@ -77,9 +77,7 @@
static int spd_read_byte(u32 device, u32 address)
{
- int result;
- result = smbus_read_byte(device, address);
- return result;
+ return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@ -190,8 +188,7 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -52,15 +52,11 @@
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- int result;
- result = smbus_read_byte(device, address);
- return result;
+ return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@ -78,11 +74,9 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@@ -91,7 +85,6 @@
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sb700_pci_port80();
}
@@ -157,13 +150,13 @@
*/
wait_all_core0_started();
- #if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS==1
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
- #endif
+#endif
post_code(0x38);
@@ -171,7 +164,7 @@
rs780_early_setup();
sb700_early_setup();
- #if CONFIG_SET_FIDVID
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
@@ -192,7 +185,7 @@
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
- #endif
+#endif
rs780_htinit();
Modified: trunk/src/mainboard/arima/hdama/romstage.c
==============================================================================
--- trunk/src/mainboard/arima/hdama/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/arima/hdama/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -32,14 +32,13 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
- }
- else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Set the memreset low. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Ensure the BIOS has control of the memory lines. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ } else {
+ /* Ensure the CPU has control of the memory lines. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
@@ -47,16 +46,13 @@
{
if (is_cpu_pre_c0()) {
udelay(800);
- /* Set memreset_high */
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Set memreset high. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -85,22 +81,18 @@
};
int needs_reset;
- unsigned bsp_apicid = 0;
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
Modified: trunk/src/mainboard/artecgroup/dbe61/romstage.c
==============================================================================
--- trunk/src/mainboard/artecgroup/dbe61/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/artecgroup/dbe61/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -66,11 +66,6 @@
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void)
-{
- /* Early mainboard specific GPIO setup */
-}
-
void main(unsigned long bist)
{
post_code(0x01);
@@ -96,7 +91,6 @@
msr.lo |= 0x7 << 20;
wrmsr(MDD_LEG_IO, msr);
- mb_gpio_init();
uart_init();
console_init();
@@ -109,7 +103,7 @@
sdram_initialize(1, memctrl);
- /* Dump memory configuratation */
+ /* Dump memory configuration. */
#if 0
msr = rdmsr(MC_CF07_DATA);
print_debug("MC_CF07_DATA: ");
Modified: trunk/src/mainboard/asi/mb_5blmp/romstage.c
==============================================================================
--- trunk/src/mainboard/asi/mb_5blmp/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/asi/mb_5blmp/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -35,20 +35,11 @@
static void main(unsigned long bist)
{
- /* Initialize the serial console. */
pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
-
- /* Halt if there was a built in self test failure. */
report_bist_failure(bist);
-
cs5530_enable_rom();
-
- /* Initialize RAM. */
sdram_init();
-
- /* Check whether RAM works. */
/* ram_check(0x00000000, 0x4000); */
}
-
Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -52,17 +52,9 @@
#define GPIO6_DEV PNP_DEV(0x2e, W83627DHG_GPIO6)
#define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345)
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-/* called in raminit_f.c */
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@@ -140,14 +132,12 @@
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
-
/* sb700_lpc_port80(); */
sb700_pci_port80();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
enable_rs780_dev8();
sb700_lpc_init();
@@ -187,8 +177,7 @@
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
- if( (cpuid1.edx & 0x6) == 0x6 ) {
-
+ if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@@ -200,7 +189,6 @@
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
Modified: trunk/src/mainboard/asus/a8n_e/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8n_e/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/asus/a8n_e/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -50,15 +50,8 @@
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
- /* Nothing to do. */
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* Nothing to do. */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -108,7 +101,6 @@
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
-
sio_setup();
}
@@ -138,7 +130,6 @@
needs_reset |= ht_setup_chains_x();
needs_reset |= ck804_early_setup_x();
-
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
Modified: trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -52,19 +52,14 @@
#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
-
#include <reset.h>
void soft_reset(void)
{
Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_se/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -52,19 +52,14 @@
#define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED)
#define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
-
#include <reset.h>
void soft_reset(void)
{
Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -54,19 +54,14 @@
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
-
// defines S3_NVRAM_EARLY:
#include "southbridge/via/k8t890/k8t890_early_car.c"
#include "northbridge/amd/amdk8/amdk8.h"
Modified: trunk/src/mainboard/asus/m2v/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m2v/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/asus/m2v/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -56,19 +56,14 @@
#define IT8712F_GPIO_BASE 0x0a20
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
-
// defines S3_NVRAM_EARLY:
#include "southbridge/via/k8t890/k8t890_early_car.c"
#include "northbridge/amd/amdk8/amdk8.h"
Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/asus/m4a785-m/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -52,15 +52,11 @@
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- int result;
- result = smbus_read_byte(device, address);
- return result;
+ return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@ -78,11 +74,9 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@@ -91,7 +85,6 @@
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sb700_pci_port80();
}
@@ -108,7 +101,7 @@
sb700_lpc_init();
it8712f_enable_serial(0, CONFIG_TTYS0_BASE);
- it8712f_kill_watchdog(); /* disable watchdog, so it does not reset while still booting */
+ it8712f_kill_watchdog();
uart_init();
#if CONFIG_USBDEBUG
Modified: trunk/src/mainboard/bcom/winnet100/romstage.c
==============================================================================
--- trunk/src/mainboard/bcom/winnet100/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/bcom/winnet100/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -35,20 +35,11 @@
static void main(unsigned long bist)
{
- /* Initialize the serial console. */
pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
-
- /* Halt if there was a built in self test failure. */
report_bist_failure(bist);
-
cs5530_enable_rom();
-
- /* Initialize RAM. */
sdram_init();
-
- /* Check whether RAM works. */
/* ram_check(0, 640 * 1024); */
}
-
Modified: trunk/src/mainboard/bcom/winnetp680/romstage.c
==============================================================================
--- trunk/src/mainboard/bcom/winnetp680/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/bcom/winnetp680/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -47,7 +47,8 @@
static void enable_mainboard_devices(void)
{
device_t dev;
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
@@ -85,26 +86,19 @@
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
w83697hf_set_clksel_48(SERIAL_DEV);
-
w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
- print_spew("In romstage.c:main()\n");
-
enable_smbus();
smbus_fixup(&ctrl);
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
- print_debug("Enabling mainboard devices\n");
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
/* ram_check(0, 640 * 1024); */
-
- print_spew("Leaving romstage.c:main()\n");
}
-
Modified: trunk/src/mainboard/broadcom/blast/romstage.c
==============================================================================
--- trunk/src/mainboard/broadcom/blast/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/broadcom/blast/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -26,13 +26,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset_setup(void) { }
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
@@ -60,7 +55,7 @@
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c" /* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@@ -80,36 +75,23 @@
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
bcm5785_enable_rom();
-
bcm5785_enable_lpc();
-
- //enable RTC
- pc87417_enable_dev(RTC_DEV);
+ pc87417_enable_dev(RTC_DEV); /* Enable RTC */
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
-// post_code(0x32);
pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-// post_code(0x33);
-
uart_init();
-// post_code(0x34);
-
console_init();
/* Halt if there was a built in self test failure */
@@ -166,9 +148,6 @@
#if 0
print_pci_devices();
-#endif
-
-#if 0
dump_pci_devices();
#endif
Modified: trunk/src/mainboard/dell/s1850/romstage.c
==============================================================================
--- trunk/src/mainboard/dell/s1850/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/dell/s1850/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -67,6 +67,7 @@
while((inb(ipmicsr) & (1<<OBF)) == 0)
;
}
+
/* quite possibly the stupidest interface ever designed. */
static inline void first_cmd_byte(unsigned char byte)
{
@@ -154,12 +155,6 @@
static const struct mem_controller mch[] = {
{
.node_id = 0,
- /*
- .f0 = PCI_DEV(0, 0x00, 0),
- .f1 = PCI_DEV(0, 0x00, 1),
- .f2 = PCI_DEV(0, 0x00, 2),
- .f3 = PCI_DEV(0, 0x00, 3),
- */
/* the wiring on this part is really messed up */
/* this is my best guess so far */
.channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
@@ -260,9 +255,8 @@
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized()) {
+ if (memory_initialized())
skip_romstage();
- }
}
/* Setup the console */
mainboard_set_ich5();
@@ -311,9 +305,8 @@
#if 0
// dump_spd_registers(&cpu[0]);
int i;
- for(i = 0; i < 1; i++) {
+ for(i = 0; i < 1; i++)
dump_spd_registers();
- }
#endif
#if 1
show_dram_slots();
Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/adl855pc/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -55,13 +55,12 @@
print_pci_devices();
#endif
- if(!bios_reset_detected()) {
+ if (!bios_reset_detected()) {
enable_smbus();
#if 0
dump_spd_registers(&memctrl[0]);
dump_smbus_registers();
#endif
-
sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
}
Modified: trunk/src/mainboard/digitallogic/msm586seg/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/msm586seg/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/digitallogic/msm586seg/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -42,10 +42,7 @@
int i;
};
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
-// return smbus_read_byte(device, address);
-}
+static int spd_read_byte(unsigned device, unsigned address) { }
static inline void dumpmem(void){
int i, j;
Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/msm800sev/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -20,7 +20,7 @@
static inline int spd_read_byte(unsigned device, unsigned address)
{
- return smbus_read_byte(device, address);
+ return smbus_read_byte(device, address);
}
#define ManualConf 0 /* Do automatic strapped PLL config */
@@ -35,11 +35,6 @@
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void)
-{
- /* Early mainboard specific GPIO setup */
-}
-
void main(unsigned long bist)
{
post_code(0x01);
@@ -59,7 +54,6 @@
*/
cs5536_disable_internal_uart();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- mb_gpio_init();
uart_init();
console_init();
Modified: trunk/src/mainboard/eaglelion/5bcm/romstage.c
==============================================================================
--- trunk/src/mainboard/eaglelion/5bcm/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/eaglelion/5bcm/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -19,32 +19,7 @@
pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
-
- /* Halt if there was a built in self test failure */
report_bist_failure(bist);
-
cs5530_enable_rom();
-
sdram_init();
-
- /* Check all of memory */
-#if 0
- ram_check(0x00000000, msr.lo);
-#endif
-#if 0
- static const struct {
- unsigned long lo, hi;
- } check_addrs[] = {
- /* Check 16MB of memory @ 0*/
- { 0x00000000, 0x01000000 },
-#if TOTAL_CPUS > 1
- /* Check 16MB of memory @ 2GB */
- { 0x80000000, 0x81000000 },
-#endif
- };
- int i;
- for(i = 0; i < ARRAY_SIZE(check_addrs); i++) {
- ram_check(check_addrs[i].lo, check_addrs[i].hi);
- }
-#endif
}
Modified: trunk/src/mainboard/emulation/qemu-x86/romstage.c
==============================================================================
--- trunk/src/mainboard/emulation/qemu-x86/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/emulation/qemu-x86/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -13,7 +13,7 @@
static void main(void)
{
- /* init_timer();*/
+ /* init_timer(); */
post_code(0x05);
uart_init();
@@ -22,4 +22,3 @@
//print_pci_devices();
//dump_pci_devices();
}
-
Modified: trunk/src/mainboard/getac/p470/romstage.c
==============================================================================
--- trunk/src/mainboard/getac/p470/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/getac/p470/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -277,9 +277,8 @@
u32 reg32;
int boot_mode = 0;
- if (bist == 0) {
+ if (bist == 0)
enable_lapic();
- }
#if 0
/* Force PCIRST# */
Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -56,14 +56,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -119,35 +113,29 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
+ // Node 0
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
+ // Node 1
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the sis966 */
sis966_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x23, 0);
@@ -194,21 +182,15 @@
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
-
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif
Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -53,14 +53,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -111,17 +105,16 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
+ // Node 0
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
+ // Node 1
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset = 0;
unsigned bsp_apicid = 0;
uint8_t tmp = 0;
@@ -129,18 +122,13 @@
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
pnp_enter_ext_func_mode(SERIAL_DEV);
/* The following line will set CLKIN to 24 MHz, external */
@@ -153,9 +141,6 @@
/* Set Serial Flash interface to 0x0820 */
pnp_write_config(GPIO_DEV, 0x64, 0x08);
pnp_write_config(GPIO_DEV, 0x65, 0x20);
- /* We can get away with not resetting the logical device because
- * it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE) will do that.
- */
}
it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
pnp_exit_ext_func_mode(SERIAL_DEV);
@@ -200,21 +185,15 @@
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
-
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif
Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -48,15 +48,11 @@
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- int result;
- result = smbus_read_byte(device, address);
- return result;
+ return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@ -76,8 +72,7 @@
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@@ -86,7 +81,6 @@
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sb700_pci_port80();
}
@@ -153,13 +147,13 @@
*/
wait_all_core0_started();
- #if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS==1
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
- #endif
+#endif
post_code(0x38);
@@ -167,7 +161,7 @@
rs780_early_setup();
sb700_early_setup();
- #if CONFIG_SET_FIDVID
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
@@ -188,7 +182,7 @@
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
- #endif
+#endif
rs780_htinit();
Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -52,15 +52,11 @@
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- int result;
- result = smbus_read_byte(device, address);
- return result;
+ return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@ -80,8 +76,7 @@
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@@ -90,7 +85,6 @@
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sb700_pci_port80();
}
@@ -155,13 +149,13 @@
*/
wait_all_core0_started();
- #if CONFIG_LOGICAL_CPUS==1
+#if CONFIG_LOGICAL_CPUS==1
/* Core0 on each node is configured. Now setup any additional cores. */
printk(BIOS_DEBUG, "start_other_cores()\n");
start_other_cores();
post_code(0x37);
wait_all_other_cores_started(bsp_apicid);
- #endif
+#endif
post_code(0x38);
@@ -169,7 +163,7 @@
rs780_early_setup();
sb700_early_setup();
- #if CONFIG_SET_FIDVID
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
@@ -190,7 +184,7 @@
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
- #endif
+#endif
rs780_htinit();
Modified: trunk/src/mainboard/hp/dl145_g1/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g1/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/hp/dl145_g1/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -27,13 +27,13 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ /* Set the memreset low. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ /* Ensure the BIOS has control of the memory lines. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
} else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ /* Ensure the CPU has control of the memory lines. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
}
@@ -41,8 +41,8 @@
{
if (is_cpu_pre_c0()) {
udelay(800);
- /* Set memreset_high */
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ /* Set memreset high. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
udelay(90);
}
}
@@ -97,37 +97,29 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
- //first node
- RC0|DIMM0, RC0|DIMM2, 0, 0,
- RC0|DIMM1, RC0|DIMM3, 0, 0,
+ //first node
+ RC0|DIMM0, RC0|DIMM2, 0, 0,
+ RC0|DIMM1, RC0|DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
- //second node
- RC1|DIMM0, RC1|DIMM2, 0, 0,
- RC1|DIMM1, RC1|DIMM3, 0, 0,
+ //second node
+ RC1|DIMM0, RC1|DIMM2, 0, 0,
+ RC1|DIMM1, RC1|DIMM3, 0, 0,
#endif
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
- /* Setup the amd8111 */
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
-
-// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g3/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/hp/dl145_g3/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -59,9 +59,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
@@ -133,7 +131,6 @@
// first node
DIMM0, DIMM2, 0, 0,
DIMM1, DIMM3, 0, 0,
-
// second node
DIMM4, DIMM6, 0, 0,
DIMM5, DIMM7, 0, 0,
@@ -141,24 +138,20 @@
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
bcm5785_enable_rom();
bcm5785_enable_lpc();
- //enable RTC
- pc87417_enable_dev(RTC_DEV);
+ pc87417_enable_dev(RTC_DEV); /* Enable RTC */
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Modified: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -100,30 +100,24 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
- /* Nothing special needs to be done to find bus 0 */
+ /* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
- /* Setup the rom access for 4M */
bcm5785_enable_rom();
bcm5785_enable_lpc();
- //enable RTC
- pc87417_enable_dev(RTC_DEV);
+ pc87417_enable_dev(RTC_DEV); /* Enable RTC */
}
post_code(0x30);
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Modified: trunk/src/mainboard/ibase/mb899/romstage.c
==============================================================================
--- trunk/src/mainboard/ibase/mb899/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/ibase/mb899/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -239,9 +239,8 @@
u32 reg32;
int boot_mode = 0;
- if (bist == 0) {
+ if (bist == 0)
enable_lapic();
- }
ich7_enable_lpc();
early_superio_config_w83627ehg();
Modified: trunk/src/mainboard/ibm/e325/romstage.c
==============================================================================
--- trunk/src/mainboard/ibm/e325/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/ibm/e325/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -29,13 +29,13 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ /* Set the memreset low. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ /* Ensure the BIOS has control of the memory lines. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
} else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ /* Ensure the CPU has control of the memory lines. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
}
@@ -43,16 +43,13 @@
{
if (is_cpu_pre_c0()) {
udelay(800);
- /* Set memreset_high */
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ /* Set memreset high. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -99,15 +96,12 @@
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
init_cpus(cpu_init_detectedx);
- }
pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
Modified: trunk/src/mainboard/ibm/e326/romstage.c
==============================================================================
--- trunk/src/mainboard/ibm/e326/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/ibm/e326/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -29,13 +29,13 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ /* Set the memreset low. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ /* Ensure the BIOS has control of the memory lines. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
} else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ /* Ensure the CPU has control of the memory lines. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
}
@@ -43,16 +43,13 @@
{
if (is_cpu_pre_c0()) {
udelay(800);
- /* Set memreset_high */
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
+ /* Set memreset high. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16);
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -99,15 +96,12 @@
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
init_cpus(cpu_init_detectedx);
- }
pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
Modified: trunk/src/mainboard/iei/juki-511p/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/juki-511p/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/iei/juki-511p/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -36,12 +36,9 @@
static void main(unsigned long bist)
{
- /* Initialize the serial console. */
w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
-
- /* Halt if there was a built in self test failure. */
report_bist_failure(bist);
/* Disable Watchdog Timer. */
@@ -49,10 +46,6 @@
inb(0x843);
cs5530_enable_rom();
-
- /* Initialize RAM. */
sdram_init();
-
- /* Check RAM. */
/* ram_check(0x00000000, 640 * 1024); */
}
Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -25,9 +25,6 @@
#define FAM10_SCAN_PCI_BUS 0
#define FAM10_ALLOCATE_IO_RANGE 0
-/* UART address and device number */
-#define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -55,15 +52,13 @@
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+#define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1)
+
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
- int result;
- result = smbus_read_byte(device, address);
- return result;
+ return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
@@ -81,11 +76,9 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@@ -94,7 +87,6 @@
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sb700_pci_port80();
}
Modified: trunk/src/mainboard/iei/nova4899r/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/nova4899r/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/iei/nova4899r/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -36,19 +36,11 @@
static void main(unsigned long bist)
{
- /* Initialize the serial console. */
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
-
- /* Halt if there was a built in self test failure. */
report_bist_failure(bist);
-
cs5530_enable_rom();
-
- /* Initialize RAM. */
sdram_init();
-
- /* Check RAM. */
/* ram_check(0x00000000, 640 * 1024); */
}
Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -58,11 +58,6 @@
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void)
-{
- /* Early mainboard specific GPIO setup. */
-}
-
void main(unsigned long bist)
{
post_code(0x01);
@@ -80,7 +75,6 @@
* early MSR setup for CS5536.
*/
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- mb_gpio_init();
uart_init();
console_init();
Modified: trunk/src/mainboard/intel/d945gclf/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/d945gclf/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/intel/d945gclf/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -201,9 +201,8 @@
u32 reg32;
int boot_mode = 0;
- if (bist == 0) {
+ if (bist == 0)
enable_lapic();
- }
ich7_enable_lpc();
early_superio_config_lpc47m15x();
Modified: trunk/src/mainboard/intel/eagleheights/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/eagleheights/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/intel/eagleheights/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -138,9 +138,8 @@
}
};
- if (bist == 0) {
+ if (bist == 0)
enable_lapic();
- }
/* Setup the console */
i3100_enable_superio();
Modified: trunk/src/mainboard/intel/jarrell/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/jarrell/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/intel/jarrell/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -45,12 +45,6 @@
static const struct mem_controller mch[] = {
{
.node_id = 0,
- /*
- .f0 = PCI_DEV(0, 0x00, 0),
- .f1 = PCI_DEV(0, 0x00, 1),
- .f2 = PCI_DEV(0, 0x00, 2),
- .f3 = PCI_DEV(0, 0x00, 3),
- */
.channel0 = { DIMM2, DIMM1, DIMM0, 0 },
.channel1 = { DIMM6, DIMM5, DIMM4, 0 },
}
@@ -59,9 +53,8 @@
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized()) {
+ if (memory_initialized())
skip_romstage();
- }
}
/* Setup the console */
@@ -86,9 +79,8 @@
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
- if (dev == PCI_DEV_INVALID) {
+ if (dev == PCI_DEV_INVALID)
die("Missing ich5?");
- }
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
@@ -99,9 +91,8 @@
#if 0
// dump_spd_registers(&cpu[0]);
int i;
- for(i = 0; i < 1; i++) {
+ for(i = 0; i < 1; i++)
dump_spd_registers();
- }
#endif
disable_watchdogs();
power_down_reset_check();
@@ -111,8 +102,6 @@
ich5_watchdog_on();
#if 0
dump_pci_devices();
-#endif
-#if 0
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
Modified: trunk/src/mainboard/intel/truxton/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/truxton/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/intel/truxton/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -68,9 +68,8 @@
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized()) {
+ if (memory_initialized())
skip_romstage();
- }
}
/* Set up the console */
Modified: trunk/src/mainboard/intel/xe7501devkit/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/xe7501devkit/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/intel/xe7501devkit/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -46,15 +46,13 @@
},
};
- if (bist == 0)
- {
+ if (bist == 0) {
// Skip this if there was a built in self test failure
early_mtrr_init();
enable_lapic();
}
// Get the serial port running and print a welcome banner
-
lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -35,13 +35,13 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Set the memreset low. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Ensure the BIOS has control of the memory lines. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
} else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Ensure the CPU has control of the memory lines. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
@@ -50,14 +50,12 @@
if (is_cpu_pre_c0()) {
udelay(800);
/* Set memreset_high */
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -69,7 +67,7 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c" /* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@@ -81,34 +79,28 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
- // first node
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
-
- // second node
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
+ // first node
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
+ // second node
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
- /* Setup the rom access for 4M */
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -143,26 +135,19 @@
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
-
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
-
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif
Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8s2/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/iwill/dk8s2/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -35,13 +35,13 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Set the memreset low. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Ensure the BIOS has control of the memory lines. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
} else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Ensure the CPU has control of the memory lines. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
@@ -49,15 +49,13 @@
{
if (is_cpu_pre_c0()) {
udelay(800);
- /* Set memreset_high */
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Set memreset high. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -69,7 +67,7 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
-#include "northbridge/amd/amdk8/resourcemap.c" /* tyan does not want the default */
+#include "northbridge/amd/amdk8/resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@@ -92,23 +90,18 @@
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
- /* Setup the rom access for 4M */
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -143,26 +136,19 @@
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
-
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
-
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif
Modified: trunk/src/mainboard/iwill/dk8x/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8x/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/iwill/dk8x/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -35,13 +35,13 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Set the memreset low. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Ensure the BIOS has control of the memory lines. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
} else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Ensure the CPU has control of the memory lines. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
@@ -49,15 +49,13 @@
{
if (is_cpu_pre_c0()) {
udelay(800);
- /* Set memreset_high */
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Set memreset high. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -69,7 +67,7 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
-#include "northbridge/amd/amdk8/resourcemap.c" /* tyan does not want the default */
+#include "northbridge/amd/amdk8/resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@@ -81,34 +79,29 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
- // first node
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
+ // first node
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
// second node
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
- /* Setup the rom access for 4M */
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -143,26 +136,19 @@
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
-
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
-
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif
Modified: trunk/src/mainboard/jetway/j7f24/romstage.c
==============================================================================
--- trunk/src/mainboard/jetway/j7f24/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/jetway/j7f24/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -53,7 +53,8 @@
{
device_t dev;
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
@@ -94,20 +95,15 @@
uart_init();
console_init();
- print_spew("In romstage.c:main()\n");
-
enable_smbus();
smbus_fixup(&ctrl);
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
- print_debug("Enabling mainboard devices\n");
enable_mainboard_devices();
ddr_ram_setup(&ctrl);
/* ram_check(0, 640 * 1024); */
-
- print_spew("Leaving romstage.c:main()\n");
}
Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/jetway/pa78vm5/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -59,9 +59,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1)
#endif
-static void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address)
{
@@ -85,8 +83,7 @@
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
@@ -95,7 +92,6 @@
/* mov bsp to bus 0xff when > 8 nodes */
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sb700_pci_port80();
}
@@ -175,7 +171,7 @@
rs780_early_setup();
sb700_early_setup();
- #if CONFIG_SET_FIDVID
+#if CONFIG_SET_FIDVID
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
@@ -196,7 +192,7 @@
/* show final fid and vid */
msr=rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
- #endif
+#endif
rs780_htinit();
Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c
==============================================================================
--- trunk/src/mainboard/kontron/986lcd-m/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/kontron/986lcd-m/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -328,9 +328,8 @@
u32 reg32;
int boot_mode = 0;
- if (bist == 0) {
+ if (bist == 0)
enable_lapic();
- }
/* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
Modified: trunk/src/mainboard/kontron/kt690/romstage.c
==============================================================================
--- trunk/src/mainboard/kontron/kt690/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/kontron/kt690/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -48,17 +48,9 @@
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-/* called in raminit_f.c */
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@@ -76,9 +68,10 @@
#include "cpu/amd/model_fxx/fidvid.c"
#include "northbridge/amd/amdk8/early_ht.c"
+#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
+
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- device_t dev;
static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, };
int needs_reset = 0;
u32 bsp_apicid = 0;
@@ -90,20 +83,17 @@
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
-
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
enable_rs690_dev8();
sb600_lpc_init();
- dev=PNP_DEV(0x2e, W83627DHG_SP1);
- w83627dhg_enable_serial(dev, CONFIG_TTYS0_BASE);
+ w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
#if CONFIG_USBDEBUG
@@ -137,8 +127,7 @@
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
- if( (cpuid1.edx & 0x6) == 0x6 ) {
-
+ if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@@ -150,7 +139,6 @@
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
printk(BIOS_SPEW, "... because cpuid returned %08x\n", cpuid1.edx);
Modified: trunk/src/mainboard/lanner/em8510/romstage.c
==============================================================================
--- trunk/src/mainboard/lanner/em8510/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/lanner/em8510/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -77,15 +77,13 @@
print_pci_devices();
#endif
- if(!bios_reset_detected()) {
+ if (!bios_reset_detected()) {
enable_smbus();
#if 1
dump_spd_registers(&memctrl[0]);
dump_smbus_registers();
#endif
-
sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
-
}
#if 0
@@ -100,4 +98,3 @@
ram_check(0x80000000, 0x81000000);
#endif
}
-
Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/frontrunner/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/lippert/frontrunner/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -77,6 +77,7 @@
{.channel0 = {DIMM0, DIMM1}}
};
unsigned char temp;
+
SystemPreInit();
msr_init();
Modified: trunk/src/mainboard/msi/ms7135/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7135/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/msi/ms7135/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -50,15 +50,8 @@
#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
- /* FIXME: Nothing to do? */
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* FIXME: Nothing to do? */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -100,22 +93,18 @@
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
-
sio_setup();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -138,9 +127,7 @@
#endif
needs_reset |= ht_setup_chains_x();
-
needs_reset |= ck804_early_setup_x();
-
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
Modified: trunk/src/mainboard/msi/ms7260/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/msi/ms7260/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -117,7 +117,6 @@
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset = 0;
unsigned bsp_apicid = 0;
@@ -125,10 +124,7 @@
/* Nothing special needs to be done to find bus 0. */
/* Allow the HT devices to be found. */
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the MCP55. */
mcp55_enable_rom();
}
@@ -186,11 +182,9 @@
print_debug_hex32(msr.lo);
print_debug("\n");
}
-
enable_fid_change();
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
-
{
msr_t msr = rdmsr(0xc0010042);
print_debug("end msr fid, vid ");
Modified: trunk/src/mainboard/msi/ms9185/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9185/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/msi/ms9185/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -52,9 +52,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
@@ -85,7 +83,7 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c" /* msi does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@@ -116,24 +114,17 @@
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
bcm5785_enable_rom();
-
bcm5785_enable_lpc();
-
//enable RTC
pc87417_enable_dev(RTC_DEV);
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
-
-// post_code(0x32);
- pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+ pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -142,11 +133,11 @@
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
+ printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
setup_ms9185_resource_map();
#if 0
- dump_pci_device(PCI_DEV(0, 0x18, 0));
+ dump_pci_device(PCI_DEV(0, 0x18, 0));
dump_pci_device(PCI_DEV(0, 0x19, 0));
#endif
@@ -166,7 +157,7 @@
#endif
/* it will set up chains and store link pair for optimization later */
- ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
+ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
bcm5785_early_setup();
@@ -177,26 +168,19 @@
#endif
#if CONFIG_SET_FIDVID
-
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
-
- enable_fid_change();
-
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
+ enable_fid_change();
+ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif
Modified: trunk/src/mainboard/msi/ms9282/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/msi/ms9282/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -49,9 +49,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
@@ -59,7 +57,7 @@
#define SMBUS_SWITCH2 0x72
unsigned device=(ctrl->channel0[0])>>8;
smbus_send_byte(SMBUS_SWITCH1, device);
- smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
+ smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
}
#if 0
@@ -68,7 +66,7 @@
#define SMBUS_SWITCH1 0x70
#define SMBUS_SWITHC2 0x72
smbus_send_byte(SMBUS_SWITCH1, device & 0x0f);
- smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
+ smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f);
}
#endif
@@ -82,7 +80,7 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c" /* msi does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
@@ -138,12 +136,8 @@
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
@@ -177,7 +171,6 @@
needs_reset = optimize_link_coherent_ht();
needs_reset |= optimize_link_incoherent_ht(sysinfo);
needs_reset |= mcp55_early_setup_x();
-
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -51,10 +51,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -110,31 +107,23 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
- u32 bsp_apicid = 0;
- u32 val;
+ u32 bsp_apicid = 0, val, wants_reset;
u8 reg;
- u32 wants_reset;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
post_code(0x30);
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
post_code(0x32);
Modified: trunk/src/mainboard/newisys/khepri/romstage.c
==============================================================================
--- trunk/src/mainboard/newisys/khepri/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/newisys/khepri/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -35,14 +35,13 @@
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
- }
- else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ /* Set the memreset low. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Ensure the BIOS has control of the memory lines. */
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ } else {
+ /* Ensure the CPU has control of the memory lines. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
}
}
@@ -50,16 +49,13 @@
{
if (is_cpu_pre_c0()) {
udelay(800);
- /* Set memreset_high */
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Set memreset high. */
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -69,7 +65,7 @@
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c" /* newisys khepri does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@@ -79,35 +75,27 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
#endif
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
- /* Setup the amd8111 */
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
-
-// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -53,14 +53,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -112,35 +106,29 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
+ // Node 0
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
+ // Node 1
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0);
@@ -183,28 +171,22 @@
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
-
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
-
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif
+
init_timer(); /* Need to use TMICT to synconize FID/VID. */
needs_reset |= optimize_link_coherent_ht();
Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c
==============================================================================
--- trunk/src/mainboard/pcengines/alix1c/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/pcengines/alix1c/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -36,9 +36,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
/* The ALIX1.C has no SMBus; the setup is hard-wired. */
-static void cs5536_enable_smbus(void)
-{
-}
+static void cs5536_enable_smbus(void) { }
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
@@ -114,11 +112,6 @@
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
-/** Early mainboard specific GPIO setup. */
-static void mb_gpio_init(void)
-{
-}
-
void main(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
@@ -137,7 +130,6 @@
*/
cs5536_disable_internal_uart();
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- mb_gpio_init();
uart_init();
console_init();
Modified: trunk/src/mainboard/pcengines/alix2d/romstage.c
==============================================================================
--- trunk/src/mainboard/pcengines/alix2d/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/pcengines/alix2d/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -36,9 +36,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
/* The ALIX.2D has no SMBus; the setup is hard-wired. */
-static void cs5536_enable_smbus(void)
-{
-}
+static void cs5536_enable_smbus(void) { }
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@ -128,13 +126,13 @@
* Ugly workaround: $ wrmsr 0x5140000C 0xf00100006100
* This resets the GPIO I/O space to 0x6100.
* This may break other things, though.
- */
+ */
outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE);
outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
/* outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_VALUE); */ /* Led 1 enabled */
- outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 2 disabled */
+ outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 2 disabled */
outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 3 disabled */
}
Modified: trunk/src/mainboard/rca/rm4100/romstage.c
==============================================================================
--- trunk/src/mainboard/rca/rm4100/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/rca/rm4100/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -99,9 +99,8 @@
void main(unsigned long bist)
{
if (bist == 0) {
- if (memory_initialized()) {
+ if (memory_initialized())
hard_reset();
- }
}
/* Set southbridge and superio gpios */
Modified: trunk/src/mainboard/roda/rk886ex/romstage.c
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/roda/rk886ex/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -250,9 +250,8 @@
u32 reg32;
int boot_mode = 0;
- if (bist == 0) {
+ if (bist == 0)
enable_lapic();
- }
/* Force PCIRST# */
pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
Modified: trunk/src/mainboard/sunw/ultra40/romstage.c
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/sunw/ultra40/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -28,9 +28,7 @@
#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
#define SUPERIO_GPIO_IO_BASE 0x400
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
#ifdef ENABLE_ONBOARD_SCSI
static void sio_gpio_setup(void)
@@ -44,10 +42,7 @@
}
#endif
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static inline void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -57,7 +52,7 @@
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c" /* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
@@ -101,32 +96,27 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
+ // Node 0
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
+ // Node 1
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
sio_setup();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -147,9 +137,7 @@
#endif
needs_reset |= ht_setup_chains_x();
-
needs_reset |= ck804_early_setup_x();
-
if (needs_reset) {
print_info("ht reset -\n");
soft_reset();
Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/supermicro/h8dme/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -49,9 +49,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void dump_smbus_registers(void)
{
@@ -183,25 +181,19 @@
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
@@ -243,7 +235,6 @@
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
-
{
msr_t msr;
msr = rdmsr(0xc0010042);
@@ -251,15 +242,10 @@
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
-
}
-
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
@@ -268,7 +254,6 @@
print_debug_hex32(msr.hi);
print_debug_hex32(msr.lo);
print_debug("\n");
-
}
#endif
Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -52,14 +52,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -85,6 +79,7 @@
{
uint32_t dword;
uint8_t byte;
+
enable_smbus();
// smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */
smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */
@@ -105,35 +100,29 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
+ // Node 0
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
+ // Node 1
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
pnp_enter_ext_func_mode(SERIAL_DEV);
pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
@@ -177,13 +166,9 @@
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo);
}
-
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -51,10 +51,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -111,30 +108,22 @@
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE +
CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
- u32 bsp_apicid = 0;
- u32 val;
- u32 wants_reset;
+ u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
post_code(0x30);
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
post_code(0x32);
Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -117,6 +117,7 @@
#define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1)
#define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2)
#define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3)
+
static void write_GPIO(void)
{
pnp_enter_ext_func_mode(GPIO1_DEV);
@@ -156,31 +157,24 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
- u32 bsp_apicid = 0;
- u32 val;
- u32 wants_reset;
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+ u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
post_code(0x30);
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
post_code(0x32);
Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dai_g/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -60,9 +60,8 @@
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized()) {
+ if (memory_initialized())
skip_romstage();
- }
}
/* Setup the console */
@@ -77,16 +76,13 @@
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
- if (dev == PCI_DEV_INVALID) {
+ if (dev == PCI_DEV_INVALID)
die("Missing 6300ESB?");
- }
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
-#endif
-#if 0
print_pci_devices();
#endif
#if 1
@@ -94,9 +90,8 @@
#endif
#if 0
int i;
- for(i = 0; i < 1; i++) {
+ for(i = 0; i < 1; i++)
dump_spd_registers();
- }
#endif
disable_watchdogs();
sdram_initialize(ARRAY_SIZE(mch), mch);
Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -49,12 +49,6 @@
static const struct mem_controller mch[] = {
{
.node_id = 0,
- /*
- .f0 = PCI_DEV(0, 0x00, 0),
- .f1 = PCI_DEV(0, 0x00, 1),
- .f2 = PCI_DEV(0, 0x00, 2),
- .f3 = PCI_DEV(0, 0x00, 3),
- */
.channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, },
.channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, },
}
@@ -63,9 +57,8 @@
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized()) {
+ if (memory_initialized())
skip_romstage();
- }
}
/* Setup the console */
@@ -83,16 +76,13 @@
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
- if (dev == PCI_DEV_INVALID) {
+ if (dev == PCI_DEV_INVALID)
die("Missing esb6300?");
- }
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
-#endif
-#if 0
print_pci_devices();
#endif
#if 1
@@ -101,9 +91,8 @@
#if 0
// dump_spd_registers(&cpu[0]);
int i;
- for(i = 0; i < 1; i++) {
+ for(i = 0; i < 1; i++)
dump_spd_registers();
- }
#endif
disable_watchdogs();
// dump_ipmi_registers();
@@ -111,8 +100,6 @@
sdram_initialize(ARRAY_SIZE(mch), mch);
#if 0
dump_pci_devices();
-#endif
-#if 0
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -47,13 +47,7 @@
static const struct mem_controller mch[] = {
{
.node_id = 0,
- /*
- .f0 = PCI_DEV(0, 0x00, 0),
- .f1 = PCI_DEV(0, 0x00, 1),
- .f2 = PCI_DEV(0, 0x00, 2),
- .f3 = PCI_DEV(0, 0x00, 3),
- */
- .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
+ .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
}
};
@@ -61,9 +55,8 @@
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized()) {
+ if (memory_initialized())
skip_romstage();
- }
}
/* Setup the console */
@@ -81,16 +74,13 @@
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0);
- if (dev == PCI_DEV_INVALID) {
+ if (dev == PCI_DEV_INVALID)
die("Missing ich5r?");
- }
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
-#endif
-#if 0
print_pci_devices();
#endif
#if 1
@@ -99,9 +89,8 @@
#if 0
// dump_spd_registers(&cpu[0]);
int i;
- for(i = 0; i < 1; i++) {
+ for(i = 0; i < 1; i++)
dump_spd_registers();
- }
#endif
disable_watchdogs();
// dump_ipmi_registers();
Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -62,9 +62,8 @@
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized()) {
+ if (memory_initialized())
skip_romstage();
- }
}
/* Setup the console */
@@ -82,16 +81,13 @@
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
- if (dev == PCI_DEV_INVALID) {
+ if (dev == PCI_DEV_INVALID)
die("Missing ich5?");
- }
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
-#endif
-#if 0
print_pci_devices();
#endif
#if 1
@@ -100,9 +96,8 @@
#if 0
// dump_spd_registers(&cpu[0]);
int i;
- for(i = 0; i < 1; i++) {
+ for(i = 0; i < 1; i++)
dump_spd_registers();
- }
#endif
disable_watchdogs();
// dump_ipmi_registers();
Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -48,12 +48,6 @@
static const struct mem_controller mch[] = {
{
.node_id = 0,
- /*
- .f0 = PCI_DEV(0, 0x00, 0),
- .f1 = PCI_DEV(0, 0x00, 1),
- .f2 = PCI_DEV(0, 0x00, 2),
- .f3 = PCI_DEV(0, 0x00, 3),
- */
.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
}
@@ -62,9 +56,8 @@
if (bist == 0) {
/* Skip this if there was a built in self test failure */
early_mtrr_init();
- if (memory_initialized()) {
+ if (memory_initialized())
skip_romstage();
- }
}
/* Setup the console */
@@ -82,16 +75,13 @@
/* config LPC decode for flash memory access */
device_t dev;
dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0);
- if (dev == PCI_DEV_INVALID) {
+ if (dev == PCI_DEV_INVALID)
die("Missing ich5?");
- }
pci_write_config32(dev, 0xe8, 0x00000000);
pci_write_config8(dev, 0xf0, 0x00);
#if 0
display_cpuid_update_microcode();
-#endif
-#if 0
print_pci_devices();
#endif
#if 1
@@ -100,9 +90,8 @@
#if 0
// dump_spd_registers(&cpu[0]);
int i;
- for(i = 0; i < 1; i++) {
+ for(i = 0; i < 1; i++)
dump_spd_registers();
- }
#endif
disable_watchdogs();
// dump_ipmi_registers();
@@ -110,8 +99,6 @@
sdram_initialize(ARRAY_SIZE(mch), mch);
#if 0
dump_pci_devices();
-#endif
-#if 0
dump_pci_device(PCI_DEV(0, 0x00, 0));
dump_bar14(PCI_DEV(0, 0x00, 0));
#endif
Modified: trunk/src/mainboard/technexion/tim5690/romstage.c
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/technexion/tim5690/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -47,17 +47,9 @@
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-/* called in raminit_f.c */
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@@ -90,7 +82,6 @@
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
-
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
@@ -98,9 +89,8 @@
technexion_post_code_init();
technexion_post_code(LED_MESSAGE_START);
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
enable_rs690_dev8();
sb600_lpc_init();
@@ -141,8 +131,7 @@
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
- if( (cpuid1.edx & 0x6) == 0x6 ) {
-
+ if ((cpuid1.edx & 0x6) == 0x6) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@@ -154,7 +143,6 @@
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
Modified: trunk/src/mainboard/technexion/tim8690/romstage.c
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/technexion/tim8690/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -47,17 +47,9 @@
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-/* called in raminit_f.c */
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */
static inline int spd_read_byte(u32 device, u32 address)
{
return smbus_read_byte(device, address);
@@ -88,14 +80,12 @@
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
-
/* sb600_lpc_port80(); */
sb600_pci_port80();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
enable_rs690_dev8();
sb600_lpc_init();
@@ -136,8 +126,7 @@
/* Check to see if processor is capable of changing FIDVID */
/* otherwise it will throw a GP# when reading FIDVID_STATUS */
cpuid1 = cpuid(0x80000007);
- if( (cpuid1.edx & 0x6) == 0x6 ) {
-
+ if ((cpuid1.edx & 0x6) == 0x6 ) {
/* Read FIDVID_STATUS */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
@@ -149,7 +138,6 @@
/* show final fid and vid */
msr=rdmsr(0xc0010042);
printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo);
-
} else {
printk(BIOS_DEBUG, "Changing FIDVID not supported\n");
}
Modified: trunk/src/mainboard/televideo/tc7020/romstage.c
==============================================================================
--- trunk/src/mainboard/televideo/tc7020/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/televideo/tc7020/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -35,20 +35,11 @@
static void main(unsigned long bist)
{
- /* Initialize the serial console. */
pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
-
- /* Halt if there was a built in self test failure. */
report_bist_failure(bist);
-
cs5530_enable_rom();
-
- /* Initialize RAM. */
sdram_init();
-
- /* Check whether RAM works. */
/* ram_check(0, 640 * 1024); */
}
-
Modified: trunk/src/mainboard/thomson/ip1000/romstage.c
==============================================================================
--- trunk/src/mainboard/thomson/ip1000/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/thomson/ip1000/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -98,9 +98,8 @@
void main(unsigned long bist)
{
if (bist == 0) {
- if (memory_initialized()) {
+ if (memory_initialized())
hard_reset();
- }
}
/* Set southbridge and superio gpios */
Modified: trunk/src/mainboard/traverse/geos/romstage.c
==============================================================================
--- trunk/src/mainboard/traverse/geos/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/traverse/geos/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -52,11 +52,6 @@
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void)
-{
- /* Early mainboard specific GPIO setup. */
-}
-
void main(unsigned long bist)
{
post_code(0x01);
@@ -78,7 +73,6 @@
*/
/* If debug. real setup done in chipset init via devicetree.cb. */
cs5536_setup_onchipuart(1);
- mb_gpio_init();
uart_init();
console_init();
Modified: trunk/src/mainboard/tyan/s2735/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2735/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/tyan/s2735/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -46,9 +46,8 @@
},
};
- if (bist == 0) {
+ if (bist == 0)
enable_lapic();
- }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -57,15 +56,12 @@
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
- if(bios_reset_detected()) {
+ if (bios_reset_detected())
hard_reset();
- }
enable_smbus();
#if 0
dump_spd_registers(&memctrl[0]);
-#endif
-#if 0
dump_smbus_registers();
#endif
@@ -79,4 +75,3 @@
dump_pci_device(PCI_DEV(0, 0, 0));
#endif
}
-
Modified: trunk/src/mainboard/tyan/s2850/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2850/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/tyan/s2850/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -29,28 +29,23 @@
static void memreset_setup(void)
{
- if (is_cpu_pre_c0()) {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
- }
- else {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- }
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ if (is_cpu_pre_c0())
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
+ else
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -86,16 +81,12 @@
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
- /* Setup the amd8111 */
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
init_cpus(cpu_init_detectedx);
- }
// post_code(0x32);
@@ -128,4 +119,3 @@
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/tyan/s2875/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2875/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/tyan/s2875/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -29,28 +29,23 @@
static void memreset_setup(void)
{
- if (is_cpu_pre_c0()) {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
- }
- else {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- }
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ if (is_cpu_pre_c0())
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
+ else
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -97,15 +92,12 @@
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
init_cpus(cpu_init_detectedx);
- }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -135,6 +127,4 @@
sdram_initialize(ARRAY_SIZE(cpu), cpu);
post_cache_as_ram();
-
}
-
Modified: trunk/src/mainboard/tyan/s2880/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2880/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/tyan/s2880/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -29,28 +29,23 @@
static void memreset_setup(void)
{
- if (is_cpu_pre_c0()) {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
- }
- else {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- }
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ if (is_cpu_pre_c0())
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
+ else
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -97,16 +92,12 @@
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
init_cpus(cpu_init_detectedx);
- }
-
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -138,4 +129,3 @@
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/tyan/s2881/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2881/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/tyan/s2881/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -28,28 +28,23 @@
static void memreset_setup(void)
{
- if (is_cpu_pre_c0()) {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
- }
- else {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- }
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ if (is_cpu_pre_c0())
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
+ else
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -69,33 +64,27 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
#if CONFIG_MAX_PHYSICAL_CPUS > 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
#endif
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
- /* Setup the amd8111 */
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
// post_code(0x32);
@@ -131,8 +120,6 @@
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
-#endif
-#if 0
dump_smbus_registers();
#endif
@@ -151,4 +138,3 @@
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/tyan/s2882/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2882/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/tyan/s2882/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -29,28 +29,23 @@
static void memreset_setup(void)
{
- if (is_cpu_pre_c0()) {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
- }
- else {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- }
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ if (is_cpu_pre_c0())
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
+ else
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -97,15 +92,12 @@
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
init_cpus(cpu_init_detectedx);
- }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
Modified: trunk/src/mainboard/tyan/s2885/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2885/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/tyan/s2885/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -28,28 +28,23 @@
static void memreset_setup(void)
{
- if (is_cpu_pre_c0()) {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
- }
- else {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- }
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ if (is_cpu_pre_c0())
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
+ else
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -59,7 +54,7 @@
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c" /* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@@ -78,26 +73,18 @@
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
- /* Setup the amd8111 */
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
-
-// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
Modified: trunk/src/mainboard/tyan/s2891/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2891/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/tyan/s2891/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -25,18 +25,9 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void memreset_setup(void) { }
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -46,7 +37,7 @@
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c" /* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
#include "southbridge/nvidia/ck804/ck804_early_setup.c"
@@ -92,23 +83,18 @@
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
sio_setup();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
// post_code(0x32);
@@ -135,9 +121,7 @@
#endif
needs_reset |= ht_setup_chains_x();
-
needs_reset |= ck804_early_setup_x();
-
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
@@ -152,8 +136,6 @@
enable_smbus();
#if 0
dump_spd_registers(&cpu[0]);
-#endif
-#if 0
dump_smbus_registers();
#endif
@@ -162,12 +144,8 @@
#if 0
print_pci_devices();
-#endif
-
-#if 0
dump_pci_devices();
#endif
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/tyan/s2892/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2892/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/tyan/s2892/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -25,14 +25,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -42,7 +36,7 @@
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c" /* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
@@ -84,23 +78,18 @@
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
sio_setup();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
// post_code(0x32);
@@ -123,9 +112,7 @@
#endif
needs_reset |= ht_setup_chains_x();
-
needs_reset |= ck804_early_setup_x();
-
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
@@ -143,4 +130,3 @@
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/tyan/s2895/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2895/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/tyan/s2895/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -19,38 +19,31 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
-#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-#define SUPERIO_GPIO_IO_BASE 0x400
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
#include <cpu/amd/mtrr.h>
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
-#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
-static void memreset_setup(void)
-{
-}
+#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
+#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
+#define SUPERIO_GPIO_IO_BASE 0x400
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
+static void memreset_setup(void) { }
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static void sio_gpio_setup(void)
{
unsigned value;
/*Enable onboard scsi*/
- lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
+ lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c,
+ (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L
value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c);
lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1)));
}
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
-
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
@@ -59,7 +52,7 @@
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c" /* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
@@ -113,23 +106,18 @@
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
sio_setup();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -151,9 +139,7 @@
wait_all_other_cores_started(bsp_apicid);
needs_reset |= ht_setup_chains_x();
-
needs_reset |= ck804_early_setup_x();
-
if (needs_reset) {
printk(BIOS_INFO, "ht reset -\n");
soft_reset();
@@ -172,4 +158,3 @@
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/tyan/s2912/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/tyan/s2912/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -53,14 +53,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void memreset(int controllers, const struct mem_controller *ctrl) { }
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -113,40 +107,32 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
- // Node 0
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
- // Node 1
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
+ // Node 0
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
+ // Node 1
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
};
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE
+ CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
int needs_reset = 0;
unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
setup_mb_resource_map();
-
uart_init();
/* Halt if there was a built in self test failure */
@@ -181,26 +167,19 @@
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
-
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
-
enable_fid_change();
-
enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
init_fidvid_bsp(bsp_apicid);
-
// show final fid and vid
{
msr_t msr;
msr=rdmsr(0xc0010042);
print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n");
-
}
#endif
Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -52,10 +52,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
+static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address)
{
@@ -117,29 +114,22 @@
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
- u32 bsp_apicid = 0;
- u32 val;
- u32 wants_reset;
+ u32 bsp_apicid = 0, val, wants_reset;
msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
set_bsp_node_CHtExtNodeCfgEn();
enumerate_ht_chain();
-
sio_setup();
-
- /* Setup the mcp55 */
mcp55_enable_rom();
}
post_code(0x30);
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
post_code(0x32);
@@ -256,4 +246,3 @@
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
-
Modified: trunk/src/mainboard/tyan/s4880/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s4880/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/tyan/s4880/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -28,23 +28,22 @@
static void memreset_setup(void)
{
- if (is_cpu_pre_c0()) {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
- }
- else {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- }
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ if (is_cpu_pre_c0())
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
+ else
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
+
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x18
@@ -52,6 +51,7 @@
smbus_write_byte(SMBUS_HUB, 0x01, device);
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
+
#if 0
static inline void change_i2c_mux(unsigned device)
{
@@ -73,7 +73,7 @@
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c" /* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@@ -110,7 +110,6 @@
},
#endif
-
#if CONFIG_MAX_PHYSICAL_CPUS > 2
{
.node_id = 2,
@@ -140,15 +139,12 @@
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
init_cpus(cpu_init_detectedx);
- }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
Modified: trunk/src/mainboard/tyan/s4882/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s4882/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/tyan/s4882/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -27,23 +27,22 @@
static void memreset_setup(void)
{
- if (is_cpu_pre_c0()) {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
- }
- else {
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
- }
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
+ if (is_cpu_pre_c0())
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0
+ else
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1
+ outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17);
}
static void memreset(int controllers, const struct mem_controller *ctrl)
{
if (is_cpu_pre_c0()) {
udelay(800);
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
+ outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1
udelay(90);
}
}
+
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_HUB 0x18
@@ -57,6 +56,7 @@
smbus_write_byte(SMBUS_HUB, 0x03, 0);
}
+
#if 0
static inline void change_i2c_mux(unsigned device)
{
@@ -81,7 +81,7 @@
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-#include "resourcemap.c" /* tyan does not want the default */
+#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
#include "cpu/amd/car/post_cache_as_ram.c"
@@ -112,24 +112,18 @@
};
int needs_reset;
- unsigned bsp_apicid = 0;
-
+ unsigned bsp_apicid = 0, nodes;
struct mem_controller ctrl[8];
- unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) {
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
-
enumerate_ht_chain();
-
amd8111_enable_rom();
}
- if (bist == 0) {
+ if (bist == 0)
bsp_apicid = init_cpus(cpu_init_detectedx);
- }
-
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
@@ -169,6 +163,4 @@
sdram_initialize(nodes, ctrl);
post_cache_as_ram();
-
}
-
Modified: trunk/src/mainboard/via/epia-cn/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-cn/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/via/epia-cn/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -47,7 +47,8 @@
{
device_t dev;
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
@@ -87,21 +88,10 @@
enable_vt8235_serial();
uart_init();
console_init();
-
- print_spew("In romstage.c:main()\n");
-
enable_smbus();
smbus_fixup(&ctrl);
-
- /* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
-
- print_debug("Enabling mainboard devices\n");
enable_mainboard_devices();
-
ddr_ram_setup(&ctrl);
-
/* ram_check(0, 640 * 1024); */
-
- print_spew("Leaving romstage.c:main()\n");
}
Modified: trunk/src/mainboard/via/epia-m/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-m/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/via/epia-m/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -30,7 +30,7 @@
device_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_8235), 0);
+ PCI_DEVICE_ID_VIA_8235), 0);
if (dev == PCI_DEV_INVALID) {
die("Southbridge not found!!!\n");
@@ -72,9 +72,7 @@
{
device_t dev;
- /*
- * Enable VGA; 32MB buffer.
- */
+ /* Enable VGA; 32MB buffer. */
pci_write_config8(0, 0xe1, 0xdd);
/*
@@ -83,9 +81,8 @@
*/
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_6305), 0);
- if (dev != PCI_DEV_INVALID) {
+ if (dev != PCI_DEV_INVALID)
pci_write_config8(dev, 0x15, 0x1c);
- }
enable_vt8235_serial();
uart_init();
@@ -122,12 +119,8 @@
}
#endif
- if (bist == 0) {
- print_debug(" Doing MTRR init.\n");
+ if (bist == 0)
early_mtrr_init();
- }
//dump_pci_devices();
-
- print_spew("Leaving romstage.c:main()\n");
}
Modified: trunk/src/mainboard/via/epia-m700/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-m700/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/via/epia-m700/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -448,17 +448,6 @@
/* This fix does help vx800!, but vx855 doesn't need this. */
/* smbus_fixup(&ctrl); */
- if (bist == 0) {
- /*
- * CAR needs MTRR until memory is ok, so disable this
- * early_mtrr_init() call.
- */
-#if 0
- print_debug("doing early_mtrr\n");
- early_mtrr_init();
-#endif
- }
-
/* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
Modified: trunk/src/mainboard/via/epia-n/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-n/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/via/epia-n/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -62,7 +62,8 @@
device_t dev;
u8 reg;
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
@@ -110,14 +111,10 @@
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
w83697hf_set_clksel_48(SERIAL_DEV);
-
w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
-
uart_init();
console_init();
- print_spew("In romstage.c:main()\n");
-
enable_smbus();
smbus_fixup(&ctrl);
@@ -130,18 +127,13 @@
print_debug("Enable F-ROM Shadow RAM\n");
enable_shadow_ram();
- /* setup cpu */
print_debug("Setup CPU Interface\n");
c3_cpu_setup(ctrl.d0f2);
ddr_ram_setup();
- if (bist == 0) {
- print_debug("doing early_mtrr\n");
+ if (bist == 0)
early_mtrr_init();
- }
//ram_check(0, 640 * 1024);
-
- print_spew("Leaving romstage.c:main()\n");
}
Modified: trunk/src/mainboard/via/epia/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/via/epia/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -31,9 +31,8 @@
dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
- if (dev == PCI_DEV_INVALID) {
+ if (dev == PCI_DEV_INVALID)
die("Southbridge not found!!!\n");
- }
pci_write_config8(dev, 0x50, 7);
pci_write_config8(dev, 0x51, 0xff);
@@ -74,9 +73,9 @@
static void main(unsigned long bist)
{
- if (bist == 0) {
+ if (bist == 0)
early_mtrr_init();
- }
+
enable_vt8231_serial();
uart_init();
console_init();
Modified: trunk/src/mainboard/via/pc2500e/romstage.c
==============================================================================
--- trunk/src/mainboard/via/pc2500e/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/via/pc2500e/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -63,14 +63,9 @@
it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
-
enable_smbus();
smbus_fixup(&ctrl);
-
- /* Halt if there was a built-in self test failure. */
report_bist_failure(bist);
-
ddr_ram_setup(&ctrl);
-
/* ram_check(0, 640 * 1024); */
}
Modified: trunk/src/mainboard/winent/pl6064/romstage.c
==============================================================================
--- trunk/src/mainboard/winent/pl6064/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/winent/pl6064/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -56,11 +56,6 @@
#include "cpu/amd/model_lx/syspreinit.c"
#include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void)
-{
- /* Early mainboard specific GPIO setup. */
-}
-
void main(unsigned long bist)
{
post_code(0x01);
@@ -79,7 +74,6 @@
*/
w83627hf_set_clksel_48(SERIAL_DEV);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
- mb_gpio_init();
uart_init();
console_init();
Modified: trunk/src/mainboard/wyse/s50/romstage.c
==============================================================================
--- trunk/src/mainboard/wyse/s50/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/mainboard/wyse/s50/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -81,5 +81,4 @@
/* Check all of memory */
/*ram_check(0x00000000, 640*1024);*/
- print_err("ram check done\n");
}
Modified: trunk/src/northbridge/via/vx800/examples/romstage.c
==============================================================================
--- trunk/src/northbridge/via/vx800/examples/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
+++ trunk/src/northbridge/via/vx800/examples/romstage.c Sun Nov 21 23:47:22 2010 (r6108)
@@ -81,9 +81,7 @@
print_debug("In enable_mainboard_devices \n");
- /*
- Enable P2P Bridge Header for External PCI BUS.
- */
+ /* Enable P2P bridge Header for external PCI bus. */
dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0);
pci_write_config8(dev, 0x4f, 0x41);
}
@@ -91,6 +89,7 @@
static void enable_shadow_ram(void)
{
uint8_t shadowreg;
+
pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0xff);
/* 0xf0000-0xfffff - ACPI tables */
shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83);
1
0
See patch.
Abuild-tested.
Uwe.
--
http://hermann-uwe.de | http://sigrok.org
http://randomprojects.org | http://unmaintained-free-software.org
3
4
[commit] r6107 - in trunk/src: mainboard/advantech/pcm-5820 mainboard/amd/db800 mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/norwich mainboard/amd/pistach...
by repository service 21 Nov '10
by repository service 21 Nov '10
21 Nov '10
Author: uwe
Date: Sun Nov 21 18:29:59 2010
New Revision: 6107
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6107
Log:
Drop excessive whitespace randomly sprinkled in romstage.c files.
Also drop some dead or useless code snippets.
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de>
Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de>
Modified:
trunk/src/mainboard/advantech/pcm-5820/romstage.c
trunk/src/mainboard/amd/db800/romstage.c
trunk/src/mainboard/amd/dbm690t/romstage.c
trunk/src/mainboard/amd/mahogany/romstage.c
trunk/src/mainboard/amd/mahogany_fam10/romstage.c
trunk/src/mainboard/amd/norwich/romstage.c
trunk/src/mainboard/amd/pistachio/romstage.c
trunk/src/mainboard/amd/rumba/romstage.c
trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
trunk/src/mainboard/amd/tilapia_fam10/romstage.c
trunk/src/mainboard/arima/hdama/romstage.c
trunk/src/mainboard/artecgroup/dbe61/romstage.c
trunk/src/mainboard/asi/mb_5blgp/romstage.c
trunk/src/mainboard/asrock/939a785gmh/romstage.c
trunk/src/mainboard/asus/a8n_e/romstage.c
trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c
trunk/src/mainboard/asus/a8v-e_se/romstage.c
trunk/src/mainboard/asus/m2v-mx_se/romstage.c
trunk/src/mainboard/asus/m2v/romstage.c
trunk/src/mainboard/asus/m4a785-m/romstage.c
trunk/src/mainboard/axus/tc320/romstage.c
trunk/src/mainboard/broadcom/blast/romstage.c
trunk/src/mainboard/dell/s1850/romstage.c
trunk/src/mainboard/digitallogic/adl855pc/romstage.c
trunk/src/mainboard/digitallogic/msm586seg/romstage.c
trunk/src/mainboard/digitallogic/msm800sev/romstage.c
trunk/src/mainboard/eaglelion/5bcm/romstage.c
trunk/src/mainboard/getac/p470/romstage.c
trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
trunk/src/mainboard/gigabyte/m57sli/romstage.c
trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
trunk/src/mainboard/gigabyte/ma78gm/romstage.c
trunk/src/mainboard/hp/dl145_g1/romstage.c
trunk/src/mainboard/hp/dl145_g3/romstage.c
trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c
trunk/src/mainboard/ibase/mb899/romstage.c
trunk/src/mainboard/ibm/e325/romstage.c
trunk/src/mainboard/ibm/e326/romstage.c
trunk/src/mainboard/iei/juki-511p/romstage.c
trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
trunk/src/mainboard/iei/nova4899r/romstage.c
trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
trunk/src/mainboard/intel/d945gclf/romstage.c
trunk/src/mainboard/intel/eagleheights/romstage.c
trunk/src/mainboard/intel/jarrell/romstage.c
trunk/src/mainboard/intel/mtarvon/romstage.c
trunk/src/mainboard/intel/truxton/romstage.c
trunk/src/mainboard/intel/xe7501devkit/romstage.c
trunk/src/mainboard/iwill/dk8_htx/romstage.c
trunk/src/mainboard/iwill/dk8s2/romstage.c
trunk/src/mainboard/iwill/dk8x/romstage.c
trunk/src/mainboard/jetway/j7f24/romstage.c
trunk/src/mainboard/jetway/pa78vm5/romstage.c
trunk/src/mainboard/kontron/986lcd-m/romstage.c
trunk/src/mainboard/kontron/kt690/romstage.c
trunk/src/mainboard/lippert/frontrunner/romstage.c
trunk/src/mainboard/lippert/hurricane-lx/romstage.c
trunk/src/mainboard/lippert/literunner-lx/romstage.c
trunk/src/mainboard/lippert/roadrunner-lx/romstage.c
trunk/src/mainboard/lippert/spacerunner-lx/romstage.c
trunk/src/mainboard/msi/ms7135/romstage.c
trunk/src/mainboard/msi/ms7260/romstage.c
trunk/src/mainboard/msi/ms9185/romstage.c
trunk/src/mainboard/msi/ms9282/romstage.c
trunk/src/mainboard/msi/ms9652_fam10/romstage.c
trunk/src/mainboard/newisys/khepri/romstage.c
trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
trunk/src/mainboard/pcengines/alix1c/romstage.c
trunk/src/mainboard/pcengines/alix2d/romstage.c
trunk/src/mainboard/rca/rm4100/romstage.c
trunk/src/mainboard/roda/rk886ex/romstage.c
trunk/src/mainboard/sunw/ultra40/romstage.c
trunk/src/mainboard/supermicro/h8dme/romstage.c
trunk/src/mainboard/supermicro/h8dmr/romstage.c
trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
trunk/src/mainboard/supermicro/x6dai_g/romstage.c
trunk/src/mainboard/supermicro/x6dhe_g/romstage.c
trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c
trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c
trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c
trunk/src/mainboard/technexion/tim5690/romstage.c
trunk/src/mainboard/technexion/tim8690/romstage.c
trunk/src/mainboard/technologic/ts5300/romstage.c
trunk/src/mainboard/thomson/ip1000/romstage.c
trunk/src/mainboard/traverse/geos/romstage.c
trunk/src/mainboard/tyan/s2735/romstage.c
trunk/src/mainboard/tyan/s2850/romstage.c
trunk/src/mainboard/tyan/s2875/romstage.c
trunk/src/mainboard/tyan/s2880/romstage.c
trunk/src/mainboard/tyan/s2881/romstage.c
trunk/src/mainboard/tyan/s2882/romstage.c
trunk/src/mainboard/tyan/s2885/romstage.c
trunk/src/mainboard/tyan/s2891/romstage.c
trunk/src/mainboard/tyan/s2892/romstage.c
trunk/src/mainboard/tyan/s2895/romstage.c
trunk/src/mainboard/tyan/s2912/romstage.c
trunk/src/mainboard/tyan/s2912_fam10/romstage.c
trunk/src/mainboard/tyan/s4880/romstage.c
trunk/src/mainboard/tyan/s4882/romstage.c
trunk/src/mainboard/via/epia-cn/romstage.c
trunk/src/mainboard/via/epia-m/romstage.c
trunk/src/mainboard/via/epia-m700/romstage.c
trunk/src/mainboard/via/epia-n/romstage.c
trunk/src/mainboard/via/epia/romstage.c
trunk/src/mainboard/via/pc2500e/romstage.c
trunk/src/mainboard/via/vt8454c/romstage.c
trunk/src/mainboard/winent/pl6064/romstage.c
trunk/src/mainboard/wyse/s50/romstage.c
trunk/src/northbridge/via/vx800/examples/romstage.c
Modified: trunk/src/mainboard/advantech/pcm-5820/romstage.c
==============================================================================
--- trunk/src/mainboard/advantech/pcm-5820/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/advantech/pcm-5820/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -42,4 +42,3 @@
sdram_init();
/* ram_check(0, 640 * 1024); */
}
-
Modified: trunk/src/mainboard/amd/db800/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/db800/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/amd/db800/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -31,13 +31,12 @@
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
static inline int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
@@ -96,4 +95,3 @@
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
-
Modified: trunk/src/mainboard/amd/dbm690t/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/amd/dbm690t/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -31,24 +31,18 @@
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
#include <spd.h>
-
#include <usbdebug.h>
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
-
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
@@ -75,16 +69,10 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "northbridge/amd/amdk8/early_ht.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -188,4 +176,3 @@
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/amd/mahogany/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/amd/mahogany/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -32,22 +32,17 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <spd.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8718f/it8718f_early_serial.c"
#include <usbdebug.h>
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
-
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
@@ -74,16 +69,10 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "northbridge/amd/amdk8/early_ht.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -186,4 +175,3 @@
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -38,22 +38,16 @@
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include <lib.h>
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
-
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-
static int smbus_read_byte(u32 device, u32 address);
-
#include "superio/ite/it8718f/it8718f_early_serial.c"
#include <usbdebug.h>
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
-
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
@@ -71,18 +65,14 @@
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
@@ -247,4 +237,3 @@
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
-
Modified: trunk/src/mainboard/amd/norwich/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/norwich/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/amd/norwich/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -31,7 +31,6 @@
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
-
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@ -97,4 +96,3 @@
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
-
Modified: trunk/src/mainboard/amd/pistachio/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/pistachio/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/amd/pistachio/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -26,23 +26,18 @@
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
#include <usbdebug.h>
#include <spd.h>
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
-
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
@@ -69,16 +64,10 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "northbridge/amd/amdk8/early_ht.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -199,4 +188,3 @@
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/amd/rumba/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/rumba/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/amd/rumba/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -10,12 +10,11 @@
#include <cpu/amd/gx2def.h>
#include <cpu/amd/geode_post_code.h>
#include <spd.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
static inline int spd_read_byte(unsigned device, unsigned address)
{
if (device != DIMM0)
@@ -61,4 +60,3 @@
/* Check all of memory */
//ram_check(0x00000000, 640*1024);
}
-
Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -11,32 +11,25 @@
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include <reset.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-
#include "cpu/x86/bist.h"
-
#include "lib/delay.c"
-
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
static void memreset_setup(void)
{
//GPIO on amd8111 to enable MEMRST ????
@@ -87,27 +80,20 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
-
-#define RC0 ((1<<0)<<8)
-#define RC1 ((1<<1)<<8)
-#define RC2 ((1<<2)<<8)
-#define RC3 ((1<<3)<<8)
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
+#define RC0 ((1<<0)<<8)
+#define RC1 ((1<<1)<<8)
+#define RC2 ((1<<2)<<8)
+#define RC3 ((1<<3)<<8)
+
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
@@ -283,6 +269,4 @@
#endif
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
}
-
Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -40,25 +40,17 @@
#include "northbridge/amd/amdfam10/amdfam10.h"
#include <lib.h>
#include <spd.h>
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
-
#include <console/loglevel.h>
-#if 0
-void die(const char *msg);
-int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
-#define printk(BIOS_EMERG, fmt, arg...) do_printk(BIOS_EMERG ,fmt, ##arg)
-#endif
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdfam10/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
static void memreset_setup(void)
{
@@ -91,18 +83,14 @@
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
@@ -201,7 +189,6 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
u32 bsp_apicid = 0;
u32 val;
@@ -353,6 +340,4 @@
printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
-
}
-
Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -38,22 +38,16 @@
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include <lib.h>
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
-
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-
static int smbus_read_byte(u32 device, u32 address);
-
#include "superio/ite/it8718f/it8718f_early_serial.c"
#include <usbdebug.h>
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
-
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
@@ -70,18 +64,14 @@
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
Modified: trunk/src/mainboard/arima/hdama/romstage.c
==============================================================================
--- trunk/src/mainboard/arima/hdama/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/arima/hdama/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -7,29 +7,24 @@
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/nsc/pc87360/pc87360_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <spd.h>
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
* GPIO29 of 8111 will control H1_MEMRESET_L
@@ -68,18 +63,13 @@
return smbus_read_byte(device, address);
}
-
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/resourcemap.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -154,4 +144,3 @@
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/artecgroup/dbe61/romstage.c
==============================================================================
--- trunk/src/mainboard/artecgroup/dbe61/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/artecgroup/dbe61/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -33,7 +33,6 @@
#include "southbridge/amd/cs5536/cs5536.h"
#include "spd_table.h"
#include <spd.h>
-
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@ -145,4 +144,3 @@
// ram_check(0x00000000, 640 * 1024);
// ram_check(1024 * 1024, 2 * 1024 * 1024);
}
-
Modified: trunk/src/mainboard/asi/mb_5blgp/romstage.c
==============================================================================
--- trunk/src/mainboard/asi/mb_5blgp/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/asi/mb_5blgp/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -42,4 +42,3 @@
sdram_init();
/* ram_check(0, 640 * 1024); */
}
-
Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -32,23 +32,18 @@
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include <spd.h>
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
#include <usbdebug.h>
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
-
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
@@ -79,16 +74,10 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_init(void)
@@ -106,7 +95,6 @@
pnp_write_config(GPIO2345_DEV, 0x2c, 0x1);
pnp_write_config(GPIO2345_DEV, 0x2d, 0x1);
-
//idx 30 e0 e1 e2 e3 e4 e5 e6 e7 e8 e9 f0 f1 f2 f3 f4 f5 f6 f7 fe
//val 07 XX XX XX f6 0e 00 00 00 00 ff d6 96 00 40 d0 83 00 00 07
@@ -240,4 +228,3 @@
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/asus/a8n_e/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8n_e/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/asus/a8n_e/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -69,10 +69,8 @@
#include "lib/generic_sdram.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
#include "southbridge/nvidia/ck804/ck804_early_setup.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
@@ -168,4 +166,3 @@
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -86,15 +86,12 @@
// defines S3_NVRAM_EARLY:
#include "southbridge/via/k8t890/k8t890_early_car.c"
-
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
@@ -232,4 +229,3 @@
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/a8v-e_se/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -86,15 +86,12 @@
// defines S3_NVRAM_EARLY:
#include "southbridge/via/k8t890/k8t890_early_car.c"
-
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
@@ -232,4 +229,3 @@
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -69,15 +69,12 @@
// defines S3_NVRAM_EARLY:
#include "southbridge/via/k8t890/k8t890_early_car.c"
-
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
@@ -202,4 +199,3 @@
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/asus/m2v/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m2v/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/asus/m2v/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -71,15 +71,12 @@
// defines S3_NVRAM_EARLY:
#include "southbridge/via/k8t890/k8t890_early_car.c"
-
#include "northbridge/amd/amdk8/amdk8.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
@@ -304,4 +301,3 @@
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/asus/m4a785-m/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -38,22 +38,16 @@
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include <lib.h>
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
-
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-
static int smbus_read_byte(u32 device, u32 address);
-
#include "superio/ite/it8712f/it8712f_early_serial.c"
#include <usbdebug.h>
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
-
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
@@ -70,18 +64,14 @@
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
Modified: trunk/src/mainboard/axus/tc320/romstage.c
==============================================================================
--- trunk/src/mainboard/axus/tc320/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/axus/tc320/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -43,4 +43,3 @@
sdram_init();
/* ram_check(0, 640 * 1024); */
}
-
Modified: trunk/src/mainboard/broadcom/blast/romstage.c
==============================================================================
--- trunk/src/mainboard/broadcom/blast/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/broadcom/blast/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -7,7 +7,6 @@
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
@@ -15,22 +14,18 @@
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/nsc/pc87417/pc87417_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
-
static void memreset_setup(void)
{
}
@@ -65,22 +60,16 @@
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
-
-#define RC0 (6<<8)
-#define RC1 (7<<8)
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "northbridge/amd/amdk8/early_ht.c"
+#define RC0 (6<<8)
+#define RC1 (7<<8)
+
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
@@ -184,6 +173,4 @@
#endif
post_cache_as_ram();
-
}
-
Modified: trunk/src/mainboard/dell/s1850/romstage.c
==============================================================================
--- trunk/src/mainboard/dell/s1850/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/dell/s1850/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -343,11 +343,4 @@
#if 0
ram_check(0x00000000, 0x02000000);
#endif
-
-#if 0
- while(1) {
- hlt();
- }
-#endif
}
-
Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/adl855pc/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -63,7 +63,6 @@
#endif
sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
-
}
#if 0
@@ -78,4 +77,3 @@
ram_check(0x80000000, 0x81000000);
#endif
}
-
Modified: trunk/src/mainboard/digitallogic/msm586seg/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/msm586seg/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/digitallogic/msm586seg/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -8,7 +8,6 @@
#include <console/console.h>
#include "lib/ramtest.c"
#include "cpu/x86/bist.h"
-//#include "lib/delay.c"
void setup_pars(void)
{
@@ -48,8 +47,6 @@
// return smbus_read_byte(device, address);
}
-//#include "lib/generic_sdram.c"
-
static inline void dumpmem(void){
int i, j;
unsigned char *l;
@@ -251,4 +248,3 @@
while(1);
#endif
}
-
Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c
==============================================================================
--- trunk/src/mainboard/digitallogic/msm800sev/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -12,13 +12,12 @@
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
@@ -27,6 +26,7 @@
#define ManualConf 0 /* Do automatic strapped PLL config */
#define PLLMSRhi 0x00001490 /* manual settings for the PLL */
#define PLLMSRlo 0x02000030
+
#include "northbridge/amd/lx/raminit.h"
#include "northbridge/amd/lx/pll_reset.c"
#include "northbridge/amd/lx/raminit.c"
@@ -97,4 +97,3 @@
void done_cache_as_ram_main(void);
done_cache_as_ram_main();
}
-
Modified: trunk/src/mainboard/eaglelion/5bcm/romstage.c
==============================================================================
--- trunk/src/mainboard/eaglelion/5bcm/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/eaglelion/5bcm/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -7,18 +7,13 @@
#include <stdlib.h>
#include <console/console.h>
#include "lib/ramtest.c"
-//#include "southbridge/intel/i440bx/i440bx_early_smbus.c"
#include "superio/nsc/pc97317/pc97317_early_serial.c"
-//#include "northbridge/intel/i440bx/raminit.h"
#include "cpu/x86/bist.h"
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
+#include "northbridge/amd/gx1/raminit.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
-//#include "lib/delay.c"
-
-#include "northbridge/amd/gx1/raminit.c"
-
static void main(unsigned long bist)
{
pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
@@ -53,4 +48,3 @@
}
#endif
}
-
Modified: trunk/src/mainboard/getac/p470/romstage.c
==============================================================================
--- trunk/src/mainboard/getac/p470/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/getac/p470/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -28,12 +28,9 @@
#include <cpu/x86/lapic.h>
#include <lib.h>
#include <usbdebug.h>
-
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
#include <cpu/x86/bist.h>
-
#include "northbridge/intel/i945/i945.h"
#include "northbridge/intel/i945/raminit.h"
#include "southbridge/intel/i82801gx/i82801gx.h"
@@ -100,7 +97,6 @@
pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x00040069);
}
-
/* This box has two superios, so enabling serial becomes slightly excessive.
* We disable a lot of stuff to make sure that there are no conflicts between
* the two. Also set up the GPIOs from the beginning. This is the "no schematic
@@ -398,4 +394,3 @@
}
#endif
}
-
Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -34,37 +34,28 @@
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
#include <usbdebug.h>
#include <spd.h>
-
#include <cpu/amd/model_fxx_rev.h>
-
#include "southbridge/sis/sis966/sis966.h"
#include "southbridge/sis/sis966/sis966_early_smbus.c"
#include "southbridge/sis/sis966/sis966_enable_rom.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8716f/it8716f_early_serial.c"
#include "superio/ite/it8716f/it8716f_early_init.c"
-
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/debug.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/sis/sis966/sis966_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
-#include "southbridge/sis/sis966/sis966_early_ctrl.c"
-
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@@ -84,9 +75,7 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
-
#include "resourcemap.c"
-
#include "cpu/amd/dualcore/dualcore.c"
#define SIS966_NUM 1
@@ -104,13 +93,9 @@
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+60, 0x00, 0x60,/* GPIO61 FANCTL1 */
#include "southbridge/sis/sis966/sis966_early_setup_ss.h"
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
@@ -205,7 +190,6 @@
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
-
{
msr_t msr;
msr=rdmsr(0xc0010042);
@@ -252,6 +236,4 @@
sis_init_stage2();
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
}
-
Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -32,36 +32,27 @@
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
#include <usbdebug.h>
#include <spd.h>
-
#include <cpu/amd/model_fxx_rev.h>
-
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/ite/it8716f/it8716f_early_serial.c"
#include "superio/ite/it8716f/it8716f_early_init.c"
-
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/debug.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
#define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO)
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@@ -86,25 +77,16 @@
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
-
-
#include "northbridge/amd/amdk8/amdk8_f.h"
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
-
#include "resourcemap.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -214,7 +196,6 @@
ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID
-
{
msr_t msr;
msr=rdmsr(0xc0010042);
@@ -260,6 +241,4 @@
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
}
-
Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -34,22 +34,16 @@
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include <lib.h>
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
-
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-
static int smbus_read_byte(u32 device, u32 address);
-
#include "superio/ite/it8718f/it8718f_early_serial.c"
#include <usbdebug.h>
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
-
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
@@ -66,25 +60,20 @@
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0;
Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -38,22 +38,16 @@
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include <lib.h>
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
-
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-
static int smbus_read_byte(u32 device, u32 address);
-
#include "superio/ite/it8718f/it8718f_early_serial.c"
#include <usbdebug.h>
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
-
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
@@ -70,25 +64,20 @@
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0;
@@ -129,7 +118,6 @@
console_init();
printk(BIOS_DEBUG, "\n");
-
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
@@ -247,4 +235,3 @@
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
-
Modified: trunk/src/mainboard/hp/dl145_g1/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g1/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/hp/dl145_g1/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -7,29 +7,23 @@
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
-
#include <cpu/amd/model_fxx_rev.h>
-
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@ -90,20 +84,15 @@
#include "resourcemap.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
-
-#define RC0 ((1<<1)<<8) // Not sure about these values
-#define RC1 ((1<<2)<<8) // Not sure about these values
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
+#define RC0 ((1<<1)<<8) // Not sure about these values
+#define RC1 ((1<<2)<<8) // Not sure about these values
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g3/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/hp/dl145_g3/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -38,37 +38,27 @@
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
-
#include <cpu/amd/model_fxx_rev.h>
-
#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-
#include "superio/serverengines/pilot/pilot_early_serial.c"
#include "superio/serverengines/pilot/pilot_early_init.c"
#include "superio/nsc/pc87417/pc87417_early_serial.c"
-
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/debug.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
-
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@@ -93,15 +83,10 @@
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
#include <spd.h>
-
#include "cpu/amd/dualcore/dualcore.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "northbridge/amd/amdk8/early_ht.c"
#if 0
@@ -248,4 +233,3 @@
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -45,29 +45,22 @@
#include "northbridge/amd/amdfam10/amdfam10.h"
#include <lib.h>
#include <spd.h>
-
#include "cpu/amd/model_10xxx/apic_timer.c"
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
-
#include "superio/serverengines/pilot/pilot_early_serial.c"
#include "superio/serverengines/pilot/pilot_early_init.c"
#include "superio/nsc/pc87417/pc87417_early_serial.c"
-
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdfam10/debug.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
-
//#include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
-
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
u8 val;
@@ -85,18 +78,13 @@
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
#include "cpu/amd/quadcore/quadcore.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-
#include "northbridge/amd/amdfam10/early_ht.c"
static const u8 spd_addr[] = {
@@ -113,7 +101,6 @@
{
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
-
u32 bsp_apicid = 0;
u32 val;
msr_t msr;
Modified: trunk/src/mainboard/ibase/mb899/romstage.c
==============================================================================
--- trunk/src/mainboard/ibase/mb899/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/ibase/mb899/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -27,23 +27,18 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <lib.h>
-
#include "superio/winbond/w83627ehg/w83627ehg.h"
-
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
#include <usbdebug.h>
#include <cpu/x86/bist.h>
-
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
-
-#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
-
#include "northbridge/intel/i945/i945.h"
#include "northbridge/intel/i945/raminit.h"
#include "southbridge/intel/i82801gx/i82801gx.h"
+#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
+
void enable_smbus(void);
void setup_ich7_gpios(void)
@@ -358,4 +353,3 @@
}
#endif
}
-
Modified: trunk/src/mainboard/ibm/e325/romstage.c
==============================================================================
--- trunk/src/mainboard/ibm/e325/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/ibm/e325/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -8,29 +8,24 @@
#include <stdlib.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/nsc/pc87366/pc87366_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
#include <spd.h>
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@ -64,18 +59,13 @@
return smbus_read_byte(device, address);
}
-
#include "northbridge/amd/amdk8/raminit.c"
#include "resourcemap.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -148,6 +138,4 @@
sdram_initialize(ARRAY_SIZE(cpu), cpu);
post_cache_as_ram();
-
}
-
Modified: trunk/src/mainboard/ibm/e326/romstage.c
==============================================================================
--- trunk/src/mainboard/ibm/e326/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/ibm/e326/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -8,29 +8,24 @@
#include <stdlib.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/nsc/pc87366/pc87366_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
-
#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#include <spd.h>
+#define SERIAL_DEV PNP_DEV(0x2e, PC87366_SP1)
+
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@ -64,18 +59,13 @@
return smbus_read_byte(device, address);
}
-
#include "northbridge/amd/amdk8/raminit.c"
#include "resourcemap.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -148,6 +138,4 @@
sdram_initialize(ARRAY_SIZE(cpu), cpu);
post_cache_as_ram();
-
}
-
Modified: trunk/src/mainboard/iei/juki-511p/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/juki-511p/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/iei/juki-511p/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -30,11 +30,10 @@
#include "southbridge/amd/cs5530/cs5530_enable_rom.c"
#include "cpu/x86/bist.h"
#include "pc80/udelay_io.c"
+#include "northbridge/amd/gx1/raminit.c"
#define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1)
-#include "northbridge/amd/gx1/raminit.c"
-
static void main(unsigned long bist)
{
/* Initialize the serial console. */
@@ -57,4 +56,3 @@
/* Check RAM. */
/* ram_check(0x00000000, 640 * 1024); */
}
-
Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -41,22 +41,16 @@
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include <lib.h>
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
-
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-
static int smbus_read_byte(u32 device, u32 address);
-
#include "superio/fintek/f71859/f71859_early_serial.c"
#include <usbdebug.h>
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
-
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
@@ -73,18 +67,14 @@
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
@@ -250,4 +240,3 @@
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
-
Modified: trunk/src/mainboard/iei/nova4899r/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/nova4899r/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/iei/nova4899r/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -52,4 +52,3 @@
/* Check RAM. */
/* ram_check(0x00000000, 640 * 1024); */
}
-
Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c
==============================================================================
--- trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -31,13 +31,12 @@
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
static inline int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
@@ -99,4 +98,3 @@
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
-
Modified: trunk/src/mainboard/intel/d945gclf/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/d945gclf/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/intel/d945gclf/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -27,23 +27,18 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <lib.h>
-
#include "superio/smsc/lpc47m15x/lpc47m15x.h"
-
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
#include <usbdebug.h>
#include <cpu/x86/bist.h>
-
#include "superio/smsc/lpc47m15x/lpc47m15x_early_serial.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
-
#include "northbridge/intel/i945/i945.h"
#include "northbridge/intel/i945/raminit.h"
#include "southbridge/intel/i82801gx/i82801gx.h"
+#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
+
void enable_smbus(void);
void setup_ich7_gpios(void)
@@ -317,4 +312,3 @@
}
#endif
}
-
Modified: trunk/src/mainboard/intel/eagleheights/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/eagleheights/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/intel/eagleheights/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -21,20 +21,16 @@
*/
#include <delay.h>
-
#include <stdint.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <device/pci_def.h>
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
-
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
#include <cpu/x86/bist.h>
#include <cpu/intel/acpi.h>
-
#include "southbridge/intel/i3100/i3100_early_smbus.c"
#include "southbridge/intel/i3100/i3100_early_lpc.c"
#include "reset.c"
@@ -196,4 +192,3 @@
/* Initialize memory */
sdram_initialize(ARRAY_SIZE(mch), mch);
}
-
Modified: trunk/src/mainboard/intel/jarrell/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/jarrell/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/intel/jarrell/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -63,6 +63,7 @@
skip_romstage();
}
}
+
/* Setup the console */
pc87427_disable_dev(CONSOLE_SERIAL_DEV);
pc87427_disable_dev(HIDDEN_SERIAL_DEV);
@@ -128,10 +129,4 @@
#endif
#endif
-#if 0
- while(1) {
- hlt();
- }
-#endif
}
-
Modified: trunk/src/mainboard/intel/mtarvon/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/mtarvon/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/intel/mtarvon/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -15,7 +15,6 @@
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- *
*/
#include <stdint.h>
@@ -122,4 +121,3 @@
ram_check(0, 1024 * 1024);
}
-
Modified: trunk/src/mainboard/intel/truxton/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/truxton/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/intel/truxton/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -105,4 +105,3 @@
ram_verify(0x00000000, 0x02000000);
#endif
}
-
Modified: trunk/src/mainboard/intel/xe7501devkit/romstage.c
==============================================================================
--- trunk/src/mainboard/intel/xe7501devkit/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/intel/xe7501devkit/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -78,4 +78,3 @@
// if the following line is removed.
print_debug("SDRAM is up.\n");
}
-
Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -11,30 +11,23 @@
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-
#include "cpu/x86/bist.h"
-
#include "lib/delay.c"
-
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
* GPIO29 of 8111 will control H1_MEMRESET_L
@@ -76,19 +69,12 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -212,6 +198,4 @@
#endif
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
}
-
Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8s2/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/iwill/dk8s2/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -11,30 +11,23 @@
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-
#include "cpu/x86/bist.h"
-
#include "lib/delay.c"
-
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
* GPIO29 of 8111 will control H1_MEMRESET_L
@@ -76,19 +69,12 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "northbridge/amd/amdk8/resourcemap.c"
-
+#include "northbridge/amd/amdk8/resourcemap.c" /* tyan does not want the default */
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -212,6 +198,4 @@
#endif
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
}
-
Modified: trunk/src/mainboard/iwill/dk8x/romstage.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8x/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/iwill/dk8x/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -11,30 +11,23 @@
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
-
#include "cpu/x86/bist.h"
-
#include "lib/delay.c"
-
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
/*
* GPIO28 of 8111 will control H0_MEMRESET_L
* GPIO29 of 8111 will control H1_MEMRESET_L
@@ -76,19 +69,12 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit.c"
#include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "northbridge/amd/amdk8/resourcemap.c"
-
+#include "northbridge/amd/amdk8/resourcemap.c" /* tyan does not want the default */
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -212,6 +198,4 @@
#endif
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
}
-
Modified: trunk/src/mainboard/jetway/j7f24/romstage.c
==============================================================================
--- trunk/src/mainboard/jetway/j7f24/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/jetway/j7f24/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -111,4 +111,3 @@
print_spew("Leaving romstage.c:main()\n");
}
-
Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/jetway/pa78vm5/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -39,64 +39,50 @@
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include <lib.h>
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
-
#include <console/loglevel.h>
#include "cpu/x86/bist.h"
-
static int smbus_read_byte(u32 device, u32 address);
-
#include "superio/fintek/f71863fg/f71863fg_early_serial.c"
-#if CONFIG_TTYS0_BASE == 0x2f8
-#define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP2)
-#else
-#define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1)
-#endif
-
#include <usbdebug.h>
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
-
#include "southbridge/amd/rs780/rs780_early_setup.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include "northbridge/amd/amdfam10/debug.c"
+#if CONFIG_TTYS0_BASE == 0x2f8
+#define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP2)
+#else
+#define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1)
+#endif
+
static void activate_spd_rom(const struct mem_controller *ctrl)
{
}
static int spd_read_byte(u32 device, u32 address)
{
- int result;
- result = smbus_read_byte(device, address);
- return result;
+ return smbus_read_byte(device, address);
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-
-
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
#include "resourcemap.c"
#include "cpu/amd/quadcore/quadcore.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-
#include "northbridge/amd/amdfam10/early_ht.c"
#include "southbridge/amd/sb700/sb700_early_setup.c"
#include <spd.h>
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
-
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, };
u32 bsp_apicid = 0;
@@ -255,4 +241,3 @@
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
-
Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c
==============================================================================
--- trunk/src/mainboard/kontron/986lcd-m/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/kontron/986lcd-m/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -28,25 +28,19 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <usbdebug.h>
-
#include "superio/winbond/w83627thg/w83627thg.h"
-
#include <pc80/mc146818rtc.h>
#include "option_table.h"
-
#include <console/console.h>
#include <cpu/x86/bist.h>
-
#include "superio/winbond/w83627thg/w83627thg_early_serial.c"
-
void enable_smbus(void);
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
-
#include "northbridge/intel/i945/i945.h"
#include "northbridge/intel/i945/raminit.h"
#include "southbridge/intel/i82801gx/i82801gx.h"
+#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1)
+
void setup_ich7_gpios(void)
{
printk(BIOS_DEBUG, " GPIOS...");
@@ -454,4 +448,3 @@
}
#endif
}
-
Modified: trunk/src/mainboard/kontron/kt690/romstage.c
==============================================================================
--- trunk/src/mainboard/kontron/kt690/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/kontron/kt690/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -32,25 +32,19 @@
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include <spd.h>
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627dhg/w83627dhg_early_serial.c"
-
#include <usbdebug.h>
-
#include <cpu/amd/mtrr.h>
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
-
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
@@ -76,16 +70,10 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "northbridge/amd/amdk8/early_ht.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -191,4 +179,3 @@
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/frontrunner/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/lippert/frontrunner/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -11,12 +11,11 @@
#include <cpu/amd/gx2def.h>
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5535/cs5535.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
#include "southbridge/amd/cs5535/cs5535_early_setup.c"
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
static const unsigned char spdbytes[] = { /* 4x Qimonda HYB25DC512160CF-6 */
0xFF, 0xFF, /* only values used by raminit.c are set */
[SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, /* (Fundamental) memory type */
@@ -131,6 +130,4 @@
// ram_check(0, 16384);
ram_check(0x20000, 0x24000);
// ram_check(0x00000000, 640*1024);
-
}
-
Modified: trunk/src/mainboard/lippert/hurricane-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/hurricane-lx/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/lippert/hurricane-lx/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -34,7 +34,6 @@
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
-
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
Modified: trunk/src/mainboard/lippert/literunner-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/literunner-lx/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/lippert/literunner-lx/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -34,7 +34,6 @@
#include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
-
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
Modified: trunk/src/mainboard/lippert/roadrunner-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -34,7 +34,6 @@
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
-
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c
==============================================================================
--- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -34,7 +34,6 @@
#include <cpu/amd/lxdef.h>
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
-
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
Modified: trunk/src/mainboard/msi/ms7135/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7135/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/msi/ms7135/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -22,8 +22,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -35,7 +33,6 @@
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627thg/w83627thg_early_serial.c"
-
#include <cpu/amd/model_fxx_rev.h>
#include <console/console.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
@@ -51,6 +48,8 @@
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
+#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
+
static void memreset(int controllers, const struct mem_controller *ctrl)
{
/* FIXME: Nothing to do? */
@@ -70,10 +69,8 @@
#include "lib/generic_sdram.c"
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
@@ -171,4 +168,3 @@
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/msi/ms7260/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/msi/ms7260/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -33,7 +33,6 @@
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
#include <usbdebug.h>
#include <cpu/amd/model_fxx_rev.h>
@@ -43,22 +42,18 @@
#include "lib/delay.c"
#include <lib.h>
#include <spd.h>
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
-
#include "cpu/x86/bist.h"
#include "northbridge/amd/amdk8/debug.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-/* Yes, on the MSI K9N Neo (MS-7260) the Super I/O is at 0x4e! */
#define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1)
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
static void memreset(int controllers, const struct mem_controller *ctrl) {}
static inline void activate_spd_rom(const struct mem_controller *ctrl) {}
@@ -72,7 +67,6 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
-
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
@@ -86,11 +80,9 @@
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
#include "cpu/amd/model_fxx/init_cpus.c"
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -233,4 +225,3 @@
/* bsp switch stack to RAM and copy sysinfo RAM now. */
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/msi/ms9185/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9185/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/msi/ms9185/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -33,7 +33,6 @@
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c"
@@ -41,19 +40,17 @@
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include <reset.h>
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/nsc/pc87417/pc87417_early_serial.c"
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
#define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1)
#define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
-#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
static void memreset(int controllers, const struct mem_controller *ctrl)
{
@@ -88,24 +85,17 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
-
- /* msi does not want the default */
-#include "resourcemap.c"
-
+#include "resourcemap.c" /* msi does not want the default */
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
-
-#define RC0 (0x10<<8)
-#define RC1 (0x01<<8)
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "northbridge/amd/amdk8/early_ht.c"
+#define RC0 (0x10<<8)
+#define RC1 (0x01<<8)
+
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr[] = {
@@ -260,6 +250,4 @@
#endif
post_cache_as_ram();
-
}
-
Modified: trunk/src/mainboard/msi/ms9282/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/msi/ms9282/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -31,29 +31,24 @@
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
#include <spd.h>
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-
#include <device/pci_ids.h>
#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
+#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
+
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@@ -87,12 +82,10 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
-
- /* msi does not want the default */
-#include "resourcemap.c"
+#include "resourcemap.c" /* msi does not want the default */
#include "cpu/amd/dualcore/dualcore.c"
-
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
+
//set GPIO to input mode
#define MCP55_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
@@ -101,13 +94,10 @@
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff), ((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
// Disabled until it's actually used:
// #include "cpu/amd/model_fxx/fidvid.c"
-
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -210,4 +200,3 @@
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -34,31 +34,23 @@
#include <usbdebug.h>
#include <lib.h>
#include <spd.h>
-
#include <cpu/amd/model_10xxx_rev.h>
-
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
-
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdfam10/debug.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
-
#include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
@@ -70,12 +62,9 @@
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
#include "resourcemap.c"
-
#include "cpu/amd/quadcore/quadcore.c"
#define MCP55_MB_SETUP \
@@ -88,16 +77,10 @@
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-
-
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
@@ -277,4 +260,3 @@
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x43); // Should never see this post code.
}
-
Modified: trunk/src/mainboard/newisys/khepri/romstage.c
==============================================================================
--- trunk/src/mainboard/newisys/khepri/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/newisys/khepri/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -15,29 +15,23 @@
#include <console/console.h>
#include <lib.h>
#include <spd.h>
-
#include <cpu/amd/model_fxx_rev.h>
-
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@ -72,22 +66,13 @@
return smbus_read_byte(device, address);
}
-
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
- /* newisys khepri does not want the default */
-#include "resourcemap.c"
-
+#include "resourcemap.c" /* newisys khepri does not want the default */
#include "cpu/amd/dualcore/dualcore.c"
-
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -171,6 +156,4 @@
#endif
post_cache_as_ram();
-
}
-
Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -32,36 +32,27 @@
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
#include <usbdebug.h>
#include <lib.h>
#include <spd.h>
-
#include <cpu/amd/model_fxx_rev.h>
-
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_serial.c"
#include "superio/winbond/w83627ehg/w83627ehg_early_init.c"
-
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/debug.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@@ -81,9 +72,7 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
-
#include "resourcemap.c"
-
#include "cpu/amd/dualcore/dualcore.c"
#define MCP55_MB_SETUP \
@@ -96,15 +85,9 @@
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -245,6 +228,4 @@
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
}
-
Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c
==============================================================================
--- trunk/src/mainboard/pcengines/alix1c/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/pcengines/alix1c/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -187,4 +187,3 @@
void done_cache_as_ram_main(void);
done_cache_as_ram_main();
}
-
Modified: trunk/src/mainboard/pcengines/alix2d/romstage.c
==============================================================================
--- trunk/src/mainboard/pcengines/alix2d/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/pcengines/alix2d/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -136,8 +136,6 @@
/* outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_VALUE); */ /* Led 1 enabled */
outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 2 disabled */
outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 3 disabled */
-
-
}
void main(unsigned long bist)
@@ -207,4 +205,3 @@
void done_cache_as_ram_main(void);
done_cache_as_ram_main();
}
-
Modified: trunk/src/mainboard/rca/rm4100/romstage.c
==============================================================================
--- trunk/src/mainboard/rca/rm4100/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/rca/rm4100/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -36,12 +36,11 @@
#include "cpu/x86/bist.h"
#include "spd_table.h"
#include "gpio.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-
#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
#include "southbridge/intel/i82801dx/i82801dx_tco_timer.c"
+#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
+
/**
* The onboard 64MB PC133 memory does not have a SPD EEPROM so the
* values have to be set manually, the SO-DIMM socket is located in
@@ -128,4 +127,3 @@
/* ram_check(0, 640 * 1024); */
/* ram_check(64512 * 1024, 65536 * 1024); */
}
-
Modified: trunk/src/mainboard/roda/rk886ex/romstage.c
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/roda/rk886ex/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -29,13 +29,10 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <lib.h>
-
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
#include <usbdebug.h>
#include <cpu/x86/bist.h>
-
#include "northbridge/intel/i945/i945.h"
#include "northbridge/intel/i945/raminit.h"
#include "southbridge/intel/i82801gx/i82801gx.h"
@@ -374,4 +371,3 @@
}
#endif
}
-
Modified: trunk/src/mainboard/sunw/ultra40/romstage.c
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/sunw/ultra40/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -9,36 +9,29 @@
#include <console/console.h>
#include <lib.h>
#include <spd.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/smsc/lpc47b397/lpc47b397_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
+#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
+#define SUPERIO_GPIO_IO_BASE 0x400
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
-#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT)
-
-#define SUPERIO_GPIO_IO_BASE 0x400
-
#ifdef ENABLE_ONBOARD_SCSI
static void sio_gpio_setup(void)
{
@@ -64,12 +57,8 @@
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
#include "cpu/amd/dualcore/dualcore.c"
-
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
//set GPIO to input mode
@@ -82,13 +71,8 @@
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
-
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
@@ -183,4 +167,3 @@
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/supermicro/h8dme/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -29,36 +29,26 @@
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
#include <lib.h>
#include <spd.h>
-
#include <cpu/amd/model_fxx_rev.h>
-
-// for enable the FAN
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
-
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/debug.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@@ -136,20 +126,13 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
-
#include "resourcemap.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -313,6 +296,4 @@
sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
}
-
Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -32,36 +32,26 @@
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
#include <lib.h>
#include <spd.h>
-
#include <cpu/amd/model_fxx_rev.h>
-
-// for enable the FAN
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
-
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/debug.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@@ -81,20 +71,13 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
-
#include "resourcemap.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -30,15 +30,11 @@
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-
#include <console/console.h>
#include <lib.h>
#include <spd.h>
-
#include <cpu/amd/model_10xxx_rev.h>
-
-// for enable the FAN
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "cpu/amd/model_10xxx/apic_timer.c"
@@ -47,19 +43,14 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
-
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdfam10/debug.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
-
#include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
@@ -71,24 +62,16 @@
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
#include "resourcemap.c"
-
#include "cpu/amd/quadcore/quadcore.c"
-
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-
-
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
@@ -113,7 +96,6 @@
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4);
dword |= (1 << 16);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE + 1, 0), 0xa4, dword);
-
}
static const u8 spd_addr[] = {
Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -30,15 +30,11 @@
#include <device/pnp_def.h>
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
-
#include <console/console.h>
#include <lib.h>
#include <spd.h>
-
#include <cpu/amd/model_10xxx_rev.h>
-
-// for enable the FAN
-#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c" // for enable the FAN
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
#include "cpu/amd/model_10xxx/apic_timer.c"
@@ -47,19 +43,14 @@
#include "northbridge/amd/amdfam10/reset_test.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
-
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdfam10/debug.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
-
#include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
#define SMBUS_SWITCH1 0x70
@@ -74,26 +65,16 @@
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
#include "resourcemap.c"
-
#include "cpu/amd/quadcore/quadcore.c"
-
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-
-
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
@@ -116,7 +97,6 @@
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4);
dword |= (1<<16);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa4, dword);
-
}
static const u8 spd_addr[] = {
@@ -317,6 +297,4 @@
// printk(BIOS_DEBUG, "\n*** Yes, the copy/decompress is taking a while, FIXME!\n");
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
post_code(0x42); // Should never see this post code.
-
}
-
Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dai_g/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -64,6 +64,7 @@
skip_romstage();
}
}
+
/* Setup the console */
outb(0x87,0x2e);
outb(0x87,0x2e);
@@ -115,11 +116,4 @@
#if 0
ram_check(0x00000000, 0x02000000);
#endif
-
-#if 0
- while(1) {
- hlt();
- }
-#endif
}
-
Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -46,10 +46,6 @@
static void main(unsigned long bist)
{
- /*
- *
- *
- */
static const struct mem_controller mch[] = {
{
.node_id = 0,
@@ -71,6 +67,7 @@
skip_romstage();
}
}
+
/* Setup the console */
outb(0x87,0x2e);
outb(0x87,0x2e);
@@ -131,11 +128,4 @@
#if 0
ram_check(0x00000000, 0x02000000);
#endif
-
-#if 0
- while(1) {
- hlt();
- }
-#endif
}
-
Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -55,7 +55,6 @@
*/
.channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, },
.channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, },
-
}
};
@@ -66,6 +65,7 @@
skip_romstage();
}
}
+
/* Setup the console */
outb(0x87,0x2e);
outb(0x87,0x2e);
@@ -126,11 +126,4 @@
#if 0
ram_check(0x00000000, 0x02000000);
#endif
-
-#if 0
- while(1) {
- hlt();
- }
-#endif
}
-
Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -45,10 +45,6 @@
static void main(unsigned long bist)
{
- /*
- *
- *
- */
static const struct mem_controller mch[] = {
{
.node_id = 0,
@@ -70,6 +66,7 @@
skip_romstage();
}
}
+
/* Setup the console */
outb(0x87,0x2e);
outb(0x87,0x2e);
@@ -131,11 +128,4 @@
#if 0
ram_check(0x00000000, 0x02000000);
#endif
-
-#if 0
- while(1) {
- hlt();
- }
-#endif
}
-
Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -66,6 +66,7 @@
skip_romstage();
}
}
+
/* Setup the console */
outb(0x87,0x2e);
outb(0x87,0x2e);
@@ -127,11 +128,4 @@
#if 0
ram_check(0x00000000, 0x02000000);
#endif
-
-#if 0
- while(1) {
- hlt();
- }
-#endif
}
-
Modified: trunk/src/mainboard/technexion/tim5690/romstage.c
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/technexion/tim5690/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -31,24 +31,19 @@
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include <spd.h>
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
#include <usbdebug.h>
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
-
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
@@ -74,19 +69,12 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "tn_post_code.c"
#include "speaker.c"
-
#include "northbridge/amd/amdk8/early_ht.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -203,4 +191,3 @@
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/technexion/tim8690/romstage.c
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/technexion/tim8690/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -31,24 +31,19 @@
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
#include <console/console.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
#include <spd.h>
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
#include <usbdebug.h>
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
-
#include "southbridge/amd/rs690/rs690_early_setup.c"
#include "southbridge/amd/sb600/sb600_early_setup.c"
@@ -74,16 +69,10 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "resourcemap.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "northbridge/amd/amdk8/early_ht.c"
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
@@ -188,4 +177,3 @@
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/technologic/ts5300/romstage.c
==============================================================================
--- trunk/src/mainboard/technologic/ts5300/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/technologic/ts5300/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -130,7 +130,6 @@
val=inb(0x19d);
if(val==0x5f)
identify_ts9500();
-
}
static void hard_reset(void)
@@ -172,4 +171,3 @@
TS5300_LED_OFF;
}
-
Modified: trunk/src/mainboard/thomson/ip1000/romstage.c
==============================================================================
--- trunk/src/mainboard/thomson/ip1000/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/thomson/ip1000/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -37,12 +37,11 @@
#include "cpu/x86/bist.h"
#include "spd_table.h"
#include "gpio.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
-
#include "southbridge/intel/i82801dx/i82801dx_early_smbus.c"
#include "southbridge/intel/i82801dx/i82801dx_tco_timer.c"
+#define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1)
+
/**
* The onboard 64MB PC133 memory does not have a SPD EEPROM so the
* values have to be set manually, the SO-DIMM socket is located in
@@ -130,4 +129,3 @@
/* ram_check(0, 640 * 1024); */
/* ram_check(64512 * 1024, 65536 * 1024); */
}
-
Modified: trunk/src/mainboard/traverse/geos/romstage.c
==============================================================================
--- trunk/src/mainboard/traverse/geos/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/traverse/geos/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -32,7 +32,6 @@
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
-
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
Modified: trunk/src/mainboard/tyan/s2735/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2735/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/tyan/s2735/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -1,4 +1,3 @@
-
#include <stdint.h>
#include <string.h>
#include <device/pci_def.h>
@@ -10,13 +9,10 @@
#include <console/console.h>
#include <lib.h>
#include <spd.h>
-
#include "southbridge/intel/i82801ex/i82801ex_early_smbus.c"
#include "northbridge/intel/e7501/raminit.h"
-
#include "northbridge/intel/e7501/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
Modified: trunk/src/mainboard/tyan/s2850/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2850/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/tyan/s2850/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -10,28 +10,23 @@
#include <console/console.h>
#include <lib.h>
#include <spd.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@ -66,15 +61,9 @@
#include "northbridge/amd/amdk8/resourcemap.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
Modified: trunk/src/mainboard/tyan/s2875/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2875/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/tyan/s2875/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -10,28 +10,23 @@
#include <console/console.h>
#include <lib.h>
#include <spd.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@ -62,20 +57,13 @@
return smbus_read_byte(device, address);
}
-
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
#include "northbridge/amd/amdk8/resourcemap.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
Modified: trunk/src/mainboard/tyan/s2880/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2880/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/tyan/s2880/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -10,28 +10,23 @@
#include <console/console.h>
#include <lib.h>
#include <spd.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@ -62,20 +57,13 @@
return smbus_read_byte(device, address);
}
-
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/resourcemap.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
Modified: trunk/src/mainboard/tyan/s2881/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2881/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/tyan/s2881/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -9,29 +9,23 @@
#include <console/console.h>
#include <lib.h>
#include <spd.h>
-
#include <cpu/amd/model_fxx_rev.h>
-
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@ -66,15 +60,9 @@
#include "resourcemap.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
Modified: trunk/src/mainboard/tyan/s2882/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2882/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/tyan/s2882/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -10,28 +10,23 @@
#include <console/console.h>
#include <lib.h>
#include <spd.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@ -62,18 +57,13 @@
return smbus_read_byte(device, address);
}
-
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/resourcemap.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
#include "cpu/amd/dualcore/dualcore.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -117,7 +107,6 @@
init_cpus(cpu_init_detectedx);
}
-
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
@@ -147,6 +136,4 @@
sdram_initialize(ARRAY_SIZE(cpu), cpu);
post_cache_as_ram();
-
}
-
Modified: trunk/src/mainboard/tyan/s2885/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2885/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/tyan/s2885/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -9,29 +9,23 @@
#include <console/console.h>
#include <lib.h>
#include <spd.h>
-
#include <cpu/amd/model_fxx_rev.h>
-
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@ -62,22 +56,13 @@
return smbus_read_byte(device, address);
}
-
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
#include "cpu/amd/dualcore/dualcore.c"
-
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
@@ -161,6 +146,4 @@
#endif
post_cache_as_ram();
-
}
-
Modified: trunk/src/mainboard/tyan/s2891/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2891/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/tyan/s2891/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -9,9 +9,7 @@
#include <console/console.h>
#include <lib.h>
#include <spd.h>
-
#include <cpu/amd/model_fxx_rev.h>
-
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
#include "northbridge/amd/amdk8/raminit.h"
@@ -21,10 +19,8 @@
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -50,19 +46,12 @@
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
#include "cpu/amd/dualcore/dualcore.c"
-
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
#include "southbridge/nvidia/ck804/ck804_early_setup.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
Modified: trunk/src/mainboard/tyan/s2892/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2892/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/tyan/s2892/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -6,27 +6,21 @@
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
#include <lib.h>
#include <spd.h>
-
#include <cpu/amd/model_fxx_rev.h>
-
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/nvidia/ck804/ck804_early_smbus.h"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
@@ -48,13 +42,10 @@
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
#include "cpu/amd/dualcore/dualcore.c"
-
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
+
//set GPIO to input mode
#define CK804_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+15, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* M8,GPIO16, PCIXA_PRSNT2_L*/ \
@@ -63,13 +54,8 @@
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/ \
#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
-
-
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
Modified: trunk/src/mainboard/tyan/s2895/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2895/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/tyan/s2895/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -59,12 +59,8 @@
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
#include "cpu/amd/dualcore/dualcore.c"
-
#include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
//set GPIO to input mode
@@ -77,11 +73,8 @@
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+45, ~(0xff),((0<<4)|(0<<2)|(0<<0)),/* P7,GPIO46, PCIXB_PRSNT2_L*/
#include "southbridge/nvidia/ck804/ck804_early_setup_car.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "northbridge/amd/amdk8/early_ht.c"
static void sio_setup(void)
Modified: trunk/src/mainboard/tyan/s2912/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/tyan/s2912/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -32,36 +32,27 @@
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include <pc80/mc146818rtc.h>
-
#include <console/console.h>
#include <lib.h>
#include <spd.h>
#include <usbdebug.h>
-
#include <cpu/amd/model_fxx_rev.h>
-
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
-
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/debug.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
static void memreset(int controllers, const struct mem_controller *ctrl)
{
}
@@ -81,9 +72,7 @@
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "northbridge/amd/amdk8/raminit_f.c"
#include "lib/generic_sdram.c"
-
#include "resourcemap.c"
-
#include "cpu/amd/dualcore/dualcore.c"
#define MCP55_MB_SETUP \
@@ -96,13 +85,9 @@
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/model_fxx/init_cpus.c"
-
#include "cpu/amd/model_fxx/fidvid.c"
-
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -34,32 +34,24 @@
#include <usbdebug.h>
#include <lib.h>
#include <spd.h>
-
#include <cpu/amd/model_10xxx_rev.h>
-
#include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
#include "northbridge/amd/amdfam10/raminit.h"
#include "northbridge/amd/amdfam10/amdfam10.h"
-
#include "cpu/amd/model_10xxx/apic_timer.c"
#include "lib/delay.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdfam10/reset_test.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
#include "superio/winbond/w83627hf/w83627hf_early_init.c"
-
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdfam10/debug.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
-
#include "northbridge/amd/amdfam10/setup_resource_map.c"
+#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/nvidia/mcp55/mcp55_early_ctrl.c"
-
static inline void activate_spd_rom(const struct mem_controller *ctrl)
{
/* nothing to do */
@@ -71,12 +63,9 @@
}
#include "northbridge/amd/amdfam10/amdfam10.h"
-
#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
#include "northbridge/amd/amdfam10/amdfam10_pci.c"
-
#include "resourcemap.c"
-
#include "cpu/amd/quadcore/quadcore.c"
#define MCP55_MB_SETUP \
@@ -89,14 +78,10 @@
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
-
#include "cpu/amd/car/post_cache_as_ram.c"
-
#include "cpu/amd/microcode/microcode.c"
#include "cpu/amd/model_10xxx/update_microcode.c"
#include "cpu/amd/model_10xxx/init_cpus.c"
-
-
#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
#include "northbridge/amd/amdfam10/early_ht.c"
Modified: trunk/src/mainboard/tyan/s4880/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s4880/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/tyan/s4880/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -9,28 +9,23 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <lib.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@ -75,29 +70,22 @@
return smbus_read_byte(device, address);
}
-
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/model_fxx/init_cpus.c"
+#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
#define RC0 ((1<<2)<<8)
#define RC1 ((1<<1)<<8)
#define RC2 ((1<<4)<<8)
#define RC3 ((1<<3)<<8)
-#include "cpu/amd/car/post_cache_as_ram.c"
-
-#include "cpu/amd/model_fxx/init_cpus.c"
-
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const struct mem_controller cpu[] = {
@@ -192,4 +180,3 @@
post_cache_as_ram();
}
-
Modified: trunk/src/mainboard/tyan/s4882/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s4882/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/tyan/s4882/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -8,28 +8,23 @@
#include <pc80/mc146818rtc.h>
#include <console/console.h>
#include <lib.h>
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "lib/delay.c"
-
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#include "northbridge/amd/amdk8/debug.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
#include "cpu/x86/mtrr/earlymtrr.c"
#include "cpu/x86/bist.h"
-
#include "northbridge/amd/amdk8/setup_resource_map.c"
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
static void memreset_setup(void)
{
if (is_cpu_pre_c0()) {
@@ -83,29 +78,22 @@
return smbus_read_byte(device, address);
}
-
#include "northbridge/amd/amdk8/raminit.c"
#include "northbridge/amd/amdk8/coherent_ht.c"
#include "lib/generic_sdram.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
+#include "resourcemap.c" /* tyan does not want the default */
#include "cpu/amd/dualcore/dualcore.c"
#include <spd.h>
+#include "cpu/amd/car/post_cache_as_ram.c"
+#include "cpu/amd/model_fxx/init_cpus.c"
+#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
#define RC0 ((1<<2)<<8)
#define RC1 ((1<<1)<<8)
#define RC2 ((1<<4)<<8)
#define RC3 ((1<<3)<<8)
-#include "cpu/amd/car/post_cache_as_ram.c"
-
-#include "cpu/amd/model_fxx/init_cpus.c"
-
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
static const uint16_t spd_addr [] = {
Modified: trunk/src/mainboard/via/epia-cn/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-cn/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/via/epia-cn/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -105,4 +105,3 @@
print_spew("Leaving romstage.c:main()\n");
}
-
Modified: trunk/src/mainboard/via/epia-m/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-m/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/via/epia-m/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -131,4 +131,3 @@
print_spew("Leaving romstage.c:main()\n");
}
-
Modified: trunk/src/mainboard/via/epia-m700/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-m700/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/via/epia-m700/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -38,15 +38,11 @@
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include <string.h>
-
/* This file contains the board-special SI value for raminit.c. */
#include "driving_clk_phase_data.c"
-
#include "northbridge/via/vx800/raminit.h"
#include "northbridge/via/vx800/raminit.c"
-
#include "wakeup.h"
-
#include "superio/winbond/w83697hf/w83697hf_early_serial.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
@@ -676,8 +672,5 @@
);
#endif
}
-
#endif
-
}
-
Modified: trunk/src/mainboard/via/epia-n/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia-n/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/via/epia-n/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -145,4 +145,3 @@
print_spew("Leaving romstage.c:main()\n");
}
-
Modified: trunk/src/mainboard/via/epia/romstage.c
==============================================================================
--- trunk/src/mainboard/via/epia/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/via/epia/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -23,9 +23,6 @@
}
#include "northbridge/via/vt8601/raminit.c"
-/*
- #include "lib/generic_sdram.c"
-*/
static void enable_mainboard_devices(void)
{
@@ -121,4 +118,3 @@
}
#endif
}
-
Modified: trunk/src/mainboard/via/pc2500e/romstage.c
==============================================================================
--- trunk/src/mainboard/via/pc2500e/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/via/pc2500e/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -74,4 +74,3 @@
/* ram_check(0, 640 * 1024); */
}
-
Modified: trunk/src/mainboard/via/vt8454c/romstage.c
==============================================================================
--- trunk/src/mainboard/via/vt8454c/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/via/vt8454c/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -30,13 +30,10 @@
#include <lib.h>
#include "northbridge/via/cx700/raminit.h"
#include "cpu/x86/bist.h"
-
-
#include "pc80/udelay_io.c"
#include "lib/delay.c"
#include "northbridge/via/cx700/cx700_early_smbus.c"
#include "lib/debug.c"
-
#include "northbridge/via/cx700/cx700_early_serial.c"
#include "northbridge/via/cx700/raminit.c"
#include <spd.h>
@@ -114,4 +111,3 @@
enable_shadow_ram(cx700);
sdram_enable(cx700);
}
-
Modified: trunk/src/mainboard/winent/pl6064/romstage.c
==============================================================================
--- trunk/src/mainboard/winent/pl6064/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/winent/pl6064/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -33,13 +33,12 @@
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
#include <spd.h>
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
static inline int spd_read_byte(unsigned int device, unsigned int address)
{
return smbus_read_byte(device, address);
@@ -99,4 +98,3 @@
/* Memory is setup. Return to cache_as_ram.inc and continue to boot. */
return;
}
-
Modified: trunk/src/mainboard/wyse/s50/romstage.c
==============================================================================
--- trunk/src/mainboard/wyse/s50/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/mainboard/wyse/s50/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -31,7 +31,6 @@
#include <cpu/amd/gx2def.h>
#include <cpu/amd/geode_post_code.h>
#include <spd.h>
-
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@ -84,4 +83,3 @@
/*ram_check(0x00000000, 640*1024);*/
print_err("ram check done\n");
}
-
Modified: trunk/src/northbridge/via/vx800/examples/romstage.c
==============================================================================
--- trunk/src/northbridge/via/vx800/examples/romstage.c Sun Nov 21 15:41:07 2010 (r6106)
+++ trunk/src/northbridge/via/vx800/examples/romstage.c Sun Nov 21 18:29:59 2010 (r6107)
@@ -38,13 +38,10 @@
#include "lib/delay.c"
#include "lib/memcpy.c"
#include "cpu/x86/lapic/boot_cpu.c"
-
#include "driving_clk_phase_data.c"
-
#include "northbridge/via/vx800/raminit.h"
#include "northbridge/via/vx800/raminit.c"
-
static int acpi_is_wakeup_early_via_vx800(void)
{
device_t dev;
@@ -77,7 +74,6 @@
return smbus_read_byte(device, address);
}
-
static void enable_mainboard_devices(void)
{
device_t dev;
@@ -103,10 +99,8 @@
/* 0xe0000-0xeffff - elfload? */
pci_write_config8(PCI_DEV(0, 0, 3), 0x82, 0xff);
-
}
-
/*
this table contains the value needed to be set before begin to init dram.
Note: REV_Bx should be cared when porting a new board!!!!! */
@@ -182,7 +176,8 @@
#define gCom1Base 0x3f8
#define gCom2Base 0x2f8
-void EmbedComInit()
+
+void EmbedComInit(void)
{
u8 ByteVal;
u16 ComBase;
@@ -233,8 +228,6 @@
ByteVal = (ByteVal & 0x3F) | 0xC0;
pci_write_config8(PCI_DEV(0, 17, 0), 0x46, ByteVal);
-
-
//enable embeded com1 and com2 D17F0RxB0[5,4]
ByteVal = pci_read_config8(PCI_DEV(0, 17, 0), 0xB0);
ByteVal = ByteVal & 0xcf;
@@ -296,8 +289,6 @@
//while(1);
}
-/* cache_as_ram.inc jump to here
-*/
void main(unsigned long bist)
{
unsigned cpu_reset = 0;
@@ -311,7 +302,6 @@
//enable_vx800_serial();
//uart_init();
-
/* 1. D15F0
a) RxBAh = 71h
1
0
Hi there,
I am trying to understand how ASUS m2v-mx se implements S4 sleep. I
think it implemented this because I tested it on a physical machine
with coreboot and LINUX installed. And the machine can go to
hibernation and wake up without any problem.
Then I start to read the code. However, I only found following code in
mainboard/asus/m2v-mx_se/dsdt.asl:
/* For now only define 2 power states:
* - S0 which is fully on
* - S5 which is soft off
* Any others would involve declaring the wake up methods.
*/
Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
Name (\_S3, Package () { 0x01, 0x01, 0x00, 0x00 })
Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
The above code said the board only supports s0 s3, and s5. So
something is missing? Why the Linux hibernation works but the code
said it only supports s3 and s5? Any suggestions? Thanks.
BTW: the comments for the code is wrong. The code also supports S3.
Also, I tested S3 on the same machine, but it turned out to be a
reboot. Is it a coreboot problem or Linux problem?
Regards,
Jiang
2
2
Current coreboot source tree ( revision 6084 ) for ASUS M2V-MX SE cannot boot?
by Fengwei Zhang 21 Nov '10
by Fengwei Zhang 21 Nov '10
21 Nov '10
Hi all,
I am not sure if this is true. I just tried current coreboot source tree
(revision 6084) for ASUS M2V-MX SE, it cannot boot.
It could compile successfully, and it will be dead at the beginning when
booting.
Below are the info from serial port:
coreboot-4.0-r6070M Wed Nov 17 16:20:19 EST 2010 starting...
now booting...
INIT detected from --- { APICID = 00 NODEID = 00 COREID = 00} ---
Issuing SOFT_RESET...
soft reset
I also compiled old versions, it could boot. such as version 5555(I just
random picked up and tested it)
I am wondering if there is anyone has some problem?
Best,
Fengwei
4
7
[commit] r6106 - in trunk/src/mainboard: arima/hdama broadcom/blast dell/s1850 getac/p470 gigabyte/ga_2761gxdk gigabyte/m57sli hp/dl145_g1 hp/dl145_g3 hp/dl165_g6_fam10 ibase/mb899 ibm/e325 ibm/e32...
by repository service 21 Nov '10
by repository service 21 Nov '10
21 Nov '10
Author: oxygene
Date: Sun Nov 21 15:41:07 2010
New Revision: 6106
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6106
Log:
Convert more boards to use mptable_write_buses.
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de>
Modified:
trunk/src/mainboard/arima/hdama/mptable.c
trunk/src/mainboard/broadcom/blast/get_bus_conf.c
trunk/src/mainboard/broadcom/blast/irq_tables.c
trunk/src/mainboard/broadcom/blast/mptable.c
trunk/src/mainboard/dell/s1850/mptable.c
trunk/src/mainboard/getac/p470/mptable.c
trunk/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
trunk/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c
trunk/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
trunk/src/mainboard/gigabyte/m57sli/get_bus_conf.c
trunk/src/mainboard/gigabyte/m57sli/irq_tables.c
trunk/src/mainboard/gigabyte/m57sli/mptable.c
trunk/src/mainboard/hp/dl145_g1/get_bus_conf.c
trunk/src/mainboard/hp/dl145_g1/mptable.c
trunk/src/mainboard/hp/dl145_g3/get_bus_conf.c
trunk/src/mainboard/hp/dl145_g3/mb_sysconf.h
trunk/src/mainboard/hp/dl145_g3/mptable.c
trunk/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
trunk/src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h
trunk/src/mainboard/hp/dl165_g6_fam10/mptable.c
trunk/src/mainboard/ibase/mb899/mptable.c
trunk/src/mainboard/ibm/e325/mptable.c
trunk/src/mainboard/ibm/e326/mptable.c
trunk/src/mainboard/intel/d945gclf/mptable.c
trunk/src/mainboard/iwill/dk8_htx/get_bus_conf.c
trunk/src/mainboard/iwill/dk8_htx/mb_sysconf.h
trunk/src/mainboard/iwill/dk8_htx/mptable.c
trunk/src/mainboard/iwill/dk8s2/mptable.c
trunk/src/mainboard/iwill/dk8x/mptable.c
trunk/src/mainboard/msi/ms7135/get_bus_conf.c
trunk/src/mainboard/msi/ms7135/irq_tables.c
trunk/src/mainboard/msi/ms7260/get_bus_conf.c
trunk/src/mainboard/msi/ms7260/irq_tables.c
trunk/src/mainboard/msi/ms7260/mptable.c
trunk/src/mainboard/msi/ms9185/get_bus_conf.c
trunk/src/mainboard/msi/ms9185/mb_sysconf.h
trunk/src/mainboard/msi/ms9185/mptable.c
trunk/src/mainboard/msi/ms9282/get_bus_conf.c
trunk/src/mainboard/msi/ms9282/mb_sysconf.h
trunk/src/mainboard/msi/ms9282/mptable.c
trunk/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
trunk/src/mainboard/msi/ms9652_fam10/mb_sysconf.h
trunk/src/mainboard/msi/ms9652_fam10/mptable.c
trunk/src/mainboard/newisys/khepri/mptable.c
trunk/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
trunk/src/mainboard/nvidia/l1_2pvv/mb_sysconf.h
trunk/src/mainboard/nvidia/l1_2pvv/mptable.c
trunk/src/mainboard/roda/rk886ex/mptable.c
trunk/src/mainboard/sunw/ultra40/get_bus_conf.c
trunk/src/mainboard/sunw/ultra40/mptable.c
trunk/src/mainboard/tyan/s2881/get_bus_conf.c
trunk/src/mainboard/tyan/s2881/mptable.c
trunk/src/mainboard/tyan/s2882/mptable.c
trunk/src/mainboard/tyan/s2885/get_bus_conf.c
trunk/src/mainboard/tyan/s2885/mptable.c
trunk/src/mainboard/tyan/s2891/get_bus_conf.c
trunk/src/mainboard/tyan/s2891/irq_tables.c
trunk/src/mainboard/tyan/s2891/mptable.c
trunk/src/mainboard/tyan/s2892/get_bus_conf.c
trunk/src/mainboard/tyan/s2892/irq_tables.c
trunk/src/mainboard/tyan/s2892/mptable.c
trunk/src/mainboard/tyan/s2895/get_bus_conf.c
trunk/src/mainboard/tyan/s2895/mptable.c
trunk/src/mainboard/tyan/s2912/get_bus_conf.c
trunk/src/mainboard/tyan/s2912/mb_sysconf.h
trunk/src/mainboard/tyan/s2912/mptable.c
trunk/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
trunk/src/mainboard/tyan/s2912_fam10/mb_sysconf.h
trunk/src/mainboard/tyan/s2912_fam10/mptable.c
Modified: trunk/src/mainboard/arima/hdama/mptable.c
==============================================================================
--- trunk/src/mainboard/arima/hdama/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/arima/hdama/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -111,8 +111,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- unsigned char bus_num;
- unsigned char bus_isa;
+ int bus_isa;
unsigned char bus_chain_0;
unsigned char bus_8131_1;
unsigned char bus_8131_2;
@@ -146,44 +145,32 @@
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", bus_chain_0);
-
bus_8111_1 = 4;
- bus_isa = 5;
}
/* 8131-1 */
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
if (dev) {
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_chain_0);
-
bus_8131_1 = 2;
}
/* 8131-2 */
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x02,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_chain_0);
-
bus_8131_2 = 3;
}
}
- /* define bus and isa numbers */
- for(bus_num = 0; bus_num < bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
Modified: trunk/src/mainboard/broadcom/blast/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/broadcom/blast/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/broadcom/blast/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -13,7 +13,6 @@
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
-unsigned char bus_isa = 10;
unsigned char bus_bcm5780[7];
unsigned char bus_bcm5785_0 = 1;
unsigned char bus_bcm5785_1 = 8;
@@ -83,11 +82,6 @@
dev = dev_find_slot(bus_bcm5785_1, PCI_DEVFN(0x0d,0));
if(dev) {
bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
-// printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
-#endif
}
}
else {
@@ -99,12 +93,6 @@
dev = dev_find_slot(bus_bcm5780[0], PCI_DEVFN(sbdn2 + i - 1,0));
if(dev) {
bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
-// printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
-#endif
-
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:01.0, using defaults\n", bus_bcm5780[i]);
Modified: trunk/src/mainboard/broadcom/blast/irq_tables.c
==============================================================================
--- trunk/src/mainboard/broadcom/blast/irq_tables.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/broadcom/blast/irq_tables.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -32,7 +32,6 @@
pirq_info->rfu = rfu;
}
-extern unsigned char bus_isa;
extern unsigned char bus_bcm5780[7];
extern unsigned char bus_bcm5785_0;
extern unsigned char bus_bcm5785_1;
Modified: trunk/src/mainboard/broadcom/blast/mptable.c
==============================================================================
--- trunk/src/mainboard/broadcom/blast/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/broadcom/blast/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -9,7 +9,6 @@
#endif
#include <cpu/amd/amdk8_sysconf.h>
-extern unsigned char bus_isa;
extern unsigned char bus_bcm5780[7];
extern unsigned char bus_bcm5785_0;
extern unsigned char bus_bcm5785_1;
@@ -21,8 +20,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- unsigned char bus_num;
- int i;
+ int i, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -32,12 +30,7 @@
get_bus_conf();
-/*Bus: Bus ID Type*/
- /* define bus and isa numbers */
- for(bus_num = 0; bus_num < bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
Modified: trunk/src/mainboard/dell/s1850/mptable.c
==============================================================================
--- trunk/src/mainboard/dell/s1850/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/dell/s1850/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -8,8 +8,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- unsigned char bus_num;
- unsigned char bus_isa;
+ int bus_isa;
unsigned char bus_pxhd_1;
unsigned char bus_pxhd_2;
unsigned char bus_pxhd_3;
@@ -29,35 +28,27 @@
dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
if (dev) {
bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n");
-
bus_ich5r_1 = 7;
- bus_isa = 8;
}
/* pxhd-1 */
dev = dev_find_slot(1, PCI_DEVFN(0x0,0));
if (dev) {
bus_pxhd_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.0, using defaults\n");
-
bus_pxhd_1 = 2;
}
/* pxhd-2 */
dev = dev_find_slot(1, PCI_DEVFN(0x00,2));
if (dev) {
bus_pxhd_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:00.2, using defaults\n");
-
bus_pxhd_2 = 3;
}
@@ -65,32 +56,24 @@
dev = dev_find_slot(0, PCI_DEVFN(0x4,0));
if (dev) {
bus_pxhd_3 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0, using defaults\n");
-
bus_pxhd_3 = 5;
}
/* pxhd-4 */
dev = dev_find_slot(0, PCI_DEVFN(0x06,0));
if (dev) {
bus_pxhd_4 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 0:06.0, using defaults\n");
-
bus_pxhd_4 = 6;
}
}
- /* define bus and isa numbers */
- for(bus_num = 0; bus_num < bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
Modified: trunk/src/mainboard/getac/p470/mptable.c
==============================================================================
--- trunk/src/mainboard/getac/p470/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/getac/p470/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -30,8 +30,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- int i;
- int max_pci_bus, isa_bus;
+ int isa_bus;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -39,16 +38,7 @@
smp_write_processors(mc);
- max_pci_bus = 5; // XXX read me from bridges.
-
- /* ISA bus follows */
- isa_bus = max_pci_bus + 1;
-
- /* Bus: Bus ID Type */
- for (i=0; i <= max_pci_bus; i++)
- smp_write_bus(mc, i, "PCI ");
-
- smp_write_bus(mc, isa_bus, "ISA ");
+ mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -36,7 +36,6 @@
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
- unsigned char bus_isa;
unsigned char bus_sis966[8]; //1
unsigned apicid_sis966;
@@ -64,9 +63,6 @@
// 0x20202020,
// 0x20202020,
};
-unsigned bus_type[256];
-
-
static unsigned get_bus_conf_done = 0;
@@ -77,7 +73,7 @@
unsigned sbdn;
device_t dev;
- int i, j;
+ int i;
if(get_bus_conf_done==1) return; //do it only once
@@ -98,23 +94,14 @@
bus_sis966[i] = 0;
}
- for(i=0;i<256; i++) {
- bus_type[i] = 0;
- }
-
- bus_type[0] = 1; //pci
-
bus_sis966[0] = (sysconf.pci1234[0] >> 16) & 0xff;
- bus_type[bus_sis966[0]] = 1;
-
/* SIS966 */
dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn + 0x06,0));
if (dev) {
bus_sis966[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_sis966[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_sis966[2]++;
- for(j=bus_sis966[1];j<bus_sis966[2]; j++) bus_type[j] = 1;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06);
@@ -127,14 +114,7 @@
dev = dev_find_slot(bus_sis966[0], PCI_DEVFN(sbdn + 0x0a + i - 2 , 0));
if (dev) {
bus_sis966[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- for(j=bus_sis966[i];j<bus_isa; j++) bus_type[j] = 1;
}
- else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_sis966[0], sbdn + 0x0a + i - 2 );
- bus_isa = bus_sis966[i-1]+1;
- }
}
Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -52,11 +52,8 @@
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
-extern unsigned char bus_isa;
extern unsigned char bus_sis966[8]; //1
-
-
unsigned long write_pirq_routing_table(unsigned long addr)
{
Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/mptable.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ga_2761gxdk/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/gigabyte/ga_2761gxdk/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -28,18 +28,15 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
-extern unsigned char bus_isa;
extern unsigned char bus_sis966[8]; //1
extern unsigned apicid_sis966;
-extern unsigned bus_type[256];
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned sbdn;
- int i,j;
+ int i, j, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -50,13 +47,7 @@
get_bus_conf();
sbdn = sysconf.sbdn;
-/*Bus: Bus ID Type*/
- /* define bus and isa numbers */
- for(j= 0; j < 256 ; j++) {
- if(bus_type[j])
- smp_write_bus(mc, j, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
Modified: trunk/src/mainboard/gigabyte/m57sli/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/gigabyte/m57sli/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -34,7 +34,6 @@
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
- unsigned char bus_isa;
unsigned char bus_mcp55[8]; //1
unsigned apicid_mcp55;
@@ -62,9 +61,6 @@
// 0x20202020,
// 0x20202020,
};
-unsigned bus_type[256];
-
-
static unsigned get_bus_conf_done = 0;
@@ -75,7 +71,7 @@
unsigned sbdn;
device_t dev;
- int i, j;
+ int i;
if(get_bus_conf_done==1) return; //do it only once
@@ -96,23 +92,14 @@
bus_mcp55[i] = 0;
}
- for(i=0;i<256; i++) {
- bus_type[i] = 0;
- }
-
- bus_type[0] = 1; //pci
-
bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
- bus_type[bus_mcp55[0]] = 1;
-
/* MCP55 */
dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06,0));
if (dev) {
bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_mcp55[2]++;
- for(j=bus_mcp55[1];j<bus_mcp55[2]; j++) bus_type[j] = 1;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn + 0x06);
@@ -125,14 +112,7 @@
dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x0a + i - 2 , 0));
if (dev) {
bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- for(j=bus_mcp55[i];j<bus_isa; j++) bus_type[j] = 1;
}
- else {
- printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_mcp55[0], sbdn + 0x0a + i - 2 );
- bus_isa = bus_mcp55[i-1]+1;
- }
}
Modified: trunk/src/mainboard/gigabyte/m57sli/irq_tables.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/irq_tables.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/gigabyte/m57sli/irq_tables.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -50,7 +50,6 @@
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
-extern unsigned char bus_isa;
extern unsigned char bus_mcp55[8]; //1
Modified: trunk/src/mainboard/gigabyte/m57sli/mptable.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/gigabyte/m57sli/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -27,18 +27,15 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
-extern unsigned char bus_isa;
extern unsigned char bus_mcp55[8]; //1
extern unsigned apicid_mcp55;
-extern unsigned bus_type[256];
-
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned sbdn;
- int i,j,k;
+ int i, j, k, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -49,13 +46,7 @@
get_bus_conf();
sbdn = sysconf.sbdn;
-/*Bus: Bus ID Type*/
- /* define bus and isa numbers */
- for(j= 0; j < 256 ; j++) {
- if(bus_type[j])
- smp_write_bus(mc, j, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
@@ -106,7 +97,7 @@
}
/* On bus 1: the PCI bus slots...
- pyhsical PCI slots are j = 7,8
+ physical PCI slots are j = 7,8
FireWire is j = 10
*/
k=2;
Modified: trunk/src/mainboard/hp/dl145_g1/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g1/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/hp/dl145_g1/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -13,7 +13,6 @@
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
-unsigned char bus_isa = 5 ;
unsigned char bus_8131_0 = 1;
unsigned char bus_8131_1 = 2;
unsigned char bus_8131_2 = 3;
@@ -82,11 +81,6 @@
dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
-// printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
-#endif
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0);
@@ -105,11 +99,6 @@
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
-// printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
-#endif
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
Modified: trunk/src/mainboard/hp/dl145_g1/mptable.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g1/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/hp/dl145_g1/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -6,7 +6,6 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
-extern unsigned char bus_isa;
extern unsigned char bus_8131_0;
extern unsigned char bus_8131_1;
extern unsigned char bus_8131_2;
@@ -21,7 +20,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- unsigned char bus_num;
+ int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -31,13 +30,7 @@
get_bus_conf();
-/*Bus: Bus ID Type*/
- /* define bus and isa numbers */
- for(bus_num = 0; bus_num < bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
-
+ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, apicid_8111, 0x20, IO_APIC_ADDR);
Modified: trunk/src/mainboard/hp/dl145_g3/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g3/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/hp/dl145_g3/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -108,11 +108,6 @@
printk(BIOS_DEBUG, "now found %s...\n",dev_path(dev));
if(dev) {
m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
- m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- m->bus_isa++;
- printk(BIOS_DEBUG, "bus_isa 1=%d\n",m->bus_isa);
-#endif
}
}
else {
@@ -124,12 +119,6 @@
dev = dev_find_slot(m->bus_bcm5780[0], PCI_DEVFN(m->sbdn2 + i - 1,0));
if(dev) {
m->bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
- m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- m->bus_isa++;
- printk(BIOS_DEBUG, "bus_isa 2=%d\n",m->bus_isa);
-#endif
-
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5780[0], m->sbdn2+i-1);
Modified: trunk/src/mainboard/hp/dl145_g3/mb_sysconf.h
==============================================================================
--- trunk/src/mainboard/hp/dl145_g3/mb_sysconf.h Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/hp/dl145_g3/mb_sysconf.h Sun Nov 21 15:41:07 2010 (r6106)
@@ -29,7 +29,6 @@
#define MB_SYSCONF_H
struct mb_sysconf_t {
- unsigned char bus_isa;
unsigned char bus_bcm5780[7];
unsigned char bus_bcm5785_0;
unsigned char bus_bcm5785_1;
Modified: trunk/src/mainboard/hp/dl145_g3/mptable.c
==============================================================================
--- trunk/src/mainboard/hp/dl145_g3/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/hp/dl145_g3/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -43,6 +43,7 @@
{
struct mp_config_table *mc;
struct mb_sysconf_t *m;
+ int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -53,22 +54,7 @@
get_bus_conf();
m = sysconf.mb;
- /*Bus: Bus ID Type*/
- /* define bus and isa numbers */
-#if 0
- unsigned char bus_num;
- for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- printk(BIOS_DEBUG, "writing bus %d as PCI...\n",bus_num);
- }
-#endif
- smp_write_bus(mc, 0, "PCI ");
- smp_write_bus(mc, 1, "PCI ");
- smp_write_bus(mc, 7, "PCI ");
- smp_write_bus(mc, 8, "PCI ");
-
- smp_write_bus(mc,m->bus_isa, "ISA ");
- printk(BIOS_DEBUG, "writing %d as ISA...\n",m->bus_isa);
+ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
@@ -130,7 +116,7 @@
}
}
- mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_bcm5785[0], 0);
+ mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0);
//SATA
/* printk(BIOS_DEBUG, "MPTABLE_SATA: bus_id:%d irq:%d apic_id:%d pin:%d\n",m->bus_bcm5785_1, (0x0e<<2)|0, m->apicid_bcm5785[0], 0x7); */
@@ -177,9 +163,9 @@
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- printk(BIOS_DEBUG, "m->bus_isa is: %x\n",m->bus_isa);
- smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
- smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa , 0x0, MP_APIC_ALL, 0x1);
+ printk(BIOS_DEBUG, "bus_isa is: %x\n", bus_isa);
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa , 0x0, MP_APIC_ALL, 0x1);
//extended table entries
smp_write_address_space(mc,0 , ADDRESS_TYPE_IO, 0x0, 0x0, 0x0, 0x0001);
Modified: trunk/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/hp/dl165_g6_fam10/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -110,11 +110,6 @@
printk(BIOS_DEBUG, "now found %s...\n",dev_path(dev));
if(dev) {
m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
- m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- m->bus_isa++;
- printk(BIOS_DEBUG, "bus_isa 1=%d\n",m->bus_isa);
-#endif
}
}
else {
@@ -126,11 +121,6 @@
dev = dev_find_slot(m->bus_bcm5780[0], PCI_DEVFN(m->sbdn2 + i - 1,0));
if(dev) {
m->bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
- m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- m->bus_isa++;
- printk(BIOS_DEBUG, "bus_isa 2=%d\n",m->bus_isa);
-#endif
}
else {
Modified: trunk/src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h
==============================================================================
--- trunk/src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/hp/dl165_g6_fam10/mb_sysconf.h Sun Nov 21 15:41:07 2010 (r6106)
@@ -29,7 +29,6 @@
#define MB_SYSCONF_H
struct mb_sysconf_t {
- unsigned char bus_isa;
unsigned char bus_bcm5780[7];
unsigned char bus_bcm5785_0;
unsigned char bus_bcm5785_1;
@@ -37,7 +36,6 @@
unsigned apicid_bcm5785[3];
unsigned sbdn2;
- unsigned bus_type[256];
};
#endif
Modified: trunk/src/mainboard/hp/dl165_g6_fam10/mptable.c
==============================================================================
--- trunk/src/mainboard/hp/dl165_g6_fam10/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/hp/dl165_g6_fam10/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -56,7 +56,6 @@
m = sysconf.mb;
mptable_write_buses(mc, NULL, &isa_bus);
- printk(BIOS_DEBUG, "writing %d as ISA to mptable (%d for real)...\n", isa_bus, m->bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
Modified: trunk/src/mainboard/ibase/mb899/mptable.c
==============================================================================
--- trunk/src/mainboard/ibase/mb899/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/ibase/mb899/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -29,8 +29,7 @@
{
struct mp_config_table *mc;
struct device *riser = NULL, *firewire = NULL;
- int i;
- int max_pci_bus, firewire_bus = 0, riser_bus = 0, isa_bus;
+ int firewire_bus = 0, riser_bus = 0, isa_bus;
int ioapic_id;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -38,14 +37,12 @@
mptable_init(mc, "MB899 ", LAPIC_ADDR);
smp_write_processors(mc);
- max_pci_bus=0;
firewire = dev_find_device(0x104c, 0x8023, 0);
if (firewire) {
firewire_bus = firewire->bus->secondary;
printk(BIOS_SPEW, "Firewire device is on bus %x\n",
firewire_bus);
- max_pci_bus = firewire_bus;
}
// If a riser card is used, this riser is detected on bus 4, so its secondary bus is the
@@ -56,17 +53,9 @@
if (riser) {
riser_bus = riser->link_list->secondary;
printk(BIOS_SPEW, "Riser bus is %x\n", riser_bus);
- max_pci_bus = riser_bus;
}
- /* ISA bus follows */
- isa_bus = max_pci_bus + 1;
-
- /* Bus: Bus ID Type */
- for (i=0; i <= max_pci_bus; i++)
- smp_write_bus(mc, i, "PCI ");
-
- smp_write_bus(mc, isa_bus, "ISA ");
+ mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
ioapic_id = 2;
Modified: trunk/src/mainboard/ibm/e325/mptable.c
==============================================================================
--- trunk/src/mainboard/ibm/e325/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/ibm/e325/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -9,8 +9,7 @@
{
struct mp_config_table *mc;
- unsigned char bus_num;
- unsigned char bus_isa;
+ int bus_isa;
unsigned char bus_8111_0;
unsigned char bus_8111_1;
unsigned char bus_8131_1;
@@ -30,13 +29,10 @@
if (dev) {
bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
} else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
bus_8111_0 = 1;
bus_8111_1 = 4;
- bus_isa = 5;
}
/* 8131-1 */
@@ -59,11 +55,7 @@
}
}
- /* define bus and isa numbers */
- for (bus_num = 0; bus_num < bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* Legacy IOAPIC #2 */
smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
Modified: trunk/src/mainboard/ibm/e326/mptable.c
==============================================================================
--- trunk/src/mainboard/ibm/e326/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/ibm/e326/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -9,8 +9,7 @@
{
struct mp_config_table *mc;
- unsigned char bus_num;
- unsigned char bus_isa;
+ int bus_isa;
unsigned char bus_8111_0;
unsigned char bus_8111_1;
unsigned char bus_8131_1;
@@ -30,13 +29,10 @@
if (dev) {
bus_8111_0 = pci_read_config8(dev, PCI_PRIMARY_BUS);
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
} else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
bus_8111_0 = 1;
bus_8111_1 = 4;
- bus_isa = 5;
}
/* 8131-1 */
@@ -58,11 +54,7 @@
}
}
- /* define bus and isa numbers */
- for (bus_num = 0; bus_num < bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* Legacy IOAPIC #2 */
smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
Modified: trunk/src/mainboard/intel/d945gclf/mptable.c
==============================================================================
--- trunk/src/mainboard/intel/d945gclf/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/intel/d945gclf/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -28,8 +28,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- int i;
- int max_pci_bus, isa_bus;
+ int isa_bus;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -37,16 +36,7 @@
smp_write_processors(mc);
- max_pci_bus = 5; // XXX read me from bridges.
-
- /* ISA bus follows */
- isa_bus = max_pci_bus + 1;
-
- /* Bus: Bus ID Type */
- for (i=0; i <= max_pci_bus; i++)
- smp_write_bus(mc, i, "PCI ");
-
- smp_write_bus(mc, isa_bus, "ISA ");
+ mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
Modified: trunk/src/mainboard/iwill/dk8_htx/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/iwill/dk8_htx/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -109,11 +109,6 @@
dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
if (dev) {
m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
- m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- m->bus_isa++;
-// printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
-#endif
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8111_0, sysconf.sbdn);
@@ -132,11 +127,6 @@
dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0));
if (dev) {
m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
- m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- m->bus_isa++;
-// printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
-#endif
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1);
@@ -172,9 +162,6 @@
dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1,0));
if (dev) {
m->bus_8132a[j][2] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- m->bus_isa++;
- // printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]+1);
@@ -191,9 +178,6 @@
if (dev) {
m->bus_8151[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- // printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151[j][1]);
- m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- m->bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151[j][0], m->sbdn5[j]+1);
Modified: trunk/src/mainboard/iwill/dk8_htx/mb_sysconf.h
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/mb_sysconf.h Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/iwill/dk8_htx/mb_sysconf.h Sun Nov 21 15:41:07 2010 (r6106)
@@ -3,7 +3,6 @@
#define MB_SYSCONF_H
struct mb_sysconf_t {
- unsigned char bus_isa;
unsigned char bus_8132_0;
unsigned char bus_8132_1;
unsigned char bus_8132_2;
Modified: trunk/src/mainboard/iwill/dk8_htx/mptable.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8_htx/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/iwill/dk8_htx/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -13,8 +13,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- unsigned char bus_num;
- int i, j;
+ int i, j, bus_isa;
struct mb_sysconf_t *m;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -27,12 +26,7 @@
m = sysconf.mb;
-/*Bus: Bus ID Type*/
- /* define bus and isa numbers */
- for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, m->bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111
@@ -83,7 +77,7 @@
}
- mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_8111, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0);
//??? What
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
@@ -173,8 +167,8 @@
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
- smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
Modified: trunk/src/mainboard/iwill/dk8s2/mptable.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8s2/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/iwill/dk8s2/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -8,8 +8,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- unsigned char bus_num;
- unsigned char bus_isa;
+ int bus_isa;
unsigned char bus_8131_1;
unsigned char bus_8131_2;
unsigned char bus_8111_1;
@@ -27,44 +26,32 @@
dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
-
bus_8111_1 = 4;
- bus_isa = 5;
}
/* 8131-1 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
if (dev) {
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
-
bus_8131_1 = 2;
}
/* 8131-2 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
-
bus_8131_2 = 3;
}
}
- /* define bus and isa numbers */
- for(bus_num = 0; bus_num < bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
Modified: trunk/src/mainboard/iwill/dk8x/mptable.c
==============================================================================
--- trunk/src/mainboard/iwill/dk8x/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/iwill/dk8x/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -8,8 +8,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- unsigned char bus_num;
- unsigned char bus_isa;
+ int bus_isa;
unsigned char bus_8131_1;
unsigned char bus_8131_2;
unsigned char bus_8111_1;
@@ -27,44 +26,32 @@
dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
-
bus_8111_1 = 4;
- bus_isa = 5;
}
/* 8131-1 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
if (dev) {
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
-
bus_8131_1 = 2;
}
/* 8131-2 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
-
bus_8131_2 = 3;
}
}
- /* define bus and isa numbers */
- for(bus_num = 0; bus_num < bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
smp_write_ioapic(mc, 2, 0x11, IO_APIC_ADDR);
Modified: trunk/src/mainboard/msi/ms7135/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/msi/ms7135/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/msi/ms7135/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -38,7 +38,6 @@
* mptable and acpi_tables.
*/
/* busnum is default */
-unsigned char bus_isa;
unsigned char bus_ck804[6];
unsigned apicid_ck804;
@@ -49,9 +48,6 @@
unsigned hcdnx[] = { //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
0x20202020, //ms7135 has only one ht-chain
};
-unsigned bus_type[256];
-
-
static unsigned get_bus_conf_done = 0;
@@ -61,7 +57,7 @@
device_t dev;
unsigned sbdn;
- int i, j;
+ int i;
if (get_bus_conf_done == 1)
return; //do it only once
@@ -84,16 +80,8 @@
bus_ck804[i] = 0;
}
- for (i = 0; i < 256; i++) {
- bus_type[i] = 0;
- }
-
- bus_type[0] = 1; //pci
-
bus_ck804[0] = (sysconf.pci1234[0] >> 16) & 0xff;
- bus_type[bus_ck804[0]] = 1;
-
/* CK804 */
int dn = -1;
for (i = 1; i < 4; i++) {
@@ -106,15 +94,6 @@
dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + dn, 0));
if (dev) {
bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- for (j = bus_ck804[i]; j < bus_isa; j++)
- bus_type[j] = 1;
- } else {
- printk
- (BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- bus_ck804[0], sbdn + dn);
- bus_isa = bus_ck804[i - 1] + 1;
}
}
Modified: trunk/src/mainboard/msi/ms7135/irq_tables.c
==============================================================================
--- trunk/src/mainboard/msi/ms7135/irq_tables.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/msi/ms7135/irq_tables.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -35,7 +35,6 @@
#include <arch/pirq_routing.h>
#include <cpu/amd/amdk8_sysconf.h>
-extern unsigned char bus_isa;
extern unsigned char bus_ck804[6];
Modified: trunk/src/mainboard/msi/ms7260/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/msi/ms7260/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -32,7 +32,6 @@
/* Global variables for MB layouts (shared by irqtable/mptable/acpi_table). */
// busnum is default.
-unsigned char bus_isa;
unsigned char bus_mcp55[8]; // 1
unsigned apicid_mcp55;
@@ -65,17 +64,13 @@
// 0x20202020,
};
-unsigned bus_type[256];
-
-
-
static unsigned get_bus_conf_done = 0;
void get_bus_conf(void)
{
unsigned int apicid_base, sbdn;
device_t dev;
- int i, j;
+ int i;
if (get_bus_conf_done == 1)
return; /* Do it only once. */
@@ -96,23 +91,14 @@
for (i = 0; i < 8; i++)
bus_mcp55[i] = 0;
- for (i = 0; i < 256; i++)
- bus_type[i] = 0;
-
- bus_type[0] = 1; /* PCI */
-
bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
- bus_type[bus_mcp55[0]] = 1;
-
/* MCP55 */
dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x06, 0));
if (dev) {
bus_mcp55[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
bus_mcp55[2] = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
bus_mcp55[2]++;
- for (j = bus_mcp55[1]; j < bus_mcp55[2]; j++)
- bus_type[j] = 1;
} else {
printk
(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n",
@@ -127,15 +113,6 @@
PCI_DEVFN(sbdn + 0x0a + i - 2, 0));
if (dev) {
bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- for (j = bus_mcp55[i]; j < bus_isa; j++)
- bus_type[j] = 1;
- } else {
- printk
- (BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n",
- bus_mcp55[0], sbdn + 0x0a + i - 2);
- bus_isa = bus_mcp55[i - 1] + 1;
}
}
Modified: trunk/src/mainboard/msi/ms7260/irq_tables.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/irq_tables.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/msi/ms7260/irq_tables.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -46,11 +46,8 @@
pirq_info->rfu = rfu;
}
-extern unsigned char bus_isa;
extern unsigned char bus_mcp55[8]; // 1
-
-
unsigned long write_pirq_routing_table(unsigned long addr)
{
struct irq_routing_table *pirq;
Modified: trunk/src/mainboard/msi/ms7260/mptable.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/msi/ms7260/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -26,16 +26,14 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
-extern unsigned char bus_isa;
extern unsigned char bus_mcp55[8]; // 1
extern unsigned apicid_mcp55;
-extern unsigned bus_type[256];
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
unsigned int sbdn;
- int i, j;
+ int i, j, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -46,13 +44,7 @@
get_bus_conf();
sbdn = sysconf.sbdn;
- /* Bus: Bus ID Type */
- /* Define bus and ISA numbers. */
- for (j = 0; j < 256; j++) {
- if (bus_type[j])
- smp_write_bus(mc, j, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
Modified: trunk/src/mainboard/msi/ms9185/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/msi/ms9185/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/msi/ms9185/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -105,11 +105,6 @@
dev = dev_find_slot(m->bus_bcm5785_1, PCI_DEVFN(0xd,0));
if(dev) {
m->bus_bcm5785_1_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
- m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- m->bus_isa++;
- printk(BIOS_DEBUG, "bus_isa=%d\n",m->bus_isa);
-#endif
}
}
else {
@@ -121,12 +116,6 @@
dev = dev_find_slot(m->bus_bcm5780[0], PCI_DEVFN(m->sbdn2 + i - 1,0));
if(dev) {
m->bus_bcm5780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
- m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- m->bus_isa++;
- printk(BIOS_DEBUG, "bus_isa=%d\n",m->bus_isa);
-#endif
-
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_bcm5780[0], m->sbdn2+i-1);
Modified: trunk/src/mainboard/msi/ms9185/mb_sysconf.h
==============================================================================
--- trunk/src/mainboard/msi/ms9185/mb_sysconf.h Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/msi/ms9185/mb_sysconf.h Sun Nov 21 15:41:07 2010 (r6106)
@@ -25,7 +25,6 @@
#define MB_SYSCONF_H
struct mb_sysconf_t {
- unsigned char bus_isa;
unsigned char bus_bcm5780[7];
unsigned char bus_bcm5785_0;
unsigned char bus_bcm5785_1;
Modified: trunk/src/mainboard/msi/ms9185/mptable.c
==============================================================================
--- trunk/src/mainboard/msi/ms9185/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/msi/ms9185/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -40,9 +40,8 @@
{
struct mp_config_table *mc;
- unsigned char bus_num;
- int i;
- struct mb_sysconf_t *m;
+ int i, bus_isa;
+ struct mb_sysconf_t *m;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -50,15 +49,10 @@
smp_write_processors(mc);
- get_bus_conf();
- m = sysconf.mb;
+ get_bus_conf();
+ m = sysconf.mb;
-/*Bus: Bus ID Type*/
- /* define bus and isa numbers */
- for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, m->bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
@@ -76,7 +70,7 @@
}
- mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_bcm5785[0], 0);
+ mptable_add_isa_interrupts(mc, bus_isa, m->apicid_bcm5785[0], 0);
//IDE
outb(0x02, 0xc00); outb(0x0e, 0xc01);
@@ -152,8 +146,8 @@
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
- smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
Modified: trunk/src/mainboard/msi/ms9282/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/msi/ms9282/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -75,7 +75,7 @@
struct mb_sysconf_t *m;
device_t dev;
- int i, j;
+ int i;
if(get_bus_conf_done==1) return; //do it only once
@@ -96,8 +96,6 @@
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
- m->bus_type[0] = 1; //pci
-
m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
/* MCP55 */
@@ -119,20 +117,6 @@
}
}
- for(i=0; i< sysconf.hc_possible_num; i++) {
- if(!(sysconf.pci1234[i] & 0x1) ) continue;
-
- unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
- unsigned busn_max = (sysconf.pci1234[i] >> 24) & 0xff;
- for (j = busn; j <= busn_max; j++)
- m->bus_type[j] = 1;
- if(m->bus_isa <= busn_max)
- m->bus_isa = busn_max + 1;
- printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
- }
-
-
-
/*I/O APICs: APIC ID Version State Address*/
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
Modified: trunk/src/mainboard/msi/ms9282/mb_sysconf.h
==============================================================================
--- trunk/src/mainboard/msi/ms9282/mb_sysconf.h Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/msi/ms9282/mb_sysconf.h Sun Nov 21 15:41:07 2010 (r6106)
@@ -26,11 +26,8 @@
#define MB_SYSCONF_H
struct mb_sysconf_t {
- unsigned char bus_isa;
unsigned char bus_mcp55[8]; //1
unsigned apicid_mcp55;
- unsigned bus_type[256];
-
};
#endif
Modified: trunk/src/mainboard/msi/ms9282/mptable.c
==============================================================================
--- trunk/src/mainboard/msi/ms9282/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/msi/ms9282/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -36,7 +36,7 @@
struct mb_sysconf_t *m;
unsigned sbdn;
- int i,j;
+ int i, j, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -44,17 +44,11 @@
smp_write_processors(mc);
- get_bus_conf();
- sbdn = sysconf.sbdn;
- m = sysconf.mb;
-
-/*Bus: Bus ID Type*/
- /* define bus and isa numbers */
- for(j= 0; j < 256 ; j++) {
- if(m->bus_type[j])
- smp_write_bus(mc, j, "PCI ");
- }
- smp_write_bus(mc, m->bus_isa, "ISA ");
+ get_bus_conf();
+ sbdn = sysconf.sbdn;
+ m = sysconf.mb;
+
+ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
@@ -83,7 +77,7 @@
}
- mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_mcp55, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
//SMBUS
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
@@ -121,8 +115,8 @@
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
- smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
Modified: trunk/src/mainboard/msi/ms9652_fam10/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/msi/ms9652_fam10/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -72,7 +72,7 @@
struct mb_sysconf_t *m;
device_t dev;
- int i, j;
+ int i;
printk(BIOS_SPEW, "get_bus_conf()\n");
@@ -93,7 +93,6 @@
get_pci1234();
- m->bus_type[0] = 1; //pci
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff;
@@ -116,18 +115,6 @@
}
}
- for(i=0; i< sysconf.hc_possible_num; i++) {
- if(!(sysconf.pci1234[i] & 0x1) ) continue;
-
- unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
- unsigned busn_max = (sysconf.pci1234[i] >> 20) & 0xff;
- for (j = busn; j <= busn_max; j++)
- m->bus_type[j] = 1;
- if(m->bus_isa <= busn_max)
- m->bus_isa = busn_max + 1;
- printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
- }
-
/*I/O APICs: APIC ID Version State Address*/
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
Modified: trunk/src/mainboard/msi/ms9652_fam10/mb_sysconf.h
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/mb_sysconf.h Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/msi/ms9652_fam10/mb_sysconf.h Sun Nov 21 15:41:07 2010 (r6106)
@@ -23,11 +23,8 @@
#define MB_SYSCONF_H
struct mb_sysconf_t {
- unsigned char bus_isa;
unsigned char bus_mcp55[8]; //1
unsigned apicid_mcp55;
- unsigned bus_type[256];
-
};
#endif
Modified: trunk/src/mainboard/msi/ms9652_fam10/mptable.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/msi/ms9652_fam10/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -33,7 +33,7 @@
struct mb_sysconf_t *m;
unsigned sbdn;
- int i,j;
+ int i, j, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -45,13 +45,7 @@
sbdn = sysconf.sbdn;
m = sysconf.mb;
-/*Bus: Bus ID Type*/
- /* define bus and isa numbers */
- for(j= 0; j < 256 ; j++) {
- if(m->bus_type[j])
- smp_write_bus(mc, j, "PCI ");
- }
- smp_write_bus(mc, m->bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
@@ -80,7 +74,7 @@
}
- mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_mcp55, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
@@ -110,8 +104,8 @@
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
- smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
Modified: trunk/src/mainboard/newisys/khepri/mptable.c
==============================================================================
--- trunk/src/mainboard/newisys/khepri/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/newisys/khepri/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -8,8 +8,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- unsigned char bus_num;
- unsigned char bus_isa;
+ int bus_isa;
unsigned char bus_8131_1;
unsigned char bus_8131_2;
unsigned char bus_8111_1;
@@ -27,44 +26,32 @@
dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
-
bus_8111_1 = 4;
- bus_isa = 5;
}
/* 8131-1 */
dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
if (dev) {
bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:01.0, using defaults\n");
-
bus_8131_1 = 2;
}
/* 8131-2 */
dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:02.0, using defaults\n");
-
bus_8131_2 = 3;
}
}
- /* define bus and isa numbers */
- for(bus_num = 0; bus_num < bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* IOAPIC handling */
Modified: trunk/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/nvidia/l1_2pvv/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -95,7 +95,7 @@
unsigned apicid_base;
struct mb_sysconf_t *m;
- int i, j;
+ int i;
if (get_bus_conf_done)
return; //do it only once
@@ -119,25 +119,8 @@
m->sbdnb = (sysconf.hcdn[1] & 0xff); // first byte of second chain
- m->bus_type[0] = 1; //pci
-
m->bus_mcp55 = (sysconf.pci1234[0] >> 16) & 0xff;
- for (i = 0; i < sysconf.hc_possible_num; i++) {
- unsigned busn_min, busn_max;
-
- if (!(sysconf.pci1234[i] & 0x1))
- continue;
-
- busn_min = (sysconf.pci1234[i] >> 16) & 0xff;
- busn_max = (sysconf.pci1234[i] >> 24) & 0xff;
- for (j = busn_min; j <= busn_max; j++)
- m->bus_type[j] = 1;
- if(m->bus_isa <= busn_max)
- m->bus_isa = busn_max + 1;
- printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn_min, busn_max, m->bus_isa);
- }
-
/* MCP55b */
for (i = 1; i < sysconf.hc_possible_num; i++) {
if (!(sysconf.pci1234[i] & 0x0f))
Modified: trunk/src/mainboard/nvidia/l1_2pvv/mb_sysconf.h
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/mb_sysconf.h Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/nvidia/l1_2pvv/mb_sysconf.h Sun Nov 21 15:41:07 2010 (r6106)
@@ -23,15 +23,11 @@
#define MB_SYSCONF_H
struct mb_sysconf_t {
- unsigned char bus_isa;
unsigned char bus_mcp55;
unsigned char bus_mcp55b;
unsigned apicid_mcp55;
unsigned apicid_mcp55b;
- unsigned bus_type[256];
-
unsigned sbdnb;
-
};
#endif
Modified: trunk/src/mainboard/nvidia/l1_2pvv/mptable.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/nvidia/l1_2pvv/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -32,7 +32,7 @@
struct mp_config_table *mc;
struct mb_sysconf_t *m;
unsigned sbdn;
- int i,j;
+ int i, j, bus_isa;
unsigned char apicpin[4];
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -45,13 +45,7 @@
sbdn = sysconf.sbdn;
m = sysconf.mb;
-/*Bus: Bus ID Type*/
- /* define bus and isa numbers */
- for (j = 0; j < 256 ; j++) {
- if (m->bus_type[j])
- smp_write_bus(mc, j, "PCI ");
- }
- smp_write_bus(mc, m->bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
@@ -104,7 +98,7 @@
}
- mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_mcp55, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55, ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); // 10
@@ -167,8 +161,8 @@
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
- smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
Modified: trunk/src/mainboard/roda/rk886ex/mptable.c
==============================================================================
--- trunk/src/mainboard/roda/rk886ex/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/roda/rk886ex/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -30,8 +30,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- int i;
- int max_pci_bus, isa_bus;
+ int isa_bus;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -39,16 +38,7 @@
smp_write_processors(mc);
- max_pci_bus = 5; // XXX read me from bridges.
-
- /* ISA bus follows */
- isa_bus = max_pci_bus + 1;
-
- /* Bus: Bus ID Type */
- for (i=0; i <= max_pci_bus; i++)
- smp_write_bus(mc, i, "PCI ");
-
- smp_write_bus(mc, isa_bus, "ISA ");
+ mptable_write_buses(mc, NULL, &isa_bus);
/* I/O APICs: APIC ID Version State Address */
smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR);
Modified: trunk/src/mainboard/sunw/ultra40/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/sunw/ultra40/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -12,7 +12,6 @@
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
- unsigned char bus_isa;
unsigned char bus_ck804_0; //1
unsigned char bus_ck804_1; //2
unsigned char bus_ck804_2; //3
@@ -178,8 +177,6 @@
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
@@ -245,8 +242,6 @@
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0e,0));
if (dev) {
bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0e);
@@ -254,7 +249,6 @@
bus_ck804b_5 = bus_ck804b_4+1;
#endif
- bus_isa = bus_ck804b_5+1;
}
}
Modified: trunk/src/mainboard/sunw/ultra40/mptable.c
==============================================================================
--- trunk/src/mainboard/sunw/ultra40/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/sunw/ultra40/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -5,7 +5,6 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
-extern unsigned char bus_isa;
extern unsigned char bus_ck804_0; //1
extern unsigned char bus_ck804_1; //2
extern unsigned char bus_ck804_2; //3
@@ -36,8 +35,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- unsigned char bus_num;
- int i;
+ int i, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -47,12 +45,7 @@
get_bus_conf();
-/*Bus: Bus ID Type*/
- /* define bus and isa numbers */
- for(bus_num = 0; bus_num < bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
Modified: trunk/src/mainboard/tyan/s2881/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/tyan/s2881/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/tyan/s2881/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -13,7 +13,6 @@
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
-unsigned char bus_isa = 5 ;
unsigned char bus_8131_0 = 1;
unsigned char bus_8131_1 = 2;
unsigned char bus_8131_2 = 3;
@@ -82,11 +81,6 @@
dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
-// printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
-#endif
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0);
@@ -105,11 +99,6 @@
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
-// printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
-#endif
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
Modified: trunk/src/mainboard/tyan/s2881/mptable.c
==============================================================================
--- trunk/src/mainboard/tyan/s2881/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/tyan/s2881/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -6,7 +6,6 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
-extern unsigned char bus_isa;
extern unsigned char bus_8131_0;
extern unsigned char bus_8131_1;
extern unsigned char bus_8131_2;
@@ -21,8 +20,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- unsigned char bus_num;
- int i;
+ int i, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -32,13 +30,7 @@
get_bus_conf();
-/*Bus: Bus ID Type*/
- /* define bus and isa numbers */
- for(bus_num = 0; bus_num < bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
-
+ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR);
Modified: trunk/src/mainboard/tyan/s2882/mptable.c
==============================================================================
--- trunk/src/mainboard/tyan/s2882/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/tyan/s2882/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -46,8 +46,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- unsigned char bus_num;
- unsigned char bus_isa;
+ int bus_isa;
unsigned char bus_chain_0;
unsigned char bus_8131_1;
unsigned char bus_8131_2;
@@ -76,14 +75,11 @@
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x03,0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:03.0, using defaults\n");
bus_8111_1 = 4;
- bus_isa = 5;
}
/* 8131-1 */
dev = dev_find_slot(bus_chain_0, PCI_DEVFN(0x01,0));
@@ -108,13 +104,7 @@
bus_8131_2 = 3;
}
}
-/*Bus: Bus ID Type*/
- /* define bus and isa numbers */
- for(bus_num = 0; bus_num < bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
-
+ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
#if CONFIG_LOGICAL_CPUS==1
Modified: trunk/src/mainboard/tyan/s2885/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/tyan/s2885/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/tyan/s2885/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -12,7 +12,6 @@
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
-unsigned char bus_isa = 7 ;
unsigned char bus_8131_0 = 1;
unsigned char bus_8131_1 = 2;
unsigned char bus_8131_2 = 3;
@@ -85,11 +84,6 @@
dev = dev_find_slot(bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
if (dev) {
bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
-// printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
-#endif
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:03.0, using defaults\n", bus_8111_0);
@@ -108,12 +102,6 @@
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
-// printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa);
-#endif
-
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
@@ -128,8 +116,6 @@
if (dev) {
bus_8151_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
// printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151_1);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
}
/*I/O APICs: APIC ID Version State Address*/
Modified: trunk/src/mainboard/tyan/s2885/mptable.c
==============================================================================
--- trunk/src/mainboard/tyan/s2885/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/tyan/s2885/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -6,7 +6,6 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
-extern unsigned char bus_isa;
extern unsigned char bus_8131_0;
extern unsigned char bus_8131_1;
extern unsigned char bus_8131_2;
@@ -24,8 +23,7 @@
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- unsigned char bus_num;
- int i;
+ int i, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -35,12 +33,7 @@
get_bus_conf();
-/*Bus: Bus ID Type*/
- /* define bus and isa numbers */
- for(bus_num = 0; bus_num < bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
smp_write_ioapic(mc, apicid_8111, 0x11, IO_APIC_ADDR); //8111
Modified: trunk/src/mainboard/tyan/s2891/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/tyan/s2891/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/tyan/s2891/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -12,7 +12,6 @@
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
- unsigned char bus_isa;
unsigned char bus_ck804_0; //1
unsigned char bus_ck804_1; //2
unsigned char bus_ck804_2; //3
@@ -117,8 +116,6 @@
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0));
if (dev) {
bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
@@ -142,14 +139,11 @@
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
bus_8131_2 = bus_8131_1+1;
- bus_isa = bus_8131_1+2;
}
if(sysconf.pci1234[2] & 1) {
Modified: trunk/src/mainboard/tyan/s2891/irq_tables.c
==============================================================================
--- trunk/src/mainboard/tyan/s2891/irq_tables.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/tyan/s2891/irq_tables.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -30,7 +30,6 @@
pirq_info->rfu = rfu;
}
-extern unsigned char bus_isa;
extern unsigned char bus_ck804_0; //1
extern unsigned char bus_ck804_1; //2
extern unsigned char bus_ck804_2; //3
Modified: trunk/src/mainboard/tyan/s2891/mptable.c
==============================================================================
--- trunk/src/mainboard/tyan/s2891/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/tyan/s2891/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -5,7 +5,6 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
-extern unsigned char bus_isa;
extern unsigned char bus_ck804_0; //1
extern unsigned char bus_ck804_1; //2
extern unsigned char bus_ck804_2; //3
@@ -25,8 +24,7 @@
{
struct mp_config_table *mc;
unsigned sbdn;
- unsigned char bus_num;
- int i;
+ int i, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -37,12 +35,7 @@
get_bus_conf();
sbdn = sysconf.sbdn;
-/*Bus: Bus ID Type*/
- /* define bus and isa numbers */
- for(bus_num = 0; bus_num < bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
Modified: trunk/src/mainboard/tyan/s2892/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/tyan/s2892/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/tyan/s2892/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -12,7 +12,6 @@
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
- unsigned char bus_isa;
unsigned char bus_ck804_0; //1
unsigned char bus_ck804_1; //2
unsigned char bus_ck804_2; //3
@@ -114,8 +113,6 @@
dev = dev_find_slot(bus_ck804_0, PCI_DEVFN(sbdn+ 0x0e,0));
if (dev) {
bus_ck804_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI 1:%02x.0, using defaults\n", sbdn+ 0x0e);
@@ -139,14 +136,11 @@
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3+1,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
bus_8131_2 = bus_8131_1+1;
- bus_isa = bus_8131_1+2;
}
Modified: trunk/src/mainboard/tyan/s2892/irq_tables.c
==============================================================================
--- trunk/src/mainboard/tyan/s2892/irq_tables.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/tyan/s2892/irq_tables.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -30,7 +30,6 @@
pirq_info->rfu = rfu;
}
-extern unsigned char bus_isa;
extern unsigned char bus_ck804_0; //1
extern unsigned char bus_ck804_1; //2
extern unsigned char bus_ck804_2; //3
Modified: trunk/src/mainboard/tyan/s2892/mptable.c
==============================================================================
--- trunk/src/mainboard/tyan/s2892/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/tyan/s2892/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -5,7 +5,6 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
-extern unsigned char bus_isa;
extern unsigned char bus_ck804_0; //1
extern unsigned char bus_ck804_1; //2
extern unsigned char bus_ck804_2; //3
@@ -25,8 +24,7 @@
{
struct mp_config_table *mc;
unsigned sbdn;
- unsigned char bus_num;
- int i;
+ int i, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -37,12 +35,7 @@
get_bus_conf();
sbdn = sysconf.sbdn;
-/*Bus: Bus ID Type*/
- /* define bus and isa numbers */
- for(bus_num = 0; bus_num < bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
Modified: trunk/src/mainboard/tyan/s2895/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/tyan/s2895/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/tyan/s2895/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -12,7 +12,6 @@
// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
//busnum is default
- unsigned char bus_isa;
unsigned char bus_ck804_0; //1
unsigned char bus_ck804_1; //2
unsigned char bus_ck804_2; //3
@@ -134,8 +133,6 @@
dev = dev_find_slot(bus_8131_0, PCI_DEVFN(sbdn3,0));
if (dev) {
bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:02.0, using defaults\n", bus_8131_0);
@@ -151,13 +148,10 @@
dev = dev_find_slot(bus_ck804b_0, PCI_DEVFN(sbdnb + 0x0e,0));
if (dev) {
bus_ck804b_5 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
}
else {
printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804b_0,sbdnb+0x0e);
bus_ck804b_5 = bus_ck804b_4+1;
- bus_isa = bus_ck804b_5+1;
}
}
Modified: trunk/src/mainboard/tyan/s2895/mptable.c
==============================================================================
--- trunk/src/mainboard/tyan/s2895/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/tyan/s2895/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -5,7 +5,6 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
-extern unsigned char bus_isa;
extern unsigned char bus_ck804_0; //1
extern unsigned char bus_ck804_1; //2
extern unsigned char bus_ck804_2; //3
@@ -33,8 +32,7 @@
{
struct mp_config_table *mc;
unsigned sbdn;
- unsigned char bus_num;
- int i;
+ int i, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -45,12 +43,7 @@
get_bus_conf();
sbdn = sysconf.sbdn;
-/*Bus: Bus ID Type*/
- /* define bus and isa numbers */
- for(bus_num = 0; bus_num < bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
Modified: trunk/src/mainboard/tyan/s2912/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/tyan/s2912/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -71,7 +71,7 @@
struct mb_sysconf_t *m;
device_t dev;
- int i, j;
+ int i;
if(get_bus_conf_done==1) return; //do it only once
@@ -92,8 +92,6 @@
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
- m->bus_type[0] = 1; //pci
-
m->bus_mcp55[0] = (sysconf.pci1234[0] >> 16) & 0xff;
/* MCP55 */
@@ -113,18 +111,6 @@
}
}
- for(i=0; i< sysconf.hc_possible_num; i++) {
- if(!(sysconf.pci1234[i] & 0x1) ) continue;
-
- unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
- unsigned busn_max = (sysconf.pci1234[i] >> 24) & 0xff;
- for (j = busn; j <= busn_max; j++)
- m->bus_type[j] = 1;
- if(m->bus_isa <= busn_max)
- m->bus_isa = busn_max + 1;
- printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
- }
-
/*I/O APICs: APIC ID Version State Address*/
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
Modified: trunk/src/mainboard/tyan/s2912/mb_sysconf.h
==============================================================================
--- trunk/src/mainboard/tyan/s2912/mb_sysconf.h Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/tyan/s2912/mb_sysconf.h Sun Nov 21 15:41:07 2010 (r6106)
@@ -23,11 +23,8 @@
#define MB_SYSCONF_H
struct mb_sysconf_t {
- unsigned char bus_isa;
unsigned char bus_mcp55[8]; //1
unsigned apicid_mcp55;
- unsigned bus_type[256];
-
};
#endif
Modified: trunk/src/mainboard/tyan/s2912/mptable.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/tyan/s2912/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -32,7 +32,7 @@
struct mp_config_table *mc;
struct mb_sysconf_t *m;
unsigned sbdn;
- int i,j;
+ int i, j, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -44,13 +44,7 @@
sbdn = sysconf.sbdn;
m = sysconf.mb;
-/*Bus: Bus ID Type*/
- /* define bus and isa numbers */
- for(j= 0; j < 256 ; j++) {
- if(m->bus_type[j])
- smp_write_bus(mc, j, "PCI ");
- }
- smp_write_bus(mc, m->bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
@@ -79,7 +73,7 @@
}
- mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_mcp55, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
@@ -108,8 +102,8 @@
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
- smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
Modified: trunk/src/mainboard/tyan/s2912_fam10/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/tyan/s2912_fam10/get_bus_conf.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -72,7 +72,7 @@
struct mb_sysconf_t *m;
device_t dev;
- int i, j;
+ int i;
if(get_bus_conf_done==1) return; //do it only once
@@ -91,7 +91,6 @@
get_pci1234();
- m->bus_type[0] = 1; //pci
sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain
m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff;
@@ -114,18 +113,6 @@
}
}
- for(i=0; i< sysconf.hc_possible_num; i++) {
- if(!(sysconf.pci1234[i] & 0x1) ) continue;
-
- unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff;
- unsigned busn_max = (sysconf.pci1234[i] >> 20) & 0xff;
- for (j = busn; j <= busn_max; j++)
- m->bus_type[j] = 1;
- if(m->bus_isa <= busn_max)
- m->bus_isa = busn_max + 1;
- printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa);
- }
-
/*I/O APICs: APIC ID Version State Address*/
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
Modified: trunk/src/mainboard/tyan/s2912_fam10/mb_sysconf.h
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/mb_sysconf.h Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/tyan/s2912_fam10/mb_sysconf.h Sun Nov 21 15:41:07 2010 (r6106)
@@ -23,11 +23,8 @@
#define MB_SYSCONF_H
struct mb_sysconf_t {
- unsigned char bus_isa;
unsigned char bus_mcp55[8]; //1
unsigned apicid_mcp55;
- unsigned bus_type[256];
-
};
#endif
Modified: trunk/src/mainboard/tyan/s2912_fam10/mptable.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
+++ trunk/src/mainboard/tyan/s2912_fam10/mptable.c Sun Nov 21 15:41:07 2010 (r6106)
@@ -32,7 +32,7 @@
struct mp_config_table *mc;
struct mb_sysconf_t *m;
unsigned sbdn;
- int i,j;
+ int i, j, bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -44,13 +44,7 @@
sbdn = sysconf.sbdn;
m = sysconf.mb;
-/*Bus: Bus ID Type*/
- /* define bus and isa numbers */
- for(j= 0; j < 256 ; j++) {
- if(m->bus_type[j])
- smp_write_bus(mc, j, "PCI ");
- }
- smp_write_bus(mc, m->bus_isa, "ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/*I/O APICs: APIC ID Version State Address*/
{
@@ -79,7 +73,7 @@
}
- mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_mcp55, 0);
+ mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0);
/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa);
@@ -108,8 +102,8 @@
}
/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
- smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1);
/* There is no extension information... */
/* Compute the checksums */
1
0
[commit] r6105 - in trunk/src/mainboard: amd/dbm690t amd/mahogany amd/mahogany_fam10 amd/pistachio amd/tilapia_fam10 asrock/939a785gmh asus/m4a785-m gigabyte/ma785gmt gigabyte/ma78gm iei/kino-780am...
by repository service 21 Nov '10
by repository service 21 Nov '10
21 Nov '10
Author: oxygene
Date: Sun Nov 21 15:40:09 2010
New Revision: 6105
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6105
Log:
Convert boards to use mptable_write_buses.
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de>
Modified:
trunk/src/mainboard/amd/dbm690t/get_bus_conf.c
trunk/src/mainboard/amd/dbm690t/irq_tables.c
trunk/src/mainboard/amd/dbm690t/mptable.c
trunk/src/mainboard/amd/mahogany/get_bus_conf.c
trunk/src/mainboard/amd/mahogany/irq_tables.c
trunk/src/mainboard/amd/mahogany/mptable.c
trunk/src/mainboard/amd/mahogany_fam10/get_bus_conf.c
trunk/src/mainboard/amd/mahogany_fam10/irq_tables.c
trunk/src/mainboard/amd/mahogany_fam10/mptable.c
trunk/src/mainboard/amd/pistachio/get_bus_conf.c
trunk/src/mainboard/amd/pistachio/irq_tables.c
trunk/src/mainboard/amd/pistachio/mptable.c
trunk/src/mainboard/amd/tilapia_fam10/get_bus_conf.c
trunk/src/mainboard/amd/tilapia_fam10/irq_tables.c
trunk/src/mainboard/amd/tilapia_fam10/mptable.c
trunk/src/mainboard/asrock/939a785gmh/get_bus_conf.c
trunk/src/mainboard/asrock/939a785gmh/irq_tables.c
trunk/src/mainboard/asrock/939a785gmh/mptable.c
trunk/src/mainboard/asus/m4a785-m/get_bus_conf.c
trunk/src/mainboard/asus/m4a785-m/mptable.c
trunk/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c
trunk/src/mainboard/gigabyte/ma785gmt/irq_tables.c
trunk/src/mainboard/gigabyte/ma785gmt/mptable.c
trunk/src/mainboard/gigabyte/ma78gm/get_bus_conf.c
trunk/src/mainboard/gigabyte/ma78gm/irq_tables.c
trunk/src/mainboard/gigabyte/ma78gm/mptable.c
trunk/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c
trunk/src/mainboard/iei/kino-780am2-fam10/irq_tables.c
trunk/src/mainboard/iei/kino-780am2-fam10/mptable.c
trunk/src/mainboard/jetway/pa78vm5/get_bus_conf.c
trunk/src/mainboard/jetway/pa78vm5/irq_tables.c
trunk/src/mainboard/jetway/pa78vm5/mptable.c
trunk/src/mainboard/kontron/kt690/get_bus_conf.c
trunk/src/mainboard/kontron/kt690/irq_tables.c
trunk/src/mainboard/kontron/kt690/mptable.c
trunk/src/mainboard/technexion/tim5690/get_bus_conf.c
trunk/src/mainboard/technexion/tim5690/irq_tables.c
trunk/src/mainboard/technexion/tim5690/mptable.c
trunk/src/mainboard/technexion/tim8690/get_bus_conf.c
trunk/src/mainboard/technexion/tim8690/irq_tables.c
trunk/src/mainboard/technexion/tim8690/mptable.c
Modified: trunk/src/mainboard/amd/dbm690t/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/get_bus_conf.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/amd/dbm690t/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -32,7 +32,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
-u8 bus_isa;
u8 bus_rs690[8];
u8 bus_sb600[2];
u32 apicid_sb600;
@@ -54,8 +53,6 @@
0x20202020,
};
-u32 bus_type[256];
-
u32 sbdn_rs690;
u32 sbdn_sb600;
@@ -67,7 +64,7 @@
{
u32 apicid_base;
device_t dev;
- int i, j;
+ int i;
if (get_bus_conf_done == 1)
return; /* do it only once */
@@ -92,25 +89,13 @@
bus_rs690[i] = 0;
}
- for (i = 0; i < 256; i++) {
- bus_type[i] = 0; /* default ISA bus. */
- }
-
- bus_type[0] = 1; /* pci */
-
bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sb600[0] = bus_rs690[0];
- bus_type[bus_rs690[0]] = 1;
-
/* sb600 */
dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4));
if (dev) {
bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- for (j = bus_sb600[1]; j < bus_isa; j++)
- bus_type[j] = 1;
}
/* rs690 */
@@ -118,16 +103,10 @@
dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0));
if (dev) {
bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- if(255 != bus_rs690[i]) {
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- bus_type[bus_rs690[i]] = 1; /* PCI bus. */
- }
}
}
/* I/O APICs: APIC ID Version State Address */
- bus_isa = 10;
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
#else
Modified: trunk/src/mainboard/amd/dbm690t/irq_tables.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/irq_tables.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/amd/dbm690t/irq_tables.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -51,7 +51,6 @@
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
-extern u8 bus_isa;
extern u8 bus_rs690[8];
extern u8 bus_sb600[2];
extern unsigned long sbdn_sb600;
Modified: trunk/src/mainboard/amd/dbm690t/mptable.c
==============================================================================
--- trunk/src/mainboard/amd/dbm690t/mptable.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/amd/dbm690t/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -25,20 +25,18 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
-extern u8 bus_isa;
extern u8 bus_rs690[8];
extern u8 bus_sb600[2];
extern u32 apicid_sb600;
-extern u32 bus_type[256];
extern u32 sbdn_rs690;
extern u32 sbdn_sb600;
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- int j;
+ int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -48,12 +46,7 @@
get_bus_conf();
- /* Bus: Bus ID Type */
- /* define bus and isa numbers */
- for (j = 0; j < bus_isa; j++) {
- smp_write_bus(mc, j, (char *)"PCI ");
- }
- smp_write_bus(mc, bus_isa, (char *)"ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
Modified: trunk/src/mainboard/amd/mahogany/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany/get_bus_conf.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/amd/mahogany/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -32,7 +32,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
-u8 bus_isa;
u8 bus_rs780[11];
u8 bus_sb700[2];
u32 apicid_sb700;
@@ -54,8 +53,6 @@
0x20202020,
};
-u32 bus_type[256];
-
u32 sbdn_rs780;
u32 sbdn_sb700;
@@ -67,7 +64,7 @@
{
u32 apicid_base;
device_t dev;
- int i, j;
+ int i;
if (get_bus_conf_done == 1)
return; /* do it only once */
@@ -92,25 +89,13 @@
bus_rs780[i] = 0;
}
- for (i = 0; i < 256; i++) {
- bus_type[i] = 0; /* default ISA bus. */
- }
-
- bus_type[0] = 1; /* pci */
-
bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sb700[0] = bus_rs780[0];
- bus_type[bus_rs780[0]] = 1;
-
/* sb700 */
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
if (dev) {
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- for (j = bus_sb700[1]; j < bus_isa; j++)
- bus_type[j] = 1;
}
/* rs780 */
@@ -118,16 +103,10 @@
dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
if (dev) {
bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- if(255 != bus_rs780[i]) {
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- bus_type[bus_rs780[i]] = 1; /* PCI bus. */
- }
}
}
/* I/O APICs: APIC ID Version State Address */
- bus_isa = 10;
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
#else
Modified: trunk/src/mainboard/amd/mahogany/irq_tables.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany/irq_tables.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/amd/mahogany/irq_tables.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -51,7 +51,6 @@
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
-extern u8 bus_isa;
extern u8 bus_rs780[8];
extern u8 bus_sb700[2];
extern unsigned long sbdn_sb700;
Modified: trunk/src/mainboard/amd/mahogany/mptable.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany/mptable.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/amd/mahogany/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -26,20 +26,18 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
-extern u8 bus_isa;
extern u8 bus_rs780[11];
extern u8 bus_sb700[2];
extern u32 apicid_sb700;
-extern u32 bus_type[256];
extern u32 sbdn_rs780;
extern u32 sbdn_sb700;
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- int j;
+ int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -49,12 +47,7 @@
get_bus_conf();
- /* Bus: Bus ID Type */
- /* define bus and isa numbers */
- for (j = 0; j < bus_isa; j++) {
- smp_write_bus(mc, j, (char *)"PCI ");
- }
- smp_write_bus(mc, bus_isa, (char *)"ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
Modified: trunk/src/mainboard/amd/mahogany_fam10/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/get_bus_conf.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/amd/mahogany_fam10/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -32,7 +32,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
-u8 bus_isa;
u8 bus_rs780[11];
u8 bus_sb700[2];
u32 apicid_sb700;
@@ -54,8 +53,6 @@
0x20202020,
};
-u32 bus_type[256];
-
u32 sbdn_rs780;
u32 sbdn_sb700;
@@ -67,7 +64,7 @@
{
u32 apicid_base;
device_t dev;
- int i, j;
+ int i;
if (get_bus_conf_done == 1)
return; /* do it only once */
@@ -92,25 +89,13 @@
bus_rs780[i] = 0;
}
- for (i = 0; i < 256; i++) {
- bus_type[i] = 0; /* default ISA bus. */
- }
-
- bus_type[0] = 1; /* pci */
-
bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sb700[0] = bus_rs780[0];
- bus_type[bus_rs780[0]] = 1;
-
/* sb700 */
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
if (dev) {
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- for (j = bus_sb700[1]; j < bus_isa; j++)
- bus_type[j] = 1;
}
/* rs780 */
@@ -118,16 +103,10 @@
dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
if (dev) {
bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- if(255 != bus_rs780[i]) {
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- bus_type[bus_rs780[i]] = 1; /* PCI bus. */
- }
}
}
/* I/O APICs: APIC ID Version State Address */
- bus_isa = 10;
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
#else
Modified: trunk/src/mainboard/amd/mahogany_fam10/irq_tables.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/irq_tables.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/amd/mahogany_fam10/irq_tables.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -45,7 +45,6 @@
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
-extern u8 bus_isa;
extern u8 bus_rs780[8];
extern u8 bus_sb700[2];
extern unsigned long sbdn_sb700;
Modified: trunk/src/mainboard/amd/mahogany_fam10/mptable.c
==============================================================================
--- trunk/src/mainboard/amd/mahogany_fam10/mptable.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/amd/mahogany_fam10/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -25,20 +25,18 @@
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
-extern u8 bus_isa;
extern u8 bus_rs780[11];
extern u8 bus_sb700[2];
extern u32 apicid_sb700;
-extern u32 bus_type[256];
extern u32 sbdn_rs780;
extern u32 sbdn_sb700;
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- int j;
+ int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -48,12 +46,7 @@
get_bus_conf();
- /* Bus: Bus ID Type */
- /* define bus and isa numbers */
- for (j = 0; j < bus_isa; j++) {
- smp_write_bus(mc, j, (char *)"PCI ");
- }
- smp_write_bus(mc, bus_isa, (char *)"ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
Modified: trunk/src/mainboard/amd/pistachio/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/amd/pistachio/get_bus_conf.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/amd/pistachio/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -32,7 +32,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
-u8 bus_isa;
u8 bus_rs690[8];
u8 bus_sb600[2];
u32 apicid_sb600;
@@ -54,8 +53,6 @@
0x20202020,
};
-u32 bus_type[256];
-
u32 sbdn_rs690;
u32 sbdn_sb600;
@@ -67,7 +64,7 @@
{
u32 apicid_base;
device_t dev;
- int i, j;
+ int i;
if (get_bus_conf_done == 1)
return; /* do it only once */
@@ -92,25 +89,13 @@
bus_rs690[i] = 0;
}
- for (i = 0; i < 256; i++) {
- bus_type[i] = 0; /* default ISA bus. */
- }
-
- bus_type[0] = 1; /* pci */
-
bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sb600[0] = bus_rs690[0];
- bus_type[bus_rs690[0]] = 1;
-
/* sb600 */
dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4));
if (dev) {
bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- for (j = bus_sb600[1]; j < bus_isa; j++)
- bus_type[j] = 1;
}
/* rs690 */
@@ -118,16 +103,10 @@
dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0));
if (dev) {
bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- if(255 != bus_rs690[i]) {
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- bus_type[bus_rs690[i]] = 1; /* PCI bus. */
- }
}
}
/* I/O APICs: APIC ID Version State Address */
- bus_isa = 10;
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
#else
Modified: trunk/src/mainboard/amd/pistachio/irq_tables.c
==============================================================================
--- trunk/src/mainboard/amd/pistachio/irq_tables.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/amd/pistachio/irq_tables.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -51,7 +51,6 @@
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
-extern u8 bus_isa;
extern u8 bus_rs690[8];
extern u8 bus_sb600[2];
extern u32 sbdn_sb600;
Modified: trunk/src/mainboard/amd/pistachio/mptable.c
==============================================================================
--- trunk/src/mainboard/amd/pistachio/mptable.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/amd/pistachio/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -25,20 +25,18 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
-extern u8 bus_isa;
extern u8 bus_rs690[8];
extern u8 bus_sb600[2];
extern u32 apicid_sb600;
-extern u32 bus_type[256];
extern u32 sbdn_rs690;
extern u32 sbdn_sb600;
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- int j;
+ int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -48,12 +46,7 @@
get_bus_conf();
- /* Bus: Bus ID Type */
- /* define bus and isa numbers */
- for (j = 0; j < bus_isa; j++) {
- smp_write_bus(mc, j, (char *)"PCI ");
- }
- smp_write_bus(mc, bus_isa, (char *)"ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
Modified: trunk/src/mainboard/amd/tilapia_fam10/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/get_bus_conf.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/amd/tilapia_fam10/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -32,7 +32,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
-u8 bus_isa;
u8 bus_rs780[11];
u8 bus_sb700[2];
u32 apicid_sb700;
@@ -54,8 +53,6 @@
0x20202020,
};
-u32 bus_type[256];
-
u32 sbdn_rs780;
u32 sbdn_sb700;
@@ -67,7 +64,7 @@
{
u32 apicid_base;
device_t dev;
- int i, j;
+ int i;
if (get_bus_conf_done == 1)
return; /* do it only once */
@@ -92,25 +89,13 @@
bus_rs780[i] = 0;
}
- for (i = 0; i < 256; i++) {
- bus_type[i] = 0; /* default ISA bus. */
- }
-
- bus_type[0] = 1; /* pci */
-
bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sb700[0] = bus_rs780[0];
- bus_type[bus_rs780[0]] = 1;
-
/* sb700 */
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
if (dev) {
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- for (j = bus_sb700[1]; j < bus_isa; j++)
- bus_type[j] = 1;
}
/* rs780 */
@@ -118,16 +103,10 @@
dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
if (dev) {
bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- if(255 != bus_rs780[i]) {
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- bus_type[bus_rs780[i]] = 1; /* PCI bus. */
- }
}
}
/* I/O APICs: APIC ID Version State Address */
- bus_isa = 10;
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
#else
Modified: trunk/src/mainboard/amd/tilapia_fam10/irq_tables.c
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/irq_tables.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/amd/tilapia_fam10/irq_tables.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -45,7 +45,6 @@
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
-extern u8 bus_isa;
extern u8 bus_rs780[8];
extern u8 bus_sb700[2];
extern unsigned long sbdn_sb700;
Modified: trunk/src/mainboard/amd/tilapia_fam10/mptable.c
==============================================================================
--- trunk/src/mainboard/amd/tilapia_fam10/mptable.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/amd/tilapia_fam10/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -25,20 +25,18 @@
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
-extern u8 bus_isa;
extern u8 bus_rs780[11];
extern u8 bus_sb700[2];
extern u32 apicid_sb700;
-extern u32 bus_type[256];
extern u32 sbdn_rs780;
extern u32 sbdn_sb700;
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- int j;
+ int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -48,12 +46,7 @@
get_bus_conf();
- /* Bus: Bus ID Type */
- /* define bus and isa numbers */
- for (j = 0; j < bus_isa; j++) {
- smp_write_bus(mc, j, (char *)"PCI ");
- }
- smp_write_bus(mc, bus_isa, (char *)"ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
Modified: trunk/src/mainboard/asrock/939a785gmh/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/get_bus_conf.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/asrock/939a785gmh/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -32,7 +32,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
-u8 bus_isa;
u8 bus_rs780[11];
u8 bus_sb700[2];
u32 apicid_sb700;
@@ -54,8 +53,6 @@
0x20202020,
};
-u32 bus_type[256];
-
u32 sbdn_rs780;
u32 sbdn_sb700;
@@ -67,7 +64,7 @@
{
u32 apicid_base;
device_t dev;
- int i, j;
+ int i;
if (get_bus_conf_done == 1)
return; /* do it only once */
@@ -92,25 +89,13 @@
bus_rs780[i] = 0;
}
- for (i = 0; i < 256; i++) {
- bus_type[i] = 0; /* default ISA bus. */
- }
-
- bus_type[0] = 1; /* pci */
-
bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sb700[0] = bus_rs780[0];
- bus_type[bus_rs780[0]] = 1;
-
/* sb700 */
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
if (dev) {
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- for (j = bus_sb700[1]; j < bus_isa; j++)
- bus_type[j] = 1;
}
/* rs780 */
@@ -118,16 +103,10 @@
dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
if (dev) {
bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- if(255 != bus_rs780[i]) {
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- bus_type[bus_rs780[i]] = 1; /* PCI bus. */
- }
}
}
/* I/O APICs: APIC ID Version State Address */
- bus_isa = 10;
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
#else
Modified: trunk/src/mainboard/asrock/939a785gmh/irq_tables.c
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/irq_tables.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/asrock/939a785gmh/irq_tables.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -51,7 +51,6 @@
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
-extern u8 bus_isa;
extern u8 bus_rs780[8];
extern u8 bus_sb700[2];
extern unsigned long sbdn_sb700;
Modified: trunk/src/mainboard/asrock/939a785gmh/mptable.c
==============================================================================
--- trunk/src/mainboard/asrock/939a785gmh/mptable.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/asrock/939a785gmh/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -25,20 +25,18 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
-extern u8 bus_isa;
extern u8 bus_rs780[11];
extern u8 bus_sb700[2];
extern u32 apicid_sb700;
-extern u32 bus_type[256];
extern u32 sbdn_rs780;
extern u32 sbdn_sb700;
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- int j;
+ int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -48,12 +46,7 @@
get_bus_conf();
- /* Bus: Bus ID Type */
- /* define bus and isa numbers */
- for (j = 0; j < bus_isa; j++) {
- smp_write_bus(mc, j, (char *)"PCI ");
- }
- smp_write_bus(mc, bus_isa, (char *)"ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
Modified: trunk/src/mainboard/asus/m4a785-m/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/get_bus_conf.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/asus/m4a785-m/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -32,7 +32,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
-u8 bus_isa;
u8 bus_rs780[11];
u8 bus_sb700[2];
u32 apicid_sb700;
@@ -54,8 +53,6 @@
0x20202020,
};
-u32 bus_type[256];
-
u32 sbdn_rs780;
u32 sbdn_sb700;
@@ -67,7 +64,7 @@
{
u32 apicid_base;
device_t dev;
- int i, j;
+ int i;
if (get_bus_conf_done == 1)
return; /* do it only once */
@@ -92,25 +89,13 @@
bus_rs780[i] = 0;
}
- for (i = 0; i < 256; i++) {
- bus_type[i] = 0; /* default ISA bus. */
- }
-
- bus_type[0] = 1; /* pci */
-
bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sb700[0] = bus_rs780[0];
- bus_type[bus_rs780[0]] = 1;
-
/* sb700 */
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
if (dev) {
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- for (j = bus_sb700[1]; j < bus_isa; j++)
- bus_type[j] = 1;
}
/* rs780 */
@@ -118,16 +103,10 @@
dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
if (dev) {
bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- if(255 != bus_rs780[i]) {
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- bus_type[bus_rs780[i]] = 1; /* PCI bus. */
- }
}
}
/* I/O APICs: APIC ID Version State Address */
- bus_isa = 10;
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
#else
Modified: trunk/src/mainboard/asus/m4a785-m/mptable.c
==============================================================================
--- trunk/src/mainboard/asus/m4a785-m/mptable.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/asus/m4a785-m/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -25,20 +25,18 @@
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
-extern u8 bus_isa;
extern u8 bus_rs780[11];
extern u8 bus_sb700[2];
extern u32 apicid_sb700;
-extern u32 bus_type[256];
extern u32 sbdn_rs780;
extern u32 sbdn_sb700;
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- int j;
+ int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -48,12 +46,7 @@
get_bus_conf();
- /* Bus: Bus ID Type */
- /* define bus and isa numbers */
- for (j = 0; j < bus_isa; j++) {
- smp_write_bus(mc, j, (char *)"PCI ");
- }
- smp_write_bus(mc, bus_isa, (char *)"ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
Modified: trunk/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/gigabyte/ma785gmt/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -32,7 +32,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
-u8 bus_isa;
u8 bus_rs780[11];
u8 bus_sb700[2];
u32 apicid_sb700;
@@ -54,8 +53,6 @@
0x20202020,
};
-u32 bus_type[256];
-
u32 sbdn_rs780;
u32 sbdn_sb700;
@@ -67,7 +64,7 @@
{
u32 apicid_base;
device_t dev;
- int i, j;
+ int i;
if (get_bus_conf_done == 1)
return; /* do it only once */
@@ -92,25 +89,13 @@
bus_rs780[i] = 0;
}
- for (i = 0; i < 256; i++) {
- bus_type[i] = 0; /* default ISA bus. */
- }
-
- bus_type[0] = 1; /* pci */
-
bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sb700[0] = bus_rs780[0];
- bus_type[bus_rs780[0]] = 1;
-
/* sb700 */
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
if (dev) {
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- for (j = bus_sb700[1]; j < bus_isa; j++)
- bus_type[j] = 1;
}
/* rs780 */
@@ -118,16 +103,10 @@
dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
if (dev) {
bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- if(255 != bus_rs780[i]) {
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- bus_type[bus_rs780[i]] = 1; /* PCI bus. */
- }
}
}
/* I/O APICs: APIC ID Version State Address */
- bus_isa = 10;
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
#else
Modified: trunk/src/mainboard/gigabyte/ma785gmt/irq_tables.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/irq_tables.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/gigabyte/ma785gmt/irq_tables.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -45,7 +45,6 @@
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
-extern u8 bus_isa;
extern u8 bus_rs780[8];
extern u8 bus_sb700[2];
extern unsigned long sbdn_sb700;
Modified: trunk/src/mainboard/gigabyte/ma785gmt/mptable.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma785gmt/mptable.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/gigabyte/ma785gmt/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -25,20 +25,18 @@
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
-extern u8 bus_isa;
extern u8 bus_rs780[11];
extern u8 bus_sb700[2];
extern u32 apicid_sb700;
-extern u32 bus_type[256];
extern u32 sbdn_rs780;
extern u32 sbdn_sb700;
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- int j;
+ int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -48,12 +46,7 @@
get_bus_conf();
- /* Bus: Bus ID Type */
- /* define bus and isa numbers */
- for (j = 0; j < bus_isa; j++) {
- smp_write_bus(mc, j, (char *)"PCI ");
- }
- smp_write_bus(mc, bus_isa, (char *)"ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
Modified: trunk/src/mainboard/gigabyte/ma78gm/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/get_bus_conf.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/gigabyte/ma78gm/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -32,7 +32,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
-u8 bus_isa;
u8 bus_rs780[11];
u8 bus_sb700[2];
u32 apicid_sb700;
@@ -54,8 +53,6 @@
0x20202020,
};
-u32 bus_type[256];
-
u32 sbdn_rs780;
u32 sbdn_sb700;
@@ -67,7 +64,7 @@
{
u32 apicid_base;
device_t dev;
- int i, j;
+ int i;
if (get_bus_conf_done == 1)
return; /* do it only once */
@@ -92,25 +89,13 @@
bus_rs780[i] = 0;
}
- for (i = 0; i < 256; i++) {
- bus_type[i] = 0; /* default ISA bus. */
- }
-
- bus_type[0] = 1; /* pci */
-
bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sb700[0] = bus_rs780[0];
- bus_type[bus_rs780[0]] = 1;
-
/* sb700 */
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
if (dev) {
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- for (j = bus_sb700[1]; j < bus_isa; j++)
- bus_type[j] = 1;
}
/* rs780 */
@@ -118,16 +103,10 @@
dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
if (dev) {
bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- if(255 != bus_rs780[i]) {
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- bus_type[bus_rs780[i]] = 1; /* PCI bus. */
- }
}
}
/* I/O APICs: APIC ID Version State Address */
- bus_isa = 10;
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
#else
Modified: trunk/src/mainboard/gigabyte/ma78gm/irq_tables.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/irq_tables.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/gigabyte/ma78gm/irq_tables.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -45,7 +45,6 @@
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
-extern u8 bus_isa;
extern u8 bus_rs780[8];
extern u8 bus_sb700[2];
extern unsigned long sbdn_sb700;
Modified: trunk/src/mainboard/gigabyte/ma78gm/mptable.c
==============================================================================
--- trunk/src/mainboard/gigabyte/ma78gm/mptable.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/gigabyte/ma78gm/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -25,20 +25,18 @@
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
-extern u8 bus_isa;
extern u8 bus_rs780[11];
extern u8 bus_sb700[2];
extern u32 apicid_sb700;
-extern u32 bus_type[256];
extern u32 sbdn_rs780;
extern u32 sbdn_sb700;
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- int j;
+ int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -48,12 +46,7 @@
get_bus_conf();
- /* Bus: Bus ID Type */
- /* define bus and isa numbers */
- for (j = 0; j < bus_isa; j++) {
- smp_write_bus(mc, j, (char *)"PCI ");
- }
- smp_write_bus(mc, bus_isa, (char *)"ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
Modified: trunk/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -32,7 +32,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
-u8 bus_isa;
u8 bus_rs780[11];
u8 bus_sb700[2];
u32 apicid_sb700;
@@ -54,8 +53,6 @@
0x20202020,
};
-u32 bus_type[256];
-
u32 sbdn_rs780;
u32 sbdn_sb700;
@@ -67,7 +64,7 @@
{
u32 apicid_base;
device_t dev;
- int i, j;
+ int i;
if (get_bus_conf_done == 1)
return; /* do it only once */
@@ -92,25 +89,13 @@
bus_rs780[i] = 0;
}
- for (i = 0; i < 256; i++) {
- bus_type[i] = 0; /* default ISA bus. */
- }
-
- bus_type[0] = 1; /* pci */
-
bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sb700[0] = bus_rs780[0];
- bus_type[bus_rs780[0]] = 1;
-
/* sb700 */
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
if (dev) {
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- for (j = bus_sb700[1]; j < bus_isa; j++)
- bus_type[j] = 1;
}
/* rs780 */
@@ -118,16 +103,10 @@
dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
if (dev) {
bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- if(255 != bus_rs780[i]) {
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- bus_type[bus_rs780[i]] = 1; /* PCI bus. */
- }
}
}
/* I/O APICs: APIC ID Version State Address */
- bus_isa = 10;
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
#else
Modified: trunk/src/mainboard/iei/kino-780am2-fam10/irq_tables.c
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/irq_tables.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/irq_tables.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -45,7 +45,6 @@
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
-extern u8 bus_isa;
extern u8 bus_rs780[8];
extern u8 bus_sb700[2];
extern unsigned long sbdn_sb700;
Modified: trunk/src/mainboard/iei/kino-780am2-fam10/mptable.c
==============================================================================
--- trunk/src/mainboard/iei/kino-780am2-fam10/mptable.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/iei/kino-780am2-fam10/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -25,20 +25,18 @@
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
-extern u8 bus_isa;
extern u8 bus_rs780[11];
extern u8 bus_sb700[2];
extern u32 apicid_sb700;
-extern u32 bus_type[256];
extern u32 sbdn_rs780;
extern u32 sbdn_sb700;
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- int j;
+ int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -48,12 +46,7 @@
get_bus_conf();
- /* Bus: Bus ID Type */
- /* define bus and isa numbers */
- for (j = 0; j < bus_isa; j++) {
- smp_write_bus(mc, j, (char *)"PCI ");
- }
- smp_write_bus(mc, bus_isa, (char *)"ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
Modified: trunk/src/mainboard/jetway/pa78vm5/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/get_bus_conf.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/jetway/pa78vm5/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -32,7 +32,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
-u8 bus_isa;
u8 bus_rs780[11];
u8 bus_sb700[2];
u32 apicid_sb700;
@@ -54,8 +53,6 @@
0x20202020,
};
-u32 bus_type[256];
-
u32 sbdn_rs780;
u32 sbdn_sb700;
@@ -67,7 +64,7 @@
{
u32 apicid_base;
device_t dev;
- int i, j;
+ int i;
if (get_bus_conf_done == 1)
return; /* do it only once */
@@ -92,25 +89,13 @@
bus_rs780[i] = 0;
}
- for (i = 0; i < 256; i++) {
- bus_type[i] = 0; /* default ISA bus. */
- }
-
- bus_type[0] = 1; /* pci */
-
bus_rs780[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sb700[0] = bus_rs780[0];
- bus_type[bus_rs780[0]] = 1;
-
/* sb700 */
dev = dev_find_slot(bus_sb700[0], PCI_DEVFN(sbdn_sb700 + 0x14, 4));
if (dev) {
bus_sb700[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- for (j = bus_sb700[1]; j < bus_isa; j++)
- bus_type[j] = 1;
}
/* rs780 */
@@ -118,16 +103,10 @@
dev = dev_find_slot(bus_rs780[0], PCI_DEVFN(sbdn_rs780 + i, 0));
if (dev) {
bus_rs780[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- if(255 != bus_rs780[i]) {
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- bus_type[bus_rs780[i]] = 1; /* PCI bus. */
- }
}
}
/* I/O APICs: APIC ID Version State Address */
- bus_isa = 10;
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
#else
Modified: trunk/src/mainboard/jetway/pa78vm5/irq_tables.c
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/irq_tables.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/jetway/pa78vm5/irq_tables.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -45,7 +45,6 @@
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
-extern u8 bus_isa;
extern u8 bus_rs780[8];
extern u8 bus_sb700[2];
extern unsigned long sbdn_sb700;
Modified: trunk/src/mainboard/jetway/pa78vm5/mptable.c
==============================================================================
--- trunk/src/mainboard/jetway/pa78vm5/mptable.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/jetway/pa78vm5/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -26,20 +26,18 @@
#include <stdint.h>
#include <cpu/amd/amdfam10_sysconf.h>
-extern u8 bus_isa;
extern u8 bus_rs780[11];
extern u8 bus_sb700[2];
extern u32 apicid_sb700;
-extern u32 bus_type[256];
extern u32 sbdn_rs780;
extern u32 sbdn_sb700;
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- int j;
+ int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -49,12 +47,7 @@
get_bus_conf();
- /* Bus: Bus ID Type */
- /* define bus and isa numbers */
- for (j = 0; j < bus_isa; j++) {
- smp_write_bus(mc, j, (char *)"PCI ");
- }
- smp_write_bus(mc, bus_isa, (char *)"ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
Modified: trunk/src/mainboard/kontron/kt690/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/kontron/kt690/get_bus_conf.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/kontron/kt690/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -32,7 +32,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
-u8 bus_isa;
u8 bus_rs690[8];
u8 bus_sb600[2];
u32 apicid_sb600;
@@ -54,8 +53,6 @@
0x20202020,
};
-u32 bus_type[256];
-
u32 sbdn_rs690;
u32 sbdn_sb600;
@@ -67,7 +64,7 @@
{
u32 apicid_base;
device_t dev;
- int i, j;
+ int i;
if (get_bus_conf_done == 1)
return; /* do it only once */
@@ -92,25 +89,13 @@
bus_rs690[i] = 0;
}
- for (i = 0; i < 256; i++) {
- bus_type[i] = 0; /* default ISA bus. */
- }
-
- bus_type[0] = 1; /* pci */
-
bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sb600[0] = bus_rs690[0];
- bus_type[bus_rs690[0]] = 1;
-
/* sb600 */
dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4));
if (dev) {
bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- for (j = bus_sb600[1]; j < bus_isa; j++)
- bus_type[j] = 1;
}
/* rs690 */
@@ -118,16 +103,10 @@
dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0));
if (dev) {
bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- if(255 != bus_rs690[i]) {
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- bus_type[bus_rs690[i]] = 1; /* PCI bus. */
- }
}
}
/* I/O APICs: APIC ID Version State Address */
- bus_isa = 10;
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
#else
Modified: trunk/src/mainboard/kontron/kt690/irq_tables.c
==============================================================================
--- trunk/src/mainboard/kontron/kt690/irq_tables.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/kontron/kt690/irq_tables.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -51,7 +51,6 @@
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
-extern u8 bus_isa;
extern u8 bus_rs690[8];
extern u8 bus_sb600[2];
extern unsigned long sbdn_sb600;
Modified: trunk/src/mainboard/kontron/kt690/mptable.c
==============================================================================
--- trunk/src/mainboard/kontron/kt690/mptable.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/kontron/kt690/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -25,20 +25,18 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
-extern u8 bus_isa;
extern u8 bus_rs690[8];
extern u8 bus_sb600[2];
extern u32 apicid_sb600;
-extern u32 bus_type[256];
extern u32 sbdn_rs690;
extern u32 sbdn_sb600;
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- int j;
+ int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -48,12 +46,7 @@
get_bus_conf();
- /* Bus: Bus ID Type */
- /* define bus and isa numbers */
- for (j = 0; j < bus_isa; j++) {
- smp_write_bus(mc, j, (char *)"PCI ");
- }
- smp_write_bus(mc, bus_isa, (char *)"ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
Modified: trunk/src/mainboard/technexion/tim5690/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/get_bus_conf.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/technexion/tim5690/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -32,7 +32,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
-u8 bus_isa;
u8 bus_rs690[8];
u8 bus_sb600[2];
u32 apicid_sb600;
@@ -54,8 +53,6 @@
0x20202020,
};
-u32 bus_type[256];
-
u32 sbdn_rs690;
u32 sbdn_sb600;
@@ -67,7 +64,7 @@
{
u32 apicid_base;
device_t dev;
- int i, j;
+ int i;
if (get_bus_conf_done == 1)
return; /* do it only once */
@@ -92,25 +89,13 @@
bus_rs690[i] = 0;
}
- for (i = 0; i < 256; i++) {
- bus_type[i] = 0; /* default ISA bus. */
- }
-
- bus_type[0] = 1; /* pci */
-
bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sb600[0] = bus_rs690[0];
- bus_type[bus_rs690[0]] = 1;
-
/* sb600 */
dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4));
if (dev) {
bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- for (j = bus_sb600[1]; j < bus_isa; j++)
- bus_type[j] = 1;
}
/* rs690 */
@@ -118,16 +103,10 @@
dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0));
if (dev) {
bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- if(255 != bus_rs690[i]) {
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- bus_type[bus_rs690[i]] = 1; /* PCI bus. */
- }
}
}
/* I/O APICs: APIC ID Version State Address */
- bus_isa = 10;
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
#else
Modified: trunk/src/mainboard/technexion/tim5690/irq_tables.c
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/irq_tables.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/technexion/tim5690/irq_tables.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -51,7 +51,6 @@
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
-extern u8 bus_isa;
extern u8 bus_rs690[8];
extern u8 bus_sb600[2];
extern unsigned long sbdn_sb600;
Modified: trunk/src/mainboard/technexion/tim5690/mptable.c
==============================================================================
--- trunk/src/mainboard/technexion/tim5690/mptable.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/technexion/tim5690/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -25,20 +25,18 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
-extern u8 bus_isa;
extern u8 bus_rs690[8];
extern u8 bus_sb600[2];
extern u32 apicid_sb600;
-extern u32 bus_type[256];
extern u32 sbdn_rs690;
extern u32 sbdn_sb600;
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- int j;
+ int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -48,12 +46,7 @@
get_bus_conf();
- /* Bus: Bus ID Type */
- /* define bus and isa numbers */
- for (j = 0; j < bus_isa; j++) {
- smp_write_bus(mc, j, (char *)"PCI ");
- }
- smp_write_bus(mc, bus_isa, (char *)"ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
Modified: trunk/src/mainboard/technexion/tim8690/get_bus_conf.c
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/get_bus_conf.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/technexion/tim8690/get_bus_conf.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -32,7 +32,6 @@
/* Global variables for MB layouts and these will be shared by irqtable mptable
* and acpi_tables busnum is default.
*/
-u8 bus_isa;
u8 bus_rs690[8];
u8 bus_sb600[2];
u32 apicid_sb600;
@@ -54,8 +53,6 @@
0x20202020,
};
-u32 bus_type[256];
-
u32 sbdn_rs690;
u32 sbdn_sb600;
@@ -67,7 +64,7 @@
{
u32 apicid_base;
device_t dev;
- int i, j;
+ int i;
if (get_bus_conf_done == 1)
return; /* do it only once */
@@ -92,25 +89,13 @@
bus_rs690[i] = 0;
}
- for (i = 0; i < 256; i++) {
- bus_type[i] = 0; /* default ISA bus. */
- }
-
- bus_type[0] = 1; /* pci */
-
bus_rs690[0] = (sysconf.pci1234[0] >> 16) & 0xff;
bus_sb600[0] = bus_rs690[0];
- bus_type[bus_rs690[0]] = 1;
-
/* sb600 */
dev = dev_find_slot(bus_sb600[0], PCI_DEVFN(sbdn_sb600 + 0x14, 4));
if (dev) {
bus_sb600[1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- for (j = bus_sb600[1]; j < bus_isa; j++)
- bus_type[j] = 1;
}
/* rs690 */
@@ -118,16 +103,10 @@
dev = dev_find_slot(bus_rs690[0], PCI_DEVFN(sbdn_rs690 + i, 0));
if (dev) {
bus_rs690[i] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- if(255 != bus_rs690[i]) {
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- bus_type[bus_rs690[i]] = 1; /* PCI bus. */
- }
}
}
/* I/O APICs: APIC ID Version State Address */
- bus_isa = 10;
#if CONFIG_LOGICAL_CPUS==1
apicid_base = get_apicid_base(1);
#else
Modified: trunk/src/mainboard/technexion/tim8690/irq_tables.c
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/irq_tables.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/technexion/tim8690/irq_tables.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -51,7 +51,6 @@
pirq_info->slot = slot;
pirq_info->rfu = rfu;
}
-extern u8 bus_isa;
extern u8 bus_rs690[8];
extern u8 bus_sb600[2];
extern unsigned long sbdn_sb600;
Modified: trunk/src/mainboard/technexion/tim8690/mptable.c
==============================================================================
--- trunk/src/mainboard/technexion/tim8690/mptable.c Sun Nov 21 15:38:24 2010 (r6104)
+++ trunk/src/mainboard/technexion/tim8690/mptable.c Sun Nov 21 15:40:09 2010 (r6105)
@@ -25,20 +25,18 @@
#include <stdint.h>
#include <cpu/amd/amdk8_sysconf.h>
-extern u8 bus_isa;
extern u8 bus_rs690[8];
extern u8 bus_sb600[2];
extern u32 apicid_sb600;
-extern u32 bus_type[256];
extern u32 sbdn_rs690;
extern u32 sbdn_sb600;
static void *smp_write_config_table(void *v)
{
struct mp_config_table *mc;
- int j;
+ int bus_isa;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
@@ -48,12 +46,7 @@
get_bus_conf();
- /* Bus: Bus ID Type */
- /* define bus and isa numbers */
- for (j = 0; j < bus_isa; j++) {
- smp_write_bus(mc, j, (char *)"PCI ");
- }
- smp_write_bus(mc, bus_isa, (char *)"ISA ");
+ mptable_write_buses(mc, NULL, &bus_isa);
/* I/O APICs: APIC ID Version State Address */
{
1
0
[commit] r6104 - in trunk/src: mainboard/gigabyte/m57sli mainboard/msi/ms7260 mainboard/msi/ms9652_fam10 mainboard/nvidia/l1_2pvv mainboard/supermicro/h8dme mainboard/supermicro/h8dmr mainboard/sup...
by repository service 21 Nov '10
by repository service 21 Nov '10
21 Nov '10
Author: oxygene
Date: Sun Nov 21 15:38:24 2010
New Revision: 6104
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6104
Log:
Move MCP55_PCI_E_X_* to Kconfig. Any useless values in romstage.cs were
not brought over to Kconfig (this applies to all #defines to 4, as
that's the default anyway)
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de>
Modified:
trunk/src/mainboard/gigabyte/m57sli/Kconfig
trunk/src/mainboard/gigabyte/m57sli/romstage.c
trunk/src/mainboard/msi/ms7260/Kconfig
trunk/src/mainboard/msi/ms7260/romstage.c
trunk/src/mainboard/msi/ms9652_fam10/Kconfig
trunk/src/mainboard/msi/ms9652_fam10/romstage.c
trunk/src/mainboard/nvidia/l1_2pvv/Kconfig
trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
trunk/src/mainboard/supermicro/h8dme/romstage.c
trunk/src/mainboard/supermicro/h8dmr/romstage.c
trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
trunk/src/mainboard/tyan/s2912/Kconfig
trunk/src/mainboard/tyan/s2912/romstage.c
trunk/src/mainboard/tyan/s2912_fam10/Kconfig
trunk/src/mainboard/tyan/s2912_fam10/romstage.c
trunk/src/southbridge/nvidia/mcp55/Kconfig
trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
Modified: trunk/src/mainboard/gigabyte/m57sli/Kconfig
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/Kconfig Sun Nov 21 12:36:03 2010 (r6103)
+++ trunk/src/mainboard/gigabyte/m57sli/Kconfig Sun Nov 21 15:38:24 2010 (r6104)
@@ -95,4 +95,8 @@
int
default 11
+config MCP55_PCI_E_X_0
+ int
+ default 0
+
endif # BOARD_GIGABYTE_M57SLI
Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c
==============================================================================
--- trunk/src/mainboard/gigabyte/m57sli/romstage.c Sun Nov 21 12:36:03 2010 (r6103)
+++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Sun Nov 21 15:38:24 2010 (r6104)
@@ -76,8 +76,6 @@
return smbus_read_byte(device, address);
}
-#define MCP55_PCI_E_X_0 0
-
#define MCP55_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x68,/* GPIO38 PCI_REQ3 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x68,/* GPIO39 PCI_GNT3 */ \
Modified: trunk/src/mainboard/msi/ms7260/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms7260/Kconfig Sun Nov 21 12:36:03 2010 (r6103)
+++ trunk/src/mainboard/msi/ms7260/Kconfig Sun Nov 21 15:38:24 2010 (r6104)
@@ -93,4 +93,8 @@
int
default 11
+config MCP55_PCI_E_X_0
+ int
+ default 0
+
endif # BOARD_MSI_MS7260
Modified: trunk/src/mainboard/msi/ms7260/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms7260/romstage.c Sun Nov 21 12:36:03 2010 (r6103)
+++ trunk/src/mainboard/msi/ms7260/romstage.c Sun Nov 21 15:38:24 2010 (r6104)
@@ -76,8 +76,6 @@
#include "resourcemap.c"
#include "cpu/amd/dualcore/dualcore.c"
-#define MCP55_PCI_E_X_0 0
-
#define MCP55_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/Kconfig Sun Nov 21 12:36:03 2010 (r6103)
+++ trunk/src/mainboard/msi/ms9652_fam10/Kconfig Sun Nov 21 15:38:24 2010 (r6104)
@@ -192,4 +192,8 @@
bool
default y
+config MCP55_PCI_E_X_0
+ int
+ default 1
+
endif # BOARD_MSI_MS9652_FAM10
Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Sun Nov 21 12:36:03 2010 (r6103)
+++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Sun Nov 21 15:38:24 2010 (r6104)
@@ -78,8 +78,6 @@
#include "cpu/amd/quadcore/quadcore.c"
-#define MCP55_PCI_E_X_0 1
-
#define MCP55_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
Modified: trunk/src/mainboard/nvidia/l1_2pvv/Kconfig
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/Kconfig Sun Nov 21 12:36:03 2010 (r6103)
+++ trunk/src/mainboard/nvidia/l1_2pvv/Kconfig Sun Nov 21 15:38:24 2010 (r6104)
@@ -97,4 +97,8 @@
int
default 11
+config MCP55_PCI_E_X_0
+ int
+ default 2
+
endif # BOARD_NVIDIA_L1_2PVV
Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
==============================================================================
--- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Sun Nov 21 12:36:03 2010 (r6103)
+++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Sun Nov 21 15:38:24 2010 (r6104)
@@ -86,9 +86,6 @@
#include "cpu/amd/dualcore/dualcore.c"
-#define MCP55_PCI_E_X_0 2
-#define MCP55_PCI_E_X_1 4
-
#define MCP55_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dme/romstage.c Sun Nov 21 12:36:03 2010 (r6103)
+++ trunk/src/mainboard/supermicro/h8dme/romstage.c Sun Nov 21 15:38:24 2010 (r6104)
@@ -141,8 +141,6 @@
#include "cpu/amd/dualcore/dualcore.c"
-#define MCP55_PCI_E_X_0 4
-
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr/romstage.c Sun Nov 21 12:36:03 2010 (r6103)
+++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Sun Nov 21 15:38:24 2010 (r6104)
@@ -86,8 +86,6 @@
#include "cpu/amd/dualcore/dualcore.c"
-#define MCP55_PCI_E_X_0 4
-
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Sun Nov 21 12:36:03 2010 (r6103)
+++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Sun Nov 21 15:38:24 2010 (r6104)
@@ -79,8 +79,6 @@
#include "cpu/amd/quadcore/quadcore.c"
-#define MCP55_PCI_E_X_0 4
-
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Sun Nov 21 12:36:03 2010 (r6103)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Sun Nov 21 15:38:24 2010 (r6104)
@@ -82,8 +82,6 @@
#include "cpu/amd/quadcore/quadcore.c"
-#define MCP55_PCI_E_X_0 4
-
#include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
#include "southbridge/nvidia/mcp55/mcp55_early_setup_car.c"
Modified: trunk/src/mainboard/tyan/s2912/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2912/Kconfig Sun Nov 21 12:36:03 2010 (r6103)
+++ trunk/src/mainboard/tyan/s2912/Kconfig Sun Nov 21 15:38:24 2010 (r6104)
@@ -88,4 +88,8 @@
int
default 11
+config MCP55_PCI_E_X_0
+ int
+ default 1
+
endif # BOARD_TYAN_S2912
Modified: trunk/src/mainboard/tyan/s2912/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912/romstage.c Sun Nov 21 12:36:03 2010 (r6103)
+++ trunk/src/mainboard/tyan/s2912/romstage.c Sun Nov 21 15:38:24 2010 (r6104)
@@ -86,8 +86,6 @@
#include "cpu/amd/dualcore/dualcore.c"
-#define MCP55_PCI_E_X_0 1
-
#define MCP55_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
Modified: trunk/src/mainboard/tyan/s2912_fam10/Kconfig
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/Kconfig Sun Nov 21 12:36:03 2010 (r6103)
+++ trunk/src/mainboard/tyan/s2912_fam10/Kconfig Sun Nov 21 15:38:24 2010 (r6104)
@@ -105,4 +105,8 @@
hex
default 0xc0000
+config MCP55_PCI_E_X_0
+ int
+ default 1
+
endif # BOARD_TYAN_S2912_FAM10
Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c
==============================================================================
--- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Sun Nov 21 12:36:03 2010 (r6103)
+++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Sun Nov 21 15:38:24 2010 (r6104)
@@ -79,8 +79,6 @@
#include "cpu/amd/quadcore/quadcore.c"
-#define MCP55_PCI_E_X_0 1
-
#define MCP55_MB_SETUP \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+37, 0x00, 0x44,/* GPIO38 PCI_REQ3 */ \
RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+38, 0x00, 0x44,/* GPIO39 PCI_GNT3 */ \
Modified: trunk/src/southbridge/nvidia/mcp55/Kconfig
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/Kconfig Sun Nov 21 12:36:03 2010 (r6103)
+++ trunk/src/southbridge/nvidia/mcp55/Kconfig Sun Nov 21 15:38:24 2010 (r6104)
@@ -3,26 +3,46 @@
select HAVE_USBDEBUG
select IOAPIC
+if SOUTHBRIDGE_NVIDIA_MCP55
+
config ID_SECTION_OFFSET
hex
- default 0x80 if SOUTHBRIDGE_NVIDIA_MCP55
+ default 0x80
config EHCI_BAR
hex
- default 0xfef00000 if SOUTHBRIDGE_NVIDIA_MCP55
+ default 0xfef00000
config EHCI_DEBUG_OFFSET
hex
- default 0x98 if SOUTHBRIDGE_NVIDIA_MCP55
+ default 0x98
config MCP55_USE_NIC
bool
- default n if SOUTHBRIDGE_NVIDIA_MCP55
+ default n
config MCP55_USE_AZA
bool
- default n if SOUTHBRIDGE_NVIDIA_MCP55
+ default n
config MCP55_NUM
int
- default 1 if SOUTHBRIDGE_NVIDIA_MCP55
+ default 1
+
+config MCP55_PCI_E_X_0
+ int
+ default 4
+
+config MCP55_PCI_E_X_1
+ int
+ default 4
+
+config MCP55_PCI_E_X_2
+ int
+ default 4
+
+config MCP55_PCI_E_X_3
+ int
+ default 4
+
+endif
Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
==============================================================================
--- trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Sun Nov 21 12:36:03 2010 (r6103)
+++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c Sun Nov 21 15:38:24 2010 (r6104)
@@ -76,19 +76,6 @@
8 0 4 4 4 8 :5
*/
-#ifndef MCP55_PCI_E_X_0
- #define MCP55_PCI_E_X_0 4
-#endif
-#ifndef MCP55_PCI_E_X_1
- #define MCP55_PCI_E_X_1 4
-#endif
-#ifndef MCP55_PCI_E_X_2
- #define MCP55_PCI_E_X_2 4
-#endif
-#ifndef MCP55_PCI_E_X_3
- #define MCP55_PCI_E_X_3 4
-#endif
-
#define MCP55_CHIP_REV 3
static void mcp55_early_set_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base)
@@ -370,7 +357,7 @@
FIXME: May have problem if there is different MCP55 HTX card with different PCI_E lane allocation
Need to use same trick about pci1234 to verify node/link connection
*/
- unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {MCP55_PCI_E_X_0, MCP55_PCI_E_X_1, MCP55_PCI_E_X_2, MCP55_PCI_E_X_3 };
+ unsigned pci_e_x[HT_CHAIN_NUM_MAX] = {CONFIG_MCP55_PCI_E_X_0, CONFIG_MCP55_PCI_E_X_1, CONFIG_MCP55_PCI_E_X_2, CONFIG_MCP55_PCI_E_X_3 };
int mcp55_num = 0;
unsigned busnx;
unsigned devnx;
1
0
Hi,
some more mptables conversions, abuild tested, but not boot tested.
This time:
arima/hdama
broadcom/blast
dell/s1850
getac/p470
gigabyte/ga_2761gxdk
gigabyte/m57sli
hp/dl145_g1
hp/dl145_g3
hp/dl165_g6_fam10
ibase/mb899
ibm/e325
ibm/e326
intel/d945gclf
iwill/dk8_htx
iwill/dk8s2
iwill/dk8x
msi/ms7135
msi/ms7260
msi/ms9185
msi/ms9282
msi/ms9652_fam10
newisys/khepri
nvidia/l1_2pvv
roda/rk886ex
sunw/ultra40
tyan/s2881
tyan/s2882
tyan/s2885
tyan/s2891
tyan/s2892
tyan/s2895
tyan/s2912
tyan/s2912_fam10
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
2
2
Hi,
conversion of mptable.c to use mptable_write_buses is still ongoing.
This patch handles a set of boards that do the bus handling reasonably
similar to each other.
All of them are abuild tested, none are boot tested.
This patch touches:
amd/dbm690t
amd/mahogany
amd/mahogany_fam10
amd/pistachio
amd/tilapia_fam10
asrock/939a785gmh
asus/m4a785-m
gigabyte/ma785gmt
gigabyte/ma78gm
iei/kino-780am2-fam10
jetway/pa78vm5
kontron/kt690
technexion/tim5690
technexion/tim8690
Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>
2
1