[commit] r6108 - in trunk/src: mainboard/amd/db800 mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/norwich mainboard/amd/pistachio mainboard/amd/serengeti_ch...
Author: uwe Date: Sun Nov 21 23:47:22 2010 New Revision: 6108 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6108
Log: Simplify a few code chunks, fix whitespace and indentation.
Also, remove some less useful comments, some dead code / unused functions.
Signed-off-by: Uwe Hermann uwe@hermann-uwe.de Acked-by: Uwe Hermann uwe@hermann-uwe.de
Modified: trunk/src/mainboard/amd/db800/romstage.c trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/norwich/romstage.c trunk/src/mainboard/amd/pistachio/romstage.c trunk/src/mainboard/amd/serengeti_cheetah/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/amd/tilapia_fam10/romstage.c trunk/src/mainboard/arima/hdama/romstage.c trunk/src/mainboard/artecgroup/dbe61/romstage.c trunk/src/mainboard/asi/mb_5blmp/romstage.c trunk/src/mainboard/asrock/939a785gmh/romstage.c trunk/src/mainboard/asus/a8n_e/romstage.c trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/asus/m2v-mx_se/romstage.c trunk/src/mainboard/asus/m2v/romstage.c trunk/src/mainboard/asus/m4a785-m/romstage.c trunk/src/mainboard/bcom/winnet100/romstage.c trunk/src/mainboard/bcom/winnetp680/romstage.c trunk/src/mainboard/broadcom/blast/romstage.c trunk/src/mainboard/dell/s1850/romstage.c trunk/src/mainboard/digitallogic/adl855pc/romstage.c trunk/src/mainboard/digitallogic/msm586seg/romstage.c trunk/src/mainboard/digitallogic/msm800sev/romstage.c trunk/src/mainboard/eaglelion/5bcm/romstage.c trunk/src/mainboard/emulation/qemu-x86/romstage.c trunk/src/mainboard/getac/p470/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/gigabyte/ma785gmt/romstage.c trunk/src/mainboard/gigabyte/ma78gm/romstage.c trunk/src/mainboard/hp/dl145_g1/romstage.c trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c trunk/src/mainboard/ibase/mb899/romstage.c trunk/src/mainboard/ibm/e325/romstage.c trunk/src/mainboard/ibm/e326/romstage.c trunk/src/mainboard/iei/juki-511p/romstage.c trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c trunk/src/mainboard/iei/nova4899r/romstage.c trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c trunk/src/mainboard/intel/d945gclf/romstage.c trunk/src/mainboard/intel/eagleheights/romstage.c trunk/src/mainboard/intel/jarrell/romstage.c trunk/src/mainboard/intel/truxton/romstage.c trunk/src/mainboard/intel/xe7501devkit/romstage.c trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/jetway/j7f24/romstage.c trunk/src/mainboard/jetway/pa78vm5/romstage.c trunk/src/mainboard/kontron/986lcd-m/romstage.c trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/lanner/em8510/romstage.c trunk/src/mainboard/lippert/frontrunner/romstage.c trunk/src/mainboard/msi/ms7135/romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/newisys/khepri/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/pcengines/alix1c/romstage.c trunk/src/mainboard/pcengines/alix2d/romstage.c trunk/src/mainboard/rca/rm4100/romstage.c trunk/src/mainboard/roda/rk886ex/romstage.c trunk/src/mainboard/sunw/ultra40/romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/supermicro/x6dai_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/romstage.c trunk/src/mainboard/televideo/tc7020/romstage.c trunk/src/mainboard/thomson/ip1000/romstage.c trunk/src/mainboard/traverse/geos/romstage.c trunk/src/mainboard/tyan/s2735/romstage.c trunk/src/mainboard/tyan/s2850/romstage.c trunk/src/mainboard/tyan/s2875/romstage.c trunk/src/mainboard/tyan/s2880/romstage.c trunk/src/mainboard/tyan/s2881/romstage.c trunk/src/mainboard/tyan/s2882/romstage.c trunk/src/mainboard/tyan/s2885/romstage.c trunk/src/mainboard/tyan/s2891/romstage.c trunk/src/mainboard/tyan/s2892/romstage.c trunk/src/mainboard/tyan/s2895/romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/mainboard/tyan/s4880/romstage.c trunk/src/mainboard/tyan/s4882/romstage.c trunk/src/mainboard/via/epia-cn/romstage.c trunk/src/mainboard/via/epia-m/romstage.c trunk/src/mainboard/via/epia-m700/romstage.c trunk/src/mainboard/via/epia-n/romstage.c trunk/src/mainboard/via/epia/romstage.c trunk/src/mainboard/via/pc2500e/romstage.c trunk/src/mainboard/winent/pl6064/romstage.c trunk/src/mainboard/wyse/s50/romstage.c trunk/src/northbridge/via/vx800/examples/romstage.c
Modified: trunk/src/mainboard/amd/db800/romstage.c ============================================================================== --- trunk/src/mainboard/amd/db800/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/amd/db800/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -54,11 +54,6 @@ #include "cpu/amd/model_lx/syspreinit.c" #include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void) -{ - /* Early mainboard specific GPIO setup. */ -} - void main(unsigned long bist) { post_code(0x01); @@ -76,7 +71,6 @@ * early MSR setup for CS5536. */ w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - mb_gpio_init(); uart_init(); console_init();
Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -47,17 +47,9 @@ #include "southbridge/amd/sb600/sb600_early_setup.c" #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -/* called in raminit_f.c */ -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */ static inline int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); @@ -88,14 +80,12 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - /* sb600_lpc_port80(); */ sb600_pci_port80(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
enable_rs690_dev8(); sb600_lpc_init(); @@ -135,8 +125,7 @@ /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ cpuid1 = cpuid(0x80000007); - if( (cpuid1.edx & 0x6) == 0x6 ) { - + if ((cpuid1.edx & 0x6) == 0x6) { /* Read FIDVID_STATUS */ msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); @@ -148,7 +137,6 @@ /* show final fid and vid */ msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); - } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); }
Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/amd/mahogany/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -47,17 +47,9 @@ #include "southbridge/amd/sb700/sb700_early_setup.c" #include "northbridge/amd/amdk8/debug.c" /* After sb700_early_setup.c! */
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -/* called in raminit_f.c */ -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */ static inline int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); @@ -88,14 +80,12 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - /* sb700_lpc_port80(); */ sb700_pci_port80(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
enable_rs780_dev8(); sb700_lpc_init(); @@ -134,8 +124,7 @@ /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ cpuid1 = cpuid(0x80000007); - if( (cpuid1.edx & 0x6) == 0x6 ) { - + if ((cpuid1.edx & 0x6) == 0x6) { /* Read FIDVID_STATUS */ msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); @@ -147,7 +136,6 @@ /* show final fid and vid */ msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); - } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); }
Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -53,15 +53,11 @@ #include "northbridge/amd/amdfam10/debug.c" #include <spd.h>
-static void activate_spd_rom(const struct mem_controller *ctrl) -{ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address) { - int result; - result = smbus_read_byte(device, address); - return result; + return smbus_read_byte(device, address); }
#include "northbridge/amd/amdfam10/amdfam10.h" @@ -78,11 +74,9 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0; - u32 val; + u32 bsp_apicid = 0, val; msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) { @@ -91,7 +85,6 @@ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - sb700_pci_port80(); }
Modified: trunk/src/mainboard/amd/norwich/romstage.c ============================================================================== --- trunk/src/mainboard/amd/norwich/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/amd/norwich/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -51,11 +51,6 @@ #include "cpu/amd/model_lx/syspreinit.c" #include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void) -{ - /* Early mainboard specific GPIO setup. */ -} - void main(unsigned long bist) { post_code(0x01); @@ -77,7 +72,6 @@ */ /* If debug. real setup done in chipset init via devicetree.cb. */ cs5536_setup_onchipuart(1); - mb_gpio_init(); uart_init(); console_init();
Modified: trunk/src/mainboard/amd/pistachio/romstage.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/amd/pistachio/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -42,17 +42,9 @@ #include "southbridge/amd/sb600/sb600_early_setup.c" #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */
-/* CAN'T BE REMOVED! memory bus reset hook for some broken amd k8 boards. */ -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -/* called in raminit_f.c */ -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */ static inline int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); @@ -85,14 +77,12 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - sb600_lpc_port80(); /* sb600_pci_port80(); */ }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
enable_rs690_dev8(); sb600_lpc_init(); @@ -138,8 +128,7 @@ /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ cpuid1 = cpuid(0x80000007); - if( (cpuid1.edx & 0x6) == 0x6 ) { - + if ((cpuid1.edx & 0x6) == 0x6) { /* Read FIDVID_STATUS */ msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); @@ -151,7 +140,6 @@ /* show final fid and vid */ msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); - } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); }
Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -33,13 +33,11 @@ static void memreset_setup(void) { //GPIO on amd8111 to enable MEMRST ???? - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
-static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl) { @@ -54,6 +52,7 @@
smbus_write_byte(SMBUS_HUB, 0x03, 0); } + #if 0 static inline void change_i2c_mux(unsigned device) { @@ -80,7 +79,7 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" /* tyan does not want the default */ +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> #include "cpu/amd/car/post_cache_as_ram.c" @@ -117,7 +116,6 @@ };
struct sys_info *sysinfo = (void*)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset; unsigned bsp_apicid = 0; #if CONFIG_SET_FIDVID @@ -127,18 +125,12 @@ if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* Setup the rom access for 4M */ amd8111_enable_rom(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - } - -// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -188,20 +180,17 @@ /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ cpuid1 = cpuid(0x80000007); - if( (cpuid1.edx & 0x6) == 0x6 ) { + if ((cpuid1.edx & 0x6) == 0x6) {
{ /* Read FIDVID_STATUS */ msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - }
enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid);
// show final fid and vid @@ -209,13 +198,11 @@ msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - }
} else { print_debug("Changing FIDVID not supported\n"); } - #endif
#if 1
Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -55,8 +55,8 @@ static void memreset_setup(void) { //GPIO on amd8111 to enable MEMRST ???? - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN=1 - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); // REVC_MEMRST_EN=1 + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
static void activate_spd_rom(const struct mem_controller *ctrl) @@ -77,9 +77,7 @@
static int spd_read_byte(u32 device, u32 address) { - int result; - result = smbus_read_byte(device, address); - return result; + return smbus_read_byte(device, address); }
#include "northbridge/amd/amdfam10/amdfam10.h" @@ -190,8 +188,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - u32 bsp_apicid = 0; - u32 val; + u32 bsp_apicid = 0, val; msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) {
Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -52,15 +52,11 @@ #include "southbridge/amd/sb700/sb700_early_setup.c" #include "northbridge/amd/amdfam10/debug.c"
-static void activate_spd_rom(const struct mem_controller *ctrl) -{ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address) { - int result; - result = smbus_read_byte(device, address); - return result; + return smbus_read_byte(device, address); }
#include "northbridge/amd/amdfam10/amdfam10.h" @@ -78,11 +74,9 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0; - u32 val; + u32 bsp_apicid = 0, val; msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) { @@ -91,7 +85,6 @@ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - sb700_pci_port80(); }
@@ -157,13 +150,13 @@ */ wait_all_core0_started();
- #if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS==1 /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); post_code(0x37); wait_all_other_cores_started(bsp_apicid); - #endif +#endif
post_code(0x38);
@@ -171,7 +164,7 @@ rs780_early_setup(); sb700_early_setup();
- #if CONFIG_SET_FIDVID +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
@@ -192,7 +185,7 @@ /* show final fid and vid */ msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); - #endif +#endif
rs780_htinit();
Modified: trunk/src/mainboard/arima/hdama/romstage.c ============================================================================== --- trunk/src/mainboard/arima/hdama/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/arima/hdama/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -32,14 +32,13 @@ static void memreset_setup(void) { if (is_cpu_pre_c0()) { - /* Set the memreset low */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); - /* Ensure the BIOS has control of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); - } - else { - /* Ensure the CPU has controll of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); + /* Set the memreset low. */ + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); + /* Ensure the BIOS has control of the memory lines. */ + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); + } else { + /* Ensure the CPU has control of the memory lines. */ + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); } }
@@ -47,16 +46,13 @@ { if (is_cpu_pre_c0()) { udelay(800); - /* Set memreset_high */ - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); + /* Set memreset high. */ + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); udelay(90); } }
-static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -85,22 +81,18 @@ };
int needs_reset; - unsigned bsp_apicid = 0; + unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; - unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - amd8111_enable_rom(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - }
pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init();
Modified: trunk/src/mainboard/artecgroup/dbe61/romstage.c ============================================================================== --- trunk/src/mainboard/artecgroup/dbe61/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/artecgroup/dbe61/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -66,11 +66,6 @@ #include "cpu/amd/model_lx/syspreinit.c" #include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void) -{ - /* Early mainboard specific GPIO setup */ -} - void main(unsigned long bist) { post_code(0x01); @@ -96,7 +91,6 @@ msr.lo |= 0x7 << 20; wrmsr(MDD_LEG_IO, msr);
- mb_gpio_init(); uart_init(); console_init();
@@ -109,7 +103,7 @@
sdram_initialize(1, memctrl);
- /* Dump memory configuratation */ + /* Dump memory configuration. */ #if 0 msr = rdmsr(MC_CF07_DATA); print_debug("MC_CF07_DATA: ");
Modified: trunk/src/mainboard/asi/mb_5blmp/romstage.c ============================================================================== --- trunk/src/mainboard/asi/mb_5blmp/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/asi/mb_5blmp/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -35,20 +35,11 @@
static void main(unsigned long bist) { - /* Initialize the serial console. */ pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - - /* Halt if there was a built in self test failure. */ report_bist_failure(bist); - cs5530_enable_rom(); - - /* Initialize RAM. */ sdram_init(); - - /* Check whether RAM works. */ /* ram_check(0x00000000, 0x4000); */ } -
Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -52,17 +52,9 @@ #define GPIO6_DEV PNP_DEV(0x2e, W83627DHG_GPIO6) #define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345)
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -/* called in raminit_f.c */ -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */ static inline int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); @@ -140,14 +132,12 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - /* sb700_lpc_port80(); */ sb700_pci_port80(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
enable_rs780_dev8(); sb700_lpc_init(); @@ -187,8 +177,7 @@ /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ cpuid1 = cpuid(0x80000007); - if( (cpuid1.edx & 0x6) == 0x6 ) { - + if ((cpuid1.edx & 0x6) == 0x6) { /* Read FIDVID_STATUS */ msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); @@ -200,7 +189,6 @@ /* show final fid and vid */ msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); - } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); }
Modified: trunk/src/mainboard/asus/a8n_e/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/asus/a8n_e/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -50,15 +50,8 @@ #include "cpu/amd/dualcore/dualcore.c" #include <spd.h>
-static void memreset(int controllers, const struct mem_controller *ctrl) -{ - /* Nothing to do. */ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* Nothing to do. */ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -108,7 +101,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - sio_setup(); }
@@ -138,7 +130,6 @@
needs_reset |= ht_setup_chains_x(); needs_reset |= ck804_early_setup_x(); - if (needs_reset) { print_info("ht reset -\n"); soft_reset();
Modified: trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -52,19 +52,14 @@ #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED) #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
-static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); }
-static void activate_spd_rom(const struct mem_controller *ctrl) -{ -} - #include <reset.h> void soft_reset(void) {
Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -52,19 +52,14 @@ #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED) #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI)
-static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); }
-static void activate_spd_rom(const struct mem_controller *ctrl) -{ -} - #include <reset.h> void soft_reset(void) {
Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -54,19 +54,14 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO)
-static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); }
-static void activate_spd_rom(const struct mem_controller *ctrl) -{ -} - // defines S3_NVRAM_EARLY: #include "southbridge/via/k8t890/k8t890_early_car.c" #include "northbridge/amd/amdk8/amdk8.h"
Modified: trunk/src/mainboard/asus/m2v/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/asus/m2v/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -56,19 +56,14 @@
#define IT8712F_GPIO_BASE 0x0a20
-static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); }
-static void activate_spd_rom(const struct mem_controller *ctrl) -{ -} - // defines S3_NVRAM_EARLY: #include "southbridge/via/k8t890/k8t890_early_car.c" #include "northbridge/amd/amdk8/amdk8.h"
Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/asus/m4a785-m/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -52,15 +52,11 @@ #include "southbridge/amd/sb700/sb700_early_setup.c" #include "northbridge/amd/amdfam10/debug.c"
-static void activate_spd_rom(const struct mem_controller *ctrl) -{ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address) { - int result; - result = smbus_read_byte(device, address); - return result; + return smbus_read_byte(device, address); }
#include "northbridge/amd/amdfam10/amdfam10.h" @@ -78,11 +74,9 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0; - u32 val; + u32 bsp_apicid = 0, val; msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) { @@ -91,7 +85,6 @@ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - sb700_pci_port80(); }
@@ -108,7 +101,7 @@ sb700_lpc_init();
it8712f_enable_serial(0, CONFIG_TTYS0_BASE); - it8712f_kill_watchdog(); /* disable watchdog, so it does not reset while still booting */ + it8712f_kill_watchdog(); uart_init();
#if CONFIG_USBDEBUG
Modified: trunk/src/mainboard/bcom/winnet100/romstage.c ============================================================================== --- trunk/src/mainboard/bcom/winnet100/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/bcom/winnet100/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -35,20 +35,11 @@
static void main(unsigned long bist) { - /* Initialize the serial console. */ pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - - /* Halt if there was a built in self test failure. */ report_bist_failure(bist); - cs5530_enable_rom(); - - /* Initialize RAM. */ sdram_init(); - - /* Check whether RAM works. */ /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/bcom/winnetp680/romstage.c ============================================================================== --- trunk/src/mainboard/bcom/winnetp680/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/bcom/winnetp680/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -47,7 +47,8 @@ static void enable_mainboard_devices(void) { device_t dev; - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev == PCI_DEV_INVALID) die("Southbridge not found!!!\n");
@@ -85,26 +86,19 @@ pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
w83697hf_set_clksel_48(SERIAL_DEV); - w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init();
- print_spew("In romstage.c:main()\n"); - enable_smbus(); smbus_fixup(&ctrl);
/* Halt if there was a built-in self test failure. */ report_bist_failure(bist);
- print_debug("Enabling mainboard devices\n"); enable_mainboard_devices();
ddr_ram_setup(&ctrl);
/* ram_check(0, 640 * 1024); */ - - print_spew("Leaving romstage.c:main()\n"); } -
Modified: trunk/src/mainboard/broadcom/blast/romstage.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/broadcom/blast/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -26,13 +26,8 @@ #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1) #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
-static void memreset_setup(void) -{ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} +static void memreset_setup(void) { } +static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl) { @@ -60,7 +55,7 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" /* tyan does not want the default */ +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> #include "cpu/amd/car/post_cache_as_ram.c" @@ -80,36 +75,23 @@ };
int needs_reset; - unsigned bsp_apicid = 0; - + unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; - unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - bcm5785_enable_rom(); - bcm5785_enable_lpc(); - - //enable RTC - pc87417_enable_dev(RTC_DEV); + pc87417_enable_dev(RTC_DEV); /* Enable RTC */ }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - } -// post_code(0x32);
pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); -// post_code(0x33); - uart_init(); -// post_code(0x34); - console_init();
/* Halt if there was a built in self test failure */ @@ -166,9 +148,6 @@
#if 0 print_pci_devices(); -#endif - -#if 0 dump_pci_devices(); #endif
Modified: trunk/src/mainboard/dell/s1850/romstage.c ============================================================================== --- trunk/src/mainboard/dell/s1850/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/dell/s1850/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -67,6 +67,7 @@ while((inb(ipmicsr) & (1<<OBF)) == 0) ; } + /* quite possibly the stupidest interface ever designed. */ static inline void first_cmd_byte(unsigned char byte) { @@ -154,12 +155,6 @@ static const struct mem_controller mch[] = { { .node_id = 0, - /* - .f0 = PCI_DEV(0, 0x00, 0), - .f1 = PCI_DEV(0, 0x00, 1), - .f2 = PCI_DEV(0, 0x00, 2), - .f3 = PCI_DEV(0, 0x00, 3), - */ /* the wiring on this part is really messed up */ /* this is my best guess so far */ .channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, }, @@ -260,9 +255,8 @@ if (bist == 0) { /* Skip this if there was a built in self test failure */ early_mtrr_init(); - if (memory_initialized()) { + if (memory_initialized()) skip_romstage(); - } } /* Setup the console */ mainboard_set_ich5(); @@ -311,9 +305,8 @@ #if 0 // dump_spd_registers(&cpu[0]); int i; - for(i = 0; i < 1; i++) { + for(i = 0; i < 1; i++) dump_spd_registers(); - } #endif #if 1 show_dram_slots();
Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -55,13 +55,12 @@ print_pci_devices(); #endif
- if(!bios_reset_detected()) { + if (!bios_reset_detected()) { enable_smbus(); #if 0 dump_spd_registers(&memctrl[0]); dump_smbus_registers(); #endif - sdram_initialize(ARRAY_SIZE(memctrl), memctrl); }
Modified: trunk/src/mainboard/digitallogic/msm586seg/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/digitallogic/msm586seg/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -42,10 +42,7 @@ int i; };
-static inline int spd_read_byte(unsigned device, unsigned address) -{ -// return smbus_read_byte(device, address); -} +static int spd_read_byte(unsigned device, unsigned address) { }
static inline void dumpmem(void){ int i, j;
Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm800sev/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -20,7 +20,7 @@
static inline int spd_read_byte(unsigned device, unsigned address) { - return smbus_read_byte(device, address); + return smbus_read_byte(device, address); }
#define ManualConf 0 /* Do automatic strapped PLL config */ @@ -35,11 +35,6 @@ #include "cpu/amd/model_lx/syspreinit.c" #include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void) -{ - /* Early mainboard specific GPIO setup */ -} - void main(unsigned long bist) { post_code(0x01); @@ -59,7 +54,6 @@ */ cs5536_disable_internal_uart(); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - mb_gpio_init(); uart_init(); console_init();
Modified: trunk/src/mainboard/eaglelion/5bcm/romstage.c ============================================================================== --- trunk/src/mainboard/eaglelion/5bcm/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/eaglelion/5bcm/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -19,32 +19,7 @@ pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - - /* Halt if there was a built in self test failure */ report_bist_failure(bist); - cs5530_enable_rom(); - sdram_init(); - - /* Check all of memory */ -#if 0 - ram_check(0x00000000, msr.lo); -#endif -#if 0 - static const struct { - unsigned long lo, hi; - } check_addrs[] = { - /* Check 16MB of memory @ 0*/ - { 0x00000000, 0x01000000 }, -#if TOTAL_CPUS > 1 - /* Check 16MB of memory @ 2GB */ - { 0x80000000, 0x81000000 }, -#endif - }; - int i; - for(i = 0; i < ARRAY_SIZE(check_addrs); i++) { - ram_check(check_addrs[i].lo, check_addrs[i].hi); - } -#endif }
Modified: trunk/src/mainboard/emulation/qemu-x86/romstage.c ============================================================================== --- trunk/src/mainboard/emulation/qemu-x86/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/emulation/qemu-x86/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -13,7 +13,7 @@
static void main(void) { - /* init_timer();*/ + /* init_timer(); */ post_code(0x05);
uart_init(); @@ -22,4 +22,3 @@ //print_pci_devices(); //dump_pci_devices(); } -
Modified: trunk/src/mainboard/getac/p470/romstage.c ============================================================================== --- trunk/src/mainboard/getac/p470/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/getac/p470/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -277,9 +277,8 @@ u32 reg32; int boot_mode = 0;
- if (bist == 0) { + if (bist == 0) enable_lapic(); - }
#if 0 /* Force PCIRST# */
Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -56,14 +56,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -119,35 +113,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, - // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, };
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset = 0; unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - sio_setup(); - - /* Setup the sis966 */ sis966_enable_rom(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
pnp_enter_ext_func_mode(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x23, 0); @@ -194,21 +182,15 @@ msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } #endif
Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -53,14 +53,8 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8716F_GPIO)
-static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -111,17 +105,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, - // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, };
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset = 0; unsigned bsp_apicid = 0; uint8_t tmp = 0; @@ -129,18 +122,13 @@ if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - sio_setup(); - - /* Setup the mcp55 */ mcp55_enable_rom(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
pnp_enter_ext_func_mode(SERIAL_DEV); /* The following line will set CLKIN to 24 MHz, external */ @@ -153,9 +141,6 @@ /* Set Serial Flash interface to 0x0820 */ pnp_write_config(GPIO_DEV, 0x64, 0x08); pnp_write_config(GPIO_DEV, 0x65, 0x20); - /* We can get away with not resetting the logical device because - * it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE) will do that. - */ } it8716f_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE); pnp_exit_ext_func_mode(SERIAL_DEV); @@ -200,21 +185,15 @@ msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } #endif
Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -48,15 +48,11 @@ #include "southbridge/amd/sb700/sb700_early_setup.c" #include "northbridge/amd/amdfam10/debug.c"
-static void activate_spd_rom(const struct mem_controller *ctrl) -{ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address) { - int result; - result = smbus_read_byte(device, address); - return result; + return smbus_read_byte(device, address); }
#include "northbridge/amd/amdfam10/amdfam10.h" @@ -76,8 +72,7 @@ { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0; - u32 val; + u32 bsp_apicid = 0, val; msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) { @@ -86,7 +81,6 @@ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - sb700_pci_port80(); }
@@ -153,13 +147,13 @@ */ wait_all_core0_started();
- #if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS==1 /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); post_code(0x37); wait_all_other_cores_started(bsp_apicid); - #endif +#endif
post_code(0x38);
@@ -167,7 +161,7 @@ rs780_early_setup(); sb700_early_setup();
- #if CONFIG_SET_FIDVID +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
@@ -188,7 +182,7 @@ /* show final fid and vid */ msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); - #endif +#endif
rs780_htinit();
Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -52,15 +52,11 @@ #include "southbridge/amd/sb700/sb700_early_setup.c" #include "northbridge/amd/amdfam10/debug.c"
-static void activate_spd_rom(const struct mem_controller *ctrl) -{ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address) { - int result; - result = smbus_read_byte(device, address); - return result; + return smbus_read_byte(device, address); }
#include "northbridge/amd/amdfam10/amdfam10.h" @@ -80,8 +76,7 @@ { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0; - u32 val; + u32 bsp_apicid = 0, val; msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) { @@ -90,7 +85,6 @@ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - sb700_pci_port80(); }
@@ -155,13 +149,13 @@ */ wait_all_core0_started();
- #if CONFIG_LOGICAL_CPUS==1 +#if CONFIG_LOGICAL_CPUS==1 /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); post_code(0x37); wait_all_other_cores_started(bsp_apicid); - #endif +#endif
post_code(0x38);
@@ -169,7 +163,7 @@ rs780_early_setup(); sb700_early_setup();
- #if CONFIG_SET_FIDVID +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
@@ -190,7 +184,7 @@ /* show final fid and vid */ msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); - #endif +#endif
rs780_htinit();
Modified: trunk/src/mainboard/hp/dl145_g1/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g1/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/hp/dl145_g1/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -27,13 +27,13 @@ static void memreset_setup(void) { if (is_cpu_pre_c0()) { - /* Set the memreset low */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); - /* Ensure the BIOS has control of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + /* Set the memreset low. */ + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); + /* Ensure the BIOS has control of the memory lines. */ + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); } else { - /* Ensure the CPU has controll of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); + /* Ensure the CPU has control of the memory lines. */ + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); } }
@@ -41,8 +41,8 @@ { if (is_cpu_pre_c0()) { udelay(800); - /* Set memreset_high */ - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); + /* Set memreset high. */ + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); udelay(90); } } @@ -97,37 +97,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - //first node - RC0|DIMM0, RC0|DIMM2, 0, 0, - RC0|DIMM1, RC0|DIMM3, 0, 0, + //first node + RC0|DIMM0, RC0|DIMM2, 0, 0, + RC0|DIMM1, RC0|DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - //second node - RC1|DIMM0, RC1|DIMM2, 0, 0, - RC1|DIMM1, RC1|DIMM3, 0, 0, + //second node + RC1|DIMM0, RC1|DIMM2, 0, 0, + RC1|DIMM1, RC1|DIMM3, 0, 0, #endif };
int needs_reset; - unsigned bsp_apicid = 0; - + unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; - unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* Setup the amd8111 */ amd8111_enable_rom(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - } - -// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init();
Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -59,9 +59,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
-static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl) { @@ -133,7 +131,6 @@ // first node DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, - // second node DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, @@ -141,24 +138,20 @@
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset; unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); bcm5785_enable_rom(); bcm5785_enable_lpc(); - //enable RTC - pc87417_enable_dev(RTC_DEV); + pc87417_enable_dev(RTC_DEV); /* Enable RTC */ }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Modified: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -100,30 +100,24 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - - u32 bsp_apicid = 0; - u32 val; + u32 bsp_apicid = 0, val; msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) { - /* Nothing special needs to be done to find bus 0 */ + /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - - /* Setup the rom access for 4M */ bcm5785_enable_rom(); bcm5785_enable_lpc(); - //enable RTC - pc87417_enable_dev(RTC_DEV); + pc87417_enable_dev(RTC_DEV); /* Enable RTC */ }
post_code(0x30);
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
Modified: trunk/src/mainboard/ibase/mb899/romstage.c ============================================================================== --- trunk/src/mainboard/ibase/mb899/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/ibase/mb899/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -239,9 +239,8 @@ u32 reg32; int boot_mode = 0;
- if (bist == 0) { + if (bist == 0) enable_lapic(); - }
ich7_enable_lpc(); early_superio_config_w83627ehg();
Modified: trunk/src/mainboard/ibm/e325/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e325/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/ibm/e325/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -29,13 +29,13 @@ static void memreset_setup(void) { if (is_cpu_pre_c0()) { - /* Set the memreset low */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); - /* Ensure the BIOS has control of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + /* Set the memreset low. */ + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); + /* Ensure the BIOS has control of the memory lines. */ + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); } else { - /* Ensure the CPU has controll of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); + /* Ensure the CPU has control of the memory lines. */ + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); } }
@@ -43,16 +43,13 @@ { if (is_cpu_pre_c0()) { udelay(800); - /* Set memreset_high */ - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); + /* Set memreset high. */ + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); udelay(90); } }
-static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -99,15 +96,12 @@ if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - amd8111_enable_rom(); }
- if (bist == 0) { + if (bist == 0) init_cpus(cpu_init_detectedx); - }
pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init();
Modified: trunk/src/mainboard/ibm/e326/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e326/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/ibm/e326/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -29,13 +29,13 @@ static void memreset_setup(void) { if (is_cpu_pre_c0()) { - /* Set the memreset low */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); - /* Ensure the BIOS has control of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + /* Set the memreset low. */ + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); + /* Ensure the BIOS has control of the memory lines. */ + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); } else { - /* Ensure the CPU has controll of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); + /* Ensure the CPU has control of the memory lines. */ + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); } }
@@ -43,16 +43,13 @@ { if (is_cpu_pre_c0()) { udelay(800); - /* Set memreset_high */ - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); + /* Set memreset high. */ + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); udelay(90); } }
-static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -99,15 +96,12 @@ if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - amd8111_enable_rom(); }
- if (bist == 0) { + if (bist == 0) init_cpus(cpu_init_detectedx); - }
pc87366_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init();
Modified: trunk/src/mainboard/iei/juki-511p/romstage.c ============================================================================== --- trunk/src/mainboard/iei/juki-511p/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/iei/juki-511p/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -36,12 +36,9 @@
static void main(unsigned long bist) { - /* Initialize the serial console. */ w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - - /* Halt if there was a built in self test failure. */ report_bist_failure(bist);
/* Disable Watchdog Timer. */ @@ -49,10 +46,6 @@ inb(0x843);
cs5530_enable_rom(); - - /* Initialize RAM. */ sdram_init(); - - /* Check RAM. */ /* ram_check(0x00000000, 640 * 1024); */ }
Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -25,9 +25,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0
-/* UART address and device number */ -#define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1) - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -55,15 +52,13 @@ #include "southbridge/amd/sb700/sb700_early_setup.c" #include "northbridge/amd/amdfam10/debug.c"
-static void activate_spd_rom(const struct mem_controller *ctrl) -{ -} +#define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1) + +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address) { - int result; - result = smbus_read_byte(device, address); - return result; + return smbus_read_byte(device, address); }
#include "northbridge/amd/amdfam10/amdfam10.h" @@ -81,11 +76,9 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0; - u32 val; + u32 bsp_apicid = 0, val; msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) { @@ -94,7 +87,6 @@ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - sb700_pci_port80(); }
Modified: trunk/src/mainboard/iei/nova4899r/romstage.c ============================================================================== --- trunk/src/mainboard/iei/nova4899r/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/iei/nova4899r/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -36,19 +36,11 @@
static void main(unsigned long bist) { - /* Initialize the serial console. */ w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - - /* Halt if there was a built in self test failure. */ report_bist_failure(bist); - cs5530_enable_rom(); - - /* Initialize RAM. */ sdram_init(); - - /* Check RAM. */ /* ram_check(0x00000000, 640 * 1024); */ }
Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -58,11 +58,6 @@ #include "cpu/amd/model_lx/syspreinit.c" #include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void) -{ - /* Early mainboard specific GPIO setup. */ -} - void main(unsigned long bist) { post_code(0x01); @@ -80,7 +75,6 @@ * early MSR setup for CS5536. */ w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - mb_gpio_init(); uart_init(); console_init();
Modified: trunk/src/mainboard/intel/d945gclf/romstage.c ============================================================================== --- trunk/src/mainboard/intel/d945gclf/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/intel/d945gclf/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -201,9 +201,8 @@ u32 reg32; int boot_mode = 0;
- if (bist == 0) { + if (bist == 0) enable_lapic(); - }
ich7_enable_lpc(); early_superio_config_lpc47m15x();
Modified: trunk/src/mainboard/intel/eagleheights/romstage.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/intel/eagleheights/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -138,9 +138,8 @@ } };
- if (bist == 0) { + if (bist == 0) enable_lapic(); - }
/* Setup the console */ i3100_enable_superio();
Modified: trunk/src/mainboard/intel/jarrell/romstage.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/intel/jarrell/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -45,12 +45,6 @@ static const struct mem_controller mch[] = { { .node_id = 0, - /* - .f0 = PCI_DEV(0, 0x00, 0), - .f1 = PCI_DEV(0, 0x00, 1), - .f2 = PCI_DEV(0, 0x00, 2), - .f3 = PCI_DEV(0, 0x00, 3), - */ .channel0 = { DIMM2, DIMM1, DIMM0, 0 }, .channel1 = { DIMM6, DIMM5, DIMM4, 0 }, } @@ -59,9 +53,8 @@ if (bist == 0) { /* Skip this if there was a built in self test failure */ early_mtrr_init(); - if (memory_initialized()) { + if (memory_initialized()) skip_romstage(); - } }
/* Setup the console */ @@ -86,9 +79,8 @@ /* config LPC decode for flash memory access */ device_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); - if (dev == PCI_DEV_INVALID) { + if (dev == PCI_DEV_INVALID) die("Missing ich5?"); - } pci_write_config32(dev, 0xe8, 0x00000000); pci_write_config8(dev, 0xf0, 0x00);
@@ -99,9 +91,8 @@ #if 0 // dump_spd_registers(&cpu[0]); int i; - for(i = 0; i < 1; i++) { + for(i = 0; i < 1; i++) dump_spd_registers(); - } #endif disable_watchdogs(); power_down_reset_check(); @@ -111,8 +102,6 @@ ich5_watchdog_on(); #if 0 dump_pci_devices(); -#endif -#if 0 dump_pci_device(PCI_DEV(0, 0x00, 0)); dump_bar14(PCI_DEV(0, 0x00, 0)); #endif
Modified: trunk/src/mainboard/intel/truxton/romstage.c ============================================================================== --- trunk/src/mainboard/intel/truxton/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/intel/truxton/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -68,9 +68,8 @@ if (bist == 0) { /* Skip this if there was a built in self test failure */ early_mtrr_init(); - if (memory_initialized()) { + if (memory_initialized()) skip_romstage(); - } }
/* Set up the console */
Modified: trunk/src/mainboard/intel/xe7501devkit/romstage.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/intel/xe7501devkit/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -46,15 +46,13 @@ }, };
- if (bist == 0) - { + if (bist == 0) { // Skip this if there was a built in self test failure early_mtrr_init(); enable_lapic(); }
// Get the serial port running and print a welcome banner - lpc47b272_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init();
Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -35,13 +35,13 @@ static void memreset_setup(void) { if (is_cpu_pre_c0()) { - /* Set the memreset low */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); - /* Ensure the BIOS has control of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); + /* Set the memreset low. */ + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); + /* Ensure the BIOS has control of the memory lines. */ + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); } else { - /* Ensure the CPU has controll of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); + /* Ensure the CPU has control of the memory lines. */ + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); } }
@@ -50,14 +50,12 @@ if (is_cpu_pre_c0()) { udelay(800); /* Set memreset_high */ - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); udelay(90); } }
-static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -69,7 +67,7 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" /* tyan does not want the default */ +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> #include "cpu/amd/car/post_cache_as_ram.c" @@ -81,34 +79,28 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - // first node - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, - - // second node - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + // first node + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // second node + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, };
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset; unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* Setup the rom access for 4M */ amd8111_enable_rom(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -143,26 +135,19 @@ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID - { msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } #endif
Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -35,13 +35,13 @@ static void memreset_setup(void) { if (is_cpu_pre_c0()) { - /* Set the memreset low */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); - /* Ensure the BIOS has control of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); + /* Set the memreset low. */ + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); + /* Ensure the BIOS has control of the memory lines. */ + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); } else { - /* Ensure the CPU has controll of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); + /* Ensure the CPU has control of the memory lines. */ + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); } }
@@ -49,15 +49,13 @@ { if (is_cpu_pre_c0()) { udelay(800); - /* Set memreset_high */ - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); + /* Set memreset high. */ + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); udelay(90); } }
-static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -69,7 +67,7 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "lib/generic_sdram.c" -#include "northbridge/amd/amdk8/resourcemap.c" /* tyan does not want the default */ +#include "northbridge/amd/amdk8/resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> #include "cpu/amd/car/post_cache_as_ram.c" @@ -92,23 +90,18 @@
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset; unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* Setup the rom access for 4M */ amd8111_enable_rom(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -143,26 +136,19 @@ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID - { msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } #endif
Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -35,13 +35,13 @@ static void memreset_setup(void) { if (is_cpu_pre_c0()) { - /* Set the memreset low */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); - /* Ensure the BIOS has control of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); + /* Set the memreset low. */ + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); + /* Ensure the BIOS has control of the memory lines. */ + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); } else { - /* Ensure the CPU has controll of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); + /* Ensure the CPU has control of the memory lines. */ + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); } }
@@ -49,15 +49,13 @@ { if (is_cpu_pre_c0()) { udelay(800); - /* Set memreset_high */ - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); + /* Set memreset high. */ + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); udelay(90); } }
-static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -69,7 +67,7 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit.c" #include "lib/generic_sdram.c" -#include "northbridge/amd/amdk8/resourcemap.c" /* tyan does not want the default */ +#include "northbridge/amd/amdk8/resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> #include "cpu/amd/car/post_cache_as_ram.c" @@ -81,34 +79,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { - // first node - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + // first node + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0,
// second node - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, };
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset; unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* Setup the rom access for 4M */ amd8111_enable_rom(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -143,26 +136,19 @@ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID - { msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } #endif
Modified: trunk/src/mainboard/jetway/j7f24/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/j7f24/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/jetway/j7f24/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -53,7 +53,8 @@ { device_t dev;
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev == PCI_DEV_INVALID) die("Southbridge not found!!!\n");
@@ -94,20 +95,15 @@ uart_init(); console_init();
- print_spew("In romstage.c:main()\n"); - enable_smbus(); smbus_fixup(&ctrl);
/* Halt if there was a built-in self test failure. */ report_bist_failure(bist);
- print_debug("Enabling mainboard devices\n"); enable_mainboard_devices();
ddr_ram_setup(&ctrl);
/* ram_check(0, 640 * 1024); */ - - print_spew("Leaving romstage.c:main()\n"); }
Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/jetway/pa78vm5/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -59,9 +59,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, F71863FG_SP1) #endif
-static void activate_spd_rom(const struct mem_controller *ctrl) -{ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static int spd_read_byte(u32 device, u32 address) { @@ -85,8 +83,7 @@ { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); static const u8 spd_addr[] = {RC00, DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; - u32 bsp_apicid = 0; - u32 val; + u32 bsp_apicid = 0, val; msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) { @@ -95,7 +92,6 @@ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - sb700_pci_port80(); }
@@ -175,7 +171,7 @@ rs780_early_setup(); sb700_early_setup();
- #if CONFIG_SET_FIDVID +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
@@ -196,7 +192,7 @@ /* show final fid and vid */ msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); - #endif +#endif
rs780_htinit();
Modified: trunk/src/mainboard/kontron/986lcd-m/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/986lcd-m/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/kontron/986lcd-m/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -328,9 +328,8 @@ u32 reg32; int boot_mode = 0;
- if (bist == 0) { + if (bist == 0) enable_lapic(); - }
/* Force PCIRST# */ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/kontron/kt690/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -48,17 +48,9 @@ #include "southbridge/amd/rs690/rs690_early_setup.c" #include "southbridge/amd/sb600/sb600_early_setup.c"
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -/* called in raminit_f.c */ -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */ static inline int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); @@ -76,9 +68,10 @@ #include "cpu/amd/model_fxx/fidvid.c" #include "northbridge/amd/amdk8/early_ht.c"
+#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) + void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - device_t dev; static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; @@ -90,20 +83,17 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - /* sb600_lpc_port80(); */ sb600_pci_port80(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
enable_rs690_dev8(); sb600_lpc_init();
- dev=PNP_DEV(0x2e, W83627DHG_SP1); - w83627dhg_enable_serial(dev, CONFIG_TTYS0_BASE); + w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init();
#if CONFIG_USBDEBUG @@ -137,8 +127,7 @@ /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ cpuid1 = cpuid(0x80000007); - if( (cpuid1.edx & 0x6) == 0x6 ) { - + if ((cpuid1.edx & 0x6) == 0x6) { /* Read FIDVID_STATUS */ msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); @@ -150,7 +139,6 @@ /* show final fid and vid */ msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); - } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); printk(BIOS_SPEW, "... because cpuid returned %08x\n", cpuid1.edx);
Modified: trunk/src/mainboard/lanner/em8510/romstage.c ============================================================================== --- trunk/src/mainboard/lanner/em8510/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/lanner/em8510/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -77,15 +77,13 @@ print_pci_devices(); #endif
- if(!bios_reset_detected()) { + if (!bios_reset_detected()) { enable_smbus(); #if 1 dump_spd_registers(&memctrl[0]); dump_smbus_registers(); #endif - sdram_initialize(ARRAY_SIZE(memctrl), memctrl); - }
#if 0 @@ -100,4 +98,3 @@ ram_check(0x80000000, 0x81000000); #endif } -
Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/lippert/frontrunner/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -77,6 +77,7 @@ {.channel0 = {DIMM0, DIMM1}} }; unsigned char temp; + SystemPreInit(); msr_init();
Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/msi/ms7135/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -50,15 +50,8 @@
#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl) -{ - /* FIXME: Nothing to do? */ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* FIXME: Nothing to do? */ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -100,22 +93,18 @@ };
int needs_reset; - unsigned bsp_apicid = 0; - + unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; - unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - sio_setup(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - }
w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -138,9 +127,7 @@ #endif
needs_reset |= ht_setup_chains_x(); - needs_reset |= ck804_early_setup_x(); - if (needs_reset) { print_info("ht reset -\n"); soft_reset();
Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/msi/ms7260/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -117,7 +117,6 @@
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset = 0; unsigned bsp_apicid = 0;
@@ -125,10 +124,7 @@ /* Nothing special needs to be done to find bus 0. */ /* Allow the HT devices to be found. */ enumerate_ht_chain(); - sio_setup(); - - /* Setup the MCP55. */ mcp55_enable_rom(); }
@@ -186,11 +182,9 @@ print_debug_hex32(msr.lo); print_debug("\n"); } - enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); - { msr_t msr = rdmsr(0xc0010042); print_debug("end msr fid, vid ");
Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/msi/ms9185/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -52,9 +52,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1) #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC)
-static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl) { @@ -85,7 +83,7 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" /* msi does not want the default */ +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> #include "cpu/amd/car/post_cache_as_ram.c" @@ -116,24 +114,17 @@ if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - bcm5785_enable_rom(); - bcm5785_enable_lpc(); - //enable RTC pc87417_enable_dev(RTC_DEV); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - } - -// post_code(0x32);
- pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + pc87417_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init();
@@ -142,11 +133,11 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist);
- printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); + printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
setup_ms9185_resource_map(); #if 0 - dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif
@@ -166,7 +157,7 @@ #endif
/* it will set up chains and store link pair for optimization later */ - ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
bcm5785_early_setup();
@@ -177,26 +168,19 @@ #endif
#if CONFIG_SET_FIDVID - { msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } - - enable_fid_change(); - - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - + enable_fid_change(); + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); - // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } #endif
Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/msi/ms9282/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -49,9 +49,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void activate_spd_rom(const struct mem_controller *ctrl) { @@ -59,7 +57,7 @@ #define SMBUS_SWITCH2 0x72 unsigned device=(ctrl->channel0[0])>>8; smbus_send_byte(SMBUS_SWITCH1, device); - smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); + smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); }
#if 0 @@ -68,7 +66,7 @@ #define SMBUS_SWITCH1 0x70 #define SMBUS_SWITHC2 0x72 smbus_send_byte(SMBUS_SWITCH1, device & 0x0f); - smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); + smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); } #endif
@@ -82,7 +80,7 @@ #include "northbridge/amd/amdk8/coherent_ht.c" #include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" /* msi does not want the default */ +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/nvidia/mcp55/mcp55_early_setup_ss.h"
@@ -138,12 +136,8 @@ if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - sio_setup(); - - /* Setup the mcp55 */ mcp55_enable_rom(); }
@@ -177,7 +171,6 @@ needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); needs_reset |= mcp55_early_setup_x(); - if (needs_reset) { print_info("ht reset -\n"); soft_reset();
Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -51,10 +51,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -110,31 +107,23 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - - u32 bsp_apicid = 0; - u32 val; + u32 bsp_apicid = 0, val, wants_reset; u8 reg; - u32 wants_reset; msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - sio_setup(); - - /* Setup the mcp55 */ mcp55_enable_rom(); }
post_code(0x30);
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
post_code(0x32);
Modified: trunk/src/mainboard/newisys/khepri/romstage.c ============================================================================== --- trunk/src/mainboard/newisys/khepri/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/newisys/khepri/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -35,14 +35,13 @@ static void memreset_setup(void) { if (is_cpu_pre_c0()) { - /* Set the memreset low */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); - /* Ensure the BIOS has control of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); - } - else { - /* Ensure the CPU has controll of the memory lines */ - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); + /* Set the memreset low. */ + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28); + /* Ensure the BIOS has control of the memory lines. */ + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29); + } else { + /* Ensure the CPU has control of the memory lines. */ + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29); } }
@@ -50,16 +49,13 @@ { if (is_cpu_pre_c0()) { udelay(800); - /* Set memreset_high */ - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); + /* Set memreset high. */ + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28); udelay(90); } }
-static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -69,7 +65,7 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" /* newisys khepri does not want the default */ +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" @@ -79,35 +75,27 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, #endif };
int needs_reset; - unsigned bsp_apicid = 0; - + unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; - unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* Setup the amd8111 */ amd8111_enable_rom(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - } - -// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init();
Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -53,14 +53,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -112,35 +106,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, - // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, };
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset = 0; unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - sio_setup(); - - /* Setup the mcp55 */ mcp55_enable_rom(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
pnp_enter_ext_func_mode(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x24, 0); @@ -183,28 +171,22 @@ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID - { msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } #endif + init_timer(); /* Need to use TMICT to synconize FID/VID. */
needs_reset |= optimize_link_coherent_ht();
Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/pcengines/alix1c/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -36,9 +36,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
/* The ALIX1.C has no SMBus; the setup is hard-wired. */ -static void cs5536_enable_smbus(void) -{ -} +static void cs5536_enable_smbus(void) { }
#include "southbridge/amd/cs5536/cs5536_early_setup.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" @@ -114,11 +112,6 @@ #include "cpu/amd/model_lx/syspreinit.c" #include "cpu/amd/model_lx/msrinit.c"
-/** Early mainboard specific GPIO setup. */ -static void mb_gpio_init(void) -{ -} - void main(unsigned long bist) { static const struct mem_controller memctrl[] = { @@ -137,7 +130,6 @@ */ cs5536_disable_internal_uart(); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - mb_gpio_init(); uart_init(); console_init();
Modified: trunk/src/mainboard/pcengines/alix2d/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix2d/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/pcengines/alix2d/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -36,9 +36,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
/* The ALIX.2D has no SMBus; the setup is hard-wired. */ -static void cs5536_enable_smbus(void) -{ -} +static void cs5536_enable_smbus(void) { }
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
@@ -128,13 +126,13 @@ * Ugly workaround: $ wrmsr 0x5140000C 0xf00100006100 * This resets the GPIO I/O space to 0x6100. * This may break other things, though. - */ + */ outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE); outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_ENABLE);
/* outl(1 << 6, GPIO_IO_BASE + GPIOL_OUTPUT_VALUE); */ /* Led 1 enabled */ - outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 2 disabled */ + outl(1 << 9, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 2 disabled */ outl(1 << 11, GPIO_IO_BASE + GPIOH_OUTPUT_VALUE); /* Led 3 disabled */ }
Modified: trunk/src/mainboard/rca/rm4100/romstage.c ============================================================================== --- trunk/src/mainboard/rca/rm4100/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/rca/rm4100/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -99,9 +99,8 @@ void main(unsigned long bist) { if (bist == 0) { - if (memory_initialized()) { + if (memory_initialized()) hard_reset(); - } }
/* Set southbridge and superio gpios */
Modified: trunk/src/mainboard/roda/rk886ex/romstage.c ============================================================================== --- trunk/src/mainboard/roda/rk886ex/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/roda/rk886ex/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -250,9 +250,8 @@ u32 reg32; int boot_mode = 0;
- if (bist == 0) { + if (bist == 0) enable_lapic(); - }
/* Force PCIRST# */ pci_write_config16(PCI_DEV(0, 0x1e, 0), BCTRL, SBR);
Modified: trunk/src/mainboard/sunw/ultra40/romstage.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/sunw/ultra40/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -28,9 +28,7 @@ #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT) #define SUPERIO_GPIO_IO_BASE 0x400
-static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { }
#ifdef ENABLE_ONBOARD_SCSI static void sio_gpio_setup(void) @@ -44,10 +42,7 @@ } #endif
-static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static inline void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -57,7 +52,7 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" /* tyan does not want the default */ +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
@@ -101,32 +96,27 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, - // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, };
int needs_reset; - unsigned bsp_apicid = 0; - + unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; - unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - sio_setup(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - }
lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -147,9 +137,7 @@ #endif
needs_reset |= ht_setup_chains_x(); - needs_reset |= ck804_early_setup_x(); - if (needs_reset) { print_info("ht reset -\n"); soft_reset();
Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -49,9 +49,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { }
static inline void dump_smbus_registers(void) { @@ -183,25 +181,19 @@
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset = 0; unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - sio_setup(); - - /* Setup the mcp55 */ mcp55_enable_rom(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
pnp_enter_ext_func_mode(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); @@ -243,7 +235,6 @@ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID - { msr_t msr; msr = rdmsr(0xc0010042); @@ -251,15 +242,10 @@ print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); print_debug("\n"); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid { msr_t msr; @@ -268,7 +254,6 @@ print_debug_hex32(msr.hi); print_debug_hex32(msr.lo); print_debug("\n"); - } #endif
Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -52,14 +52,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -85,6 +79,7 @@ { uint32_t dword; uint8_t byte; + enable_smbus(); // smbusx_write_byte(1, (0x58>>1), 0, 0x80); /* select bank0 */ smbusx_write_byte(1, (0x58>>1), 0xb1, 0xff); /* set FAN ctrl to DC mode */ @@ -105,35 +100,29 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, - // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, };
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset = 0; unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - sio_setup(); - - /* Setup the mcp55 */ mcp55_enable_rom(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
pnp_enter_ext_func_mode(SERIAL_DEV); pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6)); @@ -177,13 +166,9 @@ msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x, %08x\n", msr.hi, msr.lo); } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid { msr_t msr;
Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -51,10 +51,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -111,30 +108,22 @@ { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - - u32 bsp_apicid = 0; - u32 val; - u32 wants_reset; + u32 bsp_apicid = 0, val, wants_reset; msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - sio_setup(); - - /* Setup the mcp55 */ mcp55_enable_rom(); }
post_code(0x30);
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
post_code(0x32);
Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -117,6 +117,7 @@ #define GPIO1_DEV PNP_DEV(0x2e, W83627HF_GAME_MIDI_GPIO1) #define GPIO2_DEV PNP_DEV(0x2e, W83627HF_GPIO2) #define GPIO3_DEV PNP_DEV(0x2e, W83627HF_GPIO3) + static void write_GPIO(void) { pnp_enter_ext_func_mode(GPIO1_DEV); @@ -156,31 +157,24 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - - u32 bsp_apicid = 0; - u32 val; - u32 wants_reset; + struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + u32 bsp_apicid = 0, val, wants_reset; msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - sio_setup(); - - /* Setup the mcp55 */ mcp55_enable_rom(); }
post_code(0x30);
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
post_code(0x32);
Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -60,9 +60,8 @@ if (bist == 0) { /* Skip this if there was a built in self test failure */ early_mtrr_init(); - if (memory_initialized()) { + if (memory_initialized()) skip_romstage(); - } }
/* Setup the console */ @@ -77,16 +76,13 @@ /* config LPC decode for flash memory access */ device_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); - if (dev == PCI_DEV_INVALID) { + if (dev == PCI_DEV_INVALID) die("Missing 6300ESB?"); - } pci_write_config32(dev, 0xe8, 0x00000000); pci_write_config8(dev, 0xf0, 0x00);
#if 0 display_cpuid_update_microcode(); -#endif -#if 0 print_pci_devices(); #endif #if 1 @@ -94,9 +90,8 @@ #endif #if 0 int i; - for(i = 0; i < 1; i++) { + for(i = 0; i < 1; i++) dump_spd_registers(); - } #endif disable_watchdogs(); sdram_initialize(ARRAY_SIZE(mch), mch);
Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -49,12 +49,6 @@ static const struct mem_controller mch[] = { { .node_id = 0, - /* - .f0 = PCI_DEV(0, 0x00, 0), - .f1 = PCI_DEV(0, 0x00, 1), - .f2 = PCI_DEV(0, 0x00, 2), - .f3 = PCI_DEV(0, 0x00, 3), - */ .channel0 = {DIMM0, DIMM1, DIMM2, DIMM3, }, .channel1 = {DIMM4, DIMM5, DIMM6, DIMM7, }, } @@ -63,9 +57,8 @@ if (bist == 0) { /* Skip this if there was a built in self test failure */ early_mtrr_init(); - if (memory_initialized()) { + if (memory_initialized()) skip_romstage(); - } }
/* Setup the console */ @@ -83,16 +76,13 @@ /* config LPC decode for flash memory access */ device_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); - if (dev == PCI_DEV_INVALID) { + if (dev == PCI_DEV_INVALID) die("Missing esb6300?"); - } pci_write_config32(dev, 0xe8, 0x00000000); pci_write_config8(dev, 0xf0, 0x00);
#if 0 display_cpuid_update_microcode(); -#endif -#if 0 print_pci_devices(); #endif #if 1 @@ -101,9 +91,8 @@ #if 0 // dump_spd_registers(&cpu[0]); int i; - for(i = 0; i < 1; i++) { + for(i = 0; i < 1; i++) dump_spd_registers(); - } #endif disable_watchdogs(); // dump_ipmi_registers(); @@ -111,8 +100,6 @@ sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); -#endif -#if 0 dump_pci_device(PCI_DEV(0, 0x00, 0)); dump_bar14(PCI_DEV(0, 0x00, 0)); #endif
Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -47,13 +47,7 @@ static const struct mem_controller mch[] = { { .node_id = 0, - /* - .f0 = PCI_DEV(0, 0x00, 0), - .f1 = PCI_DEV(0, 0x00, 1), - .f2 = PCI_DEV(0, 0x00, 2), - .f3 = PCI_DEV(0, 0x00, 3), - */ - .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, }, + .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, }, .channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, }, } }; @@ -61,9 +55,8 @@ if (bist == 0) { /* Skip this if there was a built in self test failure */ early_mtrr_init(); - if (memory_initialized()) { + if (memory_initialized()) skip_romstage(); - } }
/* Setup the console */ @@ -81,16 +74,13 @@ /* config LPC decode for flash memory access */ device_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x25a1), 0); - if (dev == PCI_DEV_INVALID) { + if (dev == PCI_DEV_INVALID) die("Missing ich5r?"); - } pci_write_config32(dev, 0xe8, 0x00000000); pci_write_config8(dev, 0xf0, 0x00);
#if 0 display_cpuid_update_microcode(); -#endif -#if 0 print_pci_devices(); #endif #if 1 @@ -99,9 +89,8 @@ #if 0 // dump_spd_registers(&cpu[0]); int i; - for(i = 0; i < 1; i++) { + for(i = 0; i < 1; i++) dump_spd_registers(); - } #endif disable_watchdogs(); // dump_ipmi_registers();
Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -62,9 +62,8 @@ if (bist == 0) { /* Skip this if there was a built in self test failure */ early_mtrr_init(); - if (memory_initialized()) { + if (memory_initialized()) skip_romstage(); - } }
/* Setup the console */ @@ -82,16 +81,13 @@ /* config LPC decode for flash memory access */ device_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); - if (dev == PCI_DEV_INVALID) { + if (dev == PCI_DEV_INVALID) die("Missing ich5?"); - } pci_write_config32(dev, 0xe8, 0x00000000); pci_write_config8(dev, 0xf0, 0x00);
#if 0 display_cpuid_update_microcode(); -#endif -#if 0 print_pci_devices(); #endif #if 1 @@ -100,9 +96,8 @@ #if 0 // dump_spd_registers(&cpu[0]); int i; - for(i = 0; i < 1; i++) { + for(i = 0; i < 1; i++) dump_spd_registers(); - } #endif disable_watchdogs(); // dump_ipmi_registers();
Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -48,12 +48,6 @@ static const struct mem_controller mch[] = { { .node_id = 0, - /* - .f0 = PCI_DEV(0, 0x00, 0), - .f1 = PCI_DEV(0, 0x00, 1), - .f2 = PCI_DEV(0, 0x00, 2), - .f3 = PCI_DEV(0, 0x00, 3), - */ .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, }, .channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, }, } @@ -62,9 +56,8 @@ if (bist == 0) { /* Skip this if there was a built in self test failure */ early_mtrr_init(); - if (memory_initialized()) { + if (memory_initialized()) skip_romstage(); - } }
/* Setup the console */ @@ -82,16 +75,13 @@ /* config LPC decode for flash memory access */ device_t dev; dev = pci_locate_device(PCI_ID(0x8086, 0x24d0), 0); - if (dev == PCI_DEV_INVALID) { + if (dev == PCI_DEV_INVALID) die("Missing ich5?"); - } pci_write_config32(dev, 0xe8, 0x00000000); pci_write_config8(dev, 0xf0, 0x00);
#if 0 display_cpuid_update_microcode(); -#endif -#if 0 print_pci_devices(); #endif #if 1 @@ -100,9 +90,8 @@ #if 0 // dump_spd_registers(&cpu[0]); int i; - for(i = 0; i < 1; i++) { + for(i = 0; i < 1; i++) dump_spd_registers(); - } #endif disable_watchdogs(); // dump_ipmi_registers(); @@ -110,8 +99,6 @@ sdram_initialize(ARRAY_SIZE(mch), mch); #if 0 dump_pci_devices(); -#endif -#if 0 dump_pci_device(PCI_DEV(0, 0x00, 0)); dump_bar14(PCI_DEV(0, 0x00, 0)); #endif
Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -47,17 +47,9 @@ #include "southbridge/amd/rs690/rs690_early_setup.c" #include "southbridge/amd/sb600/sb600_early_setup.c"
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -/* called in raminit_f.c */ -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */ static inline int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); @@ -90,7 +82,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - /* sb600_lpc_port80(); */ sb600_pci_port80(); } @@ -98,9 +89,8 @@ technexion_post_code_init(); technexion_post_code(LED_MESSAGE_START);
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
enable_rs690_dev8(); sb600_lpc_init(); @@ -141,8 +131,7 @@ /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ cpuid1 = cpuid(0x80000007); - if( (cpuid1.edx & 0x6) == 0x6 ) { - + if ((cpuid1.edx & 0x6) == 0x6) { /* Read FIDVID_STATUS */ msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); @@ -154,7 +143,6 @@ /* show final fid and vid */ msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); - } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); }
Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -47,17 +47,9 @@ #include "southbridge/amd/rs690/rs690_early_setup.c" #include "southbridge/amd/sb600/sb600_early_setup.c"
-/* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -/* called in raminit_f.c */ -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
-/*called in raminit_f.c */ static inline int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); @@ -88,14 +80,12 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - /* sb600_lpc_port80(); */ sb600_pci_port80(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
enable_rs690_dev8(); sb600_lpc_init(); @@ -136,8 +126,7 @@ /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ cpuid1 = cpuid(0x80000007); - if( (cpuid1.edx & 0x6) == 0x6 ) { - + if ((cpuid1.edx & 0x6) == 0x6 ) { /* Read FIDVID_STATUS */ msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); @@ -149,7 +138,6 @@ /* show final fid and vid */ msr=rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); - } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); }
Modified: trunk/src/mainboard/televideo/tc7020/romstage.c ============================================================================== --- trunk/src/mainboard/televideo/tc7020/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/televideo/tc7020/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -35,20 +35,11 @@
static void main(unsigned long bist) { - /* Initialize the serial console. */ pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - - /* Halt if there was a built in self test failure. */ report_bist_failure(bist); - cs5530_enable_rom(); - - /* Initialize RAM. */ sdram_init(); - - /* Check whether RAM works. */ /* ram_check(0, 640 * 1024); */ } -
Modified: trunk/src/mainboard/thomson/ip1000/romstage.c ============================================================================== --- trunk/src/mainboard/thomson/ip1000/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/thomson/ip1000/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -98,9 +98,8 @@ void main(unsigned long bist) { if (bist == 0) { - if (memory_initialized()) { + if (memory_initialized()) hard_reset(); - } }
/* Set southbridge and superio gpios */
Modified: trunk/src/mainboard/traverse/geos/romstage.c ============================================================================== --- trunk/src/mainboard/traverse/geos/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/traverse/geos/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -52,11 +52,6 @@ #include "cpu/amd/model_lx/syspreinit.c" #include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void) -{ - /* Early mainboard specific GPIO setup. */ -} - void main(unsigned long bist) { post_code(0x01); @@ -78,7 +73,6 @@ */ /* If debug. real setup done in chipset init via devicetree.cb. */ cs5536_setup_onchipuart(1); - mb_gpio_init(); uart_init(); console_init();
Modified: trunk/src/mainboard/tyan/s2735/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2735/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/tyan/s2735/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -46,9 +46,8 @@ }, };
- if (bist == 0) { + if (bist == 0) enable_lapic(); - }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -57,15 +56,12 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist);
- if(bios_reset_detected()) { + if (bios_reset_detected()) hard_reset(); - }
enable_smbus(); #if 0 dump_spd_registers(&memctrl[0]); -#endif -#if 0 dump_smbus_registers(); #endif
@@ -79,4 +75,3 @@ dump_pci_device(PCI_DEV(0, 0, 0)); #endif } -
Modified: trunk/src/mainboard/tyan/s2850/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2850/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/tyan/s2850/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -29,28 +29,23 @@
static void memreset_setup(void) { - if (is_cpu_pre_c0()) { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 - } - else { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 - } - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + if (is_cpu_pre_c0()) + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 + else + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
static void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { udelay(800); - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 udelay(90); } }
-static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -86,16 +81,12 @@ if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* Setup the amd8111 */ amd8111_enable_rom(); }
- if (bist == 0) { + if (bist == 0) init_cpus(cpu_init_detectedx); - }
// post_code(0x32);
@@ -128,4 +119,3 @@
post_cache_as_ram(); } -
Modified: trunk/src/mainboard/tyan/s2875/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2875/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/tyan/s2875/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -29,28 +29,23 @@
static void memreset_setup(void) { - if (is_cpu_pre_c0()) { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 - } - else { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 - } - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + if (is_cpu_pre_c0()) + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 + else + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
static void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { udelay(800); - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 udelay(90); } }
-static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -97,15 +92,12 @@ if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - amd8111_enable_rom(); }
- if (bist == 0) { + if (bist == 0) init_cpus(cpu_init_detectedx); - }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -135,6 +127,4 @@ sdram_initialize(ARRAY_SIZE(cpu), cpu);
post_cache_as_ram(); - } -
Modified: trunk/src/mainboard/tyan/s2880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2880/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/tyan/s2880/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -29,28 +29,23 @@
static void memreset_setup(void) { - if (is_cpu_pre_c0()) { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 - } - else { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 - } - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + if (is_cpu_pre_c0()) + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 + else + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
static void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { udelay(800); - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 udelay(90); } }
-static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -97,16 +92,12 @@ if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - amd8111_enable_rom(); }
- if (bist == 0) { + if (bist == 0) init_cpus(cpu_init_detectedx); - } -
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -138,4 +129,3 @@
post_cache_as_ram(); } -
Modified: trunk/src/mainboard/tyan/s2881/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2881/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/tyan/s2881/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -28,28 +28,23 @@
static void memreset_setup(void) { - if (is_cpu_pre_c0()) { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 - } - else { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 - } - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + if (is_cpu_pre_c0()) + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 + else + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
static void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { udelay(800); - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 udelay(90); } }
-static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -69,33 +64,27 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, #endif };
int needs_reset; - unsigned bsp_apicid = 0; - + unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; - unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* Setup the amd8111 */ amd8111_enable_rom(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - }
// post_code(0x32);
@@ -131,8 +120,6 @@ enable_smbus(); #if 0 dump_spd_registers(&cpu[0]); -#endif -#if 0 dump_smbus_registers(); #endif
@@ -151,4 +138,3 @@
post_cache_as_ram(); } -
Modified: trunk/src/mainboard/tyan/s2882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2882/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/tyan/s2882/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -29,28 +29,23 @@
static void memreset_setup(void) { - if (is_cpu_pre_c0()) { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 - } - else { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 - } - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + if (is_cpu_pre_c0()) + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 + else + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
static void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { udelay(800); - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 udelay(90); } }
-static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -97,15 +92,12 @@ if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - amd8111_enable_rom(); }
- if (bist == 0) { + if (bist == 0) init_cpus(cpu_init_detectedx); - }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init();
Modified: trunk/src/mainboard/tyan/s2885/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2885/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/tyan/s2885/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -28,28 +28,23 @@
static void memreset_setup(void) { - if (is_cpu_pre_c0()) { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 - } - else { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 - } - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + if (is_cpu_pre_c0()) + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 + else + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
static void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { udelay(800); - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 udelay(90); } }
-static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -59,7 +54,7 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" /* tyan does not want the default */ +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" @@ -78,26 +73,18 @@ };
int needs_reset; - unsigned bsp_apicid = 0; - + unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; - unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - - /* Setup the amd8111 */ amd8111_enable_rom(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - } - -// post_code(0x32);
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init();
Modified: trunk/src/mainboard/tyan/s2891/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2891/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/tyan/s2891/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -25,18 +25,9 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void memreset_setup(void) -{ -} - -static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void memreset_setup(void) { } +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -46,7 +37,7 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" /* tyan does not want the default */ +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h" #include "southbridge/nvidia/ck804/ck804_early_setup.c" @@ -92,23 +83,18 @@ };
int needs_reset; - unsigned bsp_apicid = 0; - + unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; - unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - sio_setup(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - }
// post_code(0x32);
@@ -135,9 +121,7 @@ #endif
needs_reset |= ht_setup_chains_x(); - needs_reset |= ck804_early_setup_x(); - if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); soft_reset(); @@ -152,8 +136,6 @@ enable_smbus(); #if 0 dump_spd_registers(&cpu[0]); -#endif -#if 0 dump_smbus_registers(); #endif
@@ -162,12 +144,8 @@
#if 0 print_pci_devices(); -#endif - -#if 0 dump_pci_devices(); #endif
post_cache_as_ram(); } -
Modified: trunk/src/mainboard/tyan/s2892/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2892/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/tyan/s2892/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -25,14 +25,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -42,7 +36,7 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" /* tyan does not want the default */ +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
@@ -84,23 +78,18 @@ };
int needs_reset; - unsigned bsp_apicid = 0; - + unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; - unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - sio_setup(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - }
// post_code(0x32);
@@ -123,9 +112,7 @@ #endif
needs_reset |= ht_setup_chains_x(); - needs_reset |= ck804_early_setup_x(); - if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); soft_reset(); @@ -143,4 +130,3 @@
post_cache_as_ram(); } -
Modified: trunk/src/mainboard/tyan/s2895/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/tyan/s2895/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -19,38 +19,31 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/smsc/lpc47b397/lpc47b397_early_serial.c" #include "superio/smsc/lpc47b397/lpc47b397_early_gpio.c" -#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT) -#define SUPERIO_GPIO_IO_BASE 0x400 #include "cpu/x86/bist.h" #include "northbridge/amd/amdk8/debug.c" #include <cpu/amd/mtrr.h> #include "cpu/x86/mtrr/earlymtrr.c" #include "northbridge/amd/amdk8/setup_resource_map.c" -#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1)
-static void memreset_setup(void) -{ -} +#define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1) +#define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT) +#define SUPERIO_GPIO_IO_BASE 0x400
-static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} +static void memreset_setup(void) { } +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static void sio_gpio_setup(void) { unsigned value;
/*Enable onboard scsi*/ - lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L + lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x2c, + (1<<7)|(0<<2)|(0<<1)|(0<<0)); // GP21, offset 0x2c, DISABLE_SCSI_L value = lpc47b397_gpio_offset_in(SUPERIO_GPIO_IO_BASE, 0x4c); lpc47b397_gpio_offset_out(SUPERIO_GPIO_IO_BASE, 0x4c, (value|(1<<1))); }
-static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} - static inline int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); @@ -59,7 +52,7 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" /* tyan does not want the default */ +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include "southbridge/nvidia/ck804/ck804_early_setup_ss.h"
@@ -113,23 +106,18 @@ };
int needs_reset; - unsigned bsp_apicid = 0; - + unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; - unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - sio_setup(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - }
lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -151,9 +139,7 @@ wait_all_other_cores_started(bsp_apicid);
needs_reset |= ht_setup_chains_x(); - needs_reset |= ck804_early_setup_x(); - if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); soft_reset(); @@ -172,4 +158,3 @@
post_cache_as_ram(); } -
Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/tyan/s2912/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -53,14 +53,8 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void memreset(int controllers, const struct mem_controller *ctrl) -{ -} - -static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void memreset(int controllers, const struct mem_controller *ctrl) { } +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -113,40 +107,32 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { - // Node 0 - DIMM0, DIMM2, 0, 0, - DIMM1, DIMM3, 0, 0, - // Node 1 - DIMM4, DIMM6, 0, 0, - DIMM5, DIMM7, 0, 0, + // Node 0 + DIMM0, DIMM2, 0, 0, + DIMM1, DIMM3, 0, 0, + // Node 1 + DIMM4, DIMM6, 0, 0, + DIMM5, DIMM7, 0, 0, };
struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); - int needs_reset = 0; unsigned bsp_apicid = 0;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - sio_setup(); - - /* Setup the mcp55 */ mcp55_enable_rom(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - setup_mb_resource_map(); - uart_init();
/* Halt if there was a built in self test failure */ @@ -181,26 +167,19 @@ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
#if CONFIG_SET_FIDVID - { msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } - enable_fid_change(); - enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); - init_fidvid_bsp(bsp_apicid); - // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); - } #endif
Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -52,10 +52,7 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static inline void activate_spd_rom(const struct mem_controller *ctrl) -{ - /* nothing to do */ -} +static void activate_spd_rom(const struct mem_controller *ctrl) { }
static inline int spd_read_byte(unsigned device, unsigned address) { @@ -117,29 +114,22 @@ { struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
- u32 bsp_apicid = 0; - u32 val; - u32 wants_reset; + u32 bsp_apicid = 0, val, wants_reset; msr_t msr;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - sio_setup(); - - /* Setup the mcp55 */ mcp55_enable_rom(); }
post_code(0x30);
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - }
post_code(0x32);
@@ -256,4 +246,3 @@ post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } -
Modified: trunk/src/mainboard/tyan/s4880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/tyan/s4880/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -28,23 +28,22 @@
static void memreset_setup(void) { - if (is_cpu_pre_c0()) { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 - } - else { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 - } - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + if (is_cpu_pre_c0()) + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 + else + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
static void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { udelay(800); - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 udelay(90); } } + static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 @@ -52,6 +51,7 @@ smbus_write_byte(SMBUS_HUB, 0x01, device); smbus_write_byte(SMBUS_HUB, 0x03, 0); } + #if 0 static inline void change_i2c_mux(unsigned device) { @@ -73,7 +73,7 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" /* tyan does not want the default */ +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> #include "cpu/amd/car/post_cache_as_ram.c" @@ -110,7 +110,6 @@
}, #endif - #if CONFIG_MAX_PHYSICAL_CPUS > 2 { .node_id = 2, @@ -140,15 +139,12 @@ if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - amd8111_enable_rom(); }
- if (bist == 0) { + if (bist == 0) init_cpus(cpu_init_detectedx); - }
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init();
Modified: trunk/src/mainboard/tyan/s4882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4882/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/tyan/s4882/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -27,23 +27,22 @@
static void memreset_setup(void) { - if (is_cpu_pre_c0()) { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 - } - else { - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 - } - outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); + if (is_cpu_pre_c0()) + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=0 + else + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 16); //REVC_MEMRST_EN=1 + outb((1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); }
static void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { udelay(800); - outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 + outb((1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 17); //REVB_MEMRST_L=1 udelay(90); } } + static inline void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 @@ -57,6 +56,7 @@
smbus_write_byte(SMBUS_HUB, 0x03, 0); } + #if 0 static inline void change_i2c_mux(unsigned device) { @@ -81,7 +81,7 @@ #include "northbridge/amd/amdk8/raminit.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" -#include "resourcemap.c" /* tyan does not want the default */ +#include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> #include "cpu/amd/car/post_cache_as_ram.c" @@ -112,24 +112,18 @@ };
int needs_reset; - unsigned bsp_apicid = 0; - + unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; - unsigned nodes;
if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ - enumerate_ht_chain(); - amd8111_enable_rom(); }
- if (bist == 0) { + if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); - } -
w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); @@ -169,6 +163,4 @@ sdram_initialize(nodes, ctrl);
post_cache_as_ram(); - } -
Modified: trunk/src/mainboard/via/epia-cn/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-cn/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/via/epia-cn/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -47,7 +47,8 @@ { device_t dev;
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev == PCI_DEV_INVALID) die("Southbridge not found!!!\n");
@@ -87,21 +88,10 @@ enable_vt8235_serial(); uart_init(); console_init(); - - print_spew("In romstage.c:main()\n"); - enable_smbus(); smbus_fixup(&ctrl); - - /* Halt if there was a built-in self test failure. */ report_bist_failure(bist); - - print_debug("Enabling mainboard devices\n"); enable_mainboard_devices(); - ddr_ram_setup(&ctrl); - /* ram_check(0, 640 * 1024); */ - - print_spew("Leaving romstage.c:main()\n"); }
Modified: trunk/src/mainboard/via/epia-m/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/via/epia-m/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -30,7 +30,7 @@ device_t dev;
dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_8235), 0); + PCI_DEVICE_ID_VIA_8235), 0);
if (dev == PCI_DEV_INVALID) { die("Southbridge not found!!!\n"); @@ -72,9 +72,7 @@ { device_t dev;
- /* - * Enable VGA; 32MB buffer. - */ + /* Enable VGA; 32MB buffer. */ pci_write_config8(0, 0xe1, 0xdd);
/* @@ -83,9 +81,8 @@ */ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_6305), 0); - if (dev != PCI_DEV_INVALID) { + if (dev != PCI_DEV_INVALID) pci_write_config8(dev, 0x15, 0x1c); - }
enable_vt8235_serial(); uart_init(); @@ -122,12 +119,8 @@ } #endif
- if (bist == 0) { - print_debug(" Doing MTRR init.\n"); + if (bist == 0) early_mtrr_init(); - }
//dump_pci_devices(); - - print_spew("Leaving romstage.c:main()\n"); }
Modified: trunk/src/mainboard/via/epia-m700/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m700/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/via/epia-m700/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -448,17 +448,6 @@ /* This fix does help vx800!, but vx855 doesn't need this. */ /* smbus_fixup(&ctrl); */
- if (bist == 0) { - /* - * CAR needs MTRR until memory is ok, so disable this - * early_mtrr_init() call. - */ -#if 0 - print_debug("doing early_mtrr\n"); - early_mtrr_init(); -#endif - } - /* Halt if there was a built-in self test failure. */ report_bist_failure(bist);
Modified: trunk/src/mainboard/via/epia-n/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-n/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/via/epia-n/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -62,7 +62,8 @@ device_t dev; u8 reg;
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); if (dev == PCI_DEV_INVALID) die("Southbridge not found!!!\n");
@@ -110,14 +111,10 @@ pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
w83697hf_set_clksel_48(SERIAL_DEV); - w83697hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - uart_init(); console_init();
- print_spew("In romstage.c:main()\n"); - enable_smbus(); smbus_fixup(&ctrl);
@@ -130,18 +127,13 @@ print_debug("Enable F-ROM Shadow RAM\n"); enable_shadow_ram();
- /* setup cpu */ print_debug("Setup CPU Interface\n"); c3_cpu_setup(ctrl.d0f2);
ddr_ram_setup();
- if (bist == 0) { - print_debug("doing early_mtrr\n"); + if (bist == 0) early_mtrr_init(); - }
//ram_check(0, 640 * 1024); - - print_spew("Leaving romstage.c:main()\n"); }
Modified: trunk/src/mainboard/via/epia/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/via/epia/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -31,9 +31,8 @@
dev = pci_locate_device(PCI_ID(0x1106,0x8231), 0);
- if (dev == PCI_DEV_INVALID) { + if (dev == PCI_DEV_INVALID) die("Southbridge not found!!!\n"); - }
pci_write_config8(dev, 0x50, 7); pci_write_config8(dev, 0x51, 0xff); @@ -74,9 +73,9 @@
static void main(unsigned long bist) { - if (bist == 0) { + if (bist == 0) early_mtrr_init(); - } + enable_vt8231_serial(); uart_init(); console_init();
Modified: trunk/src/mainboard/via/pc2500e/romstage.c ============================================================================== --- trunk/src/mainboard/via/pc2500e/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/via/pc2500e/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -63,14 +63,9 @@ it8716f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); - enable_smbus(); smbus_fixup(&ctrl); - - /* Halt if there was a built-in self test failure. */ report_bist_failure(bist); - ddr_ram_setup(&ctrl); - /* ram_check(0, 640 * 1024); */ }
Modified: trunk/src/mainboard/winent/pl6064/romstage.c ============================================================================== --- trunk/src/mainboard/winent/pl6064/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/winent/pl6064/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -56,11 +56,6 @@ #include "cpu/amd/model_lx/syspreinit.c" #include "cpu/amd/model_lx/msrinit.c"
-static void mb_gpio_init(void) -{ - /* Early mainboard specific GPIO setup. */ -} - void main(unsigned long bist) { post_code(0x01); @@ -79,7 +74,6 @@ */ w83627hf_set_clksel_48(SERIAL_DEV); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - mb_gpio_init(); uart_init(); console_init();
Modified: trunk/src/mainboard/wyse/s50/romstage.c ============================================================================== --- trunk/src/mainboard/wyse/s50/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/mainboard/wyse/s50/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -81,5 +81,4 @@
/* Check all of memory */ /*ram_check(0x00000000, 640*1024);*/ - print_err("ram check done\n"); }
Modified: trunk/src/northbridge/via/vx800/examples/romstage.c ============================================================================== --- trunk/src/northbridge/via/vx800/examples/romstage.c Sun Nov 21 18:29:59 2010 (r6107) +++ trunk/src/northbridge/via/vx800/examples/romstage.c Sun Nov 21 23:47:22 2010 (r6108) @@ -81,9 +81,7 @@
print_debug("In enable_mainboard_devices \n");
- /* - Enable P2P Bridge Header for External PCI BUS. - */ + /* Enable P2P bridge Header for external PCI bus. */ dev = pci_locate_device(PCI_ID(0x1106, 0xa353), 0); pci_write_config8(dev, 0x4f, 0x41); } @@ -91,6 +89,7 @@ static void enable_shadow_ram(void) { uint8_t shadowreg; + pci_write_config8(PCI_DEV(0, 0, 3), 0x80, 0xff); /* 0xf0000-0xfffff - ACPI tables */ shadowreg = pci_read_config8(PCI_DEV(0, 0, 3), 0x83);
-
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