coreboot November 2010

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[PATCH]Make smp_write_bus private
by Patrick Georgi 22 Nov '10

22 Nov '10

Hi, with r6114, no board in trunk uses smp_write_bus directly anymore. Instead, mptable_write_buses looks up all buses in the device tree and adds them to the table accordingly. I propose to hide smp_write_bus, so no new board can reintroduce such code. == Make smp_write_bus static (local scope), to prevent new boards from using it directly again. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de

2 1

[commit] r6114 - in trunk/src/mainboard: amd/serengeti_cheetah amd/serengeti_cheetah_fam10 asus/a8n_e asus/a8v-e_deluxe asus/a8v-e_se intel/eagleheights intel/jarrell intel/mtarvon intel/truxton in...
by repository service 22 Nov '10

22 Nov '10

Author: oxygene Date: Mon Nov 22 15:14:56 2010 New Revision: 6114 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6114 Log: Final set of smp_write_bus -> mptable_write_buses changes. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c trunk/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h trunk/src/mainboard/amd/serengeti_cheetah/mptable.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h trunk/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c trunk/src/mainboard/asus/a8n_e/get_bus_conf.c trunk/src/mainboard/asus/a8n_e/mptable.c trunk/src/mainboard/asus/a8v-e_deluxe/mptable.c trunk/src/mainboard/asus/a8v-e_se/mptable.c trunk/src/mainboard/intel/eagleheights/mptable.c trunk/src/mainboard/intel/jarrell/mptable.c trunk/src/mainboard/intel/mtarvon/mptable.c trunk/src/mainboard/intel/truxton/mptable.c trunk/src/mainboard/intel/xe7501devkit/bus.h trunk/src/mainboard/intel/xe7501devkit/mptable.c trunk/src/mainboard/supermicro/h8dme/get_bus_conf.c trunk/src/mainboard/supermicro/h8dme/mptable.c trunk/src/mainboard/supermicro/h8dmr/get_bus_conf.c trunk/src/mainboard/supermicro/h8dmr/mptable.c trunk/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c trunk/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h trunk/src/mainboard/supermicro/h8dmr_fam10/mptable.c trunk/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c trunk/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c trunk/src/mainboard/supermicro/x6dai_g/mptable.c trunk/src/mainboard/supermicro/x6dhe_g/mptable.c trunk/src/mainboard/supermicro/x6dhe_g2/mptable.c trunk/src/mainboard/supermicro/x6dhr_ig/mptable.c trunk/src/mainboard/supermicro/x6dhr_ig2/mptable.c Modified: trunk/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/amd/serengeti_cheetah/get_bus_conf.c Mon Nov 22 15:14:56 2010 (r6114) @@ -109,11 +109,6 @@ dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0)); if (dev) { m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if CONFIG_HT_CHAIN_END_UNITID_BASE >= CONFIG_HT_CHAIN_UNITID_BASE - m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - m->bus_isa++; -// printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa); -#endif } else { printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8111_0, sysconf.sbdn); @@ -132,11 +127,6 @@ dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0)); if (dev) { m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); -#if CONFIG_HT_CHAIN_END_UNITID_BASE < CONFIG_HT_CHAIN_UNITID_BASE - m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - m->bus_isa++; -// printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa); -#endif } else { printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1); @@ -172,9 +162,6 @@ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1,0)); if (dev) { m->bus_8132a[j][2] = pci_read_config8(dev, PCI_SECONDARY_BUS); - m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - m->bus_isa++; - // printk(BIOS_DEBUG, "bus_isa=%d\n",bus_isa); } else { printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]+1); @@ -192,8 +179,6 @@ if (dev) { m->bus_8151[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS); // printk(BIOS_DEBUG, "bus_8151_1=%d\n",bus_8151[j][1]); - m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - m->bus_isa++; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151[j][0], m->sbdn5[j]+1); Modified: trunk/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/amd/serengeti_cheetah/mb_sysconf.h Mon Nov 22 15:14:56 2010 (r6114) @@ -3,7 +3,6 @@ #define MB_SYSCONF_H struct mb_sysconf_t { - unsigned char bus_isa; unsigned char bus_8132_0; unsigned char bus_8132_1; unsigned char bus_8132_2; Modified: trunk/src/mainboard/amd/serengeti_cheetah/mptable.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/mptable.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/amd/serengeti_cheetah/mptable.c Mon Nov 22 15:14:56 2010 (r6114) @@ -13,8 +13,7 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - unsigned char bus_num; - int i, j; + int i, j, bus_isa; struct mb_sysconf_t *m; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -27,12 +26,7 @@ m = sysconf.mb; -/*Bus: Bus ID Type*/ - /* define bus and isa numbers */ - for(bus_num = 0; bus_num < m->bus_isa; bus_num++) { - smp_write_bus(mc, bus_num, "PCI "); - } - smp_write_bus(mc, m->bus_isa, "ISA "); + mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 @@ -83,7 +77,7 @@ } - mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_8111, 0); + mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0); /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ //??? What @@ -161,8 +155,8 @@ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/get_bus_conf.c Mon Nov 22 15:14:56 2010 (r6114) @@ -108,10 +108,6 @@ m = sysconf.mb; - for(i=0;i<256; i++) { - m->bus_type[i] = 0; - } - sysconf.hc_possible_num = ARRAY_SIZE(pci1234x); for(i=0;i<sysconf.hc_possible_num; i++) { sysconf.pci1234[i] = pci1234x[i]; @@ -120,8 +116,6 @@ get_pci1234(); - m->bus_type[0] = 1; //pci - sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff; m->sbdn3 = sysconf.hcdn[0] & 0xff; @@ -152,18 +146,6 @@ printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1); } - for(i=0; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; - - u32 busn = (sysconf.pci1234[i] >> 12) & 0xff; - u32 busn_max = (sysconf.pci1234[i] >> 20) & 0xff; - for (j = busn; j <= busn_max; j++) - m->bus_type[j] = 1; - if(m->bus_isa <= busn_max) - m->bus_isa = busn_max + 1; - printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa); - } - /* HT chain 1 */ j=0; for(i=1; i< sysconf.hc_possible_num; i++) { Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/mb_sysconf.h Mon Nov 22 15:14:56 2010 (r6114) @@ -22,7 +22,6 @@ #define MB_SYSCONF_H struct mb_sysconf_t { - u8 bus_isa; u8 bus_8132_0; u8 bus_8132_1; u8 bus_8132_2; @@ -38,7 +37,6 @@ u32 sbdn3; u32 sbdn3a[31]; u32 sbdn5[31]; - u32 bus_type[256]; }; #endif Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c Mon Nov 22 15:14:56 2010 (r6114) @@ -31,7 +31,7 @@ static void *smp_write_config_table(void *v) { - int i, j; + int i, j, bus_isa; struct mp_config_table *mc; struct mb_sysconf_t *m; @@ -45,13 +45,7 @@ m = sysconf.mb; - /*Bus: Bus ID Type*/ - /* define bus and isa numbers */ - for(j= 0; j < 256 ; j++) { - if(m->bus_type[j]) - smp_write_bus(mc, j, "PCI "); - } - smp_write_bus(mc, m->bus_isa, "ISA "); + mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, m->apicid_8111, 0x11, IO_APIC_ADDR); //8111 @@ -102,7 +96,7 @@ } - mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_8111, 0); + mptable_add_isa_interrupts(mc, bus_isa, m->apicid_8111, 0); /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ //??? What @@ -185,8 +179,8 @@ /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/asus/a8n_e/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/get_bus_conf.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/asus/a8n_e/get_bus_conf.c Mon Nov 22 15:14:56 2010 (r6114) @@ -38,7 +38,6 @@ * mptable and acpi_tables. */ /* busnum is default */ -unsigned char bus_isa; unsigned char bus_ck804[6]; unsigned apicid_ck804; @@ -59,17 +58,13 @@ 0x20202020, /* A8N-E has only one ht-chain */ }; -unsigned bus_type[256]; - - - static unsigned get_bus_conf_done = 0; void get_bus_conf(void) { unsigned apicid_base, sbdn; device_t dev; - int i, j; + int i; if (get_bus_conf_done == 1) return; /* Do it only once. */ @@ -91,15 +86,9 @@ for (i = 0; i < 6; i++) bus_ck804[i] = 0; - for (i = 0; i < 256; i++) - bus_type[i] = 0; - - bus_type[0] = 1; /* PCI */ bus_ck804[0] = (sysconf.pci1234[0] >> 16) & 0xff; - bus_type[bus_ck804[0]] = 1; - /* CK804 */ dev = dev_find_slot(bus_ck804[0], PCI_DEVFN(sbdn + 0x09, 0)); if (dev) { @@ -119,14 +108,9 @@ PCI_DEVFN(sbdn + 0x0b + i - 2, 0)); if (dev) { bus_ck804[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; - for (j = bus_ck804[i]; j < bus_isa; j++) - bus_type[j] = 1; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_ck804[0], sbdn + 0x0b + i - 2); - bus_isa = bus_ck804[i - 1] + 1; } } Modified: trunk/src/mainboard/asus/a8n_e/mptable.c ============================================================================== --- trunk/src/mainboard/asus/a8n_e/mptable.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/asus/a8n_e/mptable.c Mon Nov 22 15:14:56 2010 (r6114) @@ -28,16 +28,14 @@ #include <stdint.h> #include <cpu/amd/amdk8_sysconf.h> -extern unsigned char bus_isa; extern unsigned char bus_ck804[6]; extern unsigned apicid_ck804; -extern unsigned bus_type[256]; static void *smp_write_config_table(void *v) { struct mp_config_table *mc; unsigned sbdn; - int bus_num; + int bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -48,13 +46,7 @@ get_bus_conf(); sbdn = sysconf.sbdn; - /* Bus: Bus ID Type */ - /* Define numbers for PCI and ISA bus. */ - for (bus_num = 0; bus_num < 256; bus_num++) { - if (bus_type[bus_num]) - smp_write_bus(mc, bus_num, "PCI "); - } - smp_write_bus(mc, bus_isa, "ISA "); + mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ { Modified: trunk/src/mainboard/asus/a8v-e_deluxe/mptable.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_deluxe/mptable.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/asus/a8v-e_deluxe/mptable.c Mon Nov 22 15:14:56 2010 (r6114) @@ -27,7 +27,7 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - int bus_isa = 42; + int bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -35,15 +35,7 @@ smp_write_processors(mc); - /* Bus: Bus ID Type */ - smp_write_bus(mc, 0, "PCI "); - smp_write_bus(mc, 1, "PCI "); - smp_write_bus(mc, 2, "PCI "); - smp_write_bus(mc, 3, "PCI "); - smp_write_bus(mc, 4, "PCI "); - smp_write_bus(mc, 5, "PCI "); - smp_write_bus(mc, 6, "PCI "); - smp_write_bus(mc, bus_isa, "ISA "); + mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); Modified: trunk/src/mainboard/asus/a8v-e_se/mptable.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/mptable.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/asus/a8v-e_se/mptable.c Mon Nov 22 15:14:56 2010 (r6114) @@ -27,7 +27,7 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - int bus_isa = 42; + int bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -35,15 +35,7 @@ smp_write_processors(mc); - /* Bus: Bus ID Type */ - smp_write_bus(mc, 0, "PCI "); - smp_write_bus(mc, 1, "PCI "); - smp_write_bus(mc, 2, "PCI "); - smp_write_bus(mc, 3, "PCI "); - smp_write_bus(mc, 4, "PCI "); - smp_write_bus(mc, 5, "PCI "); - smp_write_bus(mc, 6, "PCI "); - smp_write_bus(mc, bus_isa, "ISA "); + mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x20, IO_APIC_ADDR); Modified: trunk/src/mainboard/intel/eagleheights/mptable.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/mptable.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/intel/eagleheights/mptable.c Mon Nov 22 15:14:56 2010 (r6114) @@ -61,9 +61,9 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - unsigned char bus_num, bus_chipset, bus_isa, bus_pci; + unsigned char bus_chipset, bus_pci; unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b; - int i; + int bus_isa, i; uint32_t pin, route; device_t dev; struct resource *res; @@ -89,12 +89,9 @@ dev = dev_find_slot(0, PCI_DEVFN(0x1E,0)); if (dev) { bus_pci = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); bus_pci = 6; - bus_isa = 7; } dev = dev_find_slot(0, PCI_DEVFN(2,0)); @@ -121,11 +118,7 @@ bus_pcie_b = 3; } - /*Bus: Bus ID Type*/ - for(bus_num = 0; bus_num < bus_isa; bus_num++) { - smp_write_bus(mc, bus_num, "PCI "); - } - smp_write_bus(mc, bus_isa, "ISA "); + mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ smp_write_ioapic(mc, 2, 0x20, IO_APIC_ADDR); Modified: trunk/src/mainboard/intel/jarrell/mptable.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/mptable.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/intel/jarrell/mptable.c Mon Nov 22 15:14:56 2010 (r6114) @@ -8,8 +8,7 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - unsigned char bus_num; - unsigned char bus_isa; + int bus_isa; unsigned char bus_pxhd_1; unsigned char bus_pxhd_2; unsigned char bus_pxhd_3 = 0; @@ -31,14 +30,11 @@ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); if (dev) { bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1f.0, using defaults\n"); bus_ich5r_1 = 4; - bus_isa = 5; } /* pxhd-1 */ dev = dev_find_slot(1, PCI_DEVFN(0x0,0)); @@ -88,11 +84,7 @@ } } - /* define bus and isa numbers */ - for(bus_num = 0; bus_num < bus_isa; bus_num++) { - smp_write_bus(mc, bus_num, "PCI "); - } - smp_write_bus(mc, bus_isa, "ISA "); + mptable_write_buses(mc, NULL, &bus_isa); /* IOAPIC handling */ Modified: trunk/src/mainboard/intel/mtarvon/mptable.c ============================================================================== --- trunk/src/mainboard/intel/mtarvon/mptable.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/intel/mtarvon/mptable.c Mon Nov 22 15:14:56 2010 (r6114) @@ -29,7 +29,7 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - u8 bus_isa = 7; + int bus_isa; u8 bus_pci = 6; u8 bus_pcie_a = 1; @@ -39,11 +39,7 @@ smp_write_processors(mc); - /* Define bus numbers */ - smp_write_bus(mc, 0, "PCI "); - smp_write_bus(mc, bus_pci, "PCI "); - smp_write_bus(mc, bus_pcie_a, "PCI "); - smp_write_bus(mc, bus_isa, "ISA "); + mptable_write_buses(mc, NULL, &bus_isa); /* IOAPIC handling */ smp_write_ioapic(mc, 0x01, 0x20, IO_APIC_ADDR); Modified: trunk/src/mainboard/intel/truxton/mptable.c ============================================================================== --- trunk/src/mainboard/intel/truxton/mptable.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/intel/truxton/mptable.c Mon Nov 22 15:14:56 2010 (r6114) @@ -27,8 +27,7 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - u8 bus_num; - u8 bus_isa; + int bus_isa; u8 bus_pea0 = 0; u8 bus_pea1 = 0; u8 bus_aioc; @@ -44,13 +43,10 @@ dev = dev_find_slot(0, PCI_DEVFN(0x04,0)); if (dev) { bus_aioc = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0\n"); bus_aioc = 0; - bus_isa = 9; } /* PCIe A0 */ dev = dev_find_slot(0, PCI_DEVFN(0x02,0)); @@ -71,11 +67,7 @@ bus_pea1 = 0; } - /* define bus and isa numbers */ - for(bus_num = 0; bus_num < bus_isa; bus_num++) { - smp_write_bus(mc, bus_num, "PCI "); - } - smp_write_bus(mc, bus_isa, "ISA "); + mptable_write_buses(mc, NULL, &bus_isa); /* IOAPIC handling */ smp_write_ioapic(mc, 0x8, 0x20, IO_APIC_ADDR); Modified: trunk/src/mainboard/intel/xe7501devkit/bus.h ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/bus.h Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/intel/xe7501devkit/bus.h Mon Nov 22 15:14:56 2010 (r6114) @@ -12,6 +12,5 @@ #define PCI_BUS_P64H2_1_B 5 // P64H2#1 bus B #define PCI_BUS_P64H2_1_A 6 // P64H2#1 bus A #define PCI_BUS_ICH3 7 // ICH3-S -#define SUPERIO_BUS 8 // (arbitrary but unique bus #) #endif // XE7501DEVKIT_BUS_H_INCLUDED Modified: trunk/src/mainboard/intel/xe7501devkit/mptable.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/mptable.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/intel/xe7501devkit/mptable.c Mon Nov 22 15:14:56 2010 (r6114) @@ -15,19 +15,7 @@ #define INT_D 3 #define PCI_IRQ(dev, intLine) (((dev)<<2) | intLine) -static void xe7501devkit_register_buses(struct mp_config_table *mc) -{ - // Bus ID, Bus Type - smp_write_bus(mc, PCI_BUS_CHIPSET, BUSTYPE_PCI); - smp_write_bus(mc, PCI_BUS_E7501_HI_B, BUSTYPE_PCI); - smp_write_bus(mc, PCI_BUS_P64H2_2_B, BUSTYPE_PCI); - smp_write_bus(mc, PCI_BUS_P64H2_2_A, BUSTYPE_PCI); - smp_write_bus(mc, PCI_BUS_E7501_HI_D, BUSTYPE_PCI); - smp_write_bus(mc, PCI_BUS_P64H2_1_B, BUSTYPE_PCI); - smp_write_bus(mc, PCI_BUS_P64H2_1_A, BUSTYPE_PCI); - smp_write_bus(mc, PCI_BUS_ICH3, BUSTYPE_PCI); - smp_write_bus(mc, SUPERIO_BUS, BUSTYPE_ISA); -} +static int bus_isa; static void xe7501devkit_register_ioapics(struct mp_config_table *mc) { @@ -126,7 +114,7 @@ // TODO: Not sure how to handle BT_INTR# signals from the P64H2s. Do we even need to, in APIC mode? - mptable_add_isa_interrupts(mc, SUPERIO_BUS, IOAPIC_ICH3, 0); + mptable_add_isa_interrupts(mc, bus_isa, IOAPIC_ICH3, 0); } static void *smp_write_config_table(void* v) @@ -139,7 +127,7 @@ smp_write_processors(mc); - xe7501devkit_register_buses(mc); + mptable_write_buses(mc, NULL, &bus_isa); xe7501devkit_register_ioapics(mc); xe7501devkit_register_interrupts(mc); Modified: trunk/src/mainboard/supermicro/h8dme/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/get_bus_conf.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/supermicro/h8dme/get_bus_conf.c Mon Nov 22 15:14:56 2010 (r6114) @@ -34,7 +34,6 @@ // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default - unsigned char bus_isa; unsigned char bus_mcp55[8]; //1 unsigned apicid_mcp55; @@ -124,12 +123,9 @@ dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x0a + i - 2 , 0)); if (dev) { bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_mcp55[0], sbdn + 0x0a + i - 2 ); - bus_isa = bus_mcp55[i-1]+1; } } Modified: trunk/src/mainboard/supermicro/h8dme/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/mptable.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/supermicro/h8dme/mptable.c Mon Nov 22 15:14:56 2010 (r6114) @@ -26,7 +26,6 @@ #include <stdint.h> #include <cpu/amd/amdk8_sysconf.h> -extern unsigned char bus_isa; extern unsigned char bus_mcp55[8]; //1 extern unsigned apicid_mcp55; @@ -37,8 +36,7 @@ { struct mp_config_table *mc; unsigned sbdn; - unsigned char bus_num; - int i,j; + int i, j, bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -49,12 +47,7 @@ get_bus_conf(); sbdn = sysconf.sbdn; -/*Bus: Bus ID Type*/ - /* define bus and isa numbers */ - for(bus_num = 0; bus_num < bus_isa; bus_num++) { - smp_write_bus(mc, bus_num, "PCI "); - } - smp_write_bus(mc, bus_isa, "ISA "); + mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ { Modified: trunk/src/mainboard/supermicro/h8dmr/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/get_bus_conf.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/supermicro/h8dmr/get_bus_conf.c Mon Nov 22 15:14:56 2010 (r6114) @@ -34,7 +34,6 @@ // Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables //busnum is default - unsigned char bus_isa; unsigned char bus_mcp55[8]; //1 unsigned apicid_mcp55; @@ -124,12 +123,9 @@ dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x0a + i - 2 , 0)); if (dev) { bus_mcp55[i] = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI %02x:%02x.0, using defaults\n", bus_mcp55[0], sbdn + 0x0a + i - 2 ); - bus_isa = bus_mcp55[i-1]+1; } } Modified: trunk/src/mainboard/supermicro/h8dmr/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/mptable.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/supermicro/h8dmr/mptable.c Mon Nov 22 15:14:56 2010 (r6114) @@ -26,7 +26,6 @@ #include <stdint.h> #include <cpu/amd/amdk8_sysconf.h> -extern unsigned char bus_isa; extern unsigned char bus_mcp55[8]; //1 extern unsigned apicid_mcp55; @@ -37,8 +36,7 @@ { struct mp_config_table *mc; unsigned sbdn; - unsigned char bus_num; - int i,j; + int i, j, bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -49,12 +47,7 @@ get_bus_conf(); sbdn = sysconf.sbdn; -/*Bus: Bus ID Type*/ - /* define bus and isa numbers */ - for(bus_num = 0; bus_num < bus_isa; bus_num++) { - smp_write_bus(mc, bus_num, "PCI "); - } - smp_write_bus(mc, bus_isa, "ISA "); + mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ { Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/get_bus_conf.c Mon Nov 22 15:14:56 2010 (r6114) @@ -73,7 +73,7 @@ struct mb_sysconf_t *m; device_t dev; - int i, j; + int i; if(get_bus_conf_done==1) return; //do it only once @@ -92,7 +92,6 @@ get_pci1234(); - m->bus_type[0] = 1; //pci sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff; @@ -115,18 +114,6 @@ } } - for(i=0; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; - - unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; - unsigned busn_max = (sysconf.pci1234[i] >> 20) & 0xff; - for (j = busn; j <= busn_max; j++) - m->bus_type[j] = 1; - if(m->bus_isa <= busn_max) - m->bus_isa = busn_max + 1; - printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa); - } - /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 apicid_base = get_apicid_base(1); Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/mb_sysconf.h Mon Nov 22 15:14:56 2010 (r6114) @@ -23,11 +23,8 @@ #define MB_SYSCONF_H struct mb_sysconf_t { - unsigned char bus_isa; unsigned char bus_mcp55[8]; //1 unsigned apicid_mcp55; - unsigned bus_type[256]; - }; #endif Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/mptable.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/mptable.c Mon Nov 22 15:14:56 2010 (r6114) @@ -32,7 +32,7 @@ struct mp_config_table *mc; struct mb_sysconf_t *m; unsigned sbdn; - int i,j; + int i, j, bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -44,13 +44,7 @@ sbdn = sysconf.sbdn; m = sysconf.mb; -/*Bus: Bus ID Type*/ - /* define bus and isa numbers */ - for(j= 0; j < 256 ; j++) { - if(m->bus_type[j]) - smp_write_bus(mc, j, "PCI "); - } - smp_write_bus(mc, m->bus_isa, "ISA "); + mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ { @@ -79,7 +73,7 @@ } - mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_mcp55, 0); + mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0); /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0xa); @@ -110,8 +104,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c Mon Nov 22 15:14:56 2010 (r6114) @@ -75,7 +75,7 @@ struct mb_sysconf_t *m; device_t dev; - int i, j; + int i; if(get_bus_conf_done==1) return; //do it only once @@ -94,7 +94,6 @@ get_pci1234(); - m->bus_type[0] = 1; //pci sysconf.sbdn = (sysconf.hcdn[0] & 0xff); // first byte of first chain m->bus_mcp55[0] = (sysconf.pci1234[0] >> 12) & 0xff; @@ -131,20 +130,6 @@ /* 8132_2 */ dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(sbdn3 + 1, 0)); m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - m->bus_isa++; - - for(i=0; i< sysconf.hc_possible_num; i++) { - if(!(sysconf.pci1234[i] & 0x1) ) continue; - - unsigned busn = (sysconf.pci1234[i] >> 12) & 0xff; - unsigned busn_max = (sysconf.pci1234[i] >> 20) & 0xff; - for (j = busn; j <= busn_max; j++) - m->bus_type[j] = 1; - if(m->bus_isa <= busn_max) - m->bus_isa = busn_max + 1; - printk(BIOS_DEBUG, "i=%d bus range: [%x, %x] bus_isa=%x\n",i, busn, busn_max, m->bus_isa); - } /*I/O APICs: APIC ID Version State Address*/ #if CONFIG_LOGICAL_CPUS==1 Modified: trunk/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h Mon Nov 22 15:14:56 2010 (r6114) @@ -23,10 +23,8 @@ #define MB_SYSCONF_H struct mb_sysconf_t { - unsigned char bus_isa; unsigned char bus_mcp55[8]; //1 unsigned apicid_mcp55; - unsigned bus_type[256]; unsigned char bus_8132_0; //7 unsigned char bus_8132_1; //8 Modified: trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c Mon Nov 22 15:14:56 2010 (r6114) @@ -34,7 +34,7 @@ struct mp_config_table *mc; struct mb_sysconf_t *m; unsigned sbdn; - int i,j; + int i, j, bus_isa; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -46,13 +46,7 @@ sbdn = sysconf.sbdn; m = sysconf.mb; -/*Bus: Bus ID Type*/ - /* define bus and isa numbers */ - for(j= 0; j < 256 ; j++) { - if(m->bus_type[j]) - smp_write_bus(mc, j, "PCI "); - } - smp_write_bus(mc, m->bus_isa, "ISA "); + mptable_write_buses(mc, NULL, &bus_isa); /*I/O APICs: APIC ID Version State Address*/ { @@ -81,7 +75,7 @@ } - mptable_add_isa_interrupts(mc, m->bus_isa, m->apicid_mcp55, 0); + mptable_add_isa_interrupts(mc, bus_isa, m->apicid_mcp55, 0); /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_mcp55[0], ((sbdn+1)<<2)|1, m->apicid_mcp55, 0x5); /* 5 SMBus, OK */ @@ -108,8 +102,8 @@ } /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/ - smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0); - smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, bus_isa, 0x0, MP_APIC_ALL, 0x1); /* There is no extension information... */ /* Compute the checksums */ Modified: trunk/src/mainboard/supermicro/x6dai_g/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/mptable.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/supermicro/x6dai_g/mptable.c Mon Nov 22 15:14:56 2010 (r6114) @@ -8,8 +8,7 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - unsigned char bus_num; - unsigned char bus_isa; + int bus_isa; unsigned char bus_6300; mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); @@ -25,21 +24,14 @@ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); if (dev) { bus_6300 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); bus_6300 = 5; - bus_isa = 6; } } - /* define bus and isa numbers */ - for(bus_num = 0; bus_num < bus_isa; bus_num++) { - smp_write_bus(mc, bus_num, "PCI "); - } - smp_write_bus(mc, bus_isa, "ISA "); + mptable_write_buses(mc, NULL, &bus_isa); /* IOAPIC handling */ Modified: trunk/src/mainboard/supermicro/x6dhe_g/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/mptable.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/supermicro/x6dhe_g/mptable.c Mon Nov 22 15:14:56 2010 (r6114) @@ -8,8 +8,7 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - unsigned char bus_num; - unsigned char bus_isa; + int bus_isa; unsigned char bus_pxhd_1; unsigned char bus_pxhd_2; unsigned char bus_esb6300_1; @@ -36,12 +35,9 @@ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); if (dev) { bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); bus_esb6300_2 = 7; - bus_isa = 8; } /* pxhd-1 */ dev = dev_find_slot(1, PCI_DEVFN(0x0,0)); @@ -61,11 +57,7 @@ } } - /* define bus and isa numbers */ - for(bus_num = 0; bus_num < bus_isa; bus_num++) { - smp_write_bus(mc, bus_num, "PCI "); - } - smp_write_bus(mc, bus_isa, "ISA "); + mptable_write_buses(mc, NULL, &bus_isa); /* IOAPIC handling */ Modified: trunk/src/mainboard/supermicro/x6dhe_g2/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/mptable.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/supermicro/x6dhe_g2/mptable.c Mon Nov 22 15:14:56 2010 (r6114) @@ -8,8 +8,7 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - unsigned char bus_num; - unsigned char bus_isa; + int bus_isa; unsigned char bus_pxhd_1; unsigned char bus_pxhd_2; unsigned char bus_esb6300_1; @@ -36,12 +35,9 @@ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); if (dev) { bus_esb6300_2 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); bus_esb6300_2 = 7; - bus_isa = 8; } /* pxhd-1 */ dev = dev_find_slot(1, PCI_DEVFN(0x0,0)); @@ -61,11 +57,7 @@ } } - /* define bus and isa numbers */ - for(bus_num = 0; bus_num < bus_isa; bus_num++) { - smp_write_bus(mc, bus_num, "PCI "); - } - smp_write_bus(mc, bus_isa, "ISA "); + mptable_write_buses(mc, NULL, &bus_isa); /* IOAPIC handling */ Modified: trunk/src/mainboard/supermicro/x6dhr_ig/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/mptable.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/supermicro/x6dhr_ig/mptable.c Mon Nov 22 15:14:56 2010 (r6114) @@ -8,8 +8,7 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - unsigned char bus_num; - unsigned char bus_isa; + int bus_isa; unsigned char bus_pxhd_1; unsigned char bus_pxhd_2; unsigned char bus_pxhd_3; @@ -29,14 +28,11 @@ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); if (dev) { bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1f.0, using defaults\n"); bus_ich5r_1 = 9; - bus_isa = 10; } /* pxhd-1 */ dev = dev_find_slot(2, PCI_DEVFN(0x0,0)); @@ -86,11 +82,7 @@ } - /* define bus and isa numbers */ - for(bus_num = 0; bus_num < bus_isa; bus_num++) { - smp_write_bus(mc, bus_num, "PCI "); - } - smp_write_bus(mc, bus_isa, "ISA "); + mptable_write_buses(mc, NULL, &bus_isa); /* IOAPIC handling */ Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/mptable.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/mptable.c Mon Nov 22 14:07:10 2010 (r6113) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/mptable.c Mon Nov 22 15:14:56 2010 (r6114) @@ -8,8 +8,7 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - unsigned char bus_num; - unsigned char bus_isa; + int bus_isa; unsigned char bus_pxhd_1; unsigned char bus_pxhd_2; unsigned char bus_pxhd_3; @@ -29,14 +28,11 @@ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0)); if (dev) { bus_ich5r_1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS); - bus_isa++; } else { printk(BIOS_DEBUG, "ERROR - could not find PCI 0:1e.0, using defaults\n"); bus_ich5r_1 = 7; - bus_isa = 8; } /* pxhd-1 */ dev = dev_find_slot(1, PCI_DEVFN(0x0,0)); @@ -86,11 +82,7 @@ } - /* define bus and isa numbers */ - for(bus_num = 0; bus_num < bus_isa; bus_num++) { - smp_write_bus(mc, bus_num, "PCI "); - } - smp_write_bus(mc, bus_isa, "ISA "); + mptable_write_buses(mc, NULL, &bus_isa); /* IOAPIC handling */

1 0

build service results for r6113
by repository service 22 Nov '10

22 Nov '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 6113 to the coreboot repository. This caused the following changes: Change Log: Workaround to get die.c to work with romcc. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Build Log: Compilation of advantech:pcm-5820 has been fixed Compilation of asi:mb_5blgp has been fixed Compilation of asi:mb_5blmp has been fixed Compilation of axus:tc320 has been fixed Compilation of bcom:winnet100 has been fixed Compilation of dell:s1850 has been fixed Compilation of digitallogic:msm586seg has been fixed Compilation of eaglelion:5bcm has been fixed Compilation of emulation:qemu-x86 has been fixed Compilation of iei:juki-511p has been fixed Compilation of iei:nova4899r has been fixed Compilation of intel:jarrell has been fixed Compilation of intel:truxton has been fixed Compilation of intel:xe7501devkit has been fixed Compilation of supermicro:x6dai_g has been fixed Compilation of supermicro:x6dhe_g has been fixed Compilation of supermicro:x6dhe_g2 has been fixed Compilation of supermicro:x6dhr_ig has been fixed Compilation of supermicro:x6dhr_ig2 has been fixed Compilation of technologic:ts5300 has been fixed Compilation of televideo:tc7020 has been fixed Compilation of via:epia has been fixed Compilation of via:epia-m has been fixed Compilation of via:epia-n has been fixed If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

build service results for r6112
by repository service 22 Nov '10

22 Nov '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 6112 to the coreboot repository. This caused the following changes: Change Log: i855: Remove useless memctrl indirection. This needlessly complicates the code and increases register pressure on romcc chipsets. We did the same conversion on i440BX, i830, and others. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Build Log: Compilation of advantech:pcm-5820 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=pcm-5820&vendo… Compilation of asi:mb_5blgp is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=mb_5blgp&vendo… Compilation of asi:mb_5blmp is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=mb_5blmp&vendo… Compilation of axus:tc320 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=tc320&vendor=a… Compilation of bcom:winnet100 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=winnet100&vend… Compilation of dell:s1850 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=s1850&vendor=d… Compilation of digitallogic:msm586seg is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=msm586seg&vend… Compilation of eaglelion:5bcm is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=5bcm&vendor=ea… Compilation of emulation:qemu-x86 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=qemu-x86&vendo… Compilation of iei:juki-511p is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=juki-511p&vend… Compilation of iei:nova4899r is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=nova4899r&vend… Compilation of intel:jarrell is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=jarrell&vendor… Compilation of intel:truxton is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=truxton&vendor… Compilation of intel:xe7501devkit is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=xe7501devkit&v… Compilation of supermicro:x6dai_g is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=x6dai_g&vendor… Compilation of supermicro:x6dhe_g is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=x6dhe_g&vendor… Compilation of supermicro:x6dhe_g2 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=x6dhe_g2&vendo… Compilation of supermicro:x6dhr_ig is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=x6dhr_ig&vendo… Compilation of supermicro:x6dhr_ig2 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=x6dhr_ig2&vend… Compilation of technologic:ts5300 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=ts5300&vendor=… Compilation of televideo:tc7020 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=tc7020&vendor=… Compilation of via:epia is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=epia&vendor=vi… Compilation of via:epia-m is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=epia-m&vendor=… Compilation of via:epia-n is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6112&device=epia-n&vendor=… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r6112 - in trunk/src: mainboard/digitallogic/adl855pc mainboard/lanner/em8510 northbridge/intel/i855
by repository service 22 Nov '10

22 Nov '10

Author: uwe Date: Mon Nov 22 13:59:36 2010 New Revision: 6112 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6112 Log: i855: Remove useless memctrl indirection. This needlessly complicates the code and increases register pressure on romcc chipsets. We did the same conversion on i440BX, i830, and others. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c trunk/src/mainboard/lanner/em8510/romstage.c trunk/src/northbridge/intel/i855/debug.c trunk/src/northbridge/intel/i855/raminit.c trunk/src/northbridge/intel/i855/raminit.h Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/romstage.c Mon Nov 22 09:09:50 2010 (r6111) +++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c Mon Nov 22 13:59:36 2010 (r6112) @@ -5,6 +5,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> +#include <lib.h> #include "pc80/udelay_io.c" #include <pc80/mc146818rtc.h> #include <console/console.h> @@ -26,17 +27,9 @@ #include "northbridge/intel/i855/raminit.c" #include "northbridge/intel/i855/reset_test.c" -#include "lib/generic_sdram.c" void main(unsigned long bist) { - static const struct mem_controller memctrl[] = { - { - .d0 = PCI_DEV(0, 0, 1), - .channel0 = { DIMM0, 0 }, - }, - }; - if (bist == 0) { #if 0 enable_lapic(); @@ -58,10 +51,12 @@ if (!bios_reset_detected()) { enable_smbus(); #if 0 - dump_spd_registers(&memctrl[0]); + dump_spd_registers(); dump_smbus_registers(); #endif - sdram_initialize(ARRAY_SIZE(memctrl), memctrl); + sdram_set_registers(); + sdram_set_spd_registers(); + sdram_enable(); } #if 0 Modified: trunk/src/mainboard/lanner/em8510/romstage.c ============================================================================== --- trunk/src/mainboard/lanner/em8510/romstage.c Mon Nov 22 09:09:50 2010 (r6111) +++ trunk/src/mainboard/lanner/em8510/romstage.c Mon Nov 22 13:59:36 2010 (r6112) @@ -27,6 +27,7 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <stdlib.h> +#include <lib.h> #include <spd.h> #include "pc80/udelay_io.c" #include <pc80/mc146818rtc.h> @@ -48,17 +49,9 @@ #include "northbridge/intel/i855/raminit.c" #include "northbridge/intel/i855/reset_test.c" -#include "lib/generic_sdram.c" void main(unsigned long bist) { - static const struct mem_controller memctrl[] = { - { - .d0 = PCI_DEV(0, 0, 1), - .channel0 = { DIMM0, 0 }, - }, - }; - if (bist == 0) { #if 0 enable_lapic(); @@ -80,10 +73,12 @@ if (!bios_reset_detected()) { enable_smbus(); #if 1 - dump_spd_registers(&memctrl[0]); + dump_spd_registers(); dump_smbus_registers(); #endif - sdram_initialize(ARRAY_SIZE(memctrl), memctrl); + sdram_set_registers(); + sdram_set_spd_registers(); + sdram_enable(); } #if 0 Modified: trunk/src/northbridge/intel/i855/debug.c ============================================================================== --- trunk/src/northbridge/intel/i855/debug.c Mon Nov 22 09:09:50 2010 (r6111) +++ trunk/src/northbridge/intel/i855/debug.c Mon Nov 22 13:59:36 2010 (r6112) @@ -18,6 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <spd.h> + static void print_debug_pci_dev(unsigned dev) { print_debug("PCI: "); @@ -84,13 +86,13 @@ } } -static inline void dump_spd_registers(const struct mem_controller *ctrl) +static inline void dump_spd_registers(void) { int i; print_debug("\n"); for(i = 0; i < 2; i++) { unsigned device; - device = ctrl->channel0[i]; + device = DIMM0 + i; if (device) { int j; print_debug("dimm: "); Modified: trunk/src/northbridge/intel/i855/raminit.c ============================================================================== --- trunk/src/northbridge/intel/i855/raminit.c Mon Nov 22 09:09:50 2010 (r6111) +++ trunk/src/northbridge/intel/i855/raminit.c Mon Nov 22 13:59:36 2010 (r6112) @@ -127,7 +127,7 @@ * @param dimm_socket_address SMBus address of DIMM socket to interrogate. * @return log2(page size) for each side of the DIMM. */ -static struct dimm_size sdram_spd_get_page_size(uint16_t dimm_socket_address) +static struct dimm_size sdram_spd_get_page_size(u8 dimm_socket_address) { uint16_t module_data_width; int value; @@ -187,7 +187,7 @@ * @param dimm_socket_address SMBus address of DIMM socket to interrogate. * @return Width in bits of each DIMM side's DRAMs. */ -static struct dimm_size sdram_spd_get_width(uint16_t dimm_socket_address) +static struct dimm_size sdram_spd_get_width(u8 dimm_socket_address) { int value; struct dimm_size width; @@ -274,17 +274,15 @@ /** * Scan for compatible DIMMs. * - * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. * @return A bitmask indicating which sockets contain a compatible DIMM. */ -static uint8_t spd_get_supported_dimms(const struct mem_controller *ctrl) +static uint8_t spd_get_supported_dimms(void) { int i; uint8_t dimm_mask = 0; for (i = 0; i < DIMM_SOCKETS; i++) { - uint16_t dimm = ctrl->channel0[i]; + u8 dimm = DIMM0 + i; #ifdef VALIDATE_DIMM_COMPATIBILITY struct dimm_size page_size; @@ -404,7 +402,7 @@ } } -static void set_initialize_complete(const struct mem_controller *ctrl) +static void set_initialize_complete(void) { uint32_t drc_reg; @@ -413,7 +411,7 @@ pci_write_config32(NORTHBRIDGE_MMC, DRC, drc_reg); } -static void sdram_enable(int controllers, const struct mem_controller *ctrl) +static void sdram_enable(void) { int i; @@ -470,7 +468,7 @@ delay(); print_debug("Ram enable 9\n"); - set_initialize_complete(ctrl); + set_initialize_complete(); delay(); delay(); @@ -495,11 +493,8 @@ /** * Set only what I need until it works, then make it figure things out on boot * assumes only one DIMM is populated. - * - * @param ctrl PCI addresses of memory controller functions, and SMBus - * addresses of DIMM slots on the mainboard. */ -static void sdram_set_registers(const struct mem_controller *ctrl) +static void sdram_set_registers(void) { /* print_debug("Before configuration:\n"); @@ -507,13 +502,13 @@ */ } -static void spd_set_row_attributes(const struct mem_controller *ctrl, uint8_t dimm_mask) +static void spd_set_row_attributes(uint8_t dimm_mask) { int i; uint16_t row_attributes = 0; for (i = 0; i < DIMM_SOCKETS; i++) { - uint16_t dimm = ctrl->channel0[i]; + u8 dimm = DIMM0 + i; struct dimm_size page_size; struct dimm_size sdram_width; @@ -544,7 +539,7 @@ pci_write_config16(NORTHBRIDGE_MMC, DRA, row_attributes); } -static void spd_set_dram_controller_mode(const struct mem_controller *ctrl, uint8_t dimm_mask) +static void spd_set_dram_controller_mode(uint8_t dimm_mask) { int i; @@ -558,7 +553,7 @@ controller_mode |= (2 << 10); // FIXME: Undocumented, really needed????? for (i = 0; i < DIMM_SOCKETS; i++) { - uint16_t dimm = ctrl->channel0[i]; + u8 dimm = DIMM0 + i; uint32_t dimm_refresh_mode; int value; u8 tRCD, tRP; @@ -610,7 +605,7 @@ pci_write_config32(NORTHBRIDGE_MMC, DRC, controller_mode); } -static void spd_set_dram_timing(const struct mem_controller *ctrl, uint8_t dimm_mask) +static void spd_set_dram_timing(uint8_t dimm_mask) { int i; u32 dram_timing; @@ -623,7 +618,7 @@ uint8_t slowest_active_to_precharge_delay = 0; for (i = 0; i < DIMM_SOCKETS; i++) { - uint16_t dimm = ctrl->channel0[i]; + u8 dimm = DIMM0 + i; int value; uint32_t current_cas_latency; uint32_t dimm_compatible_cas_latencies; @@ -788,14 +783,14 @@ pci_write_config32(NORTHBRIDGE_MMC, DRT, dram_timing); } -static void spd_set_dram_size(const struct mem_controller *ctrl, uint8_t dimm_mask) +static void spd_set_dram_size(uint8_t dimm_mask) { int i; int total_dram = 0; uint32_t drb_reg = 0; for (i = 0; i < DIMM_SOCKETS; i++) { - uint16_t dimm = ctrl->channel0[i]; + u8 dimm = DIMM0 + i; struct dimm_size sz; if (!(dimm_mask & (1 << i))) { @@ -818,7 +813,7 @@ } -static void spd_set_dram_pwr_management(const struct mem_controller *ctrl) +static void spd_set_dram_pwr_management(void) { uint32_t pwrmg_reg; @@ -826,7 +821,7 @@ pci_write_config32(NORTHBRIDGE_MMC, PWRMG, pwrmg_reg); } -static void spd_set_dram_throttle_control(const struct mem_controller *ctrl) +static void spd_set_dram_throttle_control(void) { uint32_t dtc_reg = 0; @@ -874,28 +869,28 @@ pci_write_config32(NORTHBRIDGE_MMC, DTC, dtc_reg); } -static void spd_update(const struct mem_controller *ctrl, u8 reg, u32 new_value) +static void spd_update(u8 reg, u32 new_value) { #if CONFIG_DEBUG_RAM_SETUP - u32 value1 = pci_read_config32(ctrl->d0, reg); + u32 value1 = pci_read_config32(NORTHBRIDGE_MMC, reg); #endif - pci_write_config32(ctrl->d0, reg, new_value); + pci_write_config32(NORTHBRIDGE_MMC, reg, new_value); #if CONFIG_DEBUG_RAM_SETUP - u32 value2 = pci_read_config32(ctrl->d0, reg); + u32 value2 = pci_read_config32(NORTHBRIDGE_MMC, reg); PRINTK_DEBUG("update reg %02x, old: %08x, new: %08x, read back: %08x\n", reg, value1, new_value, value2); #endif } /* if ram still doesn't work do this function */ -static void spd_set_undocumented_registers(const struct mem_controller *ctrl) +static void spd_set_undocumented_registers(void) { - spd_update(ctrl, 0x74, 0x00000001); - spd_update(ctrl, 0x78, 0x001fe974); - spd_update(ctrl, 0x80, 0x00af0039); - spd_update(ctrl, 0x84, 0x0000033c); - spd_update(ctrl, 0x88, 0x00000010); + spd_update(0x74, 0x00000001); + spd_update(0x78, 0x001fe974); + spd_update(0x80, 0x00af0039); + spd_update(0x84, 0x0000033c); + spd_update(0x88, 0x00000010); - spd_update(ctrl, 0xc0, 0x00000003); + spd_update(0xc0, 0x00000003); } static void northbridge_set_registers(void) @@ -961,26 +956,26 @@ printk(BIOS_DEBUG, "Initial Northbridge registers have been set.\n"); } -static void sdram_set_spd_registers(const struct mem_controller *ctrl) +static void sdram_set_spd_registers(void) { uint8_t dimm_mask; PRINTK_DEBUG("Reading SPD data...\n"); - dimm_mask = spd_get_supported_dimms(ctrl); + dimm_mask = spd_get_supported_dimms(); if (dimm_mask == 0) { print_debug("No usable memory for this controller\n"); } else { PRINTK_DEBUG("DIMM MASK: %02x\n", dimm_mask); - spd_set_row_attributes(ctrl, dimm_mask); - spd_set_dram_controller_mode(ctrl, dimm_mask); - spd_set_dram_timing(ctrl, dimm_mask); - spd_set_dram_size(ctrl, dimm_mask); - spd_set_dram_pwr_management(ctrl); - spd_set_dram_throttle_control(ctrl); - spd_set_undocumented_registers(ctrl); + spd_set_row_attributes(dimm_mask); + spd_set_dram_controller_mode(dimm_mask); + spd_set_dram_timing(dimm_mask); + spd_set_dram_size(dimm_mask); + spd_set_dram_pwr_management(); + spd_set_dram_throttle_control(); + spd_set_undocumented_registers(); } /* Setup Initial Northbridge Registers */ Modified: trunk/src/northbridge/intel/i855/raminit.h ============================================================================== --- trunk/src/northbridge/intel/i855/raminit.h Mon Nov 22 09:09:50 2010 (r6111) +++ trunk/src/northbridge/intel/i855/raminit.h Mon Nov 22 13:59:36 2010 (r6112) @@ -21,18 +21,13 @@ #ifndef NORTHBRIDGE_INTEL_I855_RAMINIT_H #define NORTHBRIDGE_INTEL_I855_RAMINIT_H -/* i855 Northbridge PCI device */ +/* i855 Northbridge PCI devices */ #define NORTHBRIDGE PCI_DEV(0, 0, 0) #define NORTHBRIDGE_MMC PCI_DEV(0, 0, 1) /* The i855 supports max. 2 dual-sided SO-DIMMs. */ #define DIMM_SOCKETS 2 -struct mem_controller { - device_t d0; - uint16_t channel0[DIMM_SOCKETS]; -}; - -void sdram_initialize(int controllers, const struct mem_controller *ctrl); +void sdram_initialize(void); #endif /* NORTHBRIDGE_INTEL_I855_RAMINIT_H */

1 0

build service results for r6111
by repository service 22 Nov '10

22 Nov '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6111 to the coreboot repository. This caused the following changes: Change Log: Printing coreboot debug messages on VGA console is pretty much useless, since initializing VGA happens pretty much as the last thing before starting the payload. Hence, drop VGA console support, as we did in coreboot v3. - Drop VGA and BTEXT console support. Console is meant to be debugging only, and by the time graphics comes up 99% of the risky stuff has already happened. Note: This patch does not remove hardware init but only the actual output functionality. The ragexl driver needs some extra love, but that's for another day - factor out die() and post() - drop some leftover RAMBASE < 0x100000 checks. Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: QingPei Wang<wangqingpei(a)gmail.com> Build Log: Compilation of advantech:pcm-5820 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=pcm-5820&vendo… Compilation of asi:mb_5blgp has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=mb_5blgp&vendo… Compilation of asi:mb_5blmp has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=mb_5blmp&vendo… Compilation of axus:tc320 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=tc320&vendor=a… Compilation of bcom:winnet100 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=winnet100&vend… Compilation of dell:s1850 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=s1850&vendor=d… Compilation of digitallogic:msm586seg has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=msm586seg&vend… Compilation of eaglelion:5bcm has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=5bcm&vendor=ea… Compilation of emulation:qemu-x86 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=qemu-x86&vendo… Compilation of iei:juki-511p has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=juki-511p&vend… Compilation of iei:nova4899r has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=nova4899r&vend… Compilation of intel:jarrell has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=jarrell&vendor… Compilation of intel:truxton has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=truxton&vendor… Compilation of intel:xe7501devkit has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=xe7501devkit&v… Compilation of supermicro:x6dai_g has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=x6dai_g&vendor… Compilation of supermicro:x6dhe_g has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=x6dhe_g&vendor… Compilation of supermicro:x6dhe_g2 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=x6dhe_g2&vendo… Compilation of supermicro:x6dhr_ig has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=x6dhr_ig&vendo… Compilation of supermicro:x6dhr_ig2 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=x6dhr_ig2&vend… Compilation of technologic:ts5300 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=ts5300&vendor=… Compilation of televideo:tc7020 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=tc7020&vendor=… Compilation of via:epia has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=epia&vendor=vi… Compilation of via:epia-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=epia-m&vendor=… Compilation of via:epia-n has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6111&device=epia-n&vendor=… If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r6111 - in trunk: payloads/libpayload/include src/arch/i386/boot src/arch/i386/lib src/console src/cpu/x86/lapic src/devices src/drivers/ati/ragexl src/drivers/emulation/qemu src/include/b...
by repository service 22 Nov '10

22 Nov '10

Author: stepan Date: Mon Nov 22 09:09:50 2010 New Revision: 6111 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6111 Log: Printing coreboot debug messages on VGA console is pretty much useless, since initializing VGA happens pretty much as the last thing before starting the payload. Hence, drop VGA console support, as we did in coreboot v3. - Drop VGA and BTEXT console support. Console is meant to be debugging only, and by the time graphics comes up 99% of the risky stuff has already happened. Note: This patch does not remove hardware init but only the actual output functionality. The ragexl driver needs some extra love, but that's for another day - factor out die() and post() - drop some leftover RAMBASE < 0x100000 checks. Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: QingPei Wang<wangqingpei(a)gmail.com> Added: trunk/src/console/die.c trunk/src/console/post.c Deleted: trunk/src/console/btext_console.c trunk/src/console/font-8x16.c trunk/src/console/vga_console.c trunk/src/include/console/btext.h Modified: trunk/payloads/libpayload/include/coreboot_tables.h trunk/src/arch/i386/boot/coreboot_table.c trunk/src/arch/i386/lib/cbfs_and_run.c trunk/src/console/Kconfig trunk/src/console/Makefile.inc trunk/src/console/console.c trunk/src/cpu/x86/lapic/lapic_cpu_init.c trunk/src/devices/Kconfig trunk/src/devices/device.c trunk/src/devices/pci_device.c trunk/src/devices/pci_rom.c trunk/src/drivers/ati/ragexl/xlinit.c trunk/src/drivers/emulation/qemu/init.c trunk/src/include/boot/coreboot_tables.h trunk/src/include/console/console.h trunk/src/mainboard/msi/ms9652_fam10/Kconfig trunk/src/northbridge/amd/amdfam10/northbridge.c trunk/src/northbridge/amd/amdk8/northbridge.c trunk/src/southbridge/via/k8t890/k8m890_chrome.c Modified: trunk/payloads/libpayload/include/coreboot_tables.h ============================================================================== --- trunk/payloads/libpayload/include/coreboot_tables.h Mon Nov 22 01:42:42 2010 (r6110) +++ trunk/payloads/libpayload/include/coreboot_tables.h Mon Nov 22 09:09:50 2010 (r6111) @@ -122,10 +122,10 @@ }; #define CB_TAG_CONSOLE_SERIAL8250 0 -#define CB_TAG_CONSOLE_VGA 1 -#define CB_TAG_CONSOLE_BTEXT 2 +#define CB_TAG_CONSOLE_VGA 1 // OBSOLETE +#define CB_TAG_CONSOLE_BTEXT 2 // OBSOLETE #define CB_TAG_CONSOLE_LOGBUF 3 -#define CB_TAG_CONSOLE_SROM 4 +#define CB_TAG_CONSOLE_SROM 4 // OBSOLETE #define CB_TAG_CONSOLE_EHCI 5 #define CB_TAG_FORWARD 0x00011 Modified: trunk/src/arch/i386/boot/coreboot_table.c ============================================================================== --- trunk/src/arch/i386/boot/coreboot_table.c Mon Nov 22 01:42:42 2010 (r6110) +++ trunk/src/arch/i386/boot/coreboot_table.c Mon Nov 22 09:09:50 2010 (r6111) @@ -134,18 +134,9 @@ #if CONFIG_CONSOLE_SERIAL8250 add_console(header, LB_TAG_CONSOLE_SERIAL8250); #endif -#if CONFIG_CONSOLE_VGA - add_console(header, LB_TAG_CONSOLE_VGA); -#endif -#if CONFIG_CONSOLE_BTEXT - add_console(header, LB_TAG_CONSOLE_BTEXT); -#endif #if CONFIG_CONSOLE_LOGBUF add_console(header, LB_TAG_CONSOLE_LOGBUF); #endif -#if CONFIG_CONSOLE_SROM - add_console(header, LB_TAG_CONSOLE_SROM); -#endif #if CONFIG_USBDEBUG add_console(header, LB_TAG_CONSOLE_EHCI); #endif Modified: trunk/src/arch/i386/lib/cbfs_and_run.c ============================================================================== --- trunk/src/arch/i386/lib/cbfs_and_run.c Mon Nov 22 01:42:42 2010 (r6110) +++ trunk/src/arch/i386/lib/cbfs_and_run.c Mon Nov 22 09:09:50 2010 (r6111) @@ -25,14 +25,10 @@ { u8 *dst; - print_debug("Loading stage image.\n"); + print_debug("Loading image.\n"); dst = cbfs_load_stage(filename); - if (dst == (void *) -1) { - /* We should use die() here. */ - print_emerg("Loading stage failed!\n"); - for (;;) - asm("hlt\n"); - } + if ((void *)dst == (void *) -1) + die("FATAL: Essential component is missing.\n"); print_debug("Jumping to image.\n"); __asm__ volatile ( Modified: trunk/src/console/Kconfig ============================================================================== --- trunk/src/console/Kconfig Mon Nov 22 01:42:42 2010 (r6110) +++ trunk/src/console/Kconfig Mon Nov 22 09:09:50 2010 (r6111) @@ -133,13 +133,9 @@ on your mainboard) is highly board-specific, and you'll likely have to find out by trial-and-error. -config CONSOLE_VGA - bool "Use VGA console once initialized" - default n - # TODO: Deps? # TODO: Improve description. -config CONSOLE_VGA_ONBOARD_AT_FIRST +config ONBOARD_VGA_IS_PRIMARY bool "Use onboard VGA as primary video device" default n help @@ -322,14 +318,6 @@ help Map the log level config names to an integer. -config CONSOLE_BTEXT - bool - default n - -config CONSOLE_SROM - bool - default n - config CONSOLE_LOGBUF bool default n Modified: trunk/src/console/Makefile.inc ============================================================================== --- trunk/src/console/Makefile.inc Mon Nov 22 01:42:42 2010 (r6110) +++ trunk/src/console/Makefile.inc Mon Nov 22 09:09:50 2010 (r6111) @@ -2,18 +2,19 @@ ramstage-y += console.c ramstage-y += vtxprintf.c ramstage-y += vsprintf.c +ramstage-y += post.c +ramstage-y += die.c smm-y += printk.c smm-y += vtxprintf.c romstage-y += vtxprintf.c romstage-$(CONFIG_CACHE_AS_RAM) += console.c +romstage-y += post.c +romstage-y += die.c driver-$(CONFIG_CONSOLE_SERIAL8250) += uart8250_console.c driver-$(CONFIG_USBDEBUG) += usbdebug_console.c -driver-$(CONFIG_CONSOLE_VGA) += vga_console.c -driver-$(CONFIG_CONSOLE_BTEXT) += btext_console.c -driver-$(CONFIG_CONSOLE_BTEXT) += font-8x16.c driver-$(CONFIG_CONSOLE_LOGBUF) += logbuf_console.c driver-$(CONFIG_CONSOLE_NE2K) += ne2k_console.c Modified: trunk/src/console/console.c ============================================================================== --- trunk/src/console/console.c Mon Nov 22 01:42:42 2010 (r6110) +++ trunk/src/console/console.c Mon Nov 22 09:09:50 2010 (r6111) @@ -91,28 +91,6 @@ return 0; } -/* - * Write POST information - */ -void post_code(u8 value) -{ -#if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0 -#if CONFIG_SERIAL_POST==1 - printk(BIOS_EMERG, "POST: 0x%02x\n", value); -#endif - outb(value, 0x80); -#endif -} - -/* Report a fatal error */ -void __attribute__((noreturn)) die(const char *msg) -{ - printk(BIOS_EMERG, "%s", msg); - //post_code(0xff); - for (;;) - hlt(); /* Halt */ -} - #else void console_init(void) @@ -129,24 +107,4 @@ " starting...\n"; print_info(console_test); } - -void post_code(u8 value) -{ -#if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0 -#if CONFIG_SERIAL_POST==1 - print_emerg("POST: 0x"); - print_emerg_hex8(value); - print_emerg("\n"); -#endif - outb(value, 0x80); -#endif -} - -void die(const char *str) -{ - print_emerg(str); - do { - hlt(); - } while(1); -} #endif Added: trunk/src/console/die.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/console/die.c Mon Nov 22 09:09:50 2010 (r6111) @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/hlt.h> +#include <console/console.h> + +/* Report a fatal error */ +void __attribute__((noreturn)) die(const char *msg) +{ + print_emerg(msg); + do { + hlt(); + } while(1); +} Added: trunk/src/console/post.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/console/post.c Mon Nov 22 09:09:50 2010 (r6111) @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Eric Biederman + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, + * MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <console/console.h> + +/* Write POST information */ + +void post_code(uint8_t value) +{ +#if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0 +#if CONFIG_SERIAL_POST==1 + print_emerg("POST: 0x"); + print_emerg_hex8(value); + print_emerg("\n"); +#endif + outb(value, 0x80); +#endif +} Modified: trunk/src/cpu/x86/lapic/lapic_cpu_init.c ============================================================================== --- trunk/src/cpu/x86/lapic/lapic_cpu_init.c Mon Nov 22 01:42:42 2010 (r6110) +++ trunk/src/cpu/x86/lapic/lapic_cpu_init.c Mon Nov 22 09:09:50 2010 (r6111) @@ -16,8 +16,6 @@ #include <cpu/cpu.h> #if CONFIG_SMP == 1 - -#if CONFIG_RAMBASE >= 0x100000 /* This is a lot more paranoid now, since Linux can NOT handle * being told there is a CPU when none exists. So any errors * will return 0, meaning no CPU. @@ -29,7 +27,6 @@ { return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000 } -#endif #if CONFIG_HAVE_ACPI_RESUME == 1 char *lowmem_backup; @@ -41,7 +38,6 @@ static void copy_secondary_start_to_1m_below(void) { -#if CONFIG_RAMBASE >= 0x100000 extern char _secondary_start_end[]; unsigned long code_size; unsigned long start_eip; @@ -67,7 +63,6 @@ memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size); printk(BIOS_DEBUG, "start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size); -#endif } static int lapic_start_cpu(unsigned long apicid) @@ -139,11 +134,7 @@ return 0; } -#if CONFIG_RAMBASE >= 0x100000 start_eip = get_valid_start_eip((unsigned long)_secondary_start); -#else - start_eip = (unsigned long)_secondary_start; -#endif #if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX) num_starts = 2; Modified: trunk/src/devices/Kconfig ============================================================================== --- trunk/src/devices/Kconfig Mon Nov 22 01:42:42 2010 (r6110) +++ trunk/src/devices/Kconfig Mon Nov 22 09:09:50 2010 (r6111) @@ -116,7 +116,7 @@ they can still access all devices in the system. Enable this option for a good compromise between security and speed. -config CONSOLE_VGA_MULTI +config MULTIPLE_VGA_ADAPTERS bool default n Modified: trunk/src/devices/device.c ============================================================================== --- trunk/src/devices/device.c Mon Nov 22 01:42:42 2010 (r6110) +++ trunk/src/devices/device.c Mon Nov 22 09:09:50 2010 (r6111) @@ -722,7 +722,7 @@ if (!vga) vga = vga_first; -#if CONFIG_CONSOLE_VGA_ONBOARD_AT_FIRST == 1 +#if CONFIG_ONBOARD_VGA_IS_PRIMARY == 1 if (vga_onboard) /* Will use onboard VGA as primary. */ #else if (!vga) /* Will use last add-on adapter as primary. */ Modified: trunk/src/devices/pci_device.c ============================================================================== --- trunk/src/devices/pci_device.c Mon Nov 22 01:42:42 2010 (r6110) +++ trunk/src/devices/pci_device.c Mon Nov 22 09:09:50 2010 (r6111) @@ -675,11 +675,6 @@ return; run_bios(dev, (unsigned long)ram); - -#if CONFIG_CONSOLE_VGA == 1 - if ((dev->class >> 8) == PCI_CLASS_DISPLAY_VGA) - vga_console_init(); -#endif /* CONFIG_CONSOLE_VGA */ #endif /* CONFIG_PCI_ROM_RUN || CONFIG_VGA_ROM_RUN */ } Modified: trunk/src/devices/pci_rom.c ============================================================================== --- trunk/src/devices/pci_rom.c Mon Nov 22 01:42:42 2010 (r6110) +++ trunk/src/devices/pci_rom.c Mon Nov 22 09:09:50 2010 (r6111) @@ -130,7 +130,7 @@ * devices have a mismatch between the hardware and the ROM. */ if (PCI_CLASS_DISPLAY_VGA == (dev->class >> 8)) { -#if CONFIG_CONSOLE_VGA == 1 && CONFIG_CONSOLE_VGA_MULTI == 0 +#if CONFIG_MULTIPLE_VGA_ADAPTERS == 0 extern device_t vga_pri; /* Primary VGA device (device.c). */ if (dev != vga_pri) return NULL; /* Only one VGA supported. */ #endif Modified: trunk/src/drivers/ati/ragexl/xlinit.c ============================================================================== --- trunk/src/drivers/ati/ragexl/xlinit.c Mon Nov 22 01:42:42 2010 (r6110) +++ trunk/src/drivers/ati/ragexl/xlinit.c Mon Nov 22 09:09:50 2010 (r6111) @@ -21,6 +21,13 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> +// FIXME BTEXT console within coreboot has been obsoleted +// and will go away. The BTEXT code in this file should be +// fixed to export a framebuffer console through the coreboot +// table (and possibly make it available for bootsplash use) +// Hence do only remove this if you fix the code. +#define CONFIG_CONSOLE_BTEXT 0 + #if CONFIG_CONSOLE_BTEXT==1 #define PLL_CRTC_DECODE 0 Modified: trunk/src/drivers/emulation/qemu/init.c ============================================================================== --- trunk/src/drivers/emulation/qemu/init.c Mon Nov 22 01:42:42 2010 (r6110) +++ trunk/src/drivers/emulation/qemu/init.c Mon Nov 22 09:09:50 2010 (r6111) @@ -9,19 +9,6 @@ #include <device/pci_ids.h> #include <device/pci_ops.h> -#if CONFIG_CONSOLE_BTEXT==1 - -#define PLL_CRTC_DECODE 0 -#define SUPPORT_8_BPP_ABOVE 0 - -#include "fb.h" -#include "fbcon.h" - -#include <console/btext.h> - -#endif /*CONFIG_CONSOLE_BTEXT*/ - - /* VGA init. We use the Bochs VESA VBE extensions */ #define VBE_DISPI_INDEX_ID 0x0 #define VBE_DISPI_INDEX_XRES 0x1 Modified: trunk/src/include/boot/coreboot_tables.h ============================================================================== --- trunk/src/include/boot/coreboot_tables.h Mon Nov 22 01:42:42 2010 (r6110) +++ trunk/src/include/boot/coreboot_tables.h Mon Nov 22 09:09:50 2010 (r6111) @@ -158,10 +158,10 @@ }; #define LB_TAG_CONSOLE_SERIAL8250 0 -#define LB_TAG_CONSOLE_VGA 1 -#define LB_TAG_CONSOLE_BTEXT 2 +#define LB_TAG_CONSOLE_VGA 1 // OBSOLETE +#define LB_TAG_CONSOLE_BTEXT 2 // OBSOLETE #define LB_TAG_CONSOLE_LOGBUF 3 -#define LB_TAG_CONSOLE_SROM 4 +#define LB_TAG_CONSOLE_SROM 4 // OBSOLETE #define LB_TAG_CONSOLE_EHCI 5 #define LB_TAG_FORWARD 0x0011 Modified: trunk/src/include/console/console.h ============================================================================== --- trunk/src/include/console/console.h Mon Nov 22 01:42:42 2010 (r6110) +++ trunk/src/include/console/console.h Mon Nov 22 09:09:50 2010 (r6111) @@ -28,9 +28,6 @@ void console_tx_flush(void); unsigned char console_rx_byte(void); int console_tst_byte(void); -#if CONFIG_CONSOLE_VGA == 1 -void vga_console_init(void); -#endif #if CONFIG_USBDEBUG #include <usbdebug.h> #endif @@ -356,6 +353,8 @@ #ifdef __ROMCC__ /* if included by romcc, include the sources, too. romcc can't use prototypes */ #include <console/console.c> +#include <console/post.c> +#include <console/die.c> #endif #endif /* CONSOLE_CONSOLE_H_ */ Modified: trunk/src/mainboard/msi/ms9652_fam10/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/Kconfig Mon Nov 22 01:42:42 2010 (r6110) +++ trunk/src/mainboard/msi/ms9652_fam10/Kconfig Mon Nov 22 09:09:50 2010 (r6111) @@ -128,10 +128,6 @@ bool default y -config CONSOLE_VGA - bool - default y - config PCI_ROM_RUN bool default y Modified: trunk/src/northbridge/amd/amdfam10/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdfam10/northbridge.c Mon Nov 22 01:42:42 2010 (r6110) +++ trunk/src/northbridge/amd/amdfam10/northbridge.c Mon Nov 22 09:09:50 2010 (r6111) @@ -545,13 +545,9 @@ } /** - * * I tried to reuse the resource allocation code in amdfam10_set_resource() - * but it is too diffcult to deal with the resource allocation magic. + * but it is too difficult to deal with the resource allocation magic. */ -#if CONFIG_CONSOLE_VGA_MULTI == 1 -extern device_t vga_pri; // the primary vga device, defined in device.c -#endif static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) { @@ -561,7 +557,8 @@ * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_CONSOLE_VGA_MULTI == 1 +#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1 + extern device_t vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ Modified: trunk/src/northbridge/amd/amdk8/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/northbridge.c Mon Nov 22 01:42:42 2010 (r6110) +++ trunk/src/northbridge/amd/amdk8/northbridge.c Mon Nov 22 09:09:50 2010 (r6111) @@ -485,10 +485,6 @@ report_resource_stored(dev, resource, buf); } -#if CONFIG_CONSOLE_VGA_MULTI == 1 -extern device_t vga_pri; // the primary vga device, defined in device.c -#endif - static void amdk8_create_vga_resource(device_t dev, unsigned nodeid) { struct resource *resource; @@ -498,7 +494,8 @@ * we only deal with the 'first' vga card */ for (link = dev->link_list; link; link = link->next) { if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG_CONSOLE_VGA_MULTI == 1 +#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1 + extern device_t vga_pri; // the primary vga device, defined in device.c printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary, link->secondary,link->subordinate); /* We need to make sure the vga_pri is under the link */ Modified: trunk/src/southbridge/via/k8t890/k8m890_chrome.c ============================================================================== --- trunk/src/southbridge/via/k8t890/k8m890_chrome.c Mon Nov 22 01:42:42 2010 (r6110) +++ trunk/src/southbridge/via/k8t890/k8m890_chrome.c Mon Nov 22 09:09:50 2010 (r6111) @@ -150,17 +150,10 @@ vga_textmode_init(); -#if CONFIG_CONSOLE_VGA == 1 - vga_console_init(); -#endif - printk(BIOS_INFO, "Chrome VGA Textmode initialized.\n"); -#if CONFIG_CONSOLE_VGA == 0 /* if we don't have console, at least print something... */ vga_line_write(0, "Chrome VGA Textmode initialized."); -#endif - #endif /* CONFIG_VGA */ }

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[PATCH] i855: Remove useless memctrl indirection
by Uwe Hermann 22 Nov '10

22 Nov '10

See patch. Build-tested on the two affected boards. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r6110 - trunk/src/arch/i386/include/arch
by repository service 22 Nov '10

22 Nov '10

Author: uwe Date: Mon Nov 22 01:42:42 2010 New Revision: 6110 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6110 Log: acpi.h: Small fixes and adding comments. - Mention full name of all the tables (SSDT, FADT, etc). - Drop obsolete / incorrect "LXBIOS" reference. - Add missing ACPI address space type #defines specified in newer versions: ACPI_ADDRESS_SPACE_EC, ACPI_ADDRESS_SPACE_SMBUS. - Add missing "enum acpi_apic_types" entries: Localx2Apic, Localx2ApicNMI. - Add ACPI_FACS_64BIT_WAKE_F #define. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/arch/i386/include/arch/acpi.h Modified: trunk/src/arch/i386/include/arch/acpi.h ============================================================================== --- trunk/src/arch/i386/include/arch/acpi.h Sun Nov 21 23:55:46 2010 (r6109) +++ trunk/src/arch/i386/include/arch/acpi.h Mon Nov 22 01:42:42 2010 (r6110) @@ -21,7 +21,7 @@ */ /* - * coreboot ACPI Support - headers and defines. + * coreboot ACPI support - headers and defines. */ #ifndef __ASM_ACPI_H @@ -31,73 +31,73 @@ #include <stdint.h> -#define RSDP_SIG "RSD PTR " /* RSDT Pointer signature */ -#define ACPI_TABLE_CREATOR "COREBOOT" -#define OEM_ID "CORE " -#define ASLC "CORE" - -/* ACPI 3.0 table RSDP */ +#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ +#define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ +#define OEM_ID "CORE " /* Must be exactly 6 bytes long! */ +#define ASLC "CORE" /* Must be exactly 4 bytes long! */ +/* RSDP (Root System Description Pointer) */ typedef struct acpi_rsdp { - char signature[8]; /* RSDP signature "RSD PTR" */ - u8 checksum; /* checksum of the first 20 bytes */ - char oem_id[6]; /* OEM ID, "LXBIOS" */ - u8 revision; /* 0 for ACPI 1.0, 2 for ACPI 2.0/3.0 */ - u32 rsdt_address; /* physical address of RSDT */ - u32 length; /* total length of RSDP (including extended part) */ - u64 xsdt_address; /* physical address of XSDT */ - u8 ext_checksum; /* chechsum of whole table */ + char signature[8]; /* RSDP signature */ + u8 checksum; /* Checksum of the first 20 bytes */ + char oem_id[6]; /* OEM ID */ + u8 revision; /* 0 for ACPI 1.0, 2 for ACPI 2.0/3.0/4.0 */ + u32 rsdt_address; /* Physical address of RSDT (32 bits) */ + u32 length; /* Total RSDP length (incl. extended part) */ + u64 xsdt_address; /* Physical address of XSDT (64 bits) */ + u8 ext_checksum; /* Checksum of the whole table */ u8 reserved[3]; -} __attribute__((packed)) acpi_rsdp_t; - -/* Generic Address Container */ +} __attribute__ ((packed)) acpi_rsdp_t; +/* Note: ACPI 1.0 didn't have length, xsdt_address, and ext_checksum. */ +/* GAS (Generic Address Structure) */ typedef struct acpi_gen_regaddr { - u8 space_id; - u8 bit_width; - u8 bit_offset; - u8 resv; - u32 addrl; - u32 addrh; + u8 space_id; /* Address space ID */ + u8 bit_width; /* Register size in bits */ + u8 bit_offset; /* Register bit offset */ + u8 resv; /* FIXME: Access size in ACPI 2.0/3.0/4.0 */ + u32 addrl; /* Register address, low 32 bits */ + u32 addrh; /* Register address, high 32 bits */ } __attribute__ ((packed)) acpi_addr_t; -#define ACPI_ADDRESS_SPACE_MEMORY 0 -#define ACPI_ADDRESS_SPACE_IO 1 -#define ACPI_ADDRESS_SPACE_PCI 2 -#define ACPI_ADDRESS_SPACE_FIXED 0x7f - - -/* Generic ACPI Header, provided by (almost) all tables */ - -typedef struct acpi_table_header /* ACPI common table header */ -{ - char signature [4]; /* ACPI signature (4 ASCII characters) */\ - u32 length; /* Length of table, in bytes, including header */\ - u8 revision; /* ACPI Specification minor version # */\ - u8 checksum; /* To make sum of entire table == 0 */\ - char oem_id [6]; /* OEM identification */\ - char oem_table_id [8]; /* OEM table identification */\ - u32 oem_revision; /* OEM revision number */\ - char asl_compiler_id [4]; /* ASL compiler vendor ID */\ +#define ACPI_ADDRESS_SPACE_MEMORY 0 /* System memory */ +#define ACPI_ADDRESS_SPACE_IO 1 /* System I/O */ +#define ACPI_ADDRESS_SPACE_PCI 2 /* PCI config space */ +#define ACPI_ADDRESS_SPACE_EC 3 /* Embedded controller */ +#define ACPI_ADDRESS_SPACE_SMBUS 4 /* SMBus */ +#define ACPI_ADDRESS_SPACE_FIXED 0x7f /* Functional fixed hardware */ +/* 0x80-0xbf: Reserved */ +/* 0xc0-0xff: OEM defined */ + +/* Generic ACPI header, provided by (almost) all tables */ +typedef struct acpi_table_header { + char signature[4]; /* ACPI signature (4 ASCII characters) */ + u32 length; /* Table length in bytes (incl. header) */ + u8 revision; /* Table version (not ACPI version!) */ + u8 checksum; /* To make sum of entire table == 0 */ + char oem_id[6]; /* OEM identification */ + char oem_table_id[8]; /* OEM table identification */ + u32 oem_revision; /* OEM revision number */ + char asl_compiler_id[4]; /* ASL compiler vendor ID */ u32 asl_compiler_revision; /* ASL compiler revision number */ } __attribute__ ((packed)) acpi_header_t; -/* A maximum number of 32 ACPI tables ought to be enough for now */ +/* A maximum number of 32 ACPI tables ought to be enough for now. */ #define MAX_ACPI_TABLES 32 -/* RSDT */ +/* RSDT (Root System Description Table) */ typedef struct acpi_rsdt { struct acpi_table_header header; u32 entry[MAX_ACPI_TABLES]; } __attribute__ ((packed)) acpi_rsdt_t; -/* XSDT */ +/* XSDT (Extended System Description Table) */ typedef struct acpi_xsdt { struct acpi_table_header header; u64 entry[MAX_ACPI_TABLES]; } __attribute__ ((packed)) acpi_xsdt_t; -/* HPET TIMERS */ +/* HPET timers */ typedef struct acpi_hpet { struct acpi_table_header header; u32 id; @@ -107,7 +107,7 @@ u8 attributes; } __attribute__ ((packed)) acpi_hpet_t; -/* MCFG */ +/* MCFG (PCI Express MMIO config space BAR description table) */ typedef struct acpi_mcfg { struct acpi_table_header header; u8 reserved[8]; @@ -122,104 +122,111 @@ u8 reserved[4]; } __attribute__ ((packed)) acpi_mcfg_mmconfig_t; - -/* SRAT */ +/* SRAT (System Resource Affinity Table) */ typedef struct acpi_srat { - struct acpi_table_header header; - u32 resv; + struct acpi_table_header header; + u32 resv; u64 resv1; - /* followed by static resource allocation structure[n]*/ + /* Followed by static resource allocation structure[n] */ } __attribute__ ((packed)) acpi_srat_t; - +/* SRAT: Processor Local APIC/SAPIC Affinity Structure */ typedef struct acpi_srat_lapic { - u8 type; - u8 length; - u8 proximity_domain_7_0; - u8 apic_id; - u32 flags; /* enable bit 0 = 1, other bits reserved to 0 */ - u8 local_sapic_eid; - u8 proximity_domain_31_8[3]; - u32 resv; + u8 type; /* Type (0) */ + u8 length; /* Length in bytes (16) */ + u8 proximity_domain_7_0; /* Proximity domain bits[7:0] */ + u8 apic_id; /* Local APIC ID */ + u32 flags; /* Enable bit 0 = 1, other bits reserved to 0 */ + u8 local_sapic_eid; /* Local SAPIC EID */ + u8 proximity_domain_31_8[3]; /* Proximity domain bits[31:8] */ + u32 resv; /* TODO: Clock domain in ACPI 4.0. */ } __attribute__ ((packed)) acpi_srat_lapic_t; +/* SRAT: Memory Affinity Structure */ typedef struct acpi_srat_mem { - u8 type; - u8 length; - u32 proximity_domain; - u16 resv; - u32 base_address_low; - u32 base_address_high; - u32 length_low; - u32 length_high; + u8 type; /* Type (1) */ + u8 length; /* Length in bytes (40) */ + u32 proximity_domain; /* Proximity domain */ + u16 resv; + u32 base_address_low; /* Mem range base address, low */ + u32 base_address_high; /* Mem range base address, high */ + u32 length_low; /* Mem range length, low */ + u32 length_high; /* Mem range length, high */ u32 resv1; - u32 flags; /* enable bit 0, hot pluggable bit 1; Non Volatile bit 2, other bits reserved */ - u32 resv2[2]; + u32 flags; /* Enable bit 0, hot pluggable bit 1; Non Volatile bit 2, other bits reserved to 0 */ + u32 resv2[2]; } __attribute__ ((packed)) acpi_srat_mem_t; -/* SLIT */ +/* SLIT (System Locality Distance Information Table) */ typedef struct acpi_slit { - struct acpi_table_header header; - /* followed by static resource allocation 8+byte[num*num]*/ + struct acpi_table_header header; + /* Followed by static resource allocation 8+byte[num*num] */ } __attribute__ ((packed)) acpi_slit_t; - -/* MADT */ +/* MADT (Multiple APIC Description Table) */ typedef struct acpi_madt { struct acpi_table_header header; - u32 lapic_addr; - u32 flags; + u32 lapic_addr; /* Local APIC address */ + u32 flags; /* Multiple APIC flags */ } __attribute__ ((packed)) acpi_madt_t; +/* MADT: APIC Structure Types */ +/* TODO: Convert to ALLCAPS. */ enum acpi_apic_types { - LocalApic = 0, - IOApic = 1, - IRQSourceOverride = 2, - NMIType = 3, - LocalApicNMI = 4, - LApicAddressOverride = 5, - IOSApic = 6, - LocalSApic = 7, - PlatformIRQSources = 8 + LocalApic = 0, /* Processor local APIC */ + IOApic = 1, /* I/O APIC */ + IRQSourceOverride = 2, /* Interrupt source override */ + NMIType = 3, /* NMI source */ + LocalApicNMI = 4, /* Local APIC NMI */ + LApicAddressOverride = 5, /* Local APIC address override */ + IOSApic = 6, /* I/O SAPIC */ + LocalSApic = 7, /* Local SAPIC */ + PlatformIRQSources = 8, /* Platform interrupt sources */ + Localx2Apic = 9, /* Processor local x2APIC */ + Localx2ApicNMI = 10, /* Local x2APIC NMI */ + /* 0x0b-0x7f: Reserved */ + /* 0x80-0xff: Reserved for OEM use */ }; +/* MADT: Processor Local APIC Structure */ typedef struct acpi_madt_lapic { - u8 type; - u8 length; - u8 processor_id; - u8 apic_id; - u32 flags; + u8 type; /* Type (0) */ + u8 length; /* Length in bytes (8) */ + u8 processor_id; /* ACPI processor ID */ + u8 apic_id; /* Local APIC ID */ + u32 flags; /* Local APIC flags */ } __attribute__ ((packed)) acpi_madt_lapic_t; +/* MADT: Local APIC NMI Structure */ typedef struct acpi_madt_lapic_nmi { - u8 type; - u8 length; - u8 processor_id; - u16 flags; - u8 lint; + u8 type; /* Type (4) */ + u8 length; /* Length in bytes (6) */ + u8 processor_id; /* ACPI processor ID */ + u16 flags; /* MPS INTI flags */ + u8 lint; /* Local APIC LINT# */ } __attribute__ ((packed)) acpi_madt_lapic_nmi_t; - +/* MADT: I/O APIC Structure */ typedef struct acpi_madt_ioapic { - u8 type; - u8 length; - u8 ioapic_id; + u8 type; /* Type (1) */ + u8 length; /* Length in bytes (12) */ + u8 ioapic_id; /* I/O APIC ID */ u8 reserved; - u32 ioapic_addr; - u32 gsi_base; + u32 ioapic_addr; /* I/O APIC address */ + u32 gsi_base; /* Global system interrupt base */ } __attribute__ ((packed)) acpi_madt_ioapic_t; +/* MADT: Interrupt Source Override Structure */ typedef struct acpi_madt_irqoverride { - u8 type; - u8 length; - u8 bus; - u8 source; - u32 gsirq; - u16 flags; + u8 type; /* Type (2) */ + u8 length; /* Length in bytes (10) */ + u8 bus; /* ISA (0) */ + u8 source; /* Bus-relative int. source (IRQ) */ + u32 gsirq; /* Global system interrupt */ + u16 flags; /* MPS INTI flags */ } __attribute__ ((packed)) acpi_madt_irqoverride_t; -/* FADT */ - +/* FADT (Fixed ACPI Description Table) */ typedef struct acpi_fadt { struct acpi_table_header header; u32 firmware_ctrl; @@ -272,16 +279,14 @@ struct acpi_gen_regaddr x_pm1a_evt_blk; struct acpi_gen_regaddr x_pm1b_evt_blk; struct acpi_gen_regaddr x_pm1a_cnt_blk; - struct acpi_gen_regaddr x_pm1b_cnt_blk; + struct acpi_gen_regaddr x_pm1b_cnt_blk; struct acpi_gen_regaddr x_pm2_cnt_blk; struct acpi_gen_regaddr x_pm_tmr_blk; struct acpi_gen_regaddr x_gpe0_blk; struct acpi_gen_regaddr x_gpe1_blk; } __attribute__ ((packed)) acpi_fadt_t; -// -// FADT Feature Flags -// +/* FADT Feature Flags */ #define ACPI_FADT_WBINVD (1 << 0) #define ACPI_FADT_WBINVD_FLUSH (1 << 1) #define ACPI_FADT_C1_SUPPORTED (1 << 2) @@ -302,19 +307,16 @@ #define ACPI_FADT_REMOTE_POWER_ON (1 << 17) #define ACPI_FADT_APIC_CLUSTER (1 << 18) #define ACPI_FADT_APIC_PHYSICAL (1 << 19) +/* Bits 20-31: reserved */ -// -// FADT Boot Architecture Flags -// +/* FADT Boot Architecture Flags */ #define ACPI_FADT_LEGACY_DEVICES (1 << 0) #define ACPI_FADT_8042 (1 << 1) #define ACPI_FADT_VGA_NOT_PRESENT (1 << 2) #define ACPI_FADT_MSI_NOT_SUPPORTED (1 << 3) #define ACPI_FADT_NO_PCIE_ASPM_CONTROL (1 << 4) -// -// FADT Preferred Power Management Profile -// +/* FADT Preferred Power Management Profile */ enum acpi_preferred_pm_profiles { PM_UNSPECIFIED = 0, PM_DESKTOP = 1, @@ -323,71 +325,74 @@ PM_ENTERPRISE_SERVER = 4, PM_SOHO_SERVER = 5, PM_APPLIANCE_PC = 6, - PM_PERFORMANCE_SERVER = 7 + PM_PERFORMANCE_SERVER = 7, }; -/* FACS */ +/* FACS (Firmware ACPI Control Structure) */ typedef struct acpi_facs { - char signature[4]; - u32 length; - u32 hardware_signature; - u32 firmware_waking_vector; - u32 global_lock; - u32 flags; - u32 x_firmware_waking_vector_l; - u32 x_firmware_waking_vector_h; - u8 version; - u8 resv[31]; + char signature[4]; /* "FACS" */ + u32 length; /* Length in bytes (>= 64) */ + u32 hardware_signature; /* Hardware signature */ + u32 firmware_waking_vector; /* Firmware waking vector */ + u32 global_lock; /* Global lock */ + u32 flags; /* FACS flags */ + u32 x_firmware_waking_vector_l; /* X FW waking vector, low */ + u32 x_firmware_waking_vector_h; /* X FW waking vector, high */ + u8 version; /* ACPI 4.0: 2 */ + u8 resv[31]; /* FIXME: 4.0: ospm_flags */ } __attribute__ ((packed)) acpi_facs_t; -// -// FACS Flags -// +/* FACS flags */ #define ACPI_FACS_S4BIOS_F (1 << 0) +#define ACPI_FACS_64BIT_WAKE_F (1 << 1) +/* Bits 31..2: reserved */ +/* ECDT (Embedded Controller Boot Resources Table) */ typedef struct acpi_ecdt { struct acpi_table_header header; - struct acpi_gen_regaddr ec_control; - struct acpi_gen_regaddr ec_data; - u32 uid; - u8 gpe_bit; - u8 ec_id[]; + struct acpi_gen_regaddr ec_control; /* EC control register */ + struct acpi_gen_regaddr ec_data; /* EC data register */ + u32 uid; /* UID */ + u8 gpe_bit; /* GPE bit */ + u8 ec_id[]; /* EC ID */ } __attribute__ ((packed)) acpi_ecdt_t; - -/* These are implemented by the target port or north/southbridge*/ +/* These are implemented by the target port or north/southbridge. */ unsigned long write_acpi_tables(unsigned long addr); unsigned long acpi_fill_madt(unsigned long current); unsigned long acpi_fill_mcfg(unsigned long current); unsigned long acpi_fill_srat(unsigned long current); unsigned long acpi_fill_slit(unsigned long current); -unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id); +unsigned long acpi_fill_ssdt_generator(unsigned long current, + const char *oem_table_id); void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id); void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt); -void update_ssdt(void* ssdt); -void update_ssdtx(void* ssdtx, int i); +void update_ssdt(void *ssdt); +void update_ssdtx(void *ssdtx, int i); -/* These can be used by the target port */ +/* These can be used by the target port. */ u8 acpi_checksum(u8 *table, u32 length); void acpi_add_table(acpi_rsdp_t *rsdp, void *table); - int acpi_create_madt_lapic(acpi_madt_lapic_t *lapic, u8 cpu, u8 apic); -int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr,u32 gsi_base); +int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, + u32 gsi_base); int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, - u8 bus, u8 source, u32 gsirq, u16 flags); + u8 bus, u8 source, u32 gsirq, u16 flags); int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, - u16 flags, u8 lint); + u16 flags, u8 lint); void acpi_create_madt(acpi_madt_t *madt); unsigned long acpi_create_madt_lapics(unsigned long current); -unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint); - +unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, + u8 lint); int acpi_create_srat_lapic(acpi_srat_lapic_t *lapic, u8 node, u8 apic); -int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek,u32 sizek, u32 flags); -int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, u16 seg_nr, u8 start, u8 end); +int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek,u32 sizek, + u32 flags); +int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u32 base, + u16 seg_nr, u8 start, u8 end); unsigned long acpi_create_srat_lapics(unsigned long current); void acpi_create_srat(acpi_srat_t *srat); @@ -422,18 +427,19 @@ /* northbridge/amd/amdfam10/amdfam10_acpi.c */ unsigned long acpi_add_ssdt_pstates(acpi_rsdp_t *rsdp, unsigned long current); + /* cpu/intel/speedstep/acpi.c */ void generate_cpu_entries(void); -#define ACPI_WRITE_MADT_IOAPIC(dev,id) \ -do { \ - struct resource *res; \ - res = find_resource(dev, PCI_BASE_ADDRESS_0); \ - if (!res) break; \ +#define ACPI_WRITE_MADT_IOAPIC(dev,id) \ +do { \ + struct resource *res; \ + res = find_resource(dev, PCI_BASE_ADDRESS_0); \ + if (!res) break; \ current += acpi_create_madt_ioapic( \ (acpi_madt_ioapic_t *)current, \ id, res->base, gsi_base); \ - gsi_base+=4; \ + gsi_base += 4; \ } while(0); #else // CONFIG_GENERATE_ACPI_TABLES

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[commit] r6109 - trunk/src/southbridge/nvidia/ck804
by repository service 21 Nov '10

21 Nov '10

Author: jakllsch Date: Sun Nov 21 23:55:46 2010 New Revision: 6109 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6109 Log: Move CK804_PCI_E_X and CK804B_PCI_E_X defines (which have been 4 by default on all boards) into Kconfig. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/southbridge/nvidia/ck804/Kconfig trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Modified: trunk/src/southbridge/nvidia/ck804/Kconfig ============================================================================== --- trunk/src/southbridge/nvidia/ck804/Kconfig Sun Nov 21 23:47:22 2010 (r6108) +++ trunk/src/southbridge/nvidia/ck804/Kconfig Sun Nov 21 23:55:46 2010 (r6109) @@ -5,30 +5,42 @@ select IOAPIC select TINY_BOOTBLOCK +if SOUTHBRIDGE_NVIDIA_CK804 + config BOOTBLOCK_SOUTHBRIDGE_INIT string - default "southbridge/nvidia/ck804/bootblock.c" if SOUTHBRIDGE_NVIDIA_CK804 + default "southbridge/nvidia/ck804/bootblock.c" config ID_SECTION_OFFSET hex - default 0x80 if SOUTHBRIDGE_NVIDIA_CK804 + default 0x80 config EHCI_BAR hex - default 0xfef00000 if SOUTHBRIDGE_NVIDIA_CK804 + default 0xfef00000 config EHCI_DEBUG_OFFSET hex - default 0x98 if SOUTHBRIDGE_NVIDIA_CK804 + default 0x98 config CK804_USE_NIC bool - default n if SOUTHBRIDGE_NVIDIA_CK804 + default n config CK804_USE_ACI bool - default n if SOUTHBRIDGE_NVIDIA_CK804 + default n + +config CK804_PCI_E_X + int + default 4 + +config CK804B_PCI_E_X + int + default 4 config CK804_NUM int - default 1 if SOUTHBRIDGE_NVIDIA_CK804 + default 1 + +endif Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c Sun Nov 21 23:47:22 2010 (r6108) +++ trunk/src/southbridge/nvidia/ck804/ck804_early_setup.c Sun Nov 21 23:55:46 2010 (r6109) @@ -56,16 +56,15 @@ #define SYSCTRL_REG_POS 0x64 /* + * Values for CONFIG_CK804_PCI_E_X and CONFIG_CK804B_PCI_E_X. + * Apparently some sort of lane configuration. + * * 16 1 1 2 :0 * 8 8 2 2 :1 * 8 8 4 :2 * 8 4 4 4 :3 * 16 4 :4 -*/ - -#ifndef CK804_PCI_E_X -#define CK804_PCI_E_X 4 -#endif + */ #if CONFIG_CK804_NUM > 1 #define CK804B_ANACTRL_IO_BASE (ANACTRL_IO_BASE + 0x8000) @@ -73,9 +72,6 @@ #ifndef CK804B_BUSN #define CK804B_BUSN 0x80 #endif -#ifndef CK804B_PCI_E_X -#define CK804B_PCI_E_X 4 -#endif #endif #define CK804_CHIP_REV 3 @@ -258,9 +254,9 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8), #if CONFIG_CK804_NUM > 1 - RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8), + RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8), #endif RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), Modified: trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c ============================================================================== --- trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Sun Nov 21 23:47:22 2010 (r6108) +++ trunk/src/southbridge/nvidia/ck804/ck804_early_setup_car.c Sun Nov 21 23:55:46 2010 (r6109) @@ -54,20 +54,15 @@ #define SYSCTRL_REG_POS 0x64 /* + * Values for CONFIG_CK804_PCI_E_X and CONFIG_CK804B_PCI_E_X. + * Apparently some sort of lane configuration. + * * 16 1 1 2 :0 * 8 8 2 2 :1 * 8 8 4 :2 * 8 4 4 4 :3 * 16 4 :4 -*/ - -#ifndef CK804_PCI_E_X -#define CK804_PCI_E_X 4 -#endif - -#ifndef CK804B_PCI_E_X -#define CK804B_PCI_E_X 4 -#endif + */ #define CK804_CHIP_REV 3 @@ -199,7 +194,7 @@ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804_PCI_E_X << 4) | (1 << 8), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804_PCI_E_X << 4) | (1 << 8), //SYSCTRL RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0 + 8, ~(0xff), ((0 << 4) | (0 << 2) | (0 << 0)), @@ -275,7 +270,7 @@ /* This line doesn't exist in the non-CAR version. */ RES_PORT_IO_32, ANACTRL_IO_BASE + 0x80, ~(1 << 3), 0x00000000, - RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CK804B_PCI_E_X << 4) | (1 << 8), + RES_PORT_IO_32, ANACTRL_IO_BASE + 0xcc, ~((7 << 4) | (1 << 8)), (CONFIG_CK804B_PCI_E_X << 4) | (1 << 8), #if CONFIG_CK804_USE_NIC RES_PCI_IO, PCI_ADDR(0, 0xa, 0, 0xf8), 0xffffffbf, 0x00000040,

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coreboot November 2010