coreboot November 2010

coreboot@coreboot.org

48 participants
285 discussions

any coreboot plans to support SuperMicro X7DVL-E?
by Fontaine, Eric R 26 Nov '10

26 Nov '10

Dear Coreboot Developers, I am very impressed with coreboot and agree with the importance of open source firmware. I am looking at your list of supported server motherboards, and see support for SuperMicro X6D series, but do not see any support for the board I am using, the X7DVL-E. I included at the bottom of this email my machine specs. My questions are: - is anyone in the process of porting code for this board? - if yes, then when do you think it will be done? - if no, then approximately how much programming effort does it typically take one of you to port coreboot to a new system, in case I decide to port it myself? - would you estimate if most of the X6D series firmware code can be reused, or would I most likely have to rewrite everything? For a little background, I am a doctoral Computer Engineering student at Georgia Tech working on a research project to identify and breakdown the power consumption breakdown of servers. I am currently using a modified gPXE (etherboot.org) network bootloader to allow me to access to the network controller to isolate and measure its power consumption under different workloads, and I am using a modified 16kb x86-64 BareMetal OS (http://www.returninfinity.com/baremetal.html) to isolate each core's power consumption and try to break down power consumption by cpu component. Anyway, I am hoping coreboot will help me selectively turn on and off or stress different motherboard components. -Eric Fontaine My machine specs (as requested by http://www.coreboot.org/FAQ#Will_coreboot_work_on_my_machine.3F): Step 1: A very brief description of your system: - board vendor, SuperMicro - board name, X7DVL-E - CPU, dual socket "Intel(R) Xeon(R) CPU E5335 @ 2.00GHz" - northbridge, Intel 5000V Northbridge - southbridge, Intel MCH + ESB2 Southbridge Step 2: Linux "lspci -tvnn" output for your system, generated by booting Linux via the original BIOS and runnning lspci. -[0000:00]-+-00.0 Intel Corporation 5000V Chipset Memory Controller Hub [8086:25d4] +-02.0-[0000:01-05]--+-00.0-[0000:02-04]--+-00.0-[0000:03]-- | | \-02.0-[0000:04]--+-00.0 Intel Corporation 80003ES2LAN Gigabit Ethernet Controller (Copper) [8086:1096] | | \-00.1 Intel Corporation 80003ES2LAN Gigabit Ethernet Controller (Copper) [8086:1096] | \-00.3-[0000:05]-- +-08.0 Intel Corporation 5000 Series Chipset DMA Engine [8086:1a38] +-10.0 Intel Corporation 5000 Series Chipset FSB Registers [8086:25f0] +-10.1 Intel Corporation 5000 Series Chipset FSB Registers [8086:25f0] +-10.2 Intel Corporation 5000 Series Chipset FSB Registers [8086:25f0] +-11.0 Intel Corporation 5000 Series Chipset Reserved Registers [8086:25f1] +-13.0 Intel Corporation 5000 Series Chipset Reserved Registers [8086:25f3] +-15.0 Intel Corporation 5000 Series Chipset FBD Registers [8086:25f5] +-16.0 Intel Corporation 5000 Series Chipset FBD Registers [8086:25f6] +-1c.0-[0000:06]-- +-1d.0 Intel Corporation 631xESB/632xESB/3100 Chipset UHCI USB Controller #1 [8086:2688] +-1d.1 Intel Corporation 631xESB/632xESB/3100 Chipset UHCI USB Controller #2 [8086:2689] +-1d.2 Intel Corporation 631xESB/632xESB/3100 Chipset UHCI USB Controller #3 [8086:268a] +-1d.3 Intel Corporation 631xESB/632xESB/3100 Chipset UHCI USB Controller #4 [8086:268b] +-1d.7 Intel Corporation 631xESB/632xESB/3100 Chipset EHCI USB2 Controller [8086:268c] +-1e.0-[0000:07]----01.0 ATI Technologies Inc ES1000 [1002:515e] +-1f.0 Intel Corporation 631xESB/632xESB/3100 Chipset LPC Interface Controller [8086:2670] +-1f.1 Intel Corporation 631xESB/632xESB IDE Controller [8086:269e] +-1f.2 Intel Corporation 631xESB/632xESB/3100 Chipset SATA IDE Controller [8086:2680] \-1f.3 Intel Corporation 631xESB/632xESB/3100 Chipset SMBus Controller [8086:269b] Step 3: Super I/O chip on the mainboard (report the model numbers on the actual chip, for example "Winbond W83627HF" and/or run "superiotool -dV"). superiotool r3844 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xc4fe, id=0x4152 Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x5241, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Found Winbond W83627HF/F/HG/G (id=0x52, rev=0x41) at 0x2e Register dump: idx 02 20 21 22 23 24 25 26 28 29 2a 2b 2c 2e 2f val ff 52 41 ff fe c4 00 00 00 50 fc 00 ff 00 ff def 00 52 NA ff 00 MM 00 00 00 00 7c c0 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 f2 f4 f5 val 01 03 f0 06 02 0e 00 ff 00 00 def 01 03 f0 06 02 0e 00 ff 00 00 LDN 0x01 (Parallel port) idx 30 60 61 70 74 f0 val 01 03 78 05 01 3a def 01 03 78 07 04 3f LDN 0x02 (COM1) idx 30 60 61 70 f0 val 01 03 f8 04 00 def 01 03 f8 04 00 LDN 0x03 (COM2) idx 30 60 61 70 f0 f1 val 01 02 f8 03 00 40 def 01 02 f8 03 00 00 LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 72 f0 val 01 00 60 00 64 01 0c 80 def 01 00 60 00 64 01 0c 80 LDN 0x06 (Consumer IR) idx 30 60 61 70 val 00 00 00 00 def 00 00 00 00 LDN 0x07 (Game port, MIDI port, GPIO 1) idx 30 60 61 62 63 70 f0 f1 f2 val 01 00 00 00 00 00 ff ff 00 def 00 02 01 03 30 09 ff 00 00 LDN 0x08 (GPIO 2, Watchdog timer) idx 30 f0 f1 f2 f3 f5 f6 f6 f7 val 00 ff ff ff 00 08 00 00 c0 def 00 ff 00 00 00 00 00 00 00 LDN 0x09 (GPIO 3) idx 30 f0 f1 f2 f3 val 01 ff 14 00 40 def 00 ff 00 00 00 LDN 0x0a (ACPI) idx 30 70 e0 e1 e2 e3 e4 e5 e6 e7 f0 f1 f3 f4 f6 f7 f9 fe ff val 01 00 00 00 37 26 40 00 00 00 00 af 33 00 00 00 00 00 00 def 00 00 00 00 NA NA 00 00 00 00 00 00 00 00 00 00 00 00 00 LDN 0x0b (Hardware monitor) idx 30 60 61 70 f0 val 01 02 95 00 01 def 00 00 00 00 00 Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Step 4: Type of BIOS device (see the question "How do I identify the BIOS chip on my mainboard?" below). Please send us the output of "flashrom -V" flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "Supermicro" DMI string system-product-name: "X7DVL" DMI string system-version: "0123456789" DMI string baseboard-manufacturer: "Supermicro" DMI string baseboard-product-name: "X7DVL" DMI string baseboard-version: "PCB Version" DMI string chassis-type: "Other" Found chipset "Intel 631xESB/632xESB/3100", enabling flash write... 0xfff80000/0xffb80000 FWH IDSEL: 0x0 0xfff00000/0xffb00000 FWH IDSEL: 0x0 0xffe80000/0xffa80000 FWH IDSEL: 0x1 0xffe00000/0xffa00000 FWH IDSEL: 0x1 0xffd80000/0xff980000 FWH IDSEL: 0x2 0xffd00000/0xff900000 FWH IDSEL: 0x2 0xffc80000/0xff880000 FWH IDSEL: 0x3 0xffc00000/0xff800000 FWH IDSEL: 0x3 0xff700000/0xff300000 FWH IDSEL: 0x4 0xff600000/0xff200000 FWH IDSEL: 0x5 0xff500000/0xff100000 FWH IDSEL: 0x6 0xff400000/0xff000000 FWH IDSEL: 0x7 0xfff80000/0xffb80000 FWH decode enabled 0xfff00000/0xffb00000 FWH decode enabled 0xffe80000/0xffa80000 FWH decode enabled 0xffe00000/0xffa00000 FWH decode enabled 0xffd80000/0xff980000 FWH decode enabled 0xffd00000/0xff900000 FWH decode enabled 0xffc80000/0xff880000 FWH decode enabled 0xffc00000/0xff800000 FWH decode enabled 0xff700000/0xff300000 FWH decode enabled 0xff600000/0xff200000 FWH decode enabled 0xff500000/0xff100000 FWH decode enabled 0xff400000/0xff000000 FWH decode enabled Maximum FWH chip size: 0x100000 bytes BIOS Lock Enable: disabled, BIOS Write Enable: disabled, BIOS_CNTL is 0x0 OK. This chipset supports the following protocols: FWH. Calibrating delay loop... 571M loops per second, 100 myus = 200 us. OK. Probing for AMD Am29F010A/B, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMD Am29F016D, 2048 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMD Am29F040B, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMD Am29F080B, 1024 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMD Am29LV040B, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMD Am29LV081B, 1024 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for ASD AE49F2008, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Atmel AT29C010A, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Atmel AT29C020, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Atmel AT29C040A, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N), 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMIC A29002T, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMIC A29040B, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for AMIC A49LF040A, 512 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for EMST F49B002UA, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Eon EN25B05, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Eon EN29F010, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)B, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for EON EN29F002(A)(N)T, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-B, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Intel 28F001BX-T, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Intel 28F004S5, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0x4d, id2 0x5a Probing for Macronix MX25L512, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Macronix MX29F001T, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Macronix MX29F002B, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Macronix MX29F002T, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Macronix MX29LV040, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for PMC Pm29F002B, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for PMC Pm39LV010, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xda, id2 0xd3 Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0xda, id2 0xd3 Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0x4d, id2 0x5a Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST29EE010, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST29LE010, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST29EE020A, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST29LE020, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST39SF512, 64 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST39SF010A, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST39SF020A, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST39SF040, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST39VF512, 64 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST39VF010, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST39VF020, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST39VF040, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST39VF080, 1024 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xda, id2 0xd3 Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xda, id2 0xd3 Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0xda, id2 0xd3 Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xda, id2 0xd3 Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0x4d, id2 0x5a Probing for SST SST49LF016C, 2048 KB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff Probing for SST SST49LF020, 256 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for SST SST49LF020A, 256 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for SST SST49LF040, 512 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for SST SST49LF040B, 512 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for SST SST49LF080A, 1024 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for SST SST49LF160C, 2048 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for ST M25P05-A, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for ST M29F002T/NT, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for ST M29F040B, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for ST M29F400BT, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for ST M29W010B, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for ST M29W040B, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for ST M29W512B, 64 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0x4d, id2 0x5a Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0x4d, id2 0x5a Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0xe0, id2 0xa7 Probing for ST M50FW016, 2048 KB: Chip size 2048 kB is bigger than supported size 1024 kB of chipset/board/programmer for FWH interface, probe/read/erase/write may fail. probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0x4d, id2 0x5a Probing for ST M50LPW116, 2048 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for SyncMOS S29C31004T, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51001T, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51002T, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for SyncMOS S29C51004T, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for TI TMS29F002RB, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for TI TMS29F002RT, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Winbond W25x10, 128 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Winbond W29C020C, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Winbond W29C040P, 512 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Winbond W29EE011, 128 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Winbond W39V040A, 512 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for Winbond W39V040B, 512 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for Winbond W39V040C, 512 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0xda, id2 0xd3 Probing for Winbond W39V080A, 1024 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for Winbond W49F002U, 256 KB: skipped. Host bus type FWH and chip bus type Parallel are incompatible. Probing for Winbond W49V002A, 256 KB: skipped. Host bus type FWH and chip bus type LPC are incompatible. Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xda, id2 0xd3 Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xda, id2 0xd3 Found chip "Winbond W39V080FA" (1024 KB, FWH) at physical address 0xfff00000. Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xda, id2 0xd3 Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type FWH and chip bus type SPI are incompatible. === This flash part has status UNTESTED for operations: PROBE READ ERASE WRITE Please email a report to flashrom(a)flashrom.org if any of the above operations work correctly for you with this flash part. Please include the flashrom output with the additional -V option for all operations you tested (-V, -rV, -wV, -EV), and mention which mainboard or programmer you tested. Thanks for your help! === No operations were specified. Step 5: URL to the mainboard specifications page (optional). http://www.supermicro.com/products/motherboard/Xeon1333/5000V/X7DVL-E.cfm

2 1

[PATCH] Broadcom BCM5785: Add TINY_BOOTBLOCK support
by Uwe Hermann 26 Nov '10

26 Nov '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

2 2

[commit] r6126 - in trunk/src: mainboard/broadcom/blast mainboard/hp/dl145_g3 mainboard/hp/dl165_g6_fam10 mainboard/msi/ms9185 southbridge/broadcom/bcm5785
by repository service 26 Nov '10

26 Nov '10

Author: uwe Date: Fri Nov 26 23:42:41 2010 New Revision: 6126 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6126 Log: Broadcom BCM5785: Add TINY_BOOTBLOCK support. In bcm5785_enable_rom(): Use PCI IDs from pci_ids.h instead of hardcoding, and use 'dev' instead of 'addr' as device_t variable name. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/src/mainboard/broadcom/blast/romstage.c trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/southbridge/broadcom/bcm5785/Kconfig trunk/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c trunk/src/southbridge/broadcom/bcm5785/bootblock.c Modified: trunk/src/mainboard/broadcom/blast/romstage.c ============================================================================== --- trunk/src/mainboard/broadcom/blast/romstage.c Fri Nov 26 23:39:40 2010 (r6125) +++ trunk/src/mainboard/broadcom/blast/romstage.c Fri Nov 26 23:42:41 2010 (r6126) @@ -10,7 +10,6 @@ #include <cpu/amd/model_fxx_rev.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" -#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -82,7 +81,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - bcm5785_enable_rom(); bcm5785_enable_lpc(); pc87417_enable_dev(RTC_DEV); /* Enable RTC */ } Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Fri Nov 26 23:39:40 2010 (r6125) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Fri Nov 26 23:42:41 2010 (r6126) @@ -41,7 +41,6 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" -#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -145,7 +144,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - bcm5785_enable_rom(); bcm5785_enable_lpc(); pc87417_enable_dev(RTC_DEV); /* Enable RTC */ } Modified: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Fri Nov 26 23:39:40 2010 (r6125) +++ trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Fri Nov 26 23:42:41 2010 (r6126) @@ -40,7 +40,6 @@ #include <console/console.h> #include <cpu/amd/model_10xxx_rev.h> #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" -#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c" #include "northbridge/amd/amdfam10/raminit.h" #include "northbridge/amd/amdfam10/amdfam10.h" #include <lib.h> @@ -109,7 +108,6 @@ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - bcm5785_enable_rom(); bcm5785_enable_lpc(); pc87417_enable_dev(RTC_DEV); /* Enable RTC */ } Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Fri Nov 26 23:39:40 2010 (r6125) +++ trunk/src/mainboard/msi/ms9185/romstage.c Fri Nov 26 23:42:41 2010 (r6126) @@ -35,7 +35,6 @@ #include <console/console.h> #include <cpu/amd/model_fxx_rev.h> #include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c" -#include "southbridge/broadcom/bcm5785/bcm5785_enable_rom.c" #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" @@ -115,7 +114,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - bcm5785_enable_rom(); bcm5785_enable_lpc(); //enable RTC pc87417_enable_dev(RTC_DEV); Modified: trunk/src/southbridge/broadcom/bcm5785/Kconfig ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/Kconfig Fri Nov 26 23:39:40 2010 (r6125) +++ trunk/src/southbridge/broadcom/bcm5785/Kconfig Fri Nov 26 23:42:41 2010 (r6126) @@ -1,6 +1,7 @@ config SOUTHBRIDGE_BROADCOM_BCM5785 bool select HAVE_HARD_RESET + select TINY_BOOTBLOCK config BOOTBLOCK_SOUTHBRIDGE_INIT string Modified: trunk/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c Fri Nov 26 23:39:40 2010 (r6125) +++ trunk/src/southbridge/broadcom/bcm5785/bcm5785_enable_rom.c Fri Nov 26 23:42:41 2010 (r6126) @@ -18,17 +18,22 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_ids.h> + +/* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ static void bcm5785_enable_rom(void) { - unsigned char byte; - device_t addr; + u8 byte; + device_t dev; - /* Enable 4MB rom access at 0xFFC00000 - 0xFFFFFFFF */ - /* Locate the BCM 5785 SB PCI Main */ - addr = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201? + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SERVERWORKS, + PCI_DEVICE_ID_SERVERWORKS_BCM5785_SB_PCI_MAIN), 0); - /* Set the 4MB enable bit bit */ - byte = pci_read_config8(addr, 0x41); + /* Set the 4MB enable bits. */ + byte = pci_read_config8(dev, 0x41); byte |= 0x0e; - pci_write_config8(addr, 0x41, byte); + pci_write_config8(dev, 0x41, byte); } Modified: trunk/src/southbridge/broadcom/bcm5785/bootblock.c ============================================================================== --- trunk/src/southbridge/broadcom/bcm5785/bootblock.c Fri Nov 26 23:39:40 2010 (r6125) +++ trunk/src/southbridge/broadcom/bcm5785/bootblock.c Fri Nov 26 23:42:41 2010 (r6126) @@ -20,6 +20,7 @@ #include "bcm5785_enable_rom.c" -static void bootblock_southbridge_init(void) { - bcm5785_enable_rom(); +static void bootblock_southbridge_init(void) +{ + bcm5785_enable_rom(); }

1 0

[PATCH] AMD SB600: Add TINY_BOOTBLOCK support
by Uwe Hermann 26 Nov '10

26 Nov '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

2 2

[commit] r6125 - trunk/src/southbridge/amd/sb600
by repository service 26 Nov '10

26 Nov '10

Author: uwe Date: Fri Nov 26 23:39:40 2010 New Revision: 6125 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6125 Log: AMD SB600: Add TINY_BOOTBLOCK support. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Added: trunk/src/southbridge/amd/sb600/bootblock.c trunk/src/southbridge/amd/sb600/sb600_enable_rom.c Modified: trunk/src/southbridge/amd/sb600/Kconfig trunk/src/southbridge/amd/sb600/sb600_early_setup.c Modified: trunk/src/southbridge/amd/sb600/Kconfig ============================================================================== --- trunk/src/southbridge/amd/sb600/Kconfig Fri Nov 26 23:35:11 2010 (r6124) +++ trunk/src/southbridge/amd/sb600/Kconfig Fri Nov 26 23:39:40 2010 (r6125) @@ -21,6 +21,7 @@ bool select IOAPIC select HAVE_USBDEBUG + select TINY_BOOTBLOCK config EHCI_BAR hex Added: trunk/src/southbridge/amd/sb600/bootblock.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/sb600/bootblock.c Fri Nov 26 23:39:40 2010 (r6125) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "southbridge/amd/sb600/sb600_enable_rom.c" + +static void bootblock_southbridge_init(void) +{ + sb600_enable_rom(); +} Modified: trunk/src/southbridge/amd/sb600/sb600_early_setup.c ============================================================================== --- trunk/src/southbridge/amd/sb600/sb600_early_setup.c Fri Nov 26 23:35:11 2010 (r6124) +++ trunk/src/southbridge/amd/sb600/sb600_early_setup.c Fri Nov 26 23:39:40 2010 (r6125) @@ -56,11 +56,9 @@ * Serial port 0 * KBC Port * ACPI Micro-controller port -* LPC ROM size * This function does not change port 0x80 decoding. * Console output through any port besides 0x3f8 is unsupported. * If you use FWH ROMs, you have to setup IDSEL. -* NOTE: Call me ASAP, because I will reset LPC ROM size! * Reviewed-by: Carl-Daniel Hailfinger * Reviewed against AMD SB600 Register Reference Manual rev. 3.03, section 3.1 * (LPC ISA Bridge) @@ -97,27 +95,13 @@ reg8 |= (1 << 5) | (1 << 6); pci_write_config8(dev, 0x47, reg8); - /* SuperIO, LPC ROM */ + /* Super I/O, RTC */ reg8 = pci_read_config8(dev, 0x48); /* Decode ports 0x2e-0x2f, 0x4e-0x4f (SuperI/O configuration) */ reg8 |= (1 << 1) | (1 << 0); - /* Decode variable LPC ROM address ranges 1&2 (see register 0x68-0x6b, 0x6c-0x6f) */ - reg8 |= (1 << 3) | (1 << 4); /* Decode port 0x70-0x73 (RTC) */ - reg8 |= 1 << 6; + reg8 |= (1 << 6); pci_write_config8(dev, 0x48, reg8); - - /* hardware should enable LPC ROM by pin straps */ - /* ROM access at 0xFFF80000/0xFFF00000 - 0xFFFFFFFF */ - /* See detail in BDG-215SB600-03.pdf page 15. */ - /* enable LPC ROM range mirroring start 0x000e(0000) */ - pci_write_config16(dev, 0x68, 0x000e); - /* enable LPC ROM range mirroring end 0x000f(ffff) */ - pci_write_config16(dev, 0x6a, 0x000f); - /* enable LPC ROM range start, 0xfff8(0000): 512KB, 0xfff0(0000): 1MB, 0xffe0(0000): 2MB, 0xffc0(0000): 4MB */ - pci_write_config16(dev, 0x6c, 0xffc0); - /* enable LPC ROM range end at 0xffff(ffff) */ - pci_write_config16(dev, 0x6e, 0xffff); } /* what is its usage? */ @@ -387,13 +371,12 @@ pci_write_config8(dev, 0x46, 0xC3); pci_write_config8(dev, 0x47, 0xFF); + // TODO: This has already been done(?) /* IO/Mem Port Decode Enable, I don't know why CIM disable some ports. * Disable LPC TimeOut counter, enable SuperIO Configuration Port (2e/2f), - * Alternate SuperIO Configuration Port (4e/4f), Wide Generic IO Port (64/65). - * Enable bits for LPC ROM memory address range 1&2 for 1M ROM setting.*/ + * Alternate SuperIO Configuration Port (4e/4f), Wide Generic IO Port (64/65). */ byte = pci_read_config8(dev, 0x48); byte |= (1 << 1) | (1 << 0); /* enable Super IO config port 2e-2h, 4e-4f */ - byte |= (1 << 3) | (1 << 4); /* enable for LPC ROM address range1&2, Enable 512KB rom access at 0xFFF80000 - 0xFFFFFFFF */ byte |= 1 << 6; /* enable for RTC I/O range */ pci_write_config8(dev, 0x48, byte); pci_write_config8(dev, 0x49, 0xFF); @@ -402,12 +385,6 @@ byte |= ((1 << 1) + (1 << 6)); /*0x42, save the configuraion for port 0x80. */ pci_write_config8(dev, 0x4A, byte); - /* Set LPC ROM size, it has been done in sb600_lpc_init(). - * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB; - * enable LPC ROM range, 0xfff8: 512KB, 0xfff0: 1MB - * pci_write_config16(dev, 0x68, 0x000e) - * pci_write_config16(dev, 0x6c, 0xfff0);*/ - /* Enable Tpm12_en and Tpm_legacy. I don't know what is its usage and copied from CIM. */ pci_write_config8(dev, 0x7C, 0x05); Added: trunk/src/southbridge/amd/sb600/sb600_enable_rom.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/amd/sb600/sb600_enable_rom.c Fri Nov 26 23:39:40 2010 (r6125) @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_ids.h> + +/* + * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. + * + * Hardware should enable LPC ROM by pin straps. This function does not + * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. + * + * The SB600 power-on default is to map 256K ROM space. + * + * Details: AMD SB600 BIOS Developer's Guide (BDG), page 15. + */ +static void sb600_enable_rom(void) +{ + u8 reg8; + device_t dev; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, + PCI_DEVICE_ID_ATI_SB600_LPC), 0); + + /* Decode variable LPC ROM address ranges 1 and 2. */ + reg8 = pci_read_config8(dev, 0x48); + reg8 |= (1 << 3) | (1 << 4); + pci_write_config8(dev, 0x48, reg8); + + /* LPC ROM address range 1: */ + /* Enable LPC ROM range mirroring start at 0x000e(0000). */ + pci_write_config16(dev, 0x68, 0x000e); + /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ + pci_write_config16(dev, 0x6a, 0x000f); + + /* LPC ROM address range 2: */ + /* + * Enable LPC ROM range start at: + * 0xfff8(0000): 512KB + * 0xfff0(0000): 1MB + * 0xffe0(0000): 2MB + * 0xffc0(0000): 4MB + */ + pci_write_config16(dev, 0x6c, 0xffc0); /* 4 MB */ + /* Enable LPC ROM range end at 0xffff(ffff). */ + pci_write_config16(dev, 0x6e, 0xffff); +}

1 0

[PATCH] AMD-8111: Add TINY_BOOTBLOCK support
by Uwe Hermann 26 Nov '10

26 Nov '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

2 2

[commit] r6124 - in trunk/src: mainboard/amd/serengeti_cheetah mainboard/amd/serengeti_cheetah_fam10 mainboard/arima/hdama mainboard/hp/dl145_g1 mainboard/ibm/e325 mainboard/ibm/e326 mainboard/iwil...
by repository service 26 Nov '10

26 Nov '10

Author: uwe Date: Fri Nov 26 23:35:11 2010 New Revision: 6124 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6124 Log: AMD-8111: Add TINY_BOOTBLOCK support. Also, add missing license header to amd8111_enable_rom.c, add some more code comments and use PCI IDs from pci_ids.h instead of hardcoding. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/arima/hdama/romstage.c trunk/src/mainboard/hp/dl145_g1/romstage.c trunk/src/mainboard/ibm/e325/romstage.c trunk/src/mainboard/ibm/e326/romstage.c trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/newisys/khepri/romstage.c trunk/src/mainboard/tyan/s2850/romstage.c trunk/src/mainboard/tyan/s2875/romstage.c trunk/src/mainboard/tyan/s2880/romstage.c trunk/src/mainboard/tyan/s2881/romstage.c trunk/src/mainboard/tyan/s2882/romstage.c trunk/src/mainboard/tyan/s2885/romstage.c trunk/src/mainboard/tyan/s4880/romstage.c trunk/src/mainboard/tyan/s4882/romstage.c trunk/src/southbridge/amd/amd8111/Kconfig trunk/src/southbridge/amd/amd8111/amd8111_enable_rom.c trunk/src/southbridge/amd/amd8111/bootblock.c Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Fri Nov 26 23:35:11 2010 (r6124) @@ -85,7 +85,6 @@ #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" #define RC0 ((1<<0)<<8) @@ -126,7 +125,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - amd8111_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Fri Nov 26 23:35:11 2010 (r6124) @@ -89,7 +89,6 @@ #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" static const u8 spd_addr[] = { @@ -197,9 +196,6 @@ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); - - /* Setup the rom access for 4M */ - amd8111_enable_rom(); } post_code(0x30); Modified: trunk/src/mainboard/arima/hdama/romstage.c ============================================================================== --- trunk/src/mainboard/arima/hdama/romstage.c Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/mainboard/arima/hdama/romstage.c Fri Nov 26 23:35:11 2010 (r6124) @@ -66,7 +66,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -88,7 +87,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - amd8111_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/hp/dl145_g1/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g1/romstage.c Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/mainboard/hp/dl145_g1/romstage.c Fri Nov 26 23:35:11 2010 (r6124) @@ -88,7 +88,6 @@ #include <spd.h> #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" #define RC0 ((1<<1)<<8) // Not sure about these values @@ -115,7 +114,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - amd8111_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/ibm/e325/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e325/romstage.c Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/mainboard/ibm/e325/romstage.c Fri Nov 26 23:35:11 2010 (r6124) @@ -63,7 +63,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -97,7 +96,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - amd8111_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/ibm/e326/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e326/romstage.c Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/mainboard/ibm/e326/romstage.c Fri Nov 26 23:35:11 2010 (r6124) @@ -63,7 +63,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -97,7 +96,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - amd8111_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Fri Nov 26 23:35:11 2010 (r6124) @@ -73,7 +73,6 @@ #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -96,7 +95,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - amd8111_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Fri Nov 26 23:35:11 2010 (r6124) @@ -73,7 +73,6 @@ #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -97,7 +96,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - amd8111_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Fri Nov 26 23:35:11 2010 (r6124) @@ -73,7 +73,6 @@ #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -97,7 +96,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - amd8111_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/newisys/khepri/romstage.c ============================================================================== --- trunk/src/mainboard/newisys/khepri/romstage.c Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/mainboard/newisys/khepri/romstage.c Fri Nov 26 23:35:11 2010 (r6124) @@ -69,7 +69,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -91,7 +90,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - amd8111_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/tyan/s2850/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2850/romstage.c Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/mainboard/tyan/s2850/romstage.c Fri Nov 26 23:35:11 2010 (r6124) @@ -59,7 +59,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -82,7 +81,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - amd8111_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/tyan/s2875/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2875/romstage.c Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/mainboard/tyan/s2875/romstage.c Fri Nov 26 23:35:11 2010 (r6124) @@ -59,7 +59,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -93,7 +92,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - amd8111_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/tyan/s2880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2880/romstage.c Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/mainboard/tyan/s2880/romstage.c Fri Nov 26 23:35:11 2010 (r6124) @@ -59,7 +59,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -93,7 +92,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - amd8111_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/tyan/s2881/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2881/romstage.c Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/mainboard/tyan/s2881/romstage.c Fri Nov 26 23:35:11 2010 (r6124) @@ -58,7 +58,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -80,7 +79,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - amd8111_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/tyan/s2882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2882/romstage.c Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/mainboard/tyan/s2882/romstage.c Fri Nov 26 23:35:11 2010 (r6124) @@ -59,7 +59,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -93,7 +92,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - amd8111_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/tyan/s2885/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2885/romstage.c Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/mainboard/tyan/s2885/romstage.c Fri Nov 26 23:35:11 2010 (r6124) @@ -58,7 +58,6 @@ #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) @@ -80,7 +79,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - amd8111_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/tyan/s4880/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4880/romstage.c Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/mainboard/tyan/s4880/romstage.c Fri Nov 26 23:35:11 2010 (r6124) @@ -78,7 +78,6 @@ #include <spd.h> #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" #define RC0 ((1<<2)<<8) @@ -140,7 +139,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - amd8111_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/tyan/s4882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s4882/romstage.c Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/mainboard/tyan/s4882/romstage.c Fri Nov 26 23:35:11 2010 (r6124) @@ -86,7 +86,6 @@ #include <spd.h> #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" -#include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" #define RC0 ((1<<2)<<8) @@ -119,7 +118,6 @@ /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); - amd8111_enable_rom(); } if (bist == 0) Modified: trunk/src/southbridge/amd/amd8111/Kconfig ============================================================================== --- trunk/src/southbridge/amd/amd8111/Kconfig Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/southbridge/amd/amd8111/Kconfig Fri Nov 26 23:35:11 2010 (r6124) @@ -20,8 +20,9 @@ config SOUTHBRIDGE_AMD_AMD8111 bool select IOAPIC + select TINY_BOOTBLOCK config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/amd/amd8111/bootblock.c" - depends on SOUTHBRIDGE_AMD_AMD8111 + string + default "southbridge/amd/amd8111/bootblock.c" + depends on SOUTHBRIDGE_AMD_AMD8111 Modified: trunk/src/southbridge/amd/amd8111/amd8111_enable_rom.c ============================================================================== --- trunk/src/southbridge/amd/amd8111/amd8111_enable_rom.c Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/southbridge/amd/amd8111/amd8111_enable_rom.c Fri Nov 26 23:35:11 2010 (r6124) @@ -1,15 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2003 Linux Networx + * (Written by Eric Biederman <ebiederman(a)lnxi.com> for Linux Networx) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_ids.h> + +/* Enable 5MB ROM access at 0xFFB00000 - 0xFFFFFFFF. */ static void amd8111_enable_rom(void) { - unsigned char byte; + u8 byte; device_t dev; - /* Enable 5MB rom access at 0xFFB00000 - 0xFFFFFFFF */ - /* Locate the amd8111 */ - dev = pci_io_locate_device(PCI_ID(0x1022, 0x7468), 0); + dev = pci_io_locate_device(PCI_ID(PCI_VENDOR_ID_AMD, + PCI_DEVICE_ID_AMD_8111_ISA), 0); + + /* Note: The 0xFFFF0000 - 0xFFFFFFFF range is always enabled. */ - /* Set the 5MB enable bits */ + /* Set the 5MB enable bits. */ byte = pci_io_read_config8(dev, 0x43); - byte |= 0xC0; + byte |= (1 << 7); /* Enable 0xFFC00000-0xFFFFFFFF (4MB). */ + byte |= (1 << 6); /* Enable 0xFFB00000-0xFFBFFFFF (1MB). */ pci_io_write_config8(dev, 0x43, byte); } Modified: trunk/src/southbridge/amd/amd8111/bootblock.c ============================================================================== --- trunk/src/southbridge/amd/amd8111/bootblock.c Thu Nov 25 10:03:55 2010 (r6123) +++ trunk/src/southbridge/amd/amd8111/bootblock.c Fri Nov 26 23:35:11 2010 (r6124) @@ -1,6 +1,6 @@ #include "southbridge/amd/amd8111/amd8111_enable_rom.c" -static void bootblock_southbridge_init(void) { - /* Setup the rom access for 4M */ +static void bootblock_southbridge_init(void) +{ amd8111_enable_rom(); }

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[PATCH] MCP55: Add TINY_BOOTBLOCK support
by Uwe Hermann 25 Nov '10

25 Nov '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[commit] r6123 - in trunk/src: mainboard/gigabyte/m57sli mainboard/msi/ms7260 mainboard/msi/ms9282 mainboard/msi/ms9652_fam10 mainboard/nvidia/l1_2pvv mainboard/supermicro/h8dme mainboard/supermicr...
by repository service 25 Nov '10

25 Nov '10

Author: uwe Date: Thu Nov 25 10:03:55 2010 New Revision: 6123 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6123 Log: MCP55: Add TINY_BOOTBLOCK support. Also, move CONFIG_HT_CHAIN_END_UNITID_BASE #ifdef block to mcp55.h to make the build work (but this is a good idea anyway, as it's used in multiple files). Abuild-tested. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Added: trunk/src/southbridge/nvidia/mcp55/bootblock.c Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c trunk/src/southbridge/nvidia/mcp55/Kconfig trunk/src/southbridge/nvidia/mcp55/chip.h trunk/src/southbridge/nvidia/mcp55/mcp55.h trunk/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Wed Nov 24 21:03:09 2010 (r6122) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Thu Nov 25 10:03:55 2010 (r6123) @@ -81,7 +81,6 @@ #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -124,7 +123,6 @@ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Wed Nov 24 21:03:09 2010 (r6122) +++ trunk/src/mainboard/msi/ms7260/romstage.c Thu Nov 25 10:03:55 2010 (r6123) @@ -83,7 +83,6 @@ #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -125,7 +124,6 @@ /* Allow the HT devices to be found. */ enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Wed Nov 24 21:03:09 2010 (r6122) +++ trunk/src/mainboard/msi/ms9282/romstage.c Thu Nov 25 10:03:55 2010 (r6123) @@ -96,7 +96,6 @@ #include "cpu/amd/model_fxx/init_cpus.c" // Disabled until it's actually used: // #include "cpu/amd/model_fxx/fidvid.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -138,7 +137,6 @@ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } if (bist == 0) { Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Wed Nov 24 21:03:09 2010 (r6122) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Thu Nov 25 10:03:55 2010 (r6123) @@ -78,7 +78,6 @@ #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" static void sio_setup(void) @@ -117,7 +116,6 @@ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } post_code(0x30); Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Wed Nov 24 21:03:09 2010 (r6122) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Thu Nov 25 10:03:55 2010 (r6123) @@ -82,7 +82,6 @@ #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -124,7 +123,6 @@ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Wed Nov 24 21:03:09 2010 (r6122) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Thu Nov 25 10:03:55 2010 (r6123) @@ -131,7 +131,6 @@ #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -189,7 +188,6 @@ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Wed Nov 24 21:03:09 2010 (r6122) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Thu Nov 25 10:03:55 2010 (r6123) @@ -72,7 +72,6 @@ #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -118,7 +117,6 @@ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Wed Nov 24 21:03:09 2010 (r6122) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Thu Nov 25 10:03:55 2010 (r6123) @@ -69,7 +69,6 @@ #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" static void sio_setup(void) @@ -117,7 +116,6 @@ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } post_code(0x30); Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Wed Nov 24 21:03:09 2010 (r6122) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Thu Nov 25 10:03:55 2010 (r6123) @@ -75,7 +75,6 @@ #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" static void sio_setup(void) @@ -168,7 +167,6 @@ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } post_code(0x30); Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Wed Nov 24 21:03:09 2010 (r6122) +++ trunk/src/mainboard/tyan/s2912/romstage.c Thu Nov 25 10:03:55 2010 (r6123) @@ -82,7 +82,6 @@ #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" #include "cpu/amd/model_fxx/fidvid.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdk8/early_ht.c" static void sio_setup(void) @@ -125,7 +124,6 @@ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } if (bist == 0) Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Wed Nov 24 21:03:09 2010 (r6122) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Thu Nov 25 10:03:55 2010 (r6123) @@ -79,7 +79,6 @@ #include "cpu/amd/microcode/microcode.c" #include "cpu/amd/model_10xxx/update_microcode.c" #include "cpu/amd/model_10xxx/init_cpus.c" -#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" static void sio_setup(void) @@ -123,7 +122,6 @@ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); sio_setup(); - mcp55_enable_rom(); } post_code(0x30); Modified: trunk/src/southbridge/nvidia/mcp55/Kconfig ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/Kconfig Wed Nov 24 21:03:09 2010 (r6122) +++ trunk/src/southbridge/nvidia/mcp55/Kconfig Thu Nov 25 10:03:55 2010 (r6123) @@ -2,9 +2,14 @@ bool select HAVE_USBDEBUG select IOAPIC + select TINY_BOOTBLOCK if SOUTHBRIDGE_NVIDIA_MCP55 +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/nvidia/mcp55/bootblock.c" + config ID_SECTION_OFFSET hex default 0x80 Added: trunk/src/southbridge/nvidia/mcp55/bootblock.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/nvidia/mcp55/bootblock.c Thu Nov 25 10:03:55 2010 (r6123) @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include "southbridge/nvidia/mcp55/mcp55_enable_rom.c" + +static void bootblock_southbridge_init(void) +{ + mcp55_enable_rom(); +} Modified: trunk/src/southbridge/nvidia/mcp55/chip.h ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/chip.h Wed Nov 24 21:03:09 2010 (r6122) +++ trunk/src/southbridge/nvidia/mcp55/chip.h Thu Nov 25 10:03:55 2010 (r6123) @@ -22,6 +22,8 @@ #ifndef MCP55_CHIP_H #define MCP55_CHIP_H +#include <device/device.h> + struct southbridge_nvidia_mcp55_config { unsigned int ide0_enable : 1; Modified: trunk/src/southbridge/nvidia/mcp55/mcp55.h ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55.h Wed Nov 24 21:03:09 2010 (r6122) +++ trunk/src/southbridge/nvidia/mcp55/mcp55.h Thu Nov 25 10:03:55 2010 (r6123) @@ -22,13 +22,21 @@ #ifndef MCP55_H #define MCP55_H -#include "chip.h" +#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 + #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE +#else + #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE +#endif #ifndef __PRE_RAM__ +#include "chip.h" void mcp55_enable(device_t dev); extern struct pci_operations mcp55_pci_ops; #else +#if !defined(__ROMCC__) void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn); -#endif void mcp55_enable_usbdebug(unsigned int port); +#endif +#endif + #endif /* MCP55_H */ Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c Wed Nov 24 21:03:09 2010 (r6122) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_enable_rom.c Thu Nov 25 10:03:55 2010 (r6123) @@ -21,11 +21,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 - #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE -#else - #define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE -#endif +#include <stdint.h> +#include <arch/io.h> +#include <arch/romcc_io.h> +#include "mcp55.h" static void mcp55_enable_rom(void) { Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c Wed Nov 24 21:03:09 2010 (r6122) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_enable_usbdebug.c Thu Nov 25 10:03:55 2010 (r6123) @@ -28,12 +28,6 @@ #include <device/pci_def.h> #include "mcp55.h" -#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20 -#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_END_UNITID_BASE -#else -#define MCP55_DEVN_BASE CONFIG_HT_CHAIN_UNITID_BASE -#endif - void set_debug_port(unsigned int port) { u32 dword;

1 0

[commit] r6116 - trunk/src/arch/i386/include/arch
by repository service 25 Nov '10

25 Nov '10

Author: uwe Date: Mon Nov 22 17:23:54 2010 New Revision: 6116 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6116 Log: Drop unused ACPI_WRITE_MADT_IOAPIC #define. This should probably be C code in some .c file anyway. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/arch/i386/include/arch/acpi.h Modified: trunk/src/arch/i386/include/arch/acpi.h ============================================================================== --- trunk/src/arch/i386/include/arch/acpi.h Mon Nov 22 16:57:57 2010 (r6115) +++ trunk/src/arch/i386/include/arch/acpi.h Mon Nov 22 17:23:54 2010 (r6116) @@ -431,17 +431,6 @@ /* cpu/intel/speedstep/acpi.c */ void generate_cpu_entries(void); -#define ACPI_WRITE_MADT_IOAPIC(dev,id) \ -do { \ - struct resource *res; \ - res = find_resource(dev, PCI_BASE_ADDRESS_0); \ - if (!res) break; \ - current += acpi_create_madt_ioapic( \ - (acpi_madt_ioapic_t *)current, \ - id, res->base, gsi_base); \ - gsi_base += 4; \ -} while(0); - #else // CONFIG_GENERATE_ACPI_TABLES #define write_acpi_tables(start) (start)

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