coreboot November 2010

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[commit] r6133 - trunk/src/southbridge/amd/rs780
by repository service 30 Nov '10

30 Nov '10

Author: zbao Date: Tue Nov 30 03:05:17 2010 New Revision: 6133 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6133 Log: Trivial. Reindent and dos2unix. Signed-off-by: Zheng Bao <zheng.bao(a)amd.com> Acked-by: Zheng Bao <zheng.bao(a)amd.com> Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c Modified: trunk/src/southbridge/amd/rs780/rs780_gfx.c ============================================================================== --- trunk/src/southbridge/amd/rs780/rs780_gfx.c Mon Nov 29 21:40:33 2010 (r6132) +++ trunk/src/southbridge/amd/rs780/rs780_gfx.c Tue Nov 30 03:05:17 2010 (r6133) @@ -361,9 +361,9 @@ /* Force allow LDT_STOP Cool'n'Quiet workaround. */ *(GpuF0MMReg + 0x655c/4) |= 1<<4; - // disable write combining, needed for stability - // reference bios does this only for RS780 rev A11 - // need to figure out why we need it for all revs + // disable write combining, needed for stability + // reference bios does this only for RS780 rev A11 + // need to figure out why we need it for all revs *(GpuF0MMReg + 0x2000/4) = 0x00000010; *(GpuF0MMReg + 0x2408/4) = 1 << 9; *(GpuF0MMReg + 0x2000/4) = 0x00000011;

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[commit] r6132 - in trunk/src: mainboard/asus/p2b southbridge/intel/i82371eb
by repository service 29 Nov '10

29 Nov '10

Author: ranma Date: Mon Nov 29 21:40:33 2010 New Revision: 6132 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6132 Log: Tobias Diedrich wrote: > Stefan Reinauer wrote: > > The specified IO port is most likely wrong. As the comment mentions, the > > SSDT is a good place for that. A preprocessor define used both in the > > CPU init code and in the asl would solve the problem without an SSDT. > > For some info on CPU SSDT creation on intel check out > > src/cpu/intel/speedstep/acpi.c > > The IO port is ok (and I wrote the comment myself ;)): > DEFAULT_PMBASE is 0xe400 > PCNTRL reg offset is 0x10 > > Using the preprocessor will probably work too if iasl can do simple > arithmetic (likely yes), I'll look into that. BTW, my first idea was to use an acpi method that looks up pmbase in the pci cfg space, but when I define a method like this: Method(TEST, 2) { Return (Add(Arg0, Arg1)) } I get: |build/mainboard/asus/p2b/dsdt.ramstage.asl 9: Processor (CPU0, |0x01, TEST(0xe400, 0x10), 0x06) {} |Error 4096 - syntax error, unexpected PARSEOP_NAMESEG, |expecting ')' ^ While using the builtin Add() directly works. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/asus/p2b/dsdt.asl trunk/src/southbridge/intel/i82371eb/i82371eb.h Modified: trunk/src/mainboard/asus/p2b/dsdt.asl ============================================================================== --- trunk/src/mainboard/asus/p2b/dsdt.asl Mon Nov 29 12:56:39 2010 (r6131) +++ trunk/src/mainboard/asus/p2b/dsdt.asl Mon Nov 29 21:40:33 2010 (r6132) @@ -17,14 +17,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include "southbridge/intel/i82371eb/i82371eb.h" + DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) { /* Define the main processor.*/ Scope (\_PR) { - /* Looks like the P_CNT field can't be a method or name - * and has to be hardcoded to 0xe410 or generated in SSDT */ - Processor (CPU0, 0x01, 0xe410, 0x06) {} + /* Looks like the P_CNT field can't be a name or method (except + * builtins like Add()) and has to be hardcoded or generated + * into SSDT */ + Processor (CPU0, 0x01, Add(DEFAULT_PMBASE, PCNTRL), 0x06) {} } /* For now only define 2 power states: Modified: trunk/src/southbridge/intel/i82371eb/i82371eb.h ============================================================================== --- trunk/src/southbridge/intel/i82371eb/i82371eb.h Mon Nov 29 12:56:39 2010 (r6131) +++ trunk/src/southbridge/intel/i82371eb/i82371eb.h Mon Nov 29 21:40:33 2010 (r6132) @@ -23,6 +23,7 @@ #if !defined(ASSEMBLY) #if !defined(__PRE_RAM__) +#if !defined(__ACPI__) /* dsdt include */ #include <arch/io.h> #include <device/device.h> @@ -33,6 +34,7 @@ #endif #endif +#endif /* If 'cond' is true this macro sets the bit(s) specified by 'bits' in the * 'reg' variable, otherwise it clears those bits.

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Trac reminder: list of new ticket(s)
by coreboot tracker 29 Nov '10

29 Nov '10

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[superiotool] patch for fintek f71889fg
by David Hendricks 29 Nov '10

29 Nov '10

The patch (attached) was tested by a user on IRC who had the F71889FG. I wrote it using documentation from Fintek's website available here: http://www.fintek.com.tw/files/productfiles/F71889_V0.28P.pdf This patch also seems to work for the F71889ED, which uses 0x09 and 0x09 for chip ID bytes 1 & 2. However, I have not been able to find documentation to verify that the two chips are identical from superiotool's perspective. The F71889 seems popular on current generation platforms with AMD chipsets, in case there are folks looking to try it on a presently unsupported board... Signed-off-by: David Hendricks <dhendrix(a)google.com> -- David Hendricks (dhendrix) Systems Software Engineer, Google Inc.

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[commit] r6131 - trunk/util/superiotool
by repository service 29 Nov '10

29 Nov '10

Author: uwe Date: Mon Nov 29 12:56:39 2010 New Revision: 6131 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6131 Log: Add Fintek F71889 detection and dump support. The patch was tested by a user on IRC who had the F71889FG. I wrote it using documentation from Fintek's website available here: http://www.fintek.com.tw/files/productfiles/F71889_V0.28P.pdf This patch also seems to work for the F71889ED, which uses 0x09 and 0x09 for chip ID bytes 1 & 2. However, I have not been able to find documentation to verify that the two chips are identical from superiotool's perspective. Signed-off-by: David Hendricks <dhendrix(a)google.com> Signed-off-by: Alec Ari <neotheuser(a)ymail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/util/superiotool/fintek.c Modified: trunk/util/superiotool/fintek.c ============================================================================== --- trunk/util/superiotool/fintek.c Mon Nov 29 01:20:20 2010 (r6130) +++ trunk/util/superiotool/fintek.c Mon Nov 29 12:56:39 2010 (r6131) @@ -76,6 +76,55 @@ {0x30,0xf0,0xf1,0xf4,0xf5,0xf7,EOT}, {0x00,0x00,NANA,0x06,0x1c,0x01,EOT}}, {EOT}}}, + {0x2307, "F71889", { + /* We assume reserved bits are read as 0. */ + {NOLDN, NULL, + {0x20,0x21,0x23,0x24,0x25,0x26,0x27,0x28,0x2a,0x2b, + 0x2c,0x2d,EOT}, + {0x07,0x23,0x19,0x34,0x00,0x00,0x00,0x00,0xf0,0x30, + 0x00,0x08,EOT}}, + {0x0, "Floppy", + {0x30,0x60,0x61,0x70,0x74,0xf0,0xf2,0xf4,EOT}, + {0x01,0x03,0xf0,0x06,0x02,0x0e,0x03,0x00,EOT}}, + {0x1, "COM1", + {0x30,0x60,0x61,0x70,0xf0,EOT}, + {0x01,0x03,0xf8,0x04,0x00,EOT}}, + {0x2, "COM2", + {0x30,0x60,0x61,0x70,0xf0,0xf1,EOT}, + {0x01,0x02,0xf8,0x03,0x00,0x04,EOT}}, + {0x3, "Parallel port", + {0x30,0x60,0x61,0x70,0x74,0xf0,EOT}, + {0x01,0x03,0x78,0x07,0x03,0x42,EOT}}, + {0x4, "Hardware monitor", + {0x30,0x60,0x61,0x70,EOT}, + {0x01,0x02,0x95,0x00,EOT}}, + {0x5, "Keyboard", + {0x30,0x60,0x61,0x70,0x72,0xfe,EOT}, + {0x01,0x00,0x60,0x01,0x0c,0x81,EOT}}, + {0x6, "GPIO", + {0x80,0x81,0x82,0x83,0x90,0x91,0x92,0x93,0xa0,0xa1, + 0xa2,0xa3,0xb0,0xb1,0xb2,0xc0,0xc1,0xc2,0xc3,0xd0, + 0xd1,0xd2,0xd3,0xe0,0xe1,0xe2,0xe3,0xf0,0xf1,0xf2, + 0xf3,0xfe,0xff,EOT}, + {0x00,0xff,NANA,0x00,0x00,0xff,NANA,0x00,0x00,0x1f, + NANA,0x00,0x00,0xff,NANA,0x00,0xff,NANA,0x00,0x00, + 0xff,NANA,0x00,0x00,0x7f,NANA,0x00,0x00,0x7f,NANA, + 0x00,0x00,0x00,EOT}}, + {0x7, "VID", + {0x30,0x60,0x61,EOT}, + {0x00,0x00,0x00,EOT}}, + {0x8, "SPI", + {0xf0,0xf1,0xf2,0xf3,0xf4,0xf5,0xf6,0xf7,0xf8,0xfa, + 0xfb,0xfc,0xfd,0xfe,0xff,EOT}, + {0x00,RSVD,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x00,0x00,0x00,0x00,0x00,EOT}}, + {0xa, "PME, ACPI", + {0x30,0xf0,0xf1,0xf4,0xf5,0xf6,EOT}, + {0x00,0x00,0x00,0x26,0x1c,0x07,EOT}}, + {0xb, "VREF", + {0xf0,0xf1,0xf2,0xf3,0xff,EOT}, + {0x64,0x64,0x64,0x00,0x00,EOT}}, + {EOT}}}, {0x4103, "F71872F/FG / F71806F/FG", { /* Same ID? Datasheet typo? */ {NOLDN, NULL, {0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,

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[commit] r6130 - trunk/src/southbridge/nvidia/mcp55
by repository service 29 Nov '10

29 Nov '10

Author: stepan Date: Mon Nov 29 01:20:20 2010 New Revision: 6130 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6130 Log: fix typo Signed-off-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_azalia.c Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_azalia.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_azalia.c Sun Nov 28 15:24:07 2010 (r6129) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_azalia.c Mon Nov 29 01:20:20 2010 (r6130) @@ -54,7 +54,7 @@ reg32 &= mask; } while ((reg32 != val) && --count); - /* Timeout occureed */ + /* Timeout occurred */ if (!count) return -1; return 0;

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[commit] r6129 - in trunk/src/mainboard: asus/a8n_e gigabyte/m57sli jetway/pa78vm5 kontron/kt690 msi/ms7260 technexion/tim5690 technexion/tim8690
by repository service 28 Nov '10

28 Nov '10

Author: uwe Date: Sun Nov 28 15:24:07 2010 New Revision: 6129 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6129 Log: devicetree.cb: Only add as many entries as there are DIMM slots. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/asus/a8n_e/devicetree.cb trunk/src/mainboard/gigabyte/m57sli/devicetree.cb trunk/src/mainboard/jetway/pa78vm5/devicetree.cb trunk/src/mainboard/kontron/kt690/devicetree.cb trunk/src/mainboard/msi/ms7260/devicetree.cb trunk/src/mainboard/technexion/tim5690/devicetree.cb trunk/src/mainboard/technexion/tim8690/devicetree.cb Modified: trunk/src/mainboard/asus/a8n_e/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/a8n_e/devicetree.cb Sat Nov 27 15:44:19 2010 (r6128) +++ trunk/src/mainboard/asus/a8n_e/devicetree.cb Sun Nov 28 15:24:07 2010 (r6129) @@ -87,18 +87,6 @@ # chip drivers/generic/generic # DIMM 0-1-1 # device i2c 53 on end # end - # chip drivers/generic/generic # DIMM 1-0-0 - # device i2c 54 on end - # end - # chip drivers/generic/generic # DIMM 1-0-1 - # device i2c 55 on end - # end - # chip drivers/generic/generic # DIMM 1-1-0 - # device i2c 56 on end - # end - # chip drivers/generic/generic # DIMM 1-1-1 - # device i2c 57 on end - # end end device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 Modified: trunk/src/mainboard/gigabyte/m57sli/devicetree.cb ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/devicetree.cb Sat Nov 27 15:44:19 2010 (r6128) +++ trunk/src/mainboard/gigabyte/m57sli/devicetree.cb Sun Nov 28 15:24:07 2010 (r6129) @@ -118,18 +118,6 @@ chip drivers/generic/generic # DIMM 0-1-1 device i2c 53 on end end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end end device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 Modified: trunk/src/mainboard/jetway/pa78vm5/devicetree.cb ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/devicetree.cb Sat Nov 27 15:44:19 2010 (r6128) +++ trunk/src/mainboard/jetway/pa78vm5/devicetree.cb Sun Nov 28 15:24:07 2010 (r6129) @@ -46,12 +46,6 @@ chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x439c device pci 14.2 on end # HDA 0x4383 Modified: trunk/src/mainboard/kontron/kt690/devicetree.cb ============================================================================== --- trunk/src/mainboard/kontron/kt690/devicetree.cb Sat Nov 27 15:44:19 2010 (r6128) +++ trunk/src/mainboard/kontron/kt690/devicetree.cb Sun Nov 28 15:24:07 2010 (r6129) @@ -54,12 +54,6 @@ chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x438c device pci 14.2 on end # HDA 0x4383 Modified: trunk/src/mainboard/msi/ms7260/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms7260/devicetree.cb Sat Nov 27 15:44:19 2010 (r6128) +++ trunk/src/mainboard/msi/ms7260/devicetree.cb Sun Nov 28 15:24:07 2010 (r6129) @@ -66,19 +66,6 @@ chip drivers/generic/generic # DIMM 0-1-1 device i2c 53 on end end - # TODO: Needed? - # chip drivers/generic/generic # DIMM 1-0-0 - # device i2c 54 on end - # end - # chip drivers/generic/generic # DIMM 1-0-1 - # device i2c 55 on end - # end - # chip drivers/generic/generic # DIMM 1-1-0 - # device i2c 56 on end - # end - # chip drivers/generic/generic # DIMM 1-1-1 - # device i2c 57 on end - # end end # TODO: Check if the stuff below is correct / needed. device pci 1.1 on # SM 1 Modified: trunk/src/mainboard/technexion/tim5690/devicetree.cb ============================================================================== --- trunk/src/mainboard/technexion/tim5690/devicetree.cb Sat Nov 27 15:44:19 2010 (r6128) +++ trunk/src/mainboard/technexion/tim5690/devicetree.cb Sun Nov 28 15:24:07 2010 (r6129) @@ -51,15 +51,6 @@ chip drivers/generic/generic #dimm 0-0-0 device i2c 50 on end end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x438c device pci 14.2 on end # HDA 0x4383 Modified: trunk/src/mainboard/technexion/tim8690/devicetree.cb ============================================================================== --- trunk/src/mainboard/technexion/tim8690/devicetree.cb Sat Nov 27 15:44:19 2010 (r6128) +++ trunk/src/mainboard/technexion/tim8690/devicetree.cb Sun Nov 28 15:24:07 2010 (r6129) @@ -54,12 +54,6 @@ chip drivers/generic/generic #dimm 0-0-1 device i2c 51 on end end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end end # SM device pci 14.1 on end # IDE 0x438c device pci 14.2 on end # HDA 0x4383

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[commit] r6128 - trunk/util/inteltool
by repository service 27 Nov '10

27 Nov '10

Author: ranma Date: Sat Nov 27 15:44:19 2010 New Revision: 6128 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6128 Log: - Add support for Intel Pentium III MSRs - pmbase is on southbridge function 3 on I82371XX Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Modified: trunk/util/inteltool/cpu.c trunk/util/inteltool/inteltool.c trunk/util/inteltool/inteltool.h trunk/util/inteltool/powermgt.c Modified: trunk/util/inteltool/cpu.c ============================================================================== --- trunk/util/inteltool/cpu.c Sat Nov 27 10:40:16 2010 (r6127) +++ trunk/util/inteltool/cpu.c Sat Nov 27 15:44:19 2010 (r6128) @@ -97,6 +97,93 @@ char *name; } msr_entry_t; + /* Pentium III */ + static const msr_entry_t model67x_global_msrs[] = { + { 0x0000, "IA32_P5_MC_ADDR" }, + { 0x0001, "IA32_P5_MC_TYPE" }, + { 0x0010, "IA32_TIME_STAMP_COUNTER" }, + { 0x0017, "IA32_PLATFORM_ID" }, + { 0x001b, "IA32_APIC_BASE" }, + { 0x002a, "EBL_CR_POWERON" }, + { 0x0033, "TEST_CTL" }, + //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO + { 0x0088, "BBL_CR_D0" }, + { 0x0089, "BBL_CR_D1" }, + { 0x008a, "BBL_CR_D2" }, + { 0x008b, "IA32_BIOS_SIGN_ID" }, + { 0x00c1, "PERFCTR0" }, + { 0x00c2, "PERFCTR1" }, + { 0x00fe, "IA32_MTRRCAP" }, + { 0x0116, "BBL_CR_ADDR" }, + { 0x0118, "BBL_CR_DECC" }, + { 0x0119, "BBL_CR_CTL" }, + //{ 0x011a, "BBL_CR_TRIG" }, + { 0x011b, "BBL_CR_BUSY" }, + { 0x011e, "BBL_CR_CTL3" }, + { 0x0174, "IA32_SYSENTER_CS" }, + { 0x0175, "IA32_SYSENTER_ESP" }, + { 0x0176, "IA32_SYSENTER_EIP" }, + { 0x0179, "IA32_MCG_CAP" }, + { 0x017a, "IA32_MCG_STATUS" }, + { 0x017b, "IA32_MCG_CTL" }, + { 0x0186, "IA32_PERF_EVNTSEL0" }, + { 0x0187, "IA32_PERF_EVNTSEL1" }, + { 0x01d9, "IA32_DEBUGCTL" }, + { 0x01db, "MSR_LASTBRANCHFROMIP" }, + { 0x01dc, "MSR_LASTBRANCHTOIP" }, + { 0x01dd, "MSR_LASTINTFROMIP" }, + { 0x01de, "MSR_LASTINTTOIP" }, + { 0x01e0, "MSR_ROB_CR_BKUPTMPDR6" }, + { 0x0200, "IA32_MTRR_PHYSBASE0" }, + { 0x0201, "IA32_MTRR_PHYSMASK0" }, + { 0x0202, "IA32_MTRR_PHYSBASE1" }, + { 0x0203, "IA32_MTRR_PHYSMASK1" }, + { 0x0204, "IA32_MTRR_PHYSBASE2" }, + { 0x0205, "IA32_MTRR_PHYSMASK2" }, + { 0x0206, "IA32_MTRR_PHYSBASE3" }, + { 0x0207, "IA32_MTRR_PHYSMASK3" }, + { 0x0208, "IA32_MTRR_PHYSBASE4" }, + { 0x0209, "IA32_MTRR_PHYSMASK4" }, + { 0x020a, "IA32_MTRR_PHYSBASE5" }, + { 0x020b, "IA32_MTRR_PHYSMASK5" }, + { 0x020c, "IA32_MTRR_PHYSBASE6" }, + { 0x020d, "IA32_MTRR_PHYSMASK6" }, + { 0x020e, "IA32_MTRR_PHYSBASE7" }, + { 0x020f, "IA32_MTRR_PHYSMASK7" }, + { 0x0250, "IA32_MTRR_FIX64K_00000" }, + { 0x0258, "IA32_MTRR_FIX16K_80000" }, + { 0x0259, "IA32_MTRR_FIX16K_A0000" }, + { 0x0268, "IA32_MTRR_FIX4K_C0000" }, + { 0x0269, "IA32_MTRR_FIX4K_C8000" }, + { 0x026a, "IA32_MTRR_FIX4K_D0000" }, + { 0x026b, "IA32_MTRR_FIX4K_D8000" }, + { 0x026c, "IA32_MTRR_FIX4K_E0000" }, + { 0x026d, "IA32_MTRR_FIX4K_E8000" }, + { 0x026e, "IA32_MTRR_FIX4K_F0000" }, + { 0x026f, "IA32_MTRR_FIX4K_F8000" }, + { 0x02ff, "IA32_MTRR_DEF_TYPE" }, + { 0x0400, "IA32_MC0_CTL" }, + { 0x0401, "IA32_MC0_STATUS" }, + { 0x0402, "IA32_MC0_ADDR" }, + //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO + { 0x0404, "IA32_MC1_CTL" }, + { 0x0405, "IA32_MC1_STATUS" }, + { 0x0406, "IA32_MC1_ADDR" }, + //{ 0x0407, "IA32_MC1_MISC" }, // Seems to be RO + { 0x0408, "IA32_MC2_CTL" }, + { 0x0409, "IA32_MC2_STATUS" }, + { 0x040a, "IA32_MC2_ADDR" }, + //{ 0x040b, "IA32_MC2_MISC" }, // Seems to be RO + { 0x040c, "IA32_MC4_CTL" }, + { 0x040d, "IA32_MC4_STATUS" }, + { 0x040e, "IA32_MC4_ADDR" }, + //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO + { 0x0410, "IA32_MC3_CTL" }, + { 0x0411, "IA32_MC3_STATUS" }, + { 0x0412, "IA32_MC3_ADDR" }, + //{ 0x0413, "IA32_MC3_MISC" }, // Seems to be RO + }; + static const msr_entry_t model6bx_global_msrs[] = { { 0x0010, "IA32_TIME_STAMP_COUNTER" }, { 0x0017, "IA32_PLATFORM_ID" }, @@ -453,6 +540,7 @@ } cpu_t; cpu_t cpulist[] = { + { 0x00670, model67x_global_msrs, ARRAY_SIZE(model67x_global_msrs), NULL, 0 }, { 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 }, { 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) }, { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) }, Modified: trunk/util/inteltool/inteltool.c ============================================================================== --- trunk/util/inteltool/inteltool.c Sat Nov 27 10:40:16 2010 (r6127) +++ trunk/util/inteltool/inteltool.c Sat Nov 27 15:44:19 2010 (r6128) @@ -322,7 +322,7 @@ } if (dump_pmbase) { - print_pmbase(sb); + print_pmbase(sb, pacc); printf("\n\n"); } Modified: trunk/util/inteltool/inteltool.h ============================================================================== --- trunk/util/inteltool/inteltool.h Sat Nov 27 10:40:16 2010 (r6127) +++ trunk/util/inteltool/inteltool.h Sat Nov 27 15:44:19 2010 (r6128) @@ -115,7 +115,7 @@ unsigned int cpuid(unsigned int op); int print_intel_core_msrs(void); int print_mchbar(struct pci_dev *nb); -int print_pmbase(struct pci_dev *sb); +int print_pmbase(struct pci_dev *sb, struct pci_access *pacc); int print_rcba(struct pci_dev *sb); int print_gpios(struct pci_dev *sb); int print_epbar(struct pci_dev *nb); Modified: trunk/util/inteltool/powermgt.c ============================================================================== --- trunk/util/inteltool/powermgt.c Sat Nov 27 10:40:16 2010 (r6127) +++ trunk/util/inteltool/powermgt.c Sat Nov 27 15:44:19 2010 (r6128) @@ -524,11 +524,12 @@ { 0x37, 1, "GPOREG 3" }, }; -int print_pmbase(struct pci_dev *sb) +int print_pmbase(struct pci_dev *sb, struct pci_access *pacc) { int i, size; uint16_t pmbase; const io_register_t *pm_registers; + struct pci_dev *acpi; printf("\n============= PMBASE ============\n\n"); @@ -584,7 +585,12 @@ size = ARRAY_SIZE(ich0_pm_registers); break; case PCI_DEVICE_ID_INTEL_82371XX: - pmbase = pci_read_word(sb, 0x40) & 0xfffc; + acpi = pci_get_dev(pacc, sb->domain, sb->bus, sb->dev, 3); + if (!acpi) { + printf("Southbridge function 3 not found.\n"); + return 1; + } + pmbase = pci_read_word(acpi, 0x40) & 0xfffc; pm_registers = i82371xx_pm_registers; size = ARRAY_SIZE(i82371xx_pm_registers); break;

1 0

Request for i852 -> i855 ACPI dump, please
by Joseph Smith 27 Nov '10

27 Nov '10

Hello, I am in desperate need of a full (all tables) ACPI dump from somone with a i852 or i855 chipset. You can send it to me offlist if you like. Thanks in advance. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org

1 0

hello
by ali hagigat 27 Nov '10

27 Nov '10

We have the following definition for CC: CC:=gcc -Wa,--divide -fno-stack-protector -Wl,--build-id=none I wonder if any one can explain the options, --divide and --build-id. Thank you.

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coreboot November 2010