coreboot November 2010

coreboot@coreboot.org

48 participants
285 discussions

Porting to Asus M4A78-EM
by Juhana Helovuo 07 Dec '10

07 Dec '10

Hello all, I bought a new Asus M4A78-EM mainboard and started porting Coreboot to it. This board is very similar to M4A785-M board I had recently. Since the chipset is almost the same, and the Super I/O is the same, I configured and compiled for M4A785-M and Coreinfo worked on the first try, VGA and all. No code changes were required. The BIOS for onboard VGA was extracted with the bios_extract utility. I documented my initial results into the Coreboot wiki: http://www.coreboot.org/ASUS_M4A78-EM Summary of results so far: * Coreinfo: runs fine, both on serial and VGA. * SeaBIOS: ok, both on serial and VGA. USB mouse attached makes SeaBIOS freeze on initialization. * SeaBIOS can load Coreinfo, which again works. * SeaBIOS can load FreeDOS from IDE CDROM. Seems to work ok. * SeaBIOS freezes when loading Debian installer (syslinux) from IDE CDROM. No useful output on serial and VGA is blank. * SeaBIOS can load Grub2 from SATA disk. Text "Welcome to Grub!" flashes on VGA, then the mainboard powers down, which makes debugging rather difficult. A boot log is attached. In this case FreeDOS was booted. Trying the same with Debian installer CD looks the same from the serial port (except for CD medium size). Any good ideas how to proceed from here? Do you see anything suspicious in the boot log? Best regards, Juhana Helovuo

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[PATCH] W83627DHG/W83627EHG fixups for virtual LDNs
by Uwe Hermann 05 Dec '10

05 Dec '10

This is abuild-tested. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

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[patch] update crossgcc
by Marc Jones 04 Dec '10

04 Dec '10

Update coreboot crossgcc toolchain, GDB 4.5.1, MPFR 3.0.0, GDB 7.2. Add libelf_cv_elf_h_works=no to produce a libelf.h for Cygwin. Add GDB patch to handle #pragma pack in the i386-elf gcc target. Signed-off-by: Marc Jones <marcj303(a)gmail.com> Tested on IEI Kino Fam10 mainboard. Can someone test that this works on some other mainboards, maybe Intel or Via based? Marc -- http://se-eng.com

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[PATCH] 939a785gmh ACPI diet
by Rudolf Marek 04 Dec '10

04 Dec '10

Hello, Following patch removes the cut-and-paste stuff from Mahagony and fixes the _CRS object to make it work (same code as on M2V-MX SE) Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Thanks, Rudolf

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[PATCH]Allow relocated .config location
by Patrick Georgi 02 Dec '10

02 Dec '10

Hi, right now, the build system assumes that .config is in $(top). abuild stores each board's .config by copying it into the build directory after the fact, while clobbering any existing files. With the attached patch, it's possible to define a new location for .config, using the DOTCONFIG variable, and abuild makes use of that. It still messes around with .xcompile and the various .config copies, so this is only the second step of many (I already started on that topic a while ago, with a minor change to Makefile), but it's a start, and should be self contained. == Allow user to relocate .config by using the DOTCONFIG variable. Make abuild use that. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>

2 1

[PATCH] ASUS P2B ACPI sleep preparations
by Tobias Diedrich 02 Dec '10

02 Dec '10

Add acpi_is_wakeup_early to i82371eb and P2B. Build fix for src/arch/i386/boot/acpi.c if !CONFIG_SMP Also check for acpi_slp_type 2 in acpi_is_wakeup, since S2 uses the same acpi wakeup vector as S3. Other chipsets so far only ever set acpi_slp_type to 0 and 3. Abuild-tested. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- Index: coreboot-svn-p2b/src/mainboard/asus/p2b/romstage.c =================================================================== --- coreboot-svn-p2b.orig/src/mainboard/asus/p2b/romstage.c 2010-11-27 11:48:28.000000000 +0100 +++ coreboot-svn-p2b/src/mainboard/asus/p2b/romstage.c 2010-11-27 11:55:12.000000000 +0100 @@ -36,6 +36,8 @@ #define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1) +void enable_pm(void); +int acpi_is_wakeup_early(void); void enable_smbus(void); int smbus_read_byte(u8 device, u8 address); @@ -46,14 +48,23 @@ void main(unsigned long bist) { + u16 boot_mode; + w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); report_bist_failure(bist); + enable_pm(); + boot_mode = acpi_is_wakeup_early(); + enable_smbus(); dump_spd_registers(); - sdram_set_registers(); - sdram_set_spd_registers(); - sdram_enable(); + if (boot_mode == 5 || boot_mode == 0) { + /* should't be needed on warm boot (boot_mode 0), + * but can't hurt... */ + sdram_set_registers(); + sdram_set_spd_registers(); + sdram_enable(); + } } Index: coreboot-svn-p2b/src/arch/i386/boot/acpi.c =================================================================== --- coreboot-svn-p2b.orig/src/arch/i386/boot/acpi.c 2010-11-27 11:48:28.000000000 +0100 +++ coreboot-svn-p2b/src/arch/i386/boot/acpi.c 2010-11-27 11:48:41.000000000 +0100 @@ -481,7 +481,7 @@ static int acpi_is_wakeup(void) { - return (acpi_slp_type == 3); + return (acpi_slp_type == 3 || acpi_slp_type == 2); } static acpi_rsdp_t *valid_rsdp(acpi_rsdp_t *rsdp) @@ -567,9 +567,11 @@ return wake_vec; } +#if CONFIG_SMP == 1 extern char *lowmem_backup; extern char *lowmem_backup_ptr; extern int lowmem_backup_size; +#endif #define WAKEUP_BASE 0x600 @@ -588,12 +590,14 @@ return; } +#if CONFIG_SMP == 1 // FIXME: This should go into the ACPI backup memory, too. No pork saussages. /* * Just restore the SMP trampoline and continue with wakeup on * assembly level. */ memcpy(lowmem_backup_ptr, lowmem_backup, lowmem_backup_size); +#endif /* Copy wakeup trampoline in place. */ memcpy((void *)WAKEUP_BASE, &__wakeup, (size_t)&__wakeup_size); Index: coreboot-svn-p2b/src/southbridge/intel/i82371eb/Kconfig =================================================================== --- coreboot-svn-p2b.orig/src/southbridge/intel/i82371eb/Kconfig 2010-11-27 11:48:28.000000000 +0100 +++ coreboot-svn-p2b/src/southbridge/intel/i82371eb/Kconfig 2010-11-27 11:48:41.000000000 +0100 @@ -1,6 +1,7 @@ config SOUTHBRIDGE_INTEL_I82371EB bool select TINY_BOOTBLOCK + select HAVE_ACPI_RESUME if HAVE_ACPI_TABLES config BOOTBLOCK_SOUTHBRIDGE_INIT string Index: coreboot-svn-p2b/src/southbridge/intel/i82371eb/i82371eb_smbus.c =================================================================== --- coreboot-svn-p2b.orig/src/southbridge/intel/i82371eb/i82371eb_smbus.c 2010-11-27 11:48:28.000000000 +0100 +++ coreboot-svn-p2b/src/southbridge/intel/i82371eb/i82371eb_smbus.c 2010-11-27 11:51:16.000000000 +0100 @@ -31,6 +31,10 @@ #include "i82371eb.h" #include "i82371eb_smbus.h" +#if CONFIG_HAVE_ACPI_RESUME == 1 +extern u8 acpi_slp_type; +#endif + static void pwrmgt_enable(struct device *dev) { struct southbridge_intel_i82371eb_config *sb = dev->chip_info; @@ -87,6 +91,24 @@ outw(0xffff, DEFAULT_PMBASE + GLBSTS); outl(0xffffffff, DEFAULT_PMBASE + DEVSTS); +#if CONFIG_HAVE_ACPI_RESUME == 1 + reg = (inw(DEFAULT_PMBASE + PMCNTRL) >> 10) & 7; + switch (reg) { + case 1: + acpi_slp_type = 3; + break; + case 2: + case 3: + acpi_slp_type = 2; + break; + default: + acpi_slp_type = 5; + break; + } + printk(BIOS_INFO, + "%s: acpi_slp_type=%d!\n", __func__, acpi_slp_type); +#endif + /* set pmcntrl default */ outw(SUS_TYP_S0|SCI_EN, DEFAULT_PMBASE + PMCNTRL); } Index: coreboot-svn-p2b/src/southbridge/intel/i82371eb/i82371eb_early_pm.c =================================================================== --- coreboot-svn-p2b.orig/src/southbridge/intel/i82371eb/i82371eb_early_pm.c 2010-11-27 11:48:28.000000000 +0100 +++ coreboot-svn-p2b/src/southbridge/intel/i82371eb/i82371eb_early_pm.c 2010-11-27 11:48:41.000000000 +0100 @@ -51,3 +51,48 @@ reg8 |= PMIOSE; pci_write_config8(dev, PMREGMISC, reg8); } + +int acpi_is_wakeup_early(void); + +/* + * Intel i82371eb (piix4e) datasheet, section 7.2.3, page 142: + * + * 000b / 0x0: soft off/suspend to disk (soff/std) S5 + * 001b / 0x1: suspend to ram (str) S3 + * 010b / 0x2: powered on suspend, context lost (poscl) S2 + * Note: 'context lost' menas the cpu restarts at the reset vector + * 011b / 0x3: powered on suspend, cpu context lost (posccl) S1 + * Note: Looks like 'cpu context lost' does _not_ mean the cpu + * restarts at the reset vector. Most likely only caches + * are lost, so both 0x3 and 0x4 map to acpi S1 + * 100b / 0x4: powered on suspend, context maintained (pos) S1 + * 101b / 0x5: working (clock control) S0 + * 110b / 0x6: reserved + * 111b / 0x7: reserved + */ +static const u8 acpi_sus_to_slp_typ[8] = { + 5, 3, 2, 1, 1, 0, 0, 0 +}; + +int acpi_is_wakeup_early(void) +{ + u16 tmp, result; + + print_debug(__func__); + print_debug("\n"); + + tmp = inw(DEFAULT_PMBASE + PMCNTRL); + print_debug(" pmcntrl="); + print_debug_hex16(tmp); + print_debug("\n"); + + result = 5; /* S5, system came out of power-off */ + tmp = (tmp >> 10) & 7; + result = acpi_sus_to_slp_typ[tmp]; + + print_debug(" boot_mode="); + print_debug_hex8(result); + print_debug("\n"); + + return result; +}

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[commit] r6135 - trunk/src/mainboard/asrock/939a785gmh
by repository service 30 Nov '10

30 Nov '10

Author: ruik Date: Tue Nov 30 22:21:33 2010 New Revision: 6135 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6135 Log: The patch just make the power LED on. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/romstage.c Tue Nov 30 21:18:53 2010 (r6134) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Tue Nov 30 22:21:33 2010 (r6135) @@ -83,6 +83,10 @@ reg = pnp_read_config(GPIO2345_DEV, 0x29); pnp_write_config(GPIO2345_DEV, 0x29, (reg | 2)); + /* Turn on the Power LED ("Suspend LED" in Super I/O) */ + reg = pnp_read_config(GPIO2345_DEV, 0xf3); + pnp_write_config(GPIO2345_DEV, 0xf3, (reg | 0x40)); + /* todo document this */ pnp_write_config(GPIO2345_DEV, 0x2c, 0x1); pnp_write_config(GPIO2345_DEV, 0x2d, 0x1);

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[PATCH] fix LED on 939a785gmh
by Rudolf Marek 30 Nov '10

30 Nov '10

The patch just make the power LED on. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Thanks, Rudolf

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[commit] r6134 - trunk/src/mainboard/asrock/939a785gmh
by repository service 30 Nov '10

30 Nov '10

Author: ruik Date: Tue Nov 30 21:18:53 2010 New Revision: 6134 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6134 Log: Fix the SPD to channel mapping. Please note that there is something wrong with UMA. Single channel (in slot DDR1 and DDR3) produces strange artefacts on screen (and hang) Dual Channel (in DDR1 and DDR2 aka blue slot) - works nice All slots populated - same case as Single channel - must be something wrong with UMA. Tested with 2x 512MB CAS 2.5 DDR400 Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/romstage.c Tue Nov 30 03:05:17 2010 (r6133) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Tue Nov 30 21:18:53 2010 (r6134) @@ -121,7 +121,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { - static const u16 spd_addr[] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; + static const u16 spd_addr[] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, }; int needs_reset = 0; u32 bsp_apicid = 0; msr_t msr;

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Where does printk(DEBUG, "msg") go after booting?
by Fengwei Zhang 30 Nov '10

30 Nov '10

Hi all, I understand the printk(DEBUG, "msg") statement will print out msg on the serial port when booting. How about after booting? Where does printk(DEBUG, "msg") go after booting? Thank you very much! Best, Fengwei

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coreboot November 2010