coreboot November 2010

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285 discussions

K8+RS780+SB710 board failed to boot linux with 4G DRAM
by Liu Tao 23 Nov '10

23 Nov '10

Hello all, I'm porting coreboot on a K8+RS780+SB710 board, the board is similiar with AMD's mahogany board in hardware routing, the major difference is my board has RS780/SB710 on CPU's HT chain1, not the default chain 0. My porting work is based on the mahogany code in official tree, the major changes including: 1) configure device/resource map to point out southbridge is on ht chain 1 2) fix hard-coded ht chain0 mmio in RS780 configuration codes (committed r5959) 3) board related MPTABLE/ IRQTABLE/ ACPI_routing configurations I use seabios to boot RHEL 5.5 X86_64 system on my SATA disk, which connects at SB710's SATA port 0. With 2G DRAM, the system boots and works fine, but with 4G DRAM, the system failed to detect the SATA disk and repeats waiting. I tried mem=4g param with 4G DRAM, that works, but wasts memory mapped to 4G above. I have tried disable UMA and Integrated Graphics, disable GART, use soft iommu in kernel, and noapic/nolapic/noacpi/noapm/acpi=off kernel params, all has no effect with the problem. Attached is the coreboot+kernel boot log, for 4G DRAM with/without mem=4g param, any suggestion is welcome, thanks. -- Regards, Liu Tao

2 2

[PATCH] fix S3 support on AMD K8 famF
by Rudolf Marek 22 Nov '10

22 Nov '10

Hi all, I think I fixed the S3 suspend/resume on AMD which was broken since Stephan did the change with cbmem :) The patch does following: 1) wraps the s3 parts of chipset code/memory init code with if CONFIG_HAVE_ACPI_RESUME == 1 getting rid of ugly define in romstage.c 2) the patch implements get_cbmem_toc in chipset specific way if defined. On Intel targets it should be unchanged. On K8T890 the the cbmem_toc is read from NVRAM. Why you ask? Because we cannot do it as on intel, because the framebuffer might be there making it hard to look for it in memory (and remember we need it so early that everying is uncached) 3) The patch removes hardcoded limits for suspend/resume save area (it was 1MB) on intel. Now it computes right numbers itself. 4) it impelements saving the memory during CAR to reserved range in sane way. First the sysinfo area (CAR data) is copied, then the rest after car is disabled (cached copy is used). I changed bit also the the copy of CAR area is now done uncached for target which I feel is more right. I think I did not change the Intel suspend/resume behaviour but best would be if someone can test it. Please note this patch was unfinished on my drive since ages and it would be very nice to get it in to prevent bit rotten it again. Now I feel it is done good way and should not break anything. I did a test with abuild and it seems fine. The Rachmann did suspend/resume support for Asus M2V he will post the patch soon. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Thanks, Rudolf

3 5

[commit] r6117 - in trunk/src: arch/i386/boot cpu/amd/car include lib mainboard/asus/a8v-e_deluxe mainboard/asus/a8v-e_se mainboard/asus/m2v mainboard/asus/m2v-mx_se northbridge/amd/amdk8 southbrid...
by repository service 22 Nov '10

22 Nov '10

Author: ruik Date: Mon Nov 22 23:00:52 2010 New Revision: 6117 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6117 Log: 1) wraps the s3 parts of chipset code/memory init code with if CONFIG_HAVE_ACPI_RESUME == 1 getting rid of ugly define in romstage.c 2) the patch implements get_cbmem_toc in chipset specific way if defined. On Intel targets it should be unchanged. On K8T890 the the cbmem_toc is read from NVRAM. Why you ask? Because we cannot do it as on intel, because the framebuffer might be there making it hard to look for it in memory (and remember we need it so early that everying is uncached) 3) The patch removes hardcoded limits for suspend/resume save area (it was 1MB) on intel. Now it computes right numbers itself. 4) it impelements saving the memory during CAR to reserved range in sane way. First the sysinfo area (CAR data) is copied, then the rest after car is disabled (cached copy is used). I changed bit also the the copy of CAR area is now done uncached for target which I feel is more right. I think I did not change the Intel suspend/resume behaviour but best would be if someone can test it. Please note this patch was unfinished on my drive since ages and it would be very nice to get it in to prevent bit rotten it again. Now I feel it is done good way and should not break anything. I did a test with abuild and it seems fine. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Modified: trunk/src/arch/i386/boot/acpi.c trunk/src/arch/i386/boot/tables.c trunk/src/cpu/amd/car/post_cache_as_ram.c trunk/src/include/cbmem.h trunk/src/lib/cbmem.c trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/asus/m2v-mx_se/Kconfig trunk/src/mainboard/asus/m2v-mx_se/mainboard.c trunk/src/mainboard/asus/m2v-mx_se/romstage.c trunk/src/mainboard/asus/m2v/romstage.c trunk/src/northbridge/amd/amdk8/northbridge.c trunk/src/northbridge/amd/amdk8/raminit_f.c trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c trunk/src/southbridge/via/k8t890/k8t890.h trunk/src/southbridge/via/k8t890/k8t890_early_car.c trunk/src/southbridge/via/k8t890/k8t890_host_ctrl.c trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Modified: trunk/src/arch/i386/boot/acpi.c ============================================================================== --- trunk/src/arch/i386/boot/acpi.c Mon Nov 22 17:23:54 2010 (r6116) +++ trunk/src/arch/i386/boot/acpi.c Mon Nov 22 23:00:52 2010 (r6117) @@ -470,17 +470,6 @@ { void *wake_vec; -#if 0 -#if CONFIG_MEM_TRAIN_SEQ != 0 - #error "So far it works on AMD and CONFIG_MEM_TRAIN_SEQ == 0" -#endif - -#if CONFIG_RAMBASE < 0x1F00000 - #error "For ACPI RESUME you need to have CONFIG_RAMBASE at least 31MB" - #error "Chipset support (S3_NVRAM_EARLY and ACPI_IS_WAKEUP_EARLY functions and memory ctrl)" - #error "And coreboot memory reserved in mainboard.c" -#endif -#endif /* If we happen to be resuming find wakeup vector and jump to OS. */ wake_vec = acpi_find_wakeup_vector(); if (wake_vec) Modified: trunk/src/arch/i386/boot/tables.c ============================================================================== --- trunk/src/arch/i386/boot/tables.c Mon Nov 22 17:23:54 2010 (r6116) +++ trunk/src/arch/i386/boot/tables.c Mon Nov 22 23:00:52 2010 (r6117) @@ -214,7 +214,7 @@ * it begin there during reboot time. We don't need the pointer, nor * the result right now. If it fails, ACPI resume will be disabled. */ - cbmem_add(CBMEM_ID_RESUME, 1024 * (1024-64)); + cbmem_add(CBMEM_ID_RESUME, HIGH_MEMORY_SAVE); #endif #if CONFIG_MULTIBOOT Modified: trunk/src/cpu/amd/car/post_cache_as_ram.c ============================================================================== --- trunk/src/cpu/amd/car/post_cache_as_ram.c Mon Nov 22 17:23:54 2010 (r6116) +++ trunk/src/cpu/amd/car/post_cache_as_ram.c Mon Nov 22 23:00:52 2010 (r6117) @@ -27,6 +27,45 @@ : "0" (bytes / 4), "g" (bytes), "1" ((long)dest), "2" ((long)src) : "memory", "cc"); } + +#if CONFIG_HAVE_ACPI_RESUME == 1 + +static inline void *backup_resume(void) { + unsigned long high_ram_base; + void *resume_backup_memory; + int suspend = acpi_is_wakeup_early(); + + if (!suspend) + return NULL; + + /* Start address of high memory tables */ + high_ram_base = (u32) get_cbmem_toc(); + + print_debug_pcar("CBMEM TOC is at: ", (uint32_t)high_ram_base); + print_debug_pcar("CBMEM TOC 0-size: ",(uint32_t)(high_ram_base + HIGH_MEMORY_SIZE + 4096)); + + cbmem_reinit((u64)high_ram_base); + + resume_backup_memory = cbmem_find(CBMEM_ID_RESUME); + + /* copy 1MB - 64K to high tables ram_base to prevent memory corruption + * through stage 2. We could keep stuff like stack and heap in high tables + * memory completely, but that's a wonderful clean up task for another + * day. + */ + + if (resume_backup_memory) { + print_debug_pcar("Will copy coreboot region to: ", (uint32_t) resume_backup_memory); + /* copy only backup only memory used for CAR */ + memcopy(resume_backup_memory+HIGH_MEMORY_SAVE-CONFIG_DCACHE_RAM_SIZE, + (void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), + CONFIG_DCACHE_RAM_SIZE); //inline + } + + return resume_backup_memory; +} +#endif + /* Disable Erratum 343 Workaround, see RevGuide for Fam10h, Pub#41322 Rev 3.33 */ static void vErrata343(void) @@ -43,7 +82,9 @@ static void post_cache_as_ram(void) { - +#if CONFIG_HAVE_ACPI_RESUME == 1 + void *resume_backup_memory; +#endif #if 1 { /* Check value of esp to verify if we have enough rom for stack in Cache as RAM */ @@ -66,17 +107,16 @@ #error "You need to set CONFIG_RAMTOP greater than 1M" #endif - /* So we can access RAM from [1M, CONFIG_RAMTOP) */ - set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); +#if CONFIG_HAVE_ACPI_RESUME == 1 + resume_backup_memory = backup_resume(); +#endif -// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x8000, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x7c00); print_debug("Copying data from cache to RAM -- switching to use RAM as stack... "); /* from here don't store more data in CAR */ vErrata343(); memcopy((void *)((CONFIG_RAMTOP)-CONFIG_DCACHE_RAM_SIZE), (void *)CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); //inline -// dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00); __asm__ volatile ( /* set new esp */ /* before CONFIG_RAMBASE */ @@ -94,9 +134,25 @@ print_debug_pcar("testx = ", testx); print_debug("Disabling cache as ram now \n"); + disable_cache_as_ram_bsp(); + disable_cache(); + set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK); + enable_cache(); + +#if CONFIG_HAVE_ACPI_RESUME == 1 + /* now copy the rest of the area, using the WB method because we already + run normal RAM */ + if (resume_backup_memory) { + memcopy(resume_backup_memory, + (void *)(CONFIG_RAMBASE), + (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); + } +#endif + print_debug("Clearing initial memory region: "); + #if CONFIG_HAVE_ACPI_RESUME == 1 /* clear only coreboot used region of memory. Note: this may break ECC enabled boards */ memset((void*) CONFIG_RAMBASE, 0, (CONFIG_RAMTOP) - CONFIG_RAMBASE - CONFIG_DCACHE_RAM_SIZE); @@ -105,8 +161,6 @@ #endif print_debug("Done\n"); -// dump_mem((CONFIG_RAMTOP) - 0x8000, (CONFIG_RAMTOP) - 0x7c00); - set_sysinfo_in_ram(1); // So other core0 could start to train mem #if CONFIG_MEM_TRAIN_SEQ == 1 Modified: trunk/src/include/cbmem.h ============================================================================== --- trunk/src/include/cbmem.h Mon Nov 22 17:23:54 2010 (r6116) +++ trunk/src/include/cbmem.h Mon Nov 22 23:00:52 2010 (r6117) @@ -24,7 +24,7 @@ #define HIGH_MEMORY_TABLES ( 64 * 1024 ) #if CONFIG_HAVE_ACPI_RESUME -#define HIGH_MEMORY_SIZE ( 1024 * 1024 ) +#define HIGH_MEMORY_SIZE ((CONFIG_RAMTOP - CONFIG_RAMBASE) + HIGH_MEMORY_TABLES) #define HIGH_MEMORY_SAVE ( HIGH_MEMORY_SIZE - HIGH_MEMORY_TABLES ) #else #define HIGH_MEMORY_SIZE HIGH_MEMORY_TABLES @@ -48,4 +48,6 @@ void cbmem_list(void); void cbmem_arch_init(void); +struct cbmem_entry *get_cbmem_toc(void); +void set_cbmem_toc(struct cbmem_entry *); #endif Modified: trunk/src/lib/cbmem.c ============================================================================== --- trunk/src/lib/cbmem.c Mon Nov 22 17:23:54 2010 (r6116) +++ trunk/src/lib/cbmem.c Mon Nov 22 23:00:52 2010 (r6117) @@ -36,11 +36,32 @@ u64 size; } __attribute__((packed)); -#ifndef __PRE_RAM__ -struct cbmem_entry *bss_cbmem_toc; -#define get_cbmem_toc() bss_cbmem_toc + +#ifdef __PRE_RAM__ + +/* note this should be done as weak function but we do #include + of C files in the romstage breaking this (in same compile + unit is weak and non weak function +struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) +*/ +#ifndef get_cbmem_toc + #define get_cbmem_toc() (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE) +#endif + #else -#define get_cbmem_toc() (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE) + +static struct cbmem_entry *bss_cbmem_toc; + +struct cbmem_entry *__attribute__((weak)) get_cbmem_toc(void) +{ + return bss_cbmem_toc; +} + +void __attribute__((weak)) set_cbmem_toc(struct cbmem_entry * x) +{ + /* do nothing, this should be called by chipset to save TOC in NVRAM */ +} + #endif /** @@ -70,6 +91,10 @@ for (;;) ; } + /* we don't need to call this in romstage, usefull only from ramstage */ +#ifndef __PRE_RAM__ + set_cbmem_toc((struct cbmem_entry *)(unsigned long)baseaddr); +#endif memset(cbmem_toc, 0, CBMEM_TOC_RESERVED); cbmem_toc[0] = (struct cbmem_entry) { Modified: trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c Mon Nov 22 17:23:54 2010 (r6116) +++ trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c Mon Nov 22 23:00:52 2010 (r6117) @@ -79,7 +79,6 @@ } } -// defines S3_NVRAM_EARLY: #include "southbridge/via/k8t890/k8t890_early_car.c" #include "northbridge/amd/amdk8/amdk8.h" #include "northbridge/amd/amdk8/incoherent_ht.c" Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Mon Nov 22 17:23:54 2010 (r6116) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Mon Nov 22 23:00:52 2010 (r6117) @@ -79,7 +79,6 @@ } } -// defines S3_NVRAM_EARLY: #include "southbridge/via/k8t890/k8t890_early_car.c" #include "northbridge/amd/amdk8/amdk8.h" #include "northbridge/amd/amdk8/incoherent_ht.c" Modified: trunk/src/mainboard/asus/m2v-mx_se/Kconfig ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/Kconfig Mon Nov 22 17:23:54 2010 (r6116) +++ trunk/src/mainboard/asus/m2v-mx_se/Kconfig Mon Nov 22 23:00:52 2010 (r6117) @@ -35,6 +35,7 @@ select RAMINIT_SYSINFO select VGA select TINY_BOOTBLOCK + select HAVE_ACPI_RESUME select HAVE_MAINBOARD_RESOURCES select QRANK_DIMM_SUPPORT select SET_FIDVID Modified: trunk/src/mainboard/asus/m2v-mx_se/mainboard.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/mainboard.c Mon Nov 22 17:23:54 2010 (r6116) +++ trunk/src/mainboard/asus/m2v-mx_se/mainboard.c Mon Nov 22 23:00:52 2010 (r6117) @@ -34,13 +34,6 @@ lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base, uma_memory_size); #endif - -#if CONFIG_HAVE_ACPI_RESUME == 1 - lb_add_memory_range(mem, LB_MEM_RESERVED, - CONFIG_RAMBASE, ((CONFIG_RAMTOP) - CONFIG_RAMBASE)); - lb_add_memory_range(mem, LB_MEM_RESERVED, - CONFIG_DCACHE_RAM_BASE, CONFIG_DCACHE_RAM_SIZE); -#endif return 0; } Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Mon Nov 22 17:23:54 2010 (r6116) +++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Mon Nov 22 23:00:52 2010 (r6117) @@ -62,7 +62,6 @@ return smbus_read_byte(device, address); } -// defines S3_NVRAM_EARLY: #include "southbridge/via/k8t890/k8t890_early_car.c" #include "northbridge/amd/amdk8/amdk8.h" #include "northbridge/amd/amdk8/incoherent_ht.c" @@ -75,6 +74,15 @@ #define SB_VFSMAF 0 + +// Now, this needs to be included because it relies on the symbol +// __PRE_RAM__ being set during CAR stage (in order to compile the +// BSS free versions of the functions). Either rewrite the code +// to be always BSS free, or invent a flag that's better suited than +// __PRE_RAM__ to determine whether we're in ram init stage (stage 1) +// +#include "lib/cbmem.c" + /* this function might fail on some K8 CPUs with errata #181 */ static void ldtstop_sb(void) { Modified: trunk/src/mainboard/asus/m2v/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v/romstage.c Mon Nov 22 17:23:54 2010 (r6116) +++ trunk/src/mainboard/asus/m2v/romstage.c Mon Nov 22 23:00:52 2010 (r6117) @@ -64,7 +64,6 @@ return smbus_read_byte(device, address); } -// defines S3_NVRAM_EARLY: #include "southbridge/via/k8t890/k8t890_early_car.c" #include "northbridge/amd/amdk8/amdk8.h" #include "northbridge/amd/amdk8/incoherent_ht.c" Modified: trunk/src/northbridge/amd/amdk8/northbridge.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/northbridge.c Mon Nov 22 17:23:54 2010 (r6116) +++ trunk/src/northbridge/amd/amdk8/northbridge.c Mon Nov 22 23:00:52 2010 (r6117) @@ -819,7 +819,8 @@ #endif #if CONFIG_WRITE_HIGH_TABLES==1 -#define HIGH_TABLES_SIZE 64 /* maximum size of high tables in KB */ +#include <cbmem.h> +#define HIGH_TABLES_SIZE ((HIGH_MEMORY_SIZE + 1024) / 1024) extern uint64_t high_tables_base, high_tables_size; #endif Modified: trunk/src/northbridge/amd/amdk8/raminit_f.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f.c Mon Nov 22 17:23:54 2010 (r6116) +++ trunk/src/northbridge/amd/amdk8/raminit_f.c Mon Nov 22 23:00:52 2010 (r6117) @@ -2988,14 +2988,15 @@ } #endif - +#if CONFIG_HAVE_ACPI_RESUME == 1 #include "exit_from_self.c" +#endif static void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo) { int i; -#ifdef ACPI_IS_WAKEUP_EARLY +#if CONFIG_HAVE_ACPI_RESUME == 1 int suspend = acpi_is_wakeup_early(); #else int suspend = 0; Modified: trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Mon Nov 22 17:23:54 2010 (r6116) +++ trunk/src/northbridge/amd/amdk8/raminit_f_dqs.c Mon Nov 22 23:00:52 2010 (r6117) @@ -1826,25 +1826,7 @@ set_htic_bit(0, val, 9); } -#ifdef S3_NVRAM_EARLY -// Don't define these prototypes as the real functions are already included -// at this point. -// -//int s3_save_nvram_early(u32 dword, int size, int nvram_pos); -//int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); -#else -static inline int s3_save_nvram_early(u32 dword, int size, int nvram_pos) -{ - return nvram_pos; -} - -static inline int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) -{ - die("No memory NVRAM loader for DQS data! Unable to restore memory state\n"); - - return nvram_pos; /* Make GCC happy */ -} -#endif +#if CONFIG_HAVE_ACPI_RESUME == 1 #if CONFIG_MEM_TRAIN_SEQ == 0 static int save_index_to_pos(unsigned int dev, int size, int index, int nvram_pos) @@ -1930,6 +1912,7 @@ reg |= pci_read_config32(dev, DRAM_CONFIG_HIGH); pci_write_config32(dev, DRAM_CONFIG_HIGH, reg); } +#endif #if CONFIG_MEM_TRAIN_SEQ == 0 #if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1 @@ -1998,7 +1981,9 @@ if(train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out; printk(BIOS_DEBUG, " done\n"); sysinfo->mem_trained[i]=1; +#if CONFIG_HAVE_ACPI_RESUME == 1 dqs_save_MC_NVRAM((ctrl+i)->f2); +#endif } out: Modified: trunk/src/southbridge/via/k8t890/k8t890.h ============================================================================== --- trunk/src/southbridge/via/k8t890/k8t890.h Mon Nov 22 17:23:54 2010 (r6116) +++ trunk/src/southbridge/via/k8t890/k8t890.h Mon Nov 22 23:00:52 2010 (r6117) @@ -31,6 +31,7 @@ /* The 256 bytes of NVRAM for S3 storage, 256B aligned */ #define K8T890_NVRAM_IO_BASE 0xf00 +#define K8T890_NVRAM_CBMEM_TOC 0xfc #define K8T890_MMCONFIG_MBAR 0x61 #define K8T890_MULTIPLE_FN_EN 0x4f Modified: trunk/src/southbridge/via/k8t890/k8t890_early_car.c ============================================================================== --- trunk/src/southbridge/via/k8t890/k8t890_early_car.c Mon Nov 22 17:23:54 2010 (r6116) +++ trunk/src/southbridge/via/k8t890/k8t890_early_car.c Mon Nov 22 23:00:52 2010 (r6117) @@ -23,16 +23,14 @@ */ #include <stdlib.h> +#include <cbmem.h> +#include <arch/io.h> #include "k8t890.h" /* The 256 bytes of NVRAM for S3 storage, 256B aligned */ #define K8T890_NVRAM_IO_BASE 0xf00 #define K8T890_MULTIPLE_FN_EN 0x4f -/* we provide S3 NVRAM to system */ -#define S3_NVRAM_EARLY 1 - - /* AMD K8 LDT0, LDT1, LDT2 Link Control Registers */ static u8 ldtreg[3] = {0x86, 0xa6, 0xc6}; @@ -155,3 +153,9 @@ printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", * old_dword, size, nvram_pos-size); return nvram_pos; } + +/* this should be a function +struct cbmem_entry *get_cbmem_toc(void) { +*/ + +#define get_cbmem_toc() ((struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC)) Modified: trunk/src/southbridge/via/k8t890/k8t890_host_ctrl.c ============================================================================== --- trunk/src/southbridge/via/k8t890/k8t890_host_ctrl.c Mon Nov 22 17:23:54 2010 (r6116) +++ trunk/src/southbridge/via/k8t890/k8t890_host_ctrl.c Mon Nov 22 23:00:52 2010 (r6117) @@ -22,6 +22,8 @@ #include <device/pci_ops.h> #include <device/pci_ids.h> #include <console/console.h> +#include <cbmem.h> +#include <arch/io.h> #include "k8t890.h" /* this may be later merged */ @@ -111,6 +113,14 @@ pci_write_config8(dev, 0xa6, 0x83); } +#if 0 +struct cbmem_entry *get_cbmem_toc(void) { + return (struct cbmem_entry *) inl(K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); +} +#endif +void set_cbmem_toc(struct cbmem_entry *toc) { + outl((u32) toc, K8T890_NVRAM_IO_BASE+K8T890_NVRAM_CBMEM_TOC); +} static const struct device_operations host_ctrl_ops_t = { .read_resources = pci_dev_read_resources, Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Mon Nov 22 17:23:54 2010 (r6116) +++ trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Mon Nov 22 23:00:52 2010 (r6117) @@ -316,9 +316,7 @@ pci_write_config8(dev, 0x41, 0x7f); } -#ifdef CONFIG_NORTHBRIDGE_AMD_K8 /* CN700 doesn't have the support yet */ -#define ACPI_IS_WAKEUP_EARLY 1 - +#if CONFIG_HAVE_ACPI_RESUME == 1 static int acpi_is_wakeup_early(void) { device_t dev; u16 tmp;

1 0

[PATCH] K8T890: wait for pcie link to come up
by Tobias Diedrich 22 Nov '10

22 Nov '10

With low serial console loglevels a pcie graphics card is not initialized properly because the pcie link takes some time to come up. I set the timeout rather arbitrary to 100ms, this is what a BIOS_ERR and higher only boot looks like on my system (with pcie printks set to BIOS_ERR so they show up): |Device error |Device error |PCI: 00:02.0 PCIe link up after 35800 us |PCI: 00:03.0 PCIe link up after 12900 us |PCI: 00:03.1 PCIe link timeout |PCI: 00:03.2 PCIe link up after 32000 us |APIC: 00 missing read_resources |I2C: 01:50 missing read_resources |I2C: 01:51 missing read_resources |I2C: 01:52 missing read_resources |I2C: 01:53 missing read_resources |Start bios (version pre-0.6.2-20101025_023503-nukunuku) Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- Index: src/southbridge/via/k8t890/k8t890_pcie.c =================================================================== --- src/southbridge/via/k8t890/k8t890_pcie.c.orig 2010-11-22 15:24:12.000000000 +0100 +++ src/southbridge/via/k8t890/k8t890_pcie.c 2010-11-22 15:27:23.000000000 +0100 @@ -22,6 +22,7 @@ #include <device/pci.h> #include <device/pciexp.h> #include <device/pci_ids.h> +#include <delay.h> #include "k8t890.h" /* @@ -30,16 +31,10 @@ * http://linux.via.com.tw/ */ -static void peg_init(struct device *dev) +static void pcie_common_init(struct device *dev) { u8 reg; - - printk(BIOS_DEBUG, "Configuring PCIe PEG\n"); - dump_south(dev); - - /* Disable link. */ - reg = pci_read_config8(dev, 0x50); - pci_write_config8(dev, 0x50, reg | 0x10); + int i, up; /* Disable downstream read cycle retry, * otherwise the bus scan will hang if no device is plugged in. */ @@ -60,14 +55,48 @@ */ pci_write_config8(dev, 0xe1, 0xb); + /* Set replay timer limit. */ + pci_write_config8(dev, 0xb1, 0xf0); + + /* Enable link. */ + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg & ~0x10); + + /* Wait up to 100ms for link to come up */ + up = 0; + for (i=0; i<1000; i++) { + if (pci_read_config16(dev, 0x52) & (1<<13)) { + up = 1; + break; + } + udelay(100); + } + + printk(BIOS_SPEW, "%s PCIe link ", dev_path(dev)); + if (up) + printk(BIOS_SPEW, "up after %d us\n", i*100); + else + printk(BIOS_SPEW, "timeout\n"); + + dump_south(dev); +} + +static void peg_init(struct device *dev) +{ + u8 reg; + + printk(BIOS_DEBUG, "Configuring PCIe PEG\n"); + dump_south(dev); + + /* Disable link. */ + reg = pci_read_config8(dev, 0x50); + pci_write_config8(dev, 0x50, reg | 0x10); + /* * pci_write_config8(dev, 0xe2, 0x0); * pci_write_config8(dev, 0xe3, 0x92); */ - /* Set replay timer limit. */ - pci_write_config8(dev, 0xb1, 0xf0); - /* Bit0 = 1 SDP (Start DLLP) always at Lane0. */ reg = pci_read_config8(dev, 0xb8); pci_write_config8(dev, 0xb8, reg | 0x1); @@ -79,11 +108,7 @@ reg = pci_read_config8(dev, 0xa4); pci_write_config8(dev, 0xa4, reg | 0x30); - /* Enable link. */ - reg = pci_read_config8(dev, 0x50); - pci_write_config8(dev, 0x50, reg & ~0x10); - - dump_south(dev); + pcie_common_init(dev); } static void pcie_init(struct device *dev) @@ -97,33 +122,7 @@ reg = pci_read_config8(dev, 0x50); pci_write_config8(dev, 0x50, reg | 0x10); - /* Disable downstream read cycle retry, - * otherwise the bus scan will hang if no device is plugged in. */ - reg = pci_read_config8(dev, 0xa3); - pci_write_config8(dev, 0xa3, reg & ~0x01); - - /* Use PHY negotiation for lane config */ - reg = pci_read_config8(dev, 0xc1); - pci_write_config8(dev, 0xc1, reg & ~0x1f); - - /* Award has 0xb, VIA recommends 0xd, default 0x8. - * bit4: receive polarity change control - * bits3:2: squelch window select 64~175mv - * bit1: Number of non-idle bits detected before exiting idle state - * 0: 10 bits, 1: 2 bits - * bit0: Number of idle bits detected before entering idle state - * 0: 10 bits, 1: 2 bits - */ - pci_write_config8(dev, 0xe1, 0xb); - - /* Set replay timer limit. */ - pci_write_config8(dev, 0xb1, 0xf0); - - /* Enable link. */ - reg = pci_read_config8(dev, 0x50); - pci_write_config8(dev, 0x50, reg & ~0x10); - - dump_south(dev); + pcie_common_init(dev); } static const struct device_operations peg_ops = {

2 1

[commit] r6113 - trunk/src/console
by repository service 22 Nov '10

22 Nov '10

Author: oxygene Date: Mon Nov 22 14:07:10 2010 New Revision: 6113 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6113 Log: Workaround to get die.c to work with romcc. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/src/console/die.c Modified: trunk/src/console/die.c ============================================================================== --- trunk/src/console/die.c Mon Nov 22 13:59:36 2010 (r6112) +++ trunk/src/console/die.c Mon Nov 22 14:07:10 2010 (r6113) @@ -23,8 +23,14 @@ #include <arch/hlt.h> #include <console/console.h> +#ifndef __ROMCC__ +#define NORETURN __attribute__((noreturn)) +#else +#define NORETURN +#endif + /* Report a fatal error */ -void __attribute__((noreturn)) die(const char *msg) +void NORETURN die(const char *msg) { print_emerg(msg); do {

3 2

[PATCH] drop vga console support.
by Stefan Reinauer 22 Nov '10

22 Nov '10

See patch.

4 4

[PATCH] Factor out a few commonly duplicated functions from northbridge.c
by Uwe Hermann 22 Nov '10

22 Nov '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

3 4

[patch] ck804 PCIe lane configuration in kconfig
by Jonathan A. Kollasch 22 Nov '10

22 Nov '10

Move CK804_PCI_E_X and CK804B_PCI_E_X defines (which have been 4 by default on all boards) into Kconfig. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> ---

2 4

[commit] r6115 - in trunk/src/mainboard: advantech/pcm-5820 amd/db800 amd/mahogany_fam10 amd/norwich amd/rumba amd/serengeti_cheetah_fam10 amd/tilapia_fam10 artecgroup/dbe61 asi/mb_5blgp asi/mb_5bl...
by repository service 22 Nov '10

22 Nov '10

Author: uwe Date: Mon Nov 22 16:57:57 2010 New Revision: 6115 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6115 Log: Drop per-board ram_check() calls for now. Every board had a slightly different invokation, very often commented out anyway. We could either decide that this is only to be used by developers during bringup (and thus added manually to romstage.c and removed before the board gets committed). This method seems to be preferred from what I have heard on IRC / mailing list in the past. Or, we add the ram_check() somewhere globally and allow the user to enable it via menuconfig (possibly only if EXPERT is selected). Either way, the current method of spreading the calls all over the place is not really the way to go. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/advantech/pcm-5820/romstage.c trunk/src/mainboard/amd/db800/romstage.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/norwich/romstage.c trunk/src/mainboard/amd/rumba/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/amd/tilapia_fam10/romstage.c trunk/src/mainboard/artecgroup/dbe61/romstage.c trunk/src/mainboard/asi/mb_5blgp/romstage.c trunk/src/mainboard/asi/mb_5blmp/romstage.c trunk/src/mainboard/asus/m4a785-m/romstage.c trunk/src/mainboard/axus/tc320/romstage.c trunk/src/mainboard/bcom/winnet100/romstage.c trunk/src/mainboard/bcom/winnetp680/romstage.c trunk/src/mainboard/dell/s1850/romstage.c trunk/src/mainboard/digitallogic/adl855pc/romstage.c trunk/src/mainboard/digitallogic/msm586seg/romstage.c trunk/src/mainboard/digitallogic/msm800sev/romstage.c trunk/src/mainboard/eaglelion/5bcm/romstage.c trunk/src/mainboard/gigabyte/ma785gmt/romstage.c trunk/src/mainboard/gigabyte/ma78gm/romstage.c trunk/src/mainboard/iei/juki-511p/romstage.c trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c trunk/src/mainboard/iei/nova4899r/romstage.c trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c trunk/src/mainboard/intel/jarrell/romstage.c trunk/src/mainboard/intel/mtarvon/romstage.c trunk/src/mainboard/intel/truxton/romstage.c trunk/src/mainboard/intel/xe7501devkit/romstage.c trunk/src/mainboard/jetway/j7f24/romstage.c trunk/src/mainboard/jetway/pa78vm5/romstage.c trunk/src/mainboard/lanner/em8510/romstage.c trunk/src/mainboard/lippert/frontrunner/romstage.c trunk/src/mainboard/lippert/hurricane-lx/romstage.c trunk/src/mainboard/lippert/literunner-lx/romstage.c trunk/src/mainboard/lippert/roadrunner-lx/romstage.c trunk/src/mainboard/lippert/spacerunner-lx/romstage.c trunk/src/mainboard/pcengines/alix1c/romstage.c trunk/src/mainboard/pcengines/alix2d/romstage.c trunk/src/mainboard/rca/rm4100/romstage.c trunk/src/mainboard/supermicro/x6dai_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g/romstage.c trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c trunk/src/mainboard/technologic/ts5300/romstage.c trunk/src/mainboard/televideo/tc7020/romstage.c trunk/src/mainboard/thomson/ip1000/romstage.c trunk/src/mainboard/traverse/geos/romstage.c trunk/src/mainboard/via/epia-cn/romstage.c trunk/src/mainboard/via/epia-m/romstage.c trunk/src/mainboard/via/epia-n/romstage.c trunk/src/mainboard/via/epia/romstage.c trunk/src/mainboard/via/pc2500e/romstage.c trunk/src/mainboard/winent/pl6064/romstage.c trunk/src/mainboard/wyse/s50/romstage.c Modified: trunk/src/mainboard/advantech/pcm-5820/romstage.c ============================================================================== --- trunk/src/mainboard/advantech/pcm-5820/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/advantech/pcm-5820/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -24,7 +24,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" #include "superio/winbond/w83977f/w83977f_early_serial.c" @@ -40,5 +39,4 @@ report_bist_failure(bist); cs5530_enable_rom(); sdram_init(); - /* ram_check(0, 640 * 1024); */ } Modified: trunk/src/mainboard/amd/db800/romstage.c ============================================================================== --- trunk/src/mainboard/amd/db800/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/amd/db800/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -83,9 +83,6 @@ sdram_initialize(1, memctrl); - /* Check memory. */ - /* ram_check(0x00000000, 640 * 1024); */ - /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -217,9 +217,6 @@ dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - // die("After MCT init before CAR disabled."); rs780_before_pci_init(); Modified: trunk/src/mainboard/amd/norwich/romstage.c ============================================================================== --- trunk/src/mainboard/amd/norwich/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/amd/norwich/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -84,9 +84,6 @@ sdram_initialize(1, memctrl); - /* Check memory. */ - /* ram_check(0x00000000, 640 * 1024); */ - /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } Modified: trunk/src/mainboard/amd/rumba/romstage.c ============================================================================== --- trunk/src/mainboard/amd/rumba/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/amd/rumba/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -56,7 +56,4 @@ sdram_initialize(1, memctrl); msr_init(); - - /* Check all of memory */ - //ram_check(0x00000000, 640*1024); } Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -328,9 +328,6 @@ dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - // die("After MCT init before CAR disabled."); post_code(0x42); Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -217,10 +217,6 @@ dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - - // die("After MCT init before CAR disabled."); rs780_before_pci_init(); Modified: trunk/src/mainboard/artecgroup/dbe61/romstage.c ============================================================================== --- trunk/src/mainboard/artecgroup/dbe61/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/artecgroup/dbe61/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -133,8 +133,4 @@ msr = rdmsr(MC_CF8F_DATA); print_debug(" \n"); #endif - - /* Check memory. */ - // ram_check(0x00000000, 640 * 1024); - // ram_check(1024 * 1024, 2 * 1024 * 1024); } Modified: trunk/src/mainboard/asi/mb_5blgp/romstage.c ============================================================================== --- trunk/src/mainboard/asi/mb_5blgp/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/asi/mb_5blgp/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -24,7 +24,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "cpu/x86/bist.h" #include "superio/nsc/pc87351/pc87351_early_serial.c" @@ -40,5 +39,4 @@ report_bist_failure(bist); cs5530_enable_rom(); sdram_init(); - /* ram_check(0, 640 * 1024); */ } Modified: trunk/src/mainboard/asi/mb_5blmp/romstage.c ============================================================================== --- trunk/src/mainboard/asi/mb_5blmp/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/asi/mb_5blmp/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc87351/pc87351_early_serial.c" #include "cpu/x86/bist.h" @@ -41,5 +40,4 @@ report_bist_failure(bist); cs5530_enable_rom(); sdram_init(); - /* ram_check(0x00000000, 0x4000); */ } Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/asus/m4a785-m/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -218,10 +218,6 @@ dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - - // die("After MCT init before CAR disabled."); rs780_before_pci_init(); Modified: trunk/src/mainboard/axus/tc320/romstage.c ============================================================================== --- trunk/src/mainboard/axus/tc320/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/axus/tc320/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" #include "cpu/x86/bist.h" @@ -41,5 +40,4 @@ report_bist_failure(bist); cs5530_enable_rom(); sdram_init(); - /* ram_check(0, 640 * 1024); */ } Modified: trunk/src/mainboard/bcom/winnet100/romstage.c ============================================================================== --- trunk/src/mainboard/bcom/winnet100/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/bcom/winnet100/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" #include "cpu/x86/bist.h" @@ -41,5 +40,4 @@ report_bist_failure(bist); cs5530_enable_rom(); sdram_init(); - /* ram_check(0, 640 * 1024); */ } Modified: trunk/src/mainboard/bcom/winnetp680/romstage.c ============================================================================== --- trunk/src/mainboard/bcom/winnetp680/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/bcom/winnetp680/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -99,6 +99,4 @@ enable_mainboard_devices(); ddr_ram_setup(&ctrl); - - /* ram_check(0, 640 * 1024); */ } Modified: trunk/src/mainboard/dell/s1850/romstage.c ============================================================================== --- trunk/src/mainboard/dell/s1850/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/dell/s1850/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -6,7 +6,6 @@ #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc8374/pc8374_early_init.c" @@ -323,17 +322,4 @@ dump_pci_device(PCI_DEV(0, 0x00, 0)); // dump_bar14(PCI_DEV(0, 0x00, 0)); #endif - -#if 1 // temporarily disabled - /* Check the first 1M */ -// ram_check(0x00000000, 0x000100000); -// ram_check(0x00000000, 0x000a0000); -// ram_check(0x00100000, 0x01000000); - ram_check(0x00100000, 0x00100100); - /* check the first 1M in the 3rd Gig */ -// ram_check(0x30100000, 0x31000000); -#endif -#if 0 - ram_check(0x00000000, 0x02000000); -#endif } Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/adl855pc/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/digitallogic/adl855pc/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -62,12 +62,5 @@ #if 0 dump_pci_devices(); dump_pci_device(PCI_DEV(0, 0, 0)); - - // Check all of memory - ram_check(0x00000000, msr.lo+(msr.hi<<32)); - // Check 16MB of memory @ 0 - ram_check(0x00000000, 0x01000000); - // Check 16MB of memory @ 2GB - ram_check(0x80000000, 0x81000000); #endif } Modified: trunk/src/mainboard/digitallogic/msm586seg/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm586seg/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/digitallogic/msm586seg/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -6,7 +6,6 @@ #include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" void setup_pars(void) @@ -203,16 +202,6 @@ dump_pci_device(PCI_DEV(0, 0, 0)); #endif -#if 0 - print_err("RAM CHECK!\n"); - // Check 16MB of memory @ 0 - ram_check(0x00000000, 0x01000000); -#endif -#if 0 - print_err("RAM CHECK for 32 MB!\n"); - // Check 32MB of memory @ 0 - ram_check(0x00000000, 0x02000000); -#endif #if 1 { volatile unsigned char *src = (unsigned char *) 0x2000000 + 0x60000; Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c ============================================================================== --- trunk/src/mainboard/digitallogic/msm800sev/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -66,9 +66,6 @@ sdram_initialize(1, memctrl); - /* Check all of memory */ - ram_check(0x00000000, 640*1024); - /* Switch from Cache as RAM to real RAM */ /* There are two ways we could think about this. 1. If we are using the romstage.inc ROMCC way, the stack is going to be re-setup in the code following this code. Modified: trunk/src/mainboard/eaglelion/5bcm/romstage.c ============================================================================== --- trunk/src/mainboard/eaglelion/5bcm/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/eaglelion/5bcm/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -6,7 +6,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" #include "cpu/x86/bist.h" #include "southbridge/amd/cs5530/cs5530_enable_rom.c" Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -214,10 +214,6 @@ dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - - // die("After MCT init before CAR disabled."); rs780_before_pci_init(); Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -216,9 +216,6 @@ dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - // die("After MCT init before CAR disabled."); rs780_before_pci_init(); Modified: trunk/src/mainboard/iei/juki-511p/romstage.c ============================================================================== --- trunk/src/mainboard/iei/juki-511p/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/iei/juki-511p/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "superio/winbond/w83977f/w83977f_early_serial.c" #include "southbridge/amd/cs5530/cs5530_enable_rom.c" #include "cpu/x86/bist.h" @@ -47,5 +46,4 @@ cs5530_enable_rom(); sdram_init(); - /* ram_check(0x00000000, 640 * 1024); */ } Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -219,9 +219,6 @@ dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - // die("After MCT init before CAR disabled."); rs780_before_pci_init(); Modified: trunk/src/mainboard/iei/nova4899r/romstage.c ============================================================================== --- trunk/src/mainboard/iei/nova4899r/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/iei/nova4899r/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "superio/winbond/w83977tf/w83977tf_early_serial.c" #include "southbridge/amd/cs5530/cs5530_enable_rom.c" #include "cpu/x86/bist.h" @@ -42,5 +41,4 @@ report_bist_failure(bist); cs5530_enable_rom(); sdram_init(); - /* ram_check(0x00000000, 640 * 1024); */ } Modified: trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/iei/pcisa-lx-800-r10/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -87,8 +87,6 @@ sdram_initialize(1, memctrl); - /* ram_check(0, 640 * 1024); */ - /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } Modified: trunk/src/mainboard/intel/jarrell/romstage.c ============================================================================== --- trunk/src/mainboard/intel/jarrell/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/intel/jarrell/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -6,7 +6,6 @@ #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" @@ -105,17 +104,4 @@ dump_pci_device(PCI_DEV(0, 0x00, 0)); dump_bar14(PCI_DEV(0, 0x00, 0)); #endif - -#if 0 // temporarily disabled - /* Check the first 1M */ -// ram_check(0x00000000, 0x000100000); -// ram_check(0x00000000, 0x000a0000); - ram_check(0x00100000, 0x01000000); - /* check the first 1M in the 3rd Gig */ - ram_check(0x30100000, 0x31000000); -#if 0 - ram_check(0x00000000, 0x02000000); -#endif - -#endif } Modified: trunk/src/mainboard/intel/mtarvon/romstage.c ============================================================================== --- trunk/src/mainboard/intel/mtarvon/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/intel/mtarvon/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -118,6 +118,4 @@ /* dump_pci_devices(); */ /* dump_pci_device(PCI_DEV(0, 0x00, 0)); */ /* dump_bar14(PCI_DEV(0, 0x00, 0)); */ - - ram_check(0, 1024 * 1024); } Modified: trunk/src/mainboard/intel/truxton/romstage.c ============================================================================== --- trunk/src/mainboard/intel/truxton/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/intel/truxton/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -28,7 +28,6 @@ #include <pc80/mc146818rtc.h> #include "pc80/udelay_io.c" #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i3100/i3100_early_smbus.c" #include "southbridge/intel/i3100/i3100_early_lpc.c" #include "northbridge/intel/i3100/raminit_ep80579.h" @@ -98,9 +97,4 @@ #ifdef TRUXTON_DEBUG dump_bar14(PCI_DEV(0, 0x00, 0)); #endif - -#ifdef TRUXTON_DEBUG - ram_fill(0x00000000, 0x02000000); - ram_verify(0x00000000, 0x02000000); -#endif } Modified: trunk/src/mainboard/intel/xe7501devkit/romstage.c ============================================================================== --- trunk/src/mainboard/intel/xe7501devkit/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/intel/xe7501devkit/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -8,7 +8,6 @@ #include <stdlib.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801cx/i82801cx_early_smbus.c" #include "northbridge/intel/e7501/raminit.h" #include "cpu/x86/lapic/boot_cpu.c" Modified: trunk/src/mainboard/jetway/j7f24/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/j7f24/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/jetway/j7f24/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -104,6 +104,4 @@ enable_mainboard_devices(); ddr_ram_setup(&ctrl); - - /* ram_check(0, 640 * 1024); */ } Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/jetway/pa78vm5/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -224,9 +224,6 @@ dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ -// ram_check(0x00200000, 0x00200000 + (640 * 1024)); -// ram_check(0x40200000, 0x40200000 + (640 * 1024)); - // die("After MCT init before CAR disabled."); rs780_before_pci_init(); Modified: trunk/src/mainboard/lanner/em8510/romstage.c ============================================================================== --- trunk/src/mainboard/lanner/em8510/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/lanner/em8510/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -80,16 +80,4 @@ sdram_set_spd_registers(); sdram_enable(); } - -#if 0 - dump_pci_devices(); - dump_pci_device(PCI_DEV(0, 0, 0)); - - // Check all of memory - ram_check(0x00000000, msr.lo+(msr.hi<<32)); - // Check 16MB of memory @ 0 - ram_check(0x00000000, 0x01000000); - // Check 16MB of memory @ 2GB - ram_check(0x80000000, 0x81000000); -#endif } Modified: trunk/src/mainboard/lippert/frontrunner/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/frontrunner/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/lippert/frontrunner/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -127,8 +127,4 @@ outb( temp, 0x4F); temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged! print_debug_hex8(temp);print_debug("\n"); - /* Check all of memory */ -// ram_check(0, 16384); - ram_check(0x20000, 0x24000); -// ram_check(0x00000000, 640*1024); } Modified: trunk/src/mainboard/lippert/hurricane-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/hurricane-lx/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/lippert/hurricane-lx/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -157,9 +157,6 @@ sdram_initialize(1, memctrl); - /* Check memory. */ - /* ram_check(0, 640 * 1024); */ - /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } Modified: trunk/src/mainboard/lippert/literunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/literunner-lx/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/lippert/literunner-lx/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -197,9 +197,6 @@ sdram_initialize(1, memctrl); - /* Check memory. */ - /* ram_check(0, 640 * 1024); */ - /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } Modified: trunk/src/mainboard/lippert/roadrunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/lippert/roadrunner-lx/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -122,9 +122,6 @@ sdram_initialize(1, memctrl); - /* Check memory. */ - /* ram_check(0x00000000, 640 * 1024); */ - /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } Modified: trunk/src/mainboard/lippert/spacerunner-lx/romstage.c ============================================================================== --- trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/lippert/spacerunner-lx/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -194,9 +194,6 @@ sdram_initialize(1, memctrl); - /* Check memory. */ - /* ram_check(0, 640 * 1024); */ - /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } Modified: trunk/src/mainboard/pcengines/alix1c/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix1c/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/pcengines/alix1c/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -142,10 +142,6 @@ sdram_initialize(1, memctrl); - /* Check memory */ - /* Enable this only if you are having questions. */ - /* ram_check(0, 640 * 1024); */ - /* Switch from Cache as RAM to real RAM. * * There are two ways we could think about this. Modified: trunk/src/mainboard/pcengines/alix2d/romstage.c ============================================================================== --- trunk/src/mainboard/pcengines/alix2d/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/pcengines/alix2d/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -166,10 +166,6 @@ sdram_initialize(1, memctrl); - /* Check memory */ - /* Enable this only if you are having questions. */ - /* ram_check(0, 640 * 1024); */ - /* Switch from Cache as RAM to real RAM. * * There are two ways we could think about this. Modified: trunk/src/mainboard/rca/rm4100/romstage.c ============================================================================== --- trunk/src/mainboard/rca/rm4100/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/rca/rm4100/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -121,8 +121,4 @@ /* Initialize memory */ sdram_initialize(); - - /* Check RAM. */ - /* ram_check(0, 640 * 1024); */ - /* ram_check(64512 * 1024, 65536 * 1024); */ } Modified: trunk/src/mainboard/supermicro/x6dai_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dai_g/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/supermicro/x6dai_g/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -6,7 +6,6 @@ #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/intel/esb6300/esb6300_early_smbus.c" @@ -99,16 +98,4 @@ dump_pci_device(PCI_DEV(0, 0x00, 0)); // dump_bar14(PCI_DEV(0, 0x00, 0)); #endif - -#if 0 // temporarily disabled - /* Check the first 1M */ -// ram_check(0x00000000, 0x000100000); -// ram_check(0x00000000, 0x000a0000); - ram_check(0x00100000, 0x01000000); - /* check the first 1M in the 3rd Gig */ - ram_check(0x30100000, 0x31000000); -#endif -#if 0 - ram_check(0x00000000, 0x02000000); -#endif } Modified: trunk/src/mainboard/supermicro/x6dhe_g/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/supermicro/x6dhe_g/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -6,7 +6,6 @@ #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "pc80/udelay_io.c" #include "lib/delay.c" #include "southbridge/intel/esb6300/esb6300_early_smbus.c" @@ -103,16 +102,4 @@ dump_pci_device(PCI_DEV(0, 0x00, 0)); dump_bar14(PCI_DEV(0, 0x00, 0)); #endif - -#if 0 // temporarily disabled - /* Check the first 1M */ -// ram_check(0x00000000, 0x000100000); -// ram_check(0x00000000, 0x000a0000); - ram_check(0x00100000, 0x01000000); - /* check the first 1M in the 3rd Gig */ - ram_check(0x30100000, 0x31000000); -#endif -#if 0 - ram_check(0x00000000, 0x02000000); -#endif } Modified: trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -6,7 +6,6 @@ #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/nsc/pc87427/pc87427.h" @@ -103,16 +102,4 @@ dump_pci_device(PCI_DEV(0, 0x00, 0)); //dump_bar14(PCI_DEV(0, 0x00, 0)); #endif - -#if 0 // temporarily disabled - /* Check the first 1M */ -// ram_check(0x00000000, 0x000100000); -// ram_check(0x00000000, 0x000a0000); - ram_check(0x00100000, 0x01000000); - /* check the first 1M in the 3rd Gig */ - ram_check(0x30100000, 0x31000000); -#endif -#if 0 - ram_check(0x00000000, 0x02000000); -#endif } Modified: trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -6,7 +6,6 @@ #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" @@ -48,12 +47,6 @@ static const struct mem_controller mch[] = { { .node_id = 0, - /* - .f0 = PCI_DEV(0, 0x00, 0), - .f1 = PCI_DEV(0, 0x00, 1), - .f2 = PCI_DEV(0, 0x00, 2), - .f3 = PCI_DEV(0, 0x00, 3), - */ .channel0 = {DIMM3, DIMM2, DIMM1, DIMM0, }, .channel1 = {DIMM7, DIMM6, DIMM5, DIMM4, }, } @@ -110,17 +103,4 @@ dump_pci_device(PCI_DEV(0, 0x00, 0)); dump_bar14(PCI_DEV(0, 0x00, 0)); #endif - -#if 0 // temporarily disabled - /* Check the first 1M */ -// ram_check(0x00000000, 0x000100000); -// ram_check(0x00000000, 0x000a0000); -// ram_check(0x00100000, 0x01000000); - ram_check(0x00100000, 0x00100100); - /* check the first 1M in the 3rd Gig */ -// ram_check(0x30100000, 0x31000000); -#endif -#if 0 - ram_check(0x00000000, 0x02000000); -#endif } Modified: trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -6,7 +6,6 @@ #include <cpu/x86/lapic.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "southbridge/intel/i82801ex/i82801ex_early_smbus.c" #include "northbridge/intel/e7520/raminit.h" #include "superio/winbond/w83627hf/w83627hf.h" @@ -102,17 +101,4 @@ dump_pci_device(PCI_DEV(0, 0x00, 0)); dump_bar14(PCI_DEV(0, 0x00, 0)); #endif - -#if 0 // temporarily disabled - /* Check the first 1M */ -// ram_check(0x00000000, 0x000100000); -// ram_check(0x00000000, 0x000a0000); -// ram_check(0x00100000, 0x01000000); - ram_check(0x00100000, 0x00100100); - /* check the first 1M in the 3rd Gig */ -// ram_check(0x30100000, 0x31000000); -#endif -#if 0 - ram_check(0x00000000, 0x02000000); -#endif } Modified: trunk/src/mainboard/technologic/ts5300/romstage.c ============================================================================== --- trunk/src/mainboard/technologic/ts5300/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/technologic/ts5300/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -12,7 +12,6 @@ #include <arch/hlt.h> #include <pc80/mc146818rtc.h> #include <console/console.h> -#include "lib/ramtest.c" #include "cpu/x86/bist.h" #define TS5300_LED_OFF outb((inb(0x77)&0xfe), 0x77) @@ -162,12 +161,5 @@ identify_system(); #endif -#if 0 - // Check 32MB of memory @ 0 (very slow!) - print_err("Checking memory:\n"); - ram_check(0x00000000, 0x000a0000); - ram_check(0x000b0000, 0x02000000); -#endif - TS5300_LED_OFF; } Modified: trunk/src/mainboard/televideo/tc7020/romstage.c ============================================================================== --- trunk/src/mainboard/televideo/tc7020/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/televideo/tc7020/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -25,7 +25,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/amd/gx1/raminit.c" #include "superio/nsc/pc97317/pc97317_early_serial.c" #include "cpu/x86/bist.h" @@ -41,5 +40,4 @@ report_bist_failure(bist); cs5530_enable_rom(); sdram_init(); - /* ram_check(0, 640 * 1024); */ } Modified: trunk/src/mainboard/thomson/ip1000/romstage.c ============================================================================== --- trunk/src/mainboard/thomson/ip1000/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/thomson/ip1000/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -124,7 +124,4 @@ #if CONFIG_LLSHELL llshell(); #endif - /* Check RAM. */ - /* ram_check(0, 640 * 1024); */ - /* ram_check(64512 * 1024, 65536 * 1024); */ } Modified: trunk/src/mainboard/traverse/geos/romstage.c ============================================================================== --- trunk/src/mainboard/traverse/geos/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/traverse/geos/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -85,9 +85,6 @@ sdram_initialize(1, memctrl); - /* Check memory. */ - /* ram_check(0x00000000, 640 * 1024); */ - /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } Modified: trunk/src/mainboard/via/epia-cn/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-cn/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/via/epia-cn/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -93,5 +93,4 @@ report_bist_failure(bist); enable_mainboard_devices(); ddr_ram_setup(&ctrl); - /* ram_check(0, 640 * 1024); */ } Modified: trunk/src/mainboard/via/epia-m/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-m/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/via/epia-m/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -7,7 +7,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/via/vt8623/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -105,20 +104,6 @@ ddr_ram_setup((const struct mem_controller *)0); - /* Check all of memory */ -#if 0 - static const struct { - unsigned long lo, hi; - } check_addrs[] = { - /* Check 16MB of memory @ 0*/ - { 0x00000000, 0x01000000 }, - }; - int i; - for(i = 0; i < ARRAY_SIZE(check_addrs); i++) { - ram_check(check_addrs[i].lo, check_addrs[i].hi); - } -#endif - if (bist == 0) early_mtrr_init(); Modified: trunk/src/mainboard/via/epia-n/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia-n/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/via/epia-n/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -27,7 +27,6 @@ #include <arch/romcc_io.h> #include <arch/hlt.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/via/cn400/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -134,6 +133,4 @@ if (bist == 0) early_mtrr_init(); - - //ram_check(0, 640 * 1024); } Modified: trunk/src/mainboard/via/epia/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/via/epia/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -6,7 +6,6 @@ #include <arch/hlt.h> #include <stdlib.h> #include <console/console.h> -#include "lib/ramtest.c" #include "northbridge/via/vt8601/raminit.h" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" @@ -95,25 +94,4 @@ sdram_set_registers((const struct mem_controller *) 0); sdram_set_spd_registers((const struct mem_controller *) 0); sdram_enable(0, (const struct mem_controller *) 0); - - /* Check all of memory */ -#if 0 - ram_check(0x00000000, msr.lo); -#endif -#if 0 - static const struct { - unsigned long lo, hi; - } check_addrs[] = { - /* Check 16MB of memory @ 0*/ - { 0x00000000, 0x01000000 }, -#if TOTAL_CPUS > 1 - /* Check 16MB of memory @ 2GB */ - { 0x80000000, 0x81000000 }, -#endif - }; - int i; - for(i = 0; i < ARRAY_SIZE(check_addrs); i++) { - ram_check(check_addrs[i].lo, check_addrs[i].hi); - } -#endif } Modified: trunk/src/mainboard/via/pc2500e/romstage.c ============================================================================== --- trunk/src/mainboard/via/pc2500e/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/via/pc2500e/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -67,5 +67,4 @@ smbus_fixup(&ctrl); report_bist_failure(bist); ddr_ram_setup(&ctrl); - /* ram_check(0, 640 * 1024); */ } Modified: trunk/src/mainboard/winent/pl6064/romstage.c ============================================================================== --- trunk/src/mainboard/winent/pl6064/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/winent/pl6064/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -86,9 +86,6 @@ sdram_initialize(1, memctrl); - /* Check memory. */ - /* ram_check(0x00000000, 640 * 1024); */ - /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } Modified: trunk/src/mainboard/wyse/s50/romstage.c ============================================================================== --- trunk/src/mainboard/wyse/s50/romstage.c Mon Nov 22 15:14:56 2010 (r6114) +++ trunk/src/mainboard/wyse/s50/romstage.c Mon Nov 22 16:57:57 2010 (r6115) @@ -78,7 +78,4 @@ print_err("ram setup done\n"); msr_init(); - - /* Check all of memory */ - /*ram_check(0x00000000, 640*1024);*/ }

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Trac reminder: list of new ticket(s)
by coreboot tracker 22 Nov '10

22 Nov '10

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coreboot November 2010