coreboot November 2010

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[commit] r6084 - in trunk/src: arch/i386/boot arch/i386/include/arch mainboard/asus/m2v mainboard/asus/m2v-mx_se
by repository service 17 Nov '10

17 Nov '10

Author: ruik Date: Wed Nov 17 17:27:06 2010 New Revision: 6084 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6084 Log: Dynamically generate PNP0C02 mainboard resources in SSDT Updated patch with improved comments and small bugfix (use same value for min and max on io resource). While adding the area between TOM1 and 4GB to \SB.PCI0._CRS seems to be the easiest way to get both Linux and Windows happy, it is not quite correct because reserved areas like APIC, MMCONF etc. ranges need to be excluded. This is a proof of concept patch for the M2V board that dynamically creates a ResourceTemplate() containing these in the SSDT and adds a corresponding PNP0C02 device to the DSDT. All resources that have IORESOURCE_RESERVE and (IORESOURCE_MEM or IORESOURCE_IO) set are added. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Added M2V-MX SE too. Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Modified: trunk/src/arch/i386/boot/acpigen.c trunk/src/arch/i386/include/arch/acpigen.h trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c trunk/src/mainboard/asus/m2v-mx_se/dsdt.asl trunk/src/mainboard/asus/m2v/acpi_tables.c trunk/src/mainboard/asus/m2v/dsdt.asl Modified: trunk/src/arch/i386/boot/acpigen.c ============================================================================== --- trunk/src/arch/i386/boot/acpigen.c Wed Nov 17 12:30:50 2010 (r6083) +++ trunk/src/arch/i386/boot/acpigen.c Wed Nov 17 17:27:06 2010 (r6084) @@ -28,6 +28,7 @@ #include <string.h> #include <arch/acpigen.h> #include <console/console.h> +#include <device/device.h> static char *gencurrent; @@ -372,3 +373,145 @@ acpigen_patch_len(len - 1); return len + lenh; } + +int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size) +{ + /* + * acpi 4.0 section 6.4.3.4: 32-Bit Fixed Memory Range Descriptor + * Byte 0: + * Bit7 : 1 => big item + * Bit6-0: 0000110 (0x6) => 32-bit fixed memory + */ + acpigen_emit_byte(0x86); + /* Byte 1+2: length (0x0009) */ + acpigen_emit_byte(0x09); + acpigen_emit_byte(0x00); + /* bit1-7 are ignored */ + acpigen_emit_byte(readwrite ? 0x01 : 0x00); + acpigen_emit_byte(base & 0xff); + acpigen_emit_byte((base >> 8) & 0xff); + acpigen_emit_byte((base >> 16) & 0xff); + acpigen_emit_byte((base >> 24) & 0xff); + acpigen_emit_byte(size & 0xff); + acpigen_emit_byte((size >> 8) & 0xff); + acpigen_emit_byte((size >> 16) & 0xff); + acpigen_emit_byte((size >> 24) & 0xff); + return 12; +} + +int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16) +{ + /* + * acpi 4.0 section 6.4.2.6: I/O Port Descriptor + * Byte 0: + * Bit7 : 0 => small item + * Bit6-3: 1000 (0x8) => I/O port descriptor + * Bit2-0: 111 (0x7) => 7 Bytes long + */ + acpigen_emit_byte(0x47); + /* does the device decode all 16 or just 10 bits? */ + /* bit1-7 are ignored */ + acpigen_emit_byte(decode16 ? 0x01 : 0x00); + /* minimum base address the device may be configured for */ + acpigen_emit_byte(min & 0xff); + acpigen_emit_byte((min >> 8) & 0xff); + /* maximum base address the device may be configured for */ + acpigen_emit_byte(max & 0xff); + acpigen_emit_byte((max >> 8) & 0xff); + /* alignment for min base */ + acpigen_emit_byte(align & 0xff); + acpigen_emit_byte(len & 0xff); + return 8; +} + +int acpigen_write_resourcetemplate_header(void) +{ + int len; + /* + * A ResourceTemplate() is a Buffer() with a + * (Byte|Word|DWord) containing the length, followed by one or more + * resource items, terminated by the end tag + * (small item 0xf, len 1) + */ + len = acpigen_emit_byte(0x11); /* Buffer opcode */ + len += acpigen_write_len_f(); + len += acpigen_emit_byte(0x0b); /* Word opcode */ + len_stack[ltop++] = acpigen_get_current(); + len += acpigen_emit_byte(0x00); + len += acpigen_emit_byte(0x00); + return len; +} + +int acpigen_write_resourcetemplate_footer(int len) +{ + char *p = len_stack[--ltop]; + /* + * end tag (acpi 4.0 Section 6.4.2.8) + * 0x79 <checksum> + * 0x00 is treated as a good checksum according to the spec + * and is what iasl generates. + */ + len += acpigen_emit_byte(0x79); + len += acpigen_emit_byte(0x00); + /* patch len word */ + p[0] = (len-6) & 0xff; + p[1] = ((len-6) >> 8) & 0xff; + /* patch len field */ + acpigen_patch_len(len-1); + return 2; +} + +static void acpigen_add_mainboard_rsvd_mem32(void *gp, struct device *dev, + struct resource *res) +{ + acpigen_write_mem32fixed(0, res->base, res->size); +} + +static void acpigen_add_mainboard_rsvd_io(void *gp, struct device *dev, + struct resource *res) +{ + resource_t base = res->base; + resource_t size = res->size; + while (size > 0) { + resource_t sz = size > 255 ? 255 : size; + acpigen_write_io16(base, base, 0, sz, 1); + size -= sz; + base += sz; + } +} + +int acpigen_write_mainboard_resource_template(void) +{ + int len; + char *start; + char *end; + len = acpigen_write_resourcetemplate_header(); + start = acpigen_get_current(); + + /* Add reserved memory ranges */ + search_global_resources( + IORESOURCE_MEM | IORESOURCE_RESERVE, + IORESOURCE_MEM | IORESOURCE_RESERVE, + acpigen_add_mainboard_rsvd_mem32, 0); + + /* Add reserved io ranges */ + search_global_resources( + IORESOURCE_IO | IORESOURCE_RESERVE, + IORESOURCE_IO | IORESOURCE_RESERVE, + acpigen_add_mainboard_rsvd_io, 0); + + end = acpigen_get_current(); + len += end-start; + len += acpigen_write_resourcetemplate_footer(len); + return len; +} + +int acpigen_write_mainboard_resources(const char *scope, const char *name) +{ + int len; + len = acpigen_write_scope(scope); + len += acpigen_write_name(name); + len += acpigen_write_mainboard_resource_template(); + acpigen_patch_len(len - 1); + return len; +} Modified: trunk/src/arch/i386/include/arch/acpigen.h ============================================================================== --- trunk/src/arch/i386/include/arch/acpigen.h Wed Nov 17 12:30:50 2010 (r6083) +++ trunk/src/arch/i386/include/arch/acpigen.h Wed Nov 17 17:27:06 2010 (r6084) @@ -46,5 +46,11 @@ typedef enum { SW_ALL=0xfc, SW_ANY=0xfd, HW_ALL=0xfe } PSD_coord; int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len); +int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size); +int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16); +int acpigen_write_resourcetemplate_header(void); +int acpigen_write_resourcetemplate_footer(int len); +int acpigen_write_mainboard_resource_template(void); +int acpigen_write_mainboard_resources(const char *scope, const char *name); #endif Modified: trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c Wed Nov 17 12:30:50 2010 (r6083) +++ trunk/src/mainboard/asus/m2v-mx_se/acpi_tables.c Wed Nov 17 17:27:06 2010 (r6084) @@ -25,6 +25,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/smp/mpspec.h> #include <arch/ioapic.h> #include <device/device.h> @@ -87,6 +88,7 @@ { k8acpi_write_vars(); amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); return (unsigned long) (acpigen_get_current()); } Modified: trunk/src/mainboard/asus/m2v-mx_se/dsdt.asl ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/dsdt.asl Wed Nov 17 12:30:50 2010 (r6083) +++ trunk/src/mainboard/asus/m2v-mx_se/dsdt.asl Wed Nov 17 17:27:06 2010 (r6084) @@ -242,6 +242,12 @@ } } } + /* Dummy device to hold auto generated reserved resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + External(_CRS) /* Resource Template in SSDT */ + } } } } Modified: trunk/src/mainboard/asus/m2v/acpi_tables.c ============================================================================== --- trunk/src/mainboard/asus/m2v/acpi_tables.c Wed Nov 17 12:30:50 2010 (r6083) +++ trunk/src/mainboard/asus/m2v/acpi_tables.c Wed Nov 17 17:27:06 2010 (r6084) @@ -25,6 +25,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/smp/mpspec.h> #include <arch/ioapic.h> #include <device/device.h> @@ -88,6 +89,7 @@ { k8acpi_write_vars(); amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS"); return (unsigned long) (acpigen_get_current()); } Modified: trunk/src/mainboard/asus/m2v/dsdt.asl ============================================================================== --- trunk/src/mainboard/asus/m2v/dsdt.asl Wed Nov 17 12:30:50 2010 (r6083) +++ trunk/src/mainboard/asus/m2v/dsdt.asl Wed Nov 17 17:27:06 2010 (r6084) @@ -399,6 +399,13 @@ } } + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + + External(_CRS) /* Resource Template in SSDT */ + } + External(TOM1) /* top of memory below 4GB */ Method(_CRS, 0) {

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Re: [coreboot] P4V800D-X need BIOS modification for PCI-E
by Tomasz Czapiewski 17 Nov '10

17 Nov '10

Now the logs from other PC with that Radeon HD4670 working: lshw: http://pastebin.ca/1994483 lshw -businfo: http://pastebin.ca/1994489 lspci -vv: http://pastebin.ca/1994491 lspci -nvv: http://pastebin.ca/1994493 lspci -xxx: http://pastebin.ca/1994494 lspci -xxxx: http://pastebin.ca/1994495 Best Regards, Tom ---------- Forwarded message ---------- Date: Mon, 15 Nov 2010 22:35:08 +0100 (CET) From: Tomasz Czapiewski <xeros(a)irc.pl> To: coreboot(a)coreboot.org Subject: Re: P4V800D-X need BIOS modification for PCI-E As requested on IRC I'm sending some logs... dmesg from P4V800D-X with inserted both AGP Radeon 9600 and (unrecognized) PCI-E Radeon HD4670: http://pastebin.com/8wx9JYBJ lspci -v -v from P4V800D-X (the same configuration as above): http://pastebin.com/qfbjNZ40 lshw: http://pastebin.com/PTdGwv0f ---------------------------------------------------------- dmesg from P4V800D-X with inserted both AGP Radeon 9600 and PCI-E Radeon X300 (both working configuration): http://pastebin.com/gtc5rvJW lshw: http://pastebin.com/wS7vS0xF lspci -v -v: http://pastebin.com/iRYGTCqL lspci -xxx: http://pastebin.com/Jv338DFR lspci -xxxx: http://pastebin.com/rdjTZtxP ---------------------------------------------------------- In next mail I'll send logs from other working PC with Radeon HD4670 card which didn't work on my P4V800D-X. With Regards, Tom ---------- Forwarded message ---------- Date: Sun, 14 Nov 2010 22:53:06 +0100 (CET) From: Tomasz Czapiewski <xeros(a)irc.pl> To: coreboot(a)coreboot.org Cc: flashrom(a)flashrom.org Subject: P4V800D-X need BIOS modification for PCI-E Hi, I've been told at Phoronix forums few months ago that you can help solve my problem as you really do miracles with BIOS. The problem is that I have Asus P4V800D-X mainboard from few years which has Via PT880Ultra chipset. The mainboard is for Intel Pentium4 with socket 478 and DDR1 and has two graphic slots (AGP x8 and PCI-E 1.0). OT: The MP spec tells it could not handle both cards but I use both Radeons R3xx (AGP RV350 - 9600 and PCI-E RV370 - x300 in multiseat) just fine althrough before doing kernel mode settings on Linux I can see BIOS POST only on one of them but that's not the case... Back to topic... Some time ago I've get PCI-E 2.0 Radeon HD4670 which I wanted to use as a replace for PCI-E 1.0 Radeon X300 and I've saw it runs without problems on different MB but with the same chipset (Asrock 775Dual-VSTA - only PCI-E without AGP, P4/DualCore socket 775, both DDR1 and DDR2) after BIOS upgrade served by Asrock. I've found that the card I've get does couply PCI-E 1.0 power requirements specs so it really should be possible to use it on PCI-E 1.0 MBs. When I put this card in PCI-E slot of my MB BIOS and even Linux after BOOT does not see that anything is put in PCI-E slot (lspci, lshw, etc... does not show anything related to this card). I know that CoreBoot site does not list any of MBs that contain such chipset so I'm still stuck with proprietary BIOS from my MB vendor. As I've said before Asrock did release BIOS updates for it's MB with fixes for Radeon HD2xxx and HD3xxx cards (althrough some people reported that after this BIOS update Radeon HD4670 works, too) but Asus did forget about P4V800D-X users long time ago and haven't released and wont release such fixes. I know it will be very hard but could you look at Asrock 775Dual-VSTA BIOS changes (last BIOSes contain only fixes for Radeon HD3xxx cards) and somekind use it for fix my Asus P4V800D-X BIOS to support such cards? I don't even imagine how would you do this but anyway I've get here to ask for help as you're the only people who could do something like this. Thanks in advance. Asus P4V800D-X spec: http://motherboardland.blogspot.com/2006/01/asus-p4v800d-x-motherboard.html Asus P4V800D-X user guide: ftp://ftp.asus.com.tw/pub/ASUS/mb/sock478/p4v800d-x/e2221_P4V800D-X.pdf Asus P4V800D-X BIOS: http://dlcdnet.asus.com/pub/ASUS/mb/sock478/p4v800d-x/P4V8D704.zip Asrock 775Dual-VSTA spec: http://www.asrock.com/mb/overview.asp?Model=775Dual-vsta Asrock 775Dual-VSTA user guide: http://europe.asrock.com/manual/775Dual-VSTA.pdf Asrock 775Dual-VSTA BIOSes with changelogs: http://www.asrock.com/mb/download.asp?Model=775Dual-VSTA&o=BIOS Btw. I don't have EEPROM/BIOS programmer/flasher and my MB has only one BIOS so if you would do that BIOS modifications will flashing it will be a lot more risky than flashing any other official BIOSes? I don't mind if after flashing for any reason I could get not video or sth that would just not break Linux boot from SATA HDD so I could SSH to my machine and flash original BIOS or any other not so hard to use fallback. I don't want to change MB for the next few years because of financial reasons as I have some hardware/peripherals which use could be problematic on never MBs like these two graphic cards, PCI analog TV card, some RS232 connected hardware, a lot of DDR1 RAM, etc. With Regards, Tom

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[commit] r6082 - in trunk/src: mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/tilapia_fam10 mainboard/asrock/939a785gmh mainboard/as...
by repository service 17 Nov '10

17 Nov '10

Author: ruik Date: Wed Nov 17 12:02:05 2010 New Revision: 6082 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6082 Log: This problem was introduced with http://tracker.coreboot.org/trac/coreboot/changeset/3953 Note that all corresponding DSDTs only ever check TOM2 against 0. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Modified: trunk/src/mainboard/amd/dbm690t/dsdt.asl trunk/src/mainboard/amd/mahogany/dsdt.asl trunk/src/mainboard/amd/mahogany_fam10/dsdt.asl trunk/src/mainboard/amd/pistachio/dsdt.asl trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl trunk/src/mainboard/asrock/939a785gmh/dsdt.asl trunk/src/mainboard/asus/m4a785-m/dsdt.asl trunk/src/mainboard/gigabyte/ma785gmt/dsdt.asl trunk/src/mainboard/gigabyte/ma78gm/dsdt.asl trunk/src/mainboard/iei/kino-780am2-fam10/dsdt.asl trunk/src/mainboard/jetway/pa78vm5/dsdt.asl trunk/src/mainboard/kontron/kt690/dsdt.asl trunk/src/mainboard/technexion/tim5690/dsdt.asl trunk/src/mainboard/technexion/tim8690/dsdt.asl trunk/src/northbridge/amd/amdk8/amdk8_acpi.c Modified: trunk/src/mainboard/amd/dbm690t/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/dbm690t/dsdt.asl Wed Nov 17 11:58:13 2010 (r6081) +++ trunk/src/mainboard/amd/dbm690t/dsdt.asl Wed Nov 17 12:02:05 2010 (r6082) @@ -1129,7 +1129,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1557,7 +1557,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Modified: trunk/src/mainboard/amd/mahogany/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/mahogany/dsdt.asl Wed Nov 17 11:58:13 2010 (r6081) +++ trunk/src/mainboard/amd/mahogany/dsdt.asl Wed Nov 17 12:02:05 2010 (r6082) @@ -1126,7 +1126,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1572,7 +1572,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Modified: trunk/src/mainboard/amd/mahogany_fam10/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/dsdt.asl Wed Nov 17 11:58:13 2010 (r6081) +++ trunk/src/mainboard/amd/mahogany_fam10/dsdt.asl Wed Nov 17 12:02:05 2010 (r6082) @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Modified: trunk/src/mainboard/amd/pistachio/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/pistachio/dsdt.asl Wed Nov 17 11:58:13 2010 (r6081) +++ trunk/src/mainboard/amd/pistachio/dsdt.asl Wed Nov 17 12:02:05 2010 (r6082) @@ -1128,7 +1128,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1480,7 +1480,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Modified: trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl Wed Nov 17 11:58:13 2010 (r6081) +++ trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl Wed Nov 17 12:02:05 2010 (r6082) @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Modified: trunk/src/mainboard/asrock/939a785gmh/dsdt.asl ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/dsdt.asl Wed Nov 17 11:58:13 2010 (r6081) +++ trunk/src/mainboard/asrock/939a785gmh/dsdt.asl Wed Nov 17 12:02:05 2010 (r6082) @@ -1122,7 +1122,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1530,7 +1530,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Modified: trunk/src/mainboard/asus/m4a785-m/dsdt.asl ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/dsdt.asl Wed Nov 17 11:58:13 2010 (r6081) +++ trunk/src/mainboard/asus/m4a785-m/dsdt.asl Wed Nov 17 12:02:05 2010 (r6082) @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Modified: trunk/src/mainboard/gigabyte/ma785gmt/dsdt.asl ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/dsdt.asl Wed Nov 17 11:58:13 2010 (r6081) +++ trunk/src/mainboard/gigabyte/ma785gmt/dsdt.asl Wed Nov 17 12:02:05 2010 (r6082) @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Modified: trunk/src/mainboard/gigabyte/ma78gm/dsdt.asl ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/dsdt.asl Wed Nov 17 11:58:13 2010 (r6081) +++ trunk/src/mainboard/gigabyte/ma78gm/dsdt.asl Wed Nov 17 12:02:05 2010 (r6082) @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Modified: trunk/src/mainboard/iei/kino-780am2-fam10/dsdt.asl ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/dsdt.asl Wed Nov 17 11:58:13 2010 (r6081) +++ trunk/src/mainboard/iei/kino-780am2-fam10/dsdt.asl Wed Nov 17 12:02:05 2010 (r6082) @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Modified: trunk/src/mainboard/jetway/pa78vm5/dsdt.asl ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/dsdt.asl Wed Nov 17 11:58:13 2010 (r6081) +++ trunk/src/mainboard/jetway/pa78vm5/dsdt.asl Wed Nov 17 12:02:05 2010 (r6082) @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Modified: trunk/src/mainboard/kontron/kt690/dsdt.asl ============================================================================== --- trunk/src/mainboard/kontron/kt690/dsdt.asl Wed Nov 17 11:58:13 2010 (r6081) +++ trunk/src/mainboard/kontron/kt690/dsdt.asl Wed Nov 17 12:02:05 2010 (r6082) @@ -1129,7 +1129,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1557,7 +1557,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Modified: trunk/src/mainboard/technexion/tim5690/dsdt.asl ============================================================================== --- trunk/src/mainboard/technexion/tim5690/dsdt.asl Wed Nov 17 11:58:13 2010 (r6081) +++ trunk/src/mainboard/technexion/tim5690/dsdt.asl Wed Nov 17 12:02:05 2010 (r6082) @@ -1129,7 +1129,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1557,7 +1557,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Modified: trunk/src/mainboard/technexion/tim8690/dsdt.asl ============================================================================== --- trunk/src/mainboard/technexion/tim8690/dsdt.asl Wed Nov 17 11:58:13 2010 (r6081) +++ trunk/src/mainboard/technexion/tim8690/dsdt.asl Wed Nov 17 12:02:05 2010 (r6082) @@ -1129,7 +1129,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1557,7 +1557,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Modified: trunk/src/northbridge/amd/amdk8/amdk8_acpi.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/amdk8_acpi.c Wed Nov 17 11:58:13 2010 (r6081) +++ trunk/src/northbridge/amd/amdk8/amdk8_acpi.c Wed Nov 17 12:02:05 2010 (r6082) @@ -270,7 +270,15 @@ msr = rdmsr(TOP_MEM); lens += acpigen_write_name_dword("TOM1", msr.lo); msr = rdmsr(TOP_MEM2); - lens += acpigen_write_name_qword("TOM2", (((uint64_t) msr.hi) << 32) | msr.lo); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); lens += k8acpi_write_HT(); //minus opcode

1 0

[commit] r6081 - in trunk/src: mainboard/asus/m2v southbridge/via/vt8237r
by repository service 17 Nov '10

17 Nov '10

Author: ruik Date: Wed Nov 17 11:58:13 2010 New Revision: 6081 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6081 Log: The only southbridge having a pirq_assign_irqs function (needed for CONFIG_PIRQ_ROUTE) so far is the amd cs5530. Add one for vt8237 too. Setting up the pci routing is important in case you want to boot DOS, OSes that don't support ACPI or MP tables and ROMs for add-in storage controllers may depend on this too. TODO: Fix the 4 routing links limitation in src/arch/i386/boot/pirq_routing.c Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Added: trunk/src/southbridge/via/vt8237r/vt8237r_pirq.c Modified: trunk/src/mainboard/asus/m2v/Kconfig trunk/src/southbridge/via/vt8237r/Makefile.inc Modified: trunk/src/mainboard/asus/m2v/Kconfig ============================================================================== --- trunk/src/mainboard/asus/m2v/Kconfig Wed Nov 17 00:15:37 2010 (r6080) +++ trunk/src/mainboard/asus/m2v/Kconfig Wed Nov 17 11:58:13 2010 (r6081) @@ -18,6 +18,7 @@ select RAMINIT_SYSINFO select TINY_BOOTBLOCK select HAVE_PIRQ_TABLE + select PIRQ_ROUTE select HAVE_ACPI_TABLES select HAVE_MP_TABLE select SET_FIDVID Modified: trunk/src/southbridge/via/vt8237r/Makefile.inc ============================================================================== --- trunk/src/southbridge/via/vt8237r/Makefile.inc Wed Nov 17 00:15:37 2010 (r6080) +++ trunk/src/southbridge/via/vt8237r/Makefile.inc Wed Nov 17 11:58:13 2010 (r6081) @@ -23,5 +23,5 @@ driver-y += vt8237r_lpc.c driver-y += vt8237r_sata.c driver-y += vt8237r_usb.c -driver-y += vt8237r_nic.c +driver-$(CONFIG_PIRQ_ROUTE) += vt8237r_pirq.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += vt8237_fadt.c Added: trunk/src/southbridge/via/vt8237r/vt8237r_pirq.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/via/vt8237r/vt8237r_pirq.c Wed Nov 17 11:58:13 2010 (r6081) @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov(a)gmail.com> + * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <pc80/i8259.h> + +#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1) +void pirq_assign_irqs(const unsigned char route[4]) +{ + device_t pdev; + + pdev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (!pdev) + pdev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237S_LPC, 0); + if (!pdev) + pdev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237A_LPC, 0); + if (!pdev) + return; + + pci_write_config8(pdev, 0x55, route[0] << 4); + pci_write_config8(pdev, 0x56, (route[2] << 4) | route[1]); + pci_write_config8(pdev, 0x57, route[3] << 4); + + /* Enable INT[E-H] mapped to INT[A-D] for simplicity */ + pci_write_config8(pdev, 0x46, 0x00); +} +#endif

1 0

Acer Aspire M3300
by treevor 17 Nov '10

17 Nov '10

Hi, The below is for an Acer Aspire m3300 I'm interested in seeing if I can get coreboot onto. I've included what was listed on the FAQ. What do you think my odds of success are with this system or what we would need to do in order to get coreboot onto it. Thanks in advance for any help. Trevor 1. System info Acer Aspire M3300 This machine came with a Phenom II X4 810 processor and currently has 6gigs of memory and 1TB hard drive. It has a AMD 780G Chipset (so rs780 and sb700/xb800 chips). 2. lspci output -[0000:00]-+-00.0 Advanced Micro Devices [AMD] RS780 Host Bridge [1022:9600] +-01.0-[01]--+-05.0 ATI Technologies Inc Radeon HD 3200 Graphics [1002:9610] | \-05.1 ATI Technologies Inc RS780 Azalia controller [1002:960f] +-05.0-[02]----00.0 Marvell Technology Group Ltd. 88E8071 PCI-E Gigabit Ethernet Controller [11ab:436b] +-11.0 ATI Technologies Inc SB700/SB800 SATA Controller [AHCI mode] [1002:4391] +-12.0 ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397] +-12.1 ATI Technologies Inc SB700 USB OHCI1 Controller [1002:4398] +-12.2 ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396] +-13.0 ATI Technologies Inc SB700/SB800 USB OHCI0 Controller [1002:4397] +-13.1 ATI Technologies Inc SB700 USB OHCI1 Controller [1002:4398] +-13.2 ATI Technologies Inc SB700/SB800 USB EHCI Controller [1002:4396] +-14.0 ATI Technologies Inc SBx00 SMBus Controller [1002:4385] +-14.1 ATI Technologies Inc SB700/SB800 IDE Controller [1002:439c] +-14.2 ATI Technologies Inc SBx00 Azalia (Intel HDA) [1002:4383] +-14.3 ATI Technologies Inc SB700/SB800 LPC host controller [1002:439d] +-14.4-[03]-- +-14.5 ATI Technologies Inc SB700/SB800 USB OHCI2 Controller [1002:4399] +-18.0 Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] HyperTransport Configuration [1022:1200] +-18.1 Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] Address Map [1022:1201] +-18.2 Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] DRAM Controller [1022:1202] +-18.3 Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] Miscellaneous Control [1022:1203] \-18.4 Advanced Micro Devices [AMD] K10 [Opteron, Athlon64, Sempron] Link Control [1022:1204] 3. Superio output superiotool r5690 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0xffff, id=0xffff Probing for ITE Super I/O (init=standard) at 0x2e... Found ITE IT8720F (id=0x8720, rev=0x8) at 0x2e No dump available for this Super I/O Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0x00, rev=0x00 Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for VIA Super I/O at 0x3f0... PCI device 1106:0686 not found. 4. Flashrom output flashrom v0.9.3-r1205 on Linux 2.6.34.6-47.fc13.x86_64 (x86_64), built with libpci 3.1.7, GCC 4.4.4 20100630 (Red Hat 4.4.4-10), little endian flashrom is free software, get the source code at http://www.flashrom.org Calibrating delay loop... OS timer resolution is 1 usecs, 1294M loops per second, 10 myus = 10 us, 100 myus = 100 us, 1000 myus = 1003 us, 10000 myus = 10002 us, 4 myus = 4 us, OK. Initializing internal programmer No coreboot table found. DMI string system-manufacturer: "Acer" DMI string system-product-name: "Aspire M3300" DMI string system-version: " " DMI string baseboard-manufacturer: "Acer" DMI string baseboard-product-name: "FRS780M" DMI string baseboard-version: " " DMI string chassis-type: "Desktop" Found ITE Super I/O, ID 0x8720. Found chipset "AMD SB700/SB710/SB750", enabling flash write... chipset PCI ID is 1002:439d, SPI base address is at 0xfec10000 AltSpiCSEnable=0, SpiRomEnable=1, AbortEnable=0 PrefetchEnSPIFromIMC=0, PrefetchEnSPIFromHost=1, SpiOpEnInLpcMode=1 SpiArbEnable=1, SpiAccessMacRomEn=1, SpiHostAccessRomEn=1, ArbWaitCount=4, SpiBridgeDisable=1, DropOneClkOnRd=0 NormSpeed is 33 MHz GPIO11 used for SPI_DO GPIO12 used for SPI_DI GPIO31 used for SPI_HOLD GPIO32 used for SPI_CS GPIO47 used for SPI_CLK SB700 IMC is not active. ROM strap override is not active OK. This chipset supports the following protocols: LPC,FWH,SPI. No IT87* serial flash segment enabled. Probing for AMD Am29F010A/B, 128 KB: skipped. Probing for AMD Am29F002(N)BB, 256 KB: skipped. Probing for AMD Am29F002(N)BT, 256 KB: skipped. Probing for AMD Am29F016D, 2048 KB: skipped. Probing for AMD Am29F040B, 512 KB: skipped. Probing for AMD Am29F080B, 1024 KB: skipped. Probing for AMD Am29LV040B, 512 KB: skipped. Probing for AMD Am29LV081B, 1024 KB: skipped. Probing for AMIC A25L05PT, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L05PU, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L10PT, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L10PU, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L20PT, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L20PU, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L40PT, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L40PU, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L80P, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L16PT, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L16PU, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L020, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L080, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L016, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25L032, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A25LQ032, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for AMIC A29002B, 256 KB: skipped. Probing for AMIC A29002T, 256 KB: skipped. Probing for AMIC A29040B, 512 KB: skipped. Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x74, id2 0xd1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT25DF021, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF041A, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF081, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF321, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF321A, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DF641, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25DQ161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25F512B, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25FS010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT25FS040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF041, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF081A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF161, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26DF161A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT26F004, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT29C512, 64 KB: skipped. Probing for Atmel AT29C010A, 128 KB: skipped. Probing for Atmel AT29C020, 256 KB: skipped. Probing for Atmel AT29C040A, 512 KB: skipped. Probing for Atmel AT45CS1282, 16896 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB011D, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB021D, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB041D, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB081D, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB161D, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB321C, 4224 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB321D, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT45DB642D, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel AT49BV512, 64 KB: skipped. Probing for Atmel AT49F020, 256 KB: skipped. Probing for Atmel AT49F002(N), 256 KB: skipped. Probing for Atmel AT49F002(N)T, 256 KB: skipped. Probing for Bright BM29F040, 512 KB: skipped. Probing for EMST F49B002UA, 256 KB: skipped. Probing for EMST F25L008A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B05T, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B10T, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B20T, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B40T, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B80T, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B16T, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B32T, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25B64T, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25D16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F05, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN25F32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon EN29F010, 128 KB: skipped. Probing for Eon EN29F002(A)(N)B, 256 KB: skipped. Probing for Eon EN29F002(A)(N)T, 256 KB: skipped. Probing for Fujitsu MBM29F004BC, 512 KB: skipped. Probing for Fujitsu MBM29F004TC, 512 KB: skipped. Probing for Fujitsu MBM29F400BC, 512 KB: skipped. Probing for Fujitsu MBM29F400TC, 512 KB: skipped. Probing for Hyundai HY29F002T, 256 KB: skipped. Probing for Hyundai HY29F002B, 256 KB: skipped. Probing for Hyundai HY29F040A, 512 KB: skipped. Probing for Intel 28F001BN/BX-B, 128 KB: skipped. Probing for Intel 28F001BN/BX-T, 128 KB: skipped. Probing for Intel 28F002BC/BL/BV/BX-T, 256 KB: skipped. Probing for Intel 28F008S3/S5/SC, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-B, 512 KB: skipped. Probing for Intel 28F004B5/BE/BV/BX-T, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-B, 512 KB: skipped. Probing for Intel 28F400BV/BX/CE/CV-T, 512 KB: skipped. Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x74, id2 0xd1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX25L512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1005, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L2005, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L4005, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L8005, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1605, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1635D, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L1635E, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L3205, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L3235D, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L6405, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX25L12805, 16384 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix MX29F001B, 128 KB: skipped. Probing for Macronix MX29F001T, 128 KB: skipped. Probing for Macronix MX29F002B, 256 KB: skipped. Probing for Macronix MX29F002T, 256 KB: skipped. Probing for Macronix MX29F040, 512 KB: skipped. Probing for Macronix MX29LV040, 512 KB: skipped. Probing for MoselVitelic V29C51000B, 64 KB: skipped. Probing for MoselVitelic V29C51000T, 64 KB: skipped. Probing for MoselVitelic V29C51400B, 512 KB: skipped. Probing for MoselVitelic V29C51400T, 512 KB: skipped. Probing for MoselVitelic V29LC51000, 64 KB: skipped. Probing for MoselVitelic V29LC51001, 128 KB: skipped. Probing for MoselVitelic V29LC51002, 256 KB: skipped. Probing for Numonyx M25PE10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Numonyx M25PE16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV010, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV020, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV040, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm25LV512, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC Pm29F002T, 256 KB: skipped. Probing for PMC Pm29F002B, 256 KB: skipped. Probing for PMC Pm39LV010, 128 KB: skipped. Probing for PMC Pm39LV020, 256 KB: skipped. Probing for PMC Pm39LV040, 512 KB: skipped. Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0x39, id2 0xbc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x74, id2 0xd1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Spansion S25FL008A, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Spansion S25FL016A, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF016B, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF032B, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF064C, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25VF040.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF040B, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST25LF040A.RES, 512 KB: probe_spi_res2: id1 0x13, id2 0x13 Probing for SST SST25VF040B.REMS, 512 KB: probe_spi_rems: id1 0xef, id2 0x13 Probing for SST SST25VF080B, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST SST28SF040A, 512 KB: skipped. Probing for SST SST29EE010, 128 KB: skipped. Probing for SST SST29LE010, 128 KB: skipped. Probing for SST SST29EE020A, 256 KB: skipped. Probing for SST SST29LE020, 256 KB: skipped. Probing for SST SST39SF512, 64 KB: skipped. Probing for SST SST39SF010A, 128 KB: skipped. Probing for SST SST39SF020A, 256 KB: skipped. Probing for SST SST39SF040, 512 KB: skipped. Probing for SST SST39VF512, 64 KB: skipped. Probing for SST SST39VF010, 128 KB: skipped. Probing for SST SST39VF020, 256 KB: skipped. Probing for SST SST39VF040, 512 KB: skipped. Probing for SST SST39VF080, 1024 KB: skipped. Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0x39, id2 0xbc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0xb6, id2 0xe0, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0x74, id2 0xd1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x74, id2 0xd1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0x39, id2 0xbc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0x39, id2 0xbc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x74, id2 0xd1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x74, id2 0xd1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M25P05-A, 64 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P05.RES, 64 KB: Ignoring RES in favour of RDID. Probing for ST M25P10-A, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P10.RES, 128 KB: Ignoring RES in favour of RDID. Probing for ST M25P20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P40-old, 512 KB: Ignoring RES in favour of RDID. Probing for ST M25P80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25P128, 16384 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25PX32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M25PX64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST M29F002B, 256 KB: skipped. Probing for ST M29F002T/NT, 256 KB: skipped. Probing for ST M29F040B, 512 KB: skipped. Probing for ST M29F400BB, 512 KB: skipped. Probing for ST M29F400BT, 512 KB: skipped. Probing for ST M29W010B, 128 KB: skipped. Probing for ST M29W040B, 512 KB: skipped. Probing for ST M29W512B, 64 KB: skipped. Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x74, id2 0xd1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x74, id2 0xd1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0x39, id2 0xbc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x74, id2 0xd1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS/MoselVitelic {F,S,V}29C51001B, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51001T, 128 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002B, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51002T, 256 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {F,S,V}29C51004T, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004B, 512 KB: skipped. Probing for SyncMOS/MoselVitelic {S,V}29C31004T, 512 KB: skipped. Probing for TI TMS29F002RB, 256 KB: skipped. Probing for TI TMS29F002RT, 256 KB: skipped. Probing for Winbond W25Q80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25Q64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x10, 128 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x20, 256 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x40, 512 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x80, 1024 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Chip status register is 00 Found chip "Winbond W25x80" (1024 KB, SPI) at physical address 0xfff00000. Probing for Winbond W25x16, 2048 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x32, 4096 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W25x64, 8192 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W29C020(C)/W29C022, 256 KB: skipped. Probing for Winbond W29C040/P, 512 KB: skipped. Probing for Winbond W29C010(M)/W29C011A/W29EE011/W29EE012, 128 KB: skipped. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x74, id2 0xd1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040(F)B, 512 KB: probe_jedec_common: id1 0x74, id2 0xd1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040(F)C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x74, id2 0xd1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0x74, id2 0xd1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U/N, 256 KB: skipped. Probing for Winbond W49F020, 256 KB: skipped. Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0x39, id2 0xbc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0x39, id2 0xbc, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x74, id2 0xd1, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC unknown AMIC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Atmel unknown Atmel SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Eon unknown Eon SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Macronix unknown Macronix SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for PMC unknown PMC SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for SST unknown SST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for ST unknown ST SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Sanyo unknown Sanyo SPI chip, 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Generic unknown SPI chip (RDID), 0 KB: probe_spi_rdid_generic: id1 0xef, id2 0x3014 Probing for Generic unknown SPI chip (REMS), 0 KB: probe_spi_rems: id1 0xef, id2 0x13 No operations were specified. 5. Website http://support.acer.com/acerpanam/desktop/2010/acer/aspire/AspireM3300/Aspi… 6. Other info here is output of dmidecode # dmidecode 2.10 SMBIOS 2.5 present. 36 structures occupying 1668 bytes. Table at 0x0009F800. Handle 0x0000, DMI type 0, 24 bytes BIOS Information Vendor: American Megatrends Inc. Version: P03-B3 Release Date: 04/26/2010 Address: 0xF0000 Runtime Size: 64 kB ROM Size: 1024 kB Characteristics: ISA is supported PCI is supported PNP is supported APM is supported BIOS is upgradeable BIOS shadowing is allowed Boot from CD is supported Selectable boot is supported BIOS ROM is socketed EDD is supported 5.25"/1.2 MB floppy services are supported (int 13h) 3.5"/720 kB floppy services are supported (int 13h) 3.5"/2.88 MB floppy services are supported (int 13h) Print screen service is supported (int 5h) 8042 keyboard services are supported (int 9h) Serial services are supported (int 14h) Printer services are supported (int 17h) CGA/mono video services are supported (int 10h) ACPI is supported USB legacy is supported LS-120 boot is supported ATAPI Zip drive boot is supported BIOS boot specification is supported Targeted content distribution is supported BIOS Revision: 8.15 Handle 0x0001, DMI type 1, 27 bytes System Information Manufacturer: Acer Product Name: Aspire M3300 Version: Serial Number: PTSBT0200201201A1A2700 UUID: 90FBA64B-F3E5-2010-0323-020213000000 Wake-up Type: Power Switch SKU Number: To Be Filled By O.E.M. Family: Acer Desktop Handle 0x0002, DMI type 2, 15 bytes Base Board Information Manufacturer: Acer Product Name: FRS780M Version: Serial Number: U00V101100956 Asset Tag: To Be Filled By O.E.M. Features: Board is a hosting board Board is replaceable Location In Chassis: To Be Filled By O.E.M. Chassis Handle: 0x0003 Type: Motherboard Contained Object Handles: 0 Handle 0x0003, DMI type 3, 21 bytes Chassis Information Manufacturer: Acer Type: Desktop Lock: Not Present Version: Serial Number: Asset Tag: Boot-up State: Safe Power Supply State: Safe Thermal State: Safe Security Status: None OEM Information: 0x00000000 Height: Unspecified Number Of Power Cords: 1 Contained Elements: 0 Handle 0x0004, DMI type 4, 42 bytes Processor Information Socket Designation: CPU 1 Type: Central Processor Family: <OUT OF SPEC> Manufacturer: AMD ID: 42 0F 10 00 FF FB 8B 17 Version: AMD Phenom(tm) II X4 810 Processor Voltage: 1.5 V External Clock: 200 MHz Max Speed: 2600 MHz Current Speed: 2600 MHz Status: Populated, Enabled Upgrade: Other L1 Cache Handle: 0x0005 L2 Cache Handle: 0x0006 L3 Cache Handle: 0x0007 Serial Number: To Be Filled By O.E.M. Asset Tag: To Be Filled By O.E.M. Part Number: To Be Filled By O.E.M. Core Count: 4 Core Enabled: 4 Thread Count: 4 Characteristics: 64-bit capable Handle 0x0005, DMI type 7, 19 bytes Cache Information Socket Designation: L1-Cache Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Varies With Memory Address Location: Internal Installed Size: 512 kB Maximum Size: 512 kB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: Unknown Error Correction Type: Single-bit ECC System Type: <OUT OF SPEC> Associativity: 4-way Set-associative Handle 0x0006, DMI type 7, 19 bytes Cache Information Socket Designation: L2-Cache Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Varies With Memory Address Location: Internal Installed Size: 2048 kB Maximum Size: 2048 kB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: Unknown Error Correction Type: Single-bit ECC System Type: <OUT OF SPEC> Associativity: 4-way Set-associative Handle 0x0007, DMI type 7, 19 bytes Cache Information Socket Designation: L3-Cache Configuration: Enabled, Not Socketed, Level 3 Operational Mode: Varies With Memory Address Location: Internal Installed Size: 4096 kB Maximum Size: 4096 kB Supported SRAM Types: Pipeline Burst Installed SRAM Type: Pipeline Burst Speed: Unknown Error Correction Type: Single-bit ECC System Type: <OUT OF SPEC> Associativity: 4-way Set-associative Handle 0x0008, DMI type 9, 17 bytes System Slot Information Designation: PCIE_X16 Type: x16 PCI Express x16 Current Usage: Available Length: Long Characteristics: 3.3 V is provided Opening is shared PME signal is supported Handle 0x0009, DMI type 9, 17 bytes System Slot Information Designation: PCIE_X1 Type: x1 PCI Express x1 Current Usage: Available Length: Short Characteristics: 3.3 V is provided Opening is shared PME signal is supported Handle 0x000A, DMI type 9, 17 bytes System Slot Information Designation: PCI1 Type: 32-bit PCI Current Usage: Available Length: Long ID: 1 Characteristics: 3.3 V is provided Opening is shared PME signal is supported Handle 0x000B, DMI type 9, 17 bytes System Slot Information Designation: PCI2 Type: 32-bit PCI Current Usage: Available Length: Long ID: 2 Characteristics: 3.3 V is provided Opening is shared PME signal is supported Handle 0x000C, DMI type 10, 6 bytes On Board Device Information Type: Video Status: Enabled Description: Onboard ATI Graphics Handle 0x000D, DMI type 10, 6 bytes On Board Device Information Type: Ethernet Status: Enabled Description: Onboard Marvell Lan Handle 0x000E, DMI type 10, 6 bytes On Board Device Information Type: Sound Status: Enabled Description: Onboard Realtek HD Audio Handle 0x000F, DMI type 10, 6 bytes On Board Device Information Type: PATA Controller Status: Enabled Description: Onboard ATI PATA Handle 0x0010, DMI type 10, 6 bytes On Board Device Information Type: SATA Controller Status: Enabled Description: Onboard ATI SATA Handle 0x0011, DMI type 11, 5 bytes OEM Strings String 1: AMD RS780/RS780L+SB710 Handle 0x0012, DMI type 16, 15 bytes Physical Memory Array Location: System Board Or Motherboard Use: System Memory Error Correction Type: None Maximum Capacity: 8 GB Error Information Handle: Not Provided Number Of Devices: 4 Handle 0x0013, DMI type 19, 15 bytes Memory Array Mapped Address Starting Address: 0x00000000000 Ending Address: 0x001AFFFFFFF Range Size: 6912 MB Physical Array Handle: 0x0012 Partition Width: 0 Handle 0x0014, DMI type 17, 28 bytes Memory Device Array Handle: 0x0012 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 72 bits Size: 2048 MB Form Factor: DIMM Set: None Locator: DIMM0 Bank Locator: BANK0 Type: DDR3 Type Detail: Synchronous Speed: 1333 MHz Manufacturer: None Serial Number: 00000000 Asset Tag: Part Number: Rank: 2 Handle 0x0015, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00000000000 Ending Address: 0x0007FFFFFFF Range Size: 2 GB Physical Device Handle: 0x0014 Memory Array Mapped Address Handle: 0x0013 Partition Row Position: 1 Handle 0x0016, DMI type 17, 28 bytes Memory Device Array Handle: 0x0012 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 72 bits Size: 2048 MB Form Factor: DIMM Set: None Locator: DIMM1 Bank Locator: BANK1 Type: DDR3 Type Detail: Synchronous Speed: 1333 MHz Manufacturer: None Serial Number: 00000000 Asset Tag: Part Number: Rank: 2 Handle 0x0017, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00080000000 Ending Address: 0x000FFFFFFFF Range Size: 2 GB Physical Device Handle: 0x0016 Memory Array Mapped Address Handle: 0x0013 Partition Row Position: 1 Handle 0x0018, DMI type 17, 28 bytes Memory Device Array Handle: 0x0012 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 72 bits Size: 1024 MB Form Factor: DIMM Set: None Locator: DIMM2 Bank Locator: BANK2 Type: DDR3 Type Detail: Synchronous Speed: 1333 MHz Manufacturer: None Serial Number: 00000000 Asset Tag: Part Number: Rank: 1 Handle 0x0019, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00100000000 Ending Address: 0x0013FFFFFFF Range Size: 1 GB Physical Device Handle: 0x0018 Memory Array Mapped Address Handle: 0x0013 Partition Row Position: 1 Handle 0x001A, DMI type 17, 28 bytes Memory Device Array Handle: 0x0012 Error Information Handle: Not Provided Total Width: 64 bits Data Width: 72 bits Size: 1024 MB Form Factor: DIMM Set: None Locator: DIMM3 Bank Locator: BANK3 Type: DDR3 Type Detail: Synchronous Speed: 1333 MHz Manufacturer: None Serial Number: 00000000 Asset Tag: Part Number: Rank: 1 Handle 0x001B, DMI type 20, 19 bytes Memory Device Mapped Address Starting Address: 0x00140000000 Ending Address: 0x0017FFFFFFF Range Size: 1 GB Physical Device Handle: 0x001A Memory Array Mapped Address Handle: 0x0013 Partition Row Position: 1 Handle 0x001C, DMI type 24, 5 bytes Hardware Security Power-On Password Status: Disabled Keyboard Password Status: Disabled Administrator Password Status: Disabled Front Panel Reset Status: Disabled Handle 0x001D, DMI type 32, 20 bytes System Boot Information Status: No errors detected Handle 0x001E, DMI type 41, 11 bytes Onboard Device Reference Designation: Onboard ATI Graphics Type: Video Status: Enabled Type Instance: 1 Bus Address: 0000:01:05.0 Handle 0x001F, DMI type 41, 11 bytes Onboard Device Reference Designation: Onboard Marvell Lan Type: Ethernet Status: Enabled Type Instance: 1 Bus Address: 0000:02:00.0 Handle 0x0020, DMI type 41, 11 bytes Onboard Device Reference Designation: Onboard Realtek HD Audio Type: Sound Status: Enabled Type Instance: 1 Bus Address: 0000:00:14.2 Handle 0x0021, DMI type 41, 11 bytes Onboard Device Reference Designation: Onboard ATI PATA Type: PATA Controller Status: Enabled Type Instance: 1 Bus Address: 0000:00:14.1 Handle 0x0022, DMI type 41, 11 bytes Onboard Device Reference Designation: Onboard ATI SATA Type: SATA Controller Status: Enabled Type Instance: 1 Bus Address: 0000:00:11.0 Handle 0x0023, DMI type 127, 4 bytes End Of Table

3 3

Supermicro E7501 based boards
by Matt Taggart 16 Nov '10

16 Nov '10

Hi, I have a couple different Supermicro board models based on the Intel E7501 chipset. The website and people in IRC indicated there is some support for this chipset and that it might be possible to get these working. Here is the information requested in the FAQ Supermicro X5DP8-G2 =================== Product Page http://www.supermicro.com/products/motherboard/Xeon/E7501/X5DP8-G2.cfm Board Manual http://www.supermicro.com/manuals/motherboard/E7501/MNL-0684.pdf Product page lists Intel E7501 chipset MCH + ICH3-S + P64H2 flashrom -V indicates "Intel ICH3-S" ""Intel 82802AB" (512 KB, FWH) at physical address 0xfff80000." flash is socketed, print on chip is "Intel N82802AB8 A3417434" superiotool -dV indicates "Winbond W83627HF/F/HG/G (id=0x52, rev=0x17) at 0x2e" Supermicro X5DPR-8G2+ ===================== Product Page http://www.supermicro.com/products/motherboard/Xeon/E7501/X5DPR-8G2_.cfm Board Manual http://www.supermicro.com/manuals/motherboard/E7501/MNL-0684.pdf Product page lists Intel E7501 chipset MCH + ICH3-S + P64H2 flashrom -V indicates "Intel ICH3-S" ""Intel 82802AB" (512 KB, FWH) at physical address 0xfff80000." superiotool -dV indicates "Winbond W83627HF/F/HG/G (id=0x52, rev=0x17) at 0x2e" Full output of lspci, flashrom, and superiotool for both boards is available at http://lackof.org/taggart/hacking/coreboot/ The manual PDF mentioned above is the same for both boards and applies to the following boards X5DP8-G2 X5DPE-G2 X5DPR-8G2+ X5DPR-iG2+ X5DPi-G2+ So hopefully that means they will be similar enough to be enabled together. I'm willing to test, I have a null modem cable and a POST card, etc. Thanks, -- Matt Taggart taggart(a)debian.org

1 0

question about switching from real mode to protected mode in smm handler
by Fengwei Zhang 16 Nov '10

16 Nov '10

Hi all, I am implementing SMM on K8/vt8237r, and I have problem with switching from real mode to protected mode in smm handler. I followed the smmhandler.S code in /src/cpu/x86/smm/ directory If I put my rsm instruction before ljmp instruction, I could invoke SMI successfully. /* Enable protected mode */ data32 ljmp $0x08, $1f but if I put rsm instruction below that(even commented out the C procedure), my machine will freeze after the invoking. The only difference between my code and ICH4 implementation is: I didn't copy the smm bin file(include smmhandler.S smihandler.c smm.ld), to location 0xa0000, I just copied the smmhandler.S file to location 0xa0000 and wrote a jmp statement at 0xa8000. In order to make it simple, I commented out the C procedure, and only assembly in smmhandler. I may didn't set global descriptor table correctly. I understand ljmp $0x08, $1f is going to use first entry of gdt, and traslate the logical address to linear address. smmhandler.S code has setted up correct smm_gdt, and I also copied the code to location 0xa0000 (since it is in smmhander.S file). .code16 .align 4, 0xff smm_gdtptr16: .word smm_gdt_end - smm_gdt - 1 .long smm_gdt - smm_handler_start + 0xa0000 + SMM_HANDLER_OFFSET .code32 smm_gdt: /* The first GDT entry can not be used. Keep it zero */ .long 0x00000000, 0x00000000 /* gdt selector 0x08, flat code segment */ .word 0xffff, 0x0000 .byte 0x00, 0x9b, 0xcf, 0x00 /* G=1 and 0x0f, 4GB limit */ /* gdt selector 0x10, flat data segment */ .word 0xffff, 0x0000 .byte 0x00, 0x93, 0xcf, 0x00 smm_gdt_end: I would appreciate it if someone could help me out. Best, Fengwei

2 1

[PATCH] Drop W83627THF, it's the same device as W83627THG
by Uwe Hermann 16 Nov '10

16 Nov '10

See patch. Uwe. -- http://hermann-uwe.de | http://sigrok.org http://randomprojects.org | http://unmaintained-free-software.org

4 6

[commit] r6080 - in trunk/src: mainboard/iwill/dk8x mainboard/lanner/em8510 mainboard/msi/ms7135 superio/winbond superio/winbond/w83627thf
by repository service 16 Nov '10

16 Nov '10

Author: uwe Date: Wed Nov 17 00:15:37 2010 New Revision: 6080 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6080 Log: Drop W83627THF, it's the same device as W83627THG. The only difference is that the "G" version is in a Pb-free package, which is not relevant from a programmer's view. We keep W83627THG (and drop W83627THF) because: - The W83627THF had a CIR device / LDN which doesn't actually exist. - The W83627THF had no GPIO2, GPIO3 LDNs (were commented out). - The W83627THF didn't use the PNP_MSC0/1 which is needed/used by boards. This also fixes an issue on MSI MS7135's devicetree.cb: device pnp 4e.6 off end # XXX keep allocator happy The line above can be (and is) removed, as it was only needed due to the incorrect CIR LDN in the W83627THF. In the iwill/dk8x target: Drop incorrect LDNs 4 and 6, add 0xb. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Deleted: trunk/src/superio/winbond/w83627thf/ Modified: trunk/src/mainboard/iwill/dk8x/Kconfig trunk/src/mainboard/iwill/dk8x/devicetree.cb trunk/src/mainboard/lanner/em8510/Kconfig trunk/src/mainboard/lanner/em8510/devicetree.cb trunk/src/mainboard/lanner/em8510/romstage.c trunk/src/mainboard/msi/ms7135/Kconfig trunk/src/mainboard/msi/ms7135/devicetree.cb trunk/src/mainboard/msi/ms7135/romstage.c trunk/src/superio/winbond/Kconfig trunk/src/superio/winbond/Makefile.inc Modified: trunk/src/mainboard/iwill/dk8x/Kconfig ============================================================================== --- trunk/src/mainboard/iwill/dk8x/Kconfig Tue Nov 16 23:15:09 2010 (r6079) +++ trunk/src/mainboard/iwill/dk8x/Kconfig Wed Nov 17 00:15:37 2010 (r6080) @@ -8,7 +8,7 @@ select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_AMD_AMD8111 select SOUTHBRIDGE_AMD_AMD8131 - select SUPERIO_WINBOND_W83627THF + select SUPERIO_WINBOND_W83627THG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE Modified: trunk/src/mainboard/iwill/dk8x/devicetree.cb ============================================================================== --- trunk/src/mainboard/iwill/dk8x/devicetree.cb Tue Nov 16 23:15:09 2010 (r6079) +++ trunk/src/mainboard/iwill/dk8x/devicetree.cb Wed Nov 17 00:15:37 2010 (r6080) @@ -25,18 +25,18 @@ device pci 1.0 off end end device pci 1.0 on - chip superio/winbond/w83627thf + # TODO: This is incomplete. + chip superio/winbond/w83627thg device pnp 2e.0 on end device pnp 2e.1 on end device pnp 2e.2 on end device pnp 2e.3 on end - device pnp 2e.4 on end device pnp 2e.5 on end - device pnp 2e.6 on end device pnp 2e.7 on end device pnp 2e.8 on end device pnp 2e.9 on end device pnp 2e.a on end + device pnp 2e.b on end end end device pci 1.1 on end Modified: trunk/src/mainboard/lanner/em8510/Kconfig ============================================================================== --- trunk/src/mainboard/lanner/em8510/Kconfig Tue Nov 16 23:15:09 2010 (r6079) +++ trunk/src/mainboard/lanner/em8510/Kconfig Wed Nov 17 00:15:37 2010 (r6080) @@ -6,7 +6,7 @@ select CPU_INTEL_SOCKET_MPGA479M select NORTHBRIDGE_INTEL_I855 select SOUTHBRIDGE_INTEL_I82801DX - select SUPERIO_WINBOND_W83627THF + select SUPERIO_WINBOND_W83627THG select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_HARD_RESET Modified: trunk/src/mainboard/lanner/em8510/devicetree.cb ============================================================================== --- trunk/src/mainboard/lanner/em8510/devicetree.cb Tue Nov 16 23:15:09 2010 (r6079) +++ trunk/src/mainboard/lanner/em8510/devicetree.cb Wed Nov 17 00:15:37 2010 (r6080) @@ -13,7 +13,7 @@ register "enable_usb" = "0" register "enable_native_ide" = "0" device pci 1f.0 on - chip superio/winbond/w83627thf # link 1 + chip superio/winbond/w83627thg # link 1 device pnp 2e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -37,7 +37,6 @@ irq 0x70 = 1 irq 0x72 = 12 end - device pnp 2e.6 off end # CIR device pnp 2e.7 off end # GAME_MIDI_GIPO1 device pnp 2e.8 off end # GPIO2 device pnp 2e.9 off end # GPIO3 Modified: trunk/src/mainboard/lanner/em8510/romstage.c ============================================================================== --- trunk/src/mainboard/lanner/em8510/romstage.c Tue Nov 16 23:15:09 2010 (r6079) +++ trunk/src/mainboard/lanner/em8510/romstage.c Wed Nov 17 00:15:37 2010 (r6080) @@ -34,11 +34,11 @@ #include "southbridge/intel/i82801dx/i82801dx_early_smbus.c" #include "northbridge/intel/i855/raminit.h" #include "northbridge/intel/i855/debug.c" -#include "superio/winbond/w83627thf/w83627thf_early_serial.c" +#include "superio/winbond/w83627thg/w83627thg_early_serial.c" #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" -#define SERIAL_DEV PNP_DEV(0x2e, W83627THF_SP1) +#define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) static inline int spd_read_byte(unsigned device, unsigned address) { @@ -65,7 +65,7 @@ #endif } - w83627thf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); Modified: trunk/src/mainboard/msi/ms7135/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms7135/Kconfig Tue Nov 16 23:15:09 2010 (r6079) +++ trunk/src/mainboard/msi/ms7135/Kconfig Wed Nov 17 00:15:37 2010 (r6080) @@ -7,7 +7,7 @@ select NORTHBRIDGE_AMD_AMDK8 select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX select SOUTHBRIDGE_NVIDIA_CK804 - select SUPERIO_WINBOND_W83627THF + select SUPERIO_WINBOND_W83627THG select HAVE_BUS_CONFIG select HAVE_HARD_RESET select HAVE_OPTION_TABLE Modified: trunk/src/mainboard/msi/ms7135/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms7135/devicetree.cb Tue Nov 16 23:15:09 2010 (r6079) +++ trunk/src/mainboard/msi/ms7135/devicetree.cb Wed Nov 17 00:15:37 2010 (r6080) @@ -11,7 +11,7 @@ chip southbridge/nvidia/ck804 # Southbridge device pci 0.0 on end # HT device pci 1.0 on # LPC - chip superio/winbond/w83627thf # Super I/O + chip superio/winbond/w83627thg # Super I/O device pnp 4e.0 on # Floppy io 0x60 = 0x3f0 irq 0x70 = 6 @@ -30,14 +30,13 @@ io 0x60 = 0x2f8 irq 0x70 = 3 end - device pnp 4e.5 on # PS/2 keyboard + device pnp 4e.5 on # PS/2 keyboard & mouse io 0x60 = 0x60 io 0x62 = 0x64 irq 0x70 = 1 irq 0x72 = 12 end - device pnp 4e.6 off end # XXX keep allocator happy - device pnp 4e.7 off end # Game, MIDI, GPIO 1, GPIO 5 + device pnp 4e.7 off end # Game port, MIDI, GPIO 1 & 5 device pnp 4e.8 off end # GPIO 2 device pnp 4e.9 off end # GPIO 3, GPIO 4 device pnp 4e.a off end # ACPI Modified: trunk/src/mainboard/msi/ms7135/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7135/romstage.c Tue Nov 16 23:15:09 2010 (r6079) +++ trunk/src/mainboard/msi/ms7135/romstage.c Wed Nov 17 00:15:37 2010 (r6080) @@ -22,7 +22,7 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SERIAL_DEV PNP_DEV(0x4e, W83627THF_SP1) +#define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) #if CONFIG_LOGICAL_CPUS == 1 #define SET_NB_CFG_54 1 @@ -38,7 +38,7 @@ #include <pc80/mc146818rtc.h> #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -#include "superio/winbond/w83627thf/w83627thf_early_serial.c" +#include "superio/winbond/w83627thg/w83627thg_early_serial.c" #include <cpu/amd/model_fxx_rev.h> #include <console/console.h> @@ -123,7 +123,7 @@ bsp_apicid = init_cpus(cpu_init_detectedx); } - w83627thf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + w83627thg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); Modified: trunk/src/superio/winbond/Kconfig ============================================================================== --- trunk/src/superio/winbond/Kconfig Tue Nov 16 23:15:09 2010 (r6079) +++ trunk/src/superio/winbond/Kconfig Wed Nov 17 00:15:37 2010 (r6080) @@ -4,8 +4,6 @@ bool config SUPERIO_WINBOND_W83627HF bool -config SUPERIO_WINBOND_W83627THF - bool config SUPERIO_WINBOND_W83627THG bool config SUPERIO_WINBOND_W83627UHG Modified: trunk/src/superio/winbond/Makefile.inc ============================================================================== --- trunk/src/superio/winbond/Makefile.inc Tue Nov 16 23:15:09 2010 (r6079) +++ trunk/src/superio/winbond/Makefile.inc Wed Nov 17 00:15:37 2010 (r6080) @@ -1,7 +1,6 @@ subdirs-y += w83627dhg subdirs-y += w83627ehg subdirs-y += w83627hf -subdirs-y += w83627thf subdirs-y += w83627thg subdirs-y += w83627uhg subdirs-y += w83697hf

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Fwd: [PATCH 0/3] i855 support
by Idwer Vollering 16 Nov '10

16 Nov '10

Forwarding this to the list, for reference/proof: ---------- Forwarded message ---------- From: Andreas Schultz <aschultz(a)tpip.net> Date: 2010/8/31 Subject: Re: [coreboot] [PATCH 0/3] i855 support To: Idwer Vollering <vidwer(a)gmail.com> Hi, Attached is the serial output and the configuration i used. However, there seems to be nothing in the log that would refer to any CPU specifics. Andreas On Tue, 2010-08-31 at 02:41 +0200, Idwer Vollering wrote: > 2010/8/30 Andreas Schultz <aschultz(a)tpip.net> > Hi, > > Here is a series of patches wich improve i855 support and a > new board > with that chipset. > > The board boots successfully with Seabios into Linux! > Nice work. Can you show the output from the console (serial output) ? > > Off topic: I'm asking this because I own a P4 CPU, with the CPU id > 0x0f29 (ergo it's not a Celeron M), that I can't get to start using > CAR. Different but similar chipset:Intel i865. > > > There are still a few blacks left to filled in (undocumented > chipset > registers, some RAM parameters i have no idea how to compute). > So any > comment is welcome! > > Regards > Andreas -- Dipl. Inform. Andreas Schultz email: as(a)travelping.com phone: +49-391-819099-224 mobil: +49-170-2226073 ------------------ managed broadband access ------------------ Travelping GmbH phone: +49-391-8190990 Roentgenstr. 13 fax: +49-391-819099299 D-39108 Magdeburg email: info(a)travelping.com GERMANY web: http://www.travelping.com Company Registration: Amtsgericht Stendal Reg No.: HRB 10578 Geschaeftsfuehrer: Holger Winkelmann | VAT ID No.: DE236673780 --------------------------------------------------------------

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coreboot November 2010