coreboot November 2010

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[commit] r6079 - in trunk/src/mainboard: intel/truxton msi/ms7260
by repository service 16 Nov '10

16 Nov '10

Author: oxygene Date: Tue Nov 16 23:15:09 2010 New Revision: 6079 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6079 Log: Drop commented out debug defines Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/src/mainboard/intel/truxton/romstage.c trunk/src/mainboard/msi/ms7260/romstage.c Modified: trunk/src/mainboard/intel/truxton/romstage.c ============================================================================== --- trunk/src/mainboard/intel/truxton/romstage.c Tue Nov 16 23:10:55 2010 (r6078) +++ trunk/src/mainboard/intel/truxton/romstage.c Tue Nov 16 23:15:09 2010 (r6079) @@ -51,8 +51,6 @@ #include "../../intel/jarrell/debug.c" #include "arch/i386/lib/stages.c" -/* #define TRUXTON_DEBUG */ - #define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1) static void main(unsigned long bist) Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Tue Nov 16 23:10:55 2010 (r6078) +++ trunk/src/mainboard/msi/ms7260/romstage.c Tue Nov 16 23:15:09 2010 (r6079) @@ -20,10 +20,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -// #define RAM_TIMING_DEBUG 1 -// #define DQS_TRAIN_DEBUG 1 -// #define RES_DEBUG 1 - #if CONFIG_LOGICAL_CPUS == 1 #define SET_NB_CFG_54 1 #endif

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[commit] r6078 - trunk/src/mainboard/asus/m2v
by repository service 16 Nov '10

16 Nov '10

Author: oxygene Date: Tue Nov 16 23:10:55 2010 New Revision: 6078 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6078 Log: Forgot to remove one set of SET_FIDVID defines Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/src/mainboard/asus/m2v/romstage.c Modified: trunk/src/mainboard/asus/m2v/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v/romstage.c Tue Nov 16 22:25:29 2010 (r6077) +++ trunk/src/mainboard/asus/m2v/romstage.c Tue Nov 16 23:10:55 2010 (r6078) @@ -24,12 +24,6 @@ unsigned int get_sbdn(unsigned bus); -/* Used by init_cpus and fidvid */ -#define SET_FIDVID 1 - -/* If we want to wait for core1 done before DQS training, set it to 0. */ -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif

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[PATCH]Move SET_FIDVID to Kconfig
by Patrick Georgi 16 Nov '10

16 Nov '10

Hi, I updated the SET_FIDVID patch to match the current tree, and also validated it against the pre-patch tree. To do this, I added to src/cpu/amd/model_*xx/fidvid.c a bunch of #if SET_FIDVID #warning SET_FIDVID #endif style blocks to the pre-patch tree, for all SET_FIDVID* flags, and with CONFIG_ prefix to the patched tree, and ran abuild. After that, I mangled all coreboot-builds/*/make.log to drop the CONFIG_ prefixes and other minor differences (line numbers of the warnings/errors), and diffed the result of both trees. This exposed one configuration change in gigabyte/ma78gm, which I fixed. All boards now show identical configuration with and without this patch. == Move the SET_FIDVID* family of configuration options to Kconfig and make their defaults more obvious. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>

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[commit] r6077 - in trunk/src: cpu/amd/model_10xxx cpu/amd/model_fxx mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/serengeti_cheeta...
by repository service 16 Nov '10

16 Nov '10

Author: oxygene Date: Tue Nov 16 22:25:29 2010 New Revision: 6077 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6077 Log: Move the SET_FIDVID* family of configuration options to Kconfig and make their defaults more obvious. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Stefan Reinauer <stepan(a)coreboot.org> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/cpu/amd/model_10xxx/Kconfig trunk/src/cpu/amd/model_10xxx/fidvid.c trunk/src/cpu/amd/model_10xxx/init_cpus.c trunk/src/cpu/amd/model_fxx/Kconfig trunk/src/cpu/amd/model_fxx/fidvid.c trunk/src/cpu/amd/model_fxx/init_cpus.c trunk/src/mainboard/amd/dbm690t/Kconfig trunk/src/mainboard/amd/dbm690t/romstage.c trunk/src/mainboard/amd/mahogany/Kconfig trunk/src/mainboard/amd/mahogany/romstage.c trunk/src/mainboard/amd/mahogany_fam10/romstage.c trunk/src/mainboard/amd/pistachio/Kconfig trunk/src/mainboard/amd/pistachio/romstage.c trunk/src/mainboard/amd/serengeti_cheetah/romstage.c trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c trunk/src/mainboard/amd/tilapia_fam10/romstage.c trunk/src/mainboard/asrock/939a785gmh/Kconfig trunk/src/mainboard/asrock/939a785gmh/romstage.c trunk/src/mainboard/asus/a8v-e_deluxe/Kconfig trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c trunk/src/mainboard/asus/a8v-e_se/Kconfig trunk/src/mainboard/asus/a8v-e_se/romstage.c trunk/src/mainboard/asus/m2v-mx_se/Kconfig trunk/src/mainboard/asus/m2v-mx_se/romstage.c trunk/src/mainboard/asus/m2v/Kconfig trunk/src/mainboard/asus/m4a785-m/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/Kconfig trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/gigabyte/ma785gmt/romstage.c trunk/src/mainboard/gigabyte/ma78gm/romstage.c trunk/src/mainboard/hp/dl145_g3/Kconfig trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/jetway/pa78vm5/romstage.c trunk/src/mainboard/kontron/kt690/Kconfig trunk/src/mainboard/kontron/kt690/romstage.c trunk/src/mainboard/msi/ms7260/Kconfig trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9185/Kconfig trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/msi/ms9282/romstage.c trunk/src/mainboard/msi/ms9652_fam10/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/supermicro/h8dme/Kconfig trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/Kconfig trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c trunk/src/mainboard/technexion/tim5690/Kconfig trunk/src/mainboard/technexion/tim5690/romstage.c trunk/src/mainboard/technexion/tim8690/Kconfig trunk/src/mainboard/technexion/tim8690/romstage.c trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/mainboard/tyan/s2912_fam10/romstage.c Modified: trunk/src/cpu/amd/model_10xxx/Kconfig ============================================================================== --- trunk/src/cpu/amd/model_10xxx/Kconfig Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/cpu/amd/model_10xxx/Kconfig Tue Nov 16 22:25:29 2010 (r6077) @@ -4,27 +4,50 @@ select SSE select SSE2 +if CPU_AMD_MODEL_10XXX config CPU_ADDR_BITS int default 48 - depends on CPU_AMD_MODEL_10XXX config DCACHE_RAM_BASE hex default 0xc4000 - depends on CPU_AMD_MODEL_10XXX config DCACHE_RAM_SIZE hex default 0x0c000 - depends on CPU_AMD_MODEL_10XXX config DCACHE_RAM_GLOBAL_VAR_SIZE hex default 0x04000 - depends on CPU_AMD_MODEL_10XXX config UDELAY_IO bool default n - depends on CPU_AMD_MODEL_10XXX + +config SET_FIDVID + bool + default y + +if SET_FIDVID +config SET_FIDVID_DEBUG + bool + default y + +config SET_FIDVID_STORE_AP_APICID_AT_FIRST + bool + default y + +config SET_FIDVID_CORE0_ONLY + bool + default n + +# 0: all cores +# 1: core 0 only +# 2: all but core 0 +config SET_FIDVID_CORE_RANGE + int + default 0 + +endif +endif Modified: trunk/src/cpu/amd/model_10xxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/fidvid.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/cpu/amd/model_10xxx/fidvid.c Tue Nov 16 22:25:29 2010 (r6077) @@ -17,31 +17,26 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID #include <northbridge/amd/amdht/AsPsDefs.h> -#define SET_FIDVID_DEBUG 1 - -// if we are tight of CAR stack, disable it -#define SET_FIDVID_STORE_AP_APICID_AT_FIRST 1 - static inline void print_debug_fv(const char *str, u32 val) { -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG printk(BIOS_DEBUG, "%s%x\n", str, val); #endif } static inline void print_debug_fv_8(const char *str, u8 val) { -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG printk(BIOS_DEBUG, "%s%02x\n", str, val); #endif } static inline void print_debug_fv_64(const char *str, u32 val, u32 val2) { -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); #endif } @@ -729,7 +724,7 @@ } -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST struct ap_apicid_st { u32 num; // it could use 256 bytes for 64 node quad core system @@ -748,7 +743,7 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes) { -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST struct ap_apicid_st ap_apicidx; u32 i; #endif @@ -806,20 +801,20 @@ fv.common_fid = (nb_cof_vid_update << 16) | (fid_max << 8); print_debug_fv("BSP fid = ", fv.common_fid); -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 && SET_FIDVID_CORE0_ONLY == 0 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST && !CONFIG_SET_FIDVID_CORE0_ONLY /* For all APs (We know the APIC ID of all APs even when the APIC ID is lifted) remote read from AP LAPIC_MSG_REG about max fid. Then calculate the common max fid that can be used for all APs and BSP */ ap_apicidx.num = 0; - for_each_ap(bsp_apicid, SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx); + for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE_RANGE, store_ap_apicid, &ap_apicidx); for (i = 0; i < ap_apicidx.num; i++) { init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv); } #else - for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); + for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); #endif print_debug_fv("common_fid = ", fv.common_fid); Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_10xxx/init_cpus.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Tue Nov 16 22:25:29 2010 (r6077) @@ -28,17 +28,6 @@ #include <cpu/x86/mtrr/earlymtrr.c> #include <northbridge/amd/amdfam10/raminit_amdmct.c> -//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID -#ifndef SET_FIDVID - #define SET_FIDVID 1 -#endif - -#ifndef SET_FIDVID_CORE0_ONLY - /* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, - Need to do every AP to set common FID/VID */ - #define SET_FIDVID_CORE0_ONLY 0 -#endif - static void prep_fid_change(void); static void init_fidvid_stage2(u32 apicid, u32 nodeid); void cpuSetAMDMSR(void); @@ -166,7 +155,7 @@ return result; } -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid); #endif @@ -338,8 +327,8 @@ update_microcode(cpuid_eax(1)); cpuSetAMDMSR(); -#if SET_FIDVID == 1 -#if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1) +#if CONFIG_SET_FIDVID +#if (CONFIG_LOGICAL_CPUS == 1) && CONFIG_SET_FIDVID_CORE0_ONLY // Run on all AP for proper FID/VID setup. if (id.coreid == 0) // only need set fid for core0 #endif @@ -928,7 +917,7 @@ cpuSetAMDPCI(i); } -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID // Prep each node for FID/VID setup. prep_fid_change(); #endif Modified: trunk/src/cpu/amd/model_fxx/Kconfig ============================================================================== --- trunk/src/cpu/amd/model_fxx/Kconfig Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/cpu/amd/model_fxx/Kconfig Tue Nov 16 22:25:29 2010 (r6077) @@ -4,7 +4,31 @@ select SSE select SSE2 +if CPU_AMD_MODEL_FXX config UDELAY_IO bool default n - depends on CPU_AMD_MODEL_FXX + +config SET_FIDVID + bool + default n + default y if K8_REV_F_SUPPORT + +if SET_FIDVID +config SET_FIDVID_DEBUG + bool + default n + +config SET_FIDVID_CORE0_ONLY + bool + default y + +config SET_FIDVID_ONE_BY_ONE + bool + default y + +config SET_FIDVID_STORE_AP_APICID_AT_FIRST + bool + default y +endif +endif Modified: trunk/src/cpu/amd/model_fxx/fidvid.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/fidvid.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/cpu/amd/model_fxx/fidvid.c Tue Nov 16 22:25:29 2010 (r6077) @@ -1,10 +1,4 @@ -#if SET_FIDVID == 1 - -#define SET_FIDVID_DEBUG 0 - -#define SET_FIDVID_ONE_BY_ONE 1 - -#define SET_FIDVID_STORE_AP_APICID_AT_FIRST 1 +#if CONFIG_SET_FIDVID #ifndef SB_VFSMAF #define SB_VFSMAF 1 @@ -14,21 +8,21 @@ static inline void print_debug_fv(const char *str, u32 val) { -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG printk(BIOS_DEBUG, "%s%x\n", str, val); #endif } static inline void print_debug_fv_8(const char *str, u8 val) { -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG printk(BIOS_DEBUG, "%s%02x\n", str, val); #endif } static inline void print_debug_fv_64(const char *str, u32 val, u32 val2) { -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2); #endif } @@ -70,7 +64,7 @@ } } -#if SET_FIDVID_ONE_BY_ONE == 0 +#if !CONFIG_SET_FIDVID_ONE_BY_ONE static unsigned set_fidvid_without_init(unsigned fidvid) { msr_t msr; @@ -276,7 +270,7 @@ ldtstop_sb(); #endif -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG if (showmessage) { print_debug_fv_8("set_fidvid APICID = ", apicid); print_debug_fv_64("fidvid ctrl msr ", msr.hi, msr.lo); @@ -290,7 +284,7 @@ } fid_cur = msr.lo & 0x3f; -#if SET_FIDVID_DEBUG == 1 +#if CONFIG_SET_FIDVID_DEBUG if (showmessage) { print_debug_fv_64("fidvid status msr ", msr.hi, msr.lo); } @@ -368,7 +362,7 @@ send |= ((msr.hi >> (48 - 32)) & 0x3f) << 16; /* max vid */ send |= (apicid << 24); /* ap apicid */ -#if SET_FIDVID_ONE_BY_ONE == 1 +#if CONFIG_SET_FIDVID_ONE_BY_ONE vid_cur = msr.hi & 0x3f; fid_cur = msr.lo & 0x3f; @@ -399,7 +393,7 @@ } if (loop > 0) { -#if SET_FIDVID_ONE_BY_ONE == 1 +#if CONFIG_SET_FIDVID_ONE_BY_ONE readback = set_fidvid(apicid, readback & 0xffff00, 1); // this AP #else readback = set_fidvid_without_init(readback & 0xffff00); // this AP @@ -502,7 +496,7 @@ print_debug_fv("\treadback=", readback); } -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST struct ap_apicid_st { u32 num; unsigned apicid[16]; /* 8 way dual core need 16 */ @@ -524,7 +518,7 @@ struct fidvid_st fv; -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST struct ap_apicid_st ap_apicidx; unsigned i; #endif @@ -551,16 +545,16 @@ /* calculate the common max fid/vid that could be used for * all APs and BSP */ -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST ap_apicidx.num = 0; - for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, store_ap_apicid, &ap_apicidx); + for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, store_ap_apicid, &ap_apicidx); for (i = 0; i < ap_apicidx.num; i++) { init_fidvid_bsp_stage1(ap_apicidx.apicid[i], &fv); } #else - for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); + for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage1, &fv); #endif #if 0 @@ -587,7 +581,7 @@ #endif -#if SET_FIDVID_ONE_BY_ONE == 1 +#if CONFIG_SET_FIDVID_ONE_BY_ONE /* set BSP fid and vid */ print_debug_fv("bsp apicid=", bsp_apicid); fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1); @@ -601,15 +595,15 @@ fv.common_fidvid &= 0xffff00; /* set state 2 allow is in init_fidvid_bsp_stage2 */ -#if SET_FIDVID_STORE_AP_APICID_AT_FIRST == 1 +#if CONFIG_SET_FIDVID_STORE_AP_APICID_AT_FIRST for (i = 0; i < ap_apicidx.num; i++) { init_fidvid_bsp_stage2(ap_apicidx.apicid[i], &fv); } #else - for_each_ap(bsp_apicid, SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv); + for_each_ap(bsp_apicid, CONFIG_SET_FIDVID_CORE0_ONLY, init_fidvid_bsp_stage2, &fv); #endif -#if SET_FIDVID_ONE_BY_ONE == 0 +#if !CONFIG_SET_FIDVID_ONE_BY_ONE /* set BSP fid and vid */ print_debug_fv("bsp apicid=", bsp_apicid); fv.common_fidvid = set_fidvid(bsp_apicid, fv.common_fidvid, 1); Modified: trunk/src/cpu/amd/model_fxx/init_cpus.c ============================================================================== --- trunk/src/cpu/amd/model_fxx/init_cpus.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/cpu/amd/model_fxx/init_cpus.c Tue Nov 16 22:25:29 2010 (r6077) @@ -2,22 +2,6 @@ #include "option_table.h" #endif -//it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID -#ifndef SET_FIDVID -#if CONFIG_K8_REV_F_SUPPORT == 0 - #define SET_FIDVID 0 -#else - // for rev F, need to set FID to max - #define SET_FIDVID 1 -#endif - -#endif - -#ifndef SET_FIDVID_CORE0_ONLY - /* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, so may don't need to do twice */ - #define SET_FIDVID_CORE0_ONLY 1 -#endif - typedef void (*process_ap_t) (u32 apicid, void *gp); //core_range = 0 : all cores @@ -135,7 +119,7 @@ #define LAPIC_MSG_REG 0x380 -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID static void init_fidvid_ap(u32 bsp_apicid, u32 apicid); #endif @@ -291,8 +275,8 @@ u32 timeout = 1; u32 loop = 100; -#if SET_FIDVID == 1 -#if (CONFIG_LOGICAL_CPUS == 1) && (SET_FIDVID_CORE0_ONLY == 1) +#if CONFIG_SET_FIDVID +#if (CONFIG_LOGICAL_CPUS == 1) && CONFIG_SET_FIDVID_CORE0_ONLY if (id.coreid == 0) // only need set fid for core0 #endif init_fidvid_ap(bsp_apicid, apicid); Modified: trunk/src/mainboard/amd/dbm690t/Kconfig ============================================================================== --- trunk/src/mainboard/amd/dbm690t/Kconfig Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/amd/dbm690t/Kconfig Tue Nov 16 22:25:29 2010 (r6077) @@ -22,6 +22,7 @@ select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string Modified: trunk/src/mainboard/amd/dbm690t/romstage.c ============================================================================== --- trunk/src/mainboard/amd/dbm690t/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/amd/dbm690t/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SET_FIDVID 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif Modified: trunk/src/mainboard/amd/mahogany/Kconfig ============================================================================== --- trunk/src/mainboard/amd/mahogany/Kconfig Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/amd/mahogany/Kconfig Tue Nov 16 22:25:29 2010 (r6077) @@ -25,6 +25,7 @@ select RAMINIT_SYSINFO select GFXUMA select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string Modified: trunk/src/mainboard/amd/mahogany/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/amd/mahogany/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SET_FIDVID 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -27,10 +27,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -196,7 +192,7 @@ rs780_early_setup(); sb700_early_setup(); - #if SET_FIDVID == 1 + #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); Modified: trunk/src/mainboard/amd/pistachio/Kconfig ============================================================================== --- trunk/src/mainboard/amd/pistachio/Kconfig Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/amd/pistachio/Kconfig Tue Nov 16 22:25:29 2010 (r6077) @@ -22,6 +22,7 @@ select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string Modified: trunk/src/mainboard/amd/pistachio/romstage.c ============================================================================== --- trunk/src/mainboard/amd/pistachio/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/amd/pistachio/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SET_FIDVID 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -1,10 +1,5 @@ #define SET_NB_CFG_54 1 -//used by init_cpus and fidvid -#define SET_FIDVID 0 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -150,7 +145,7 @@ int needs_reset; unsigned bsp_apicid = 0; -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID struct cpuid_result cpuid1; #endif @@ -214,7 +209,7 @@ needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ cpuid1 = cpuid(0x80000007); Modified: trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -27,10 +27,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -195,7 +191,7 @@ post_code(0x38); - #if SET_FIDVID == 1 + #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); Modified: trunk/src/mainboard/amd/tilapia_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/amd/tilapia_fam10/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -27,10 +27,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -196,7 +192,7 @@ rs780_early_setup(); sb700_early_setup(); - #if SET_FIDVID == 1 + #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); Modified: trunk/src/mainboard/asrock/939a785gmh/Kconfig ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/Kconfig Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/asrock/939a785gmh/Kconfig Tue Nov 16 22:25:29 2010 (r6077) @@ -25,6 +25,7 @@ select GFXUMA select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string Modified: trunk/src/mainboard/asrock/939a785gmh/romstage.c ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/asrock/939a785gmh/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -18,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SET_FIDVID 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif Modified: trunk/src/mainboard/asus/a8v-e_deluxe/Kconfig ============================================================================== --- trunk/src/mainboard/asus/a8v-e_deluxe/Kconfig Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/asus/a8v-e_deluxe/Kconfig Tue Nov 16 22:25:29 2010 (r6077) @@ -17,6 +17,7 @@ select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string Modified: trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/asus/a8v-e_deluxe/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -24,12 +24,6 @@ unsigned int get_sbdn(unsigned bus); -/* Used by init_cpus and fidvid */ -#define SET_FIDVID 1 - -/* If we want to wait for core1 done before DQS training, set it to 0. */ -#define SET_FIDVID_CORE0_ONLY 1 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/asus/a8v-e_se/Kconfig ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/Kconfig Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/asus/a8v-e_se/Kconfig Tue Nov 16 22:25:29 2010 (r6077) @@ -17,6 +17,7 @@ select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string Modified: trunk/src/mainboard/asus/a8v-e_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/asus/a8v-e_se/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -24,12 +24,6 @@ unsigned int get_sbdn(unsigned bus); -/* Used by init_cpus and fidvid */ -#define SET_FIDVID 1 - -/* If we want to wait for core1 done before DQS training, set it to 0. */ -#define SET_FIDVID_CORE0_ONLY 1 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/asus/m2v-mx_se/Kconfig ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/Kconfig Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/asus/m2v-mx_se/Kconfig Tue Nov 16 22:25:29 2010 (r6077) @@ -37,6 +37,7 @@ select TINY_BOOTBLOCK select HAVE_MAINBOARD_RESOURCES select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string Modified: trunk/src/mainboard/asus/m2v-mx_se/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m2v-mx_se/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/asus/m2v-mx_se/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -24,12 +24,6 @@ unsigned int get_sbdn(unsigned bus); -/* Used by init_cpus and fidvid */ -#define SET_FIDVID 1 - -/* If we want to wait for core1 done before DQS training, set it to 0. */ -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif Modified: trunk/src/mainboard/asus/m2v/Kconfig ============================================================================== --- trunk/src/mainboard/asus/m2v/Kconfig Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/asus/m2v/Kconfig Tue Nov 16 22:25:29 2010 (r6077) @@ -20,6 +20,7 @@ select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES select HAVE_MP_TABLE + select SET_FIDVID config MAINBOARD_DIR string Modified: trunk/src/mainboard/asus/m4a785-m/romstage.c ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/asus/m4a785-m/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -27,10 +27,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -197,7 +193,7 @@ rs780_early_setup(); sb700_early_setup(); - #if SET_FIDVID == 1 + #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig Tue Nov 16 22:25:29 2010 (r6077) @@ -21,6 +21,7 @@ select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT select K8_ALLOCATE_IO_RANGE + select SET_FIDVID config MAINBOARD_DIR string Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -25,11 +25,6 @@ #define SET_NB_CFG_54 1 #endif -//used by init_cpus and fidvid -#define SET_FIDVID 1 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -212,7 +207,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; Modified: trunk/src/mainboard/gigabyte/m57sli/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/Kconfig Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/gigabyte/m57sli/Kconfig Tue Nov 16 22:25:29 2010 (r6077) @@ -25,6 +25,7 @@ select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT select K8_ALLOCATE_IO_RANGE + select SET_FIDVID config MAINBOARD_DIR string Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -23,11 +23,6 @@ #define SET_NB_CFG_54 1 #endif -//used by init_cpus and fidvid -#define SET_FIDVID 1 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -223,7 +218,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; Modified: trunk/src/mainboard/gigabyte/ma785gmt/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/gigabyte/ma785gmt/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -23,10 +23,6 @@ #define SET_NB_CFG_54 1 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -192,7 +188,7 @@ rs780_early_setup(); sb700_early_setup(); - #if SET_FIDVID == 1 + #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); Modified: trunk/src/mainboard/gigabyte/ma78gm/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/gigabyte/ma78gm/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -27,10 +27,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -195,7 +191,7 @@ rs780_early_setup(); sb700_early_setup(); - #if SET_FIDVID == 1 + #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); Modified: trunk/src/mainboard/hp/dl145_g3/Kconfig ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/Kconfig Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/hp/dl145_g3/Kconfig Tue Nov 16 22:25:29 2010 (r6077) @@ -23,6 +23,7 @@ select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT select K8_ALLOCATE_IO_RANGE + select SET_FIDVID config MAINBOARD_DIR string Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -29,11 +29,6 @@ #define SET_NB_CFG_54 1 #endif -//used by init_cpus and fidvid -#define SET_FIDVID 1 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -229,7 +224,7 @@ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn bcm5785_early_setup(); -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; msr=rdmsr(0xc0010042); Modified: trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/hp/dl165_g6_fam10/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -33,9 +33,6 @@ #define SET_NB_CFG_54 1 #endif -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -187,7 +184,7 @@ wait_all_other_cores_started(bsp_apicid); #endif -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); Modified: trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/iei/kino-780am2-fam10/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -29,10 +29,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - /* UART address and device number */ #define SERIAL_DEV PNP_DEV(0x2e, F71859_SP1) @@ -201,7 +197,7 @@ rs780_early_setup(); sb700_early_setup(); - #if SET_FIDVID == 1 + #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -1,10 +1,5 @@ #define SET_NB_CFG_54 1 -//used by init_cpus and fidvid -#define SET_FIDVID 0 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -171,7 +166,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -1,10 +1,5 @@ #define SET_NB_CFG_54 1 -//used by init_cpus and fidvid -#define SET_FIDVID 0 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -171,7 +166,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -1,10 +1,5 @@ #define SET_NB_CFG_54 1 -//used by init_cpus and fidvid -#define SET_FIDVID 0 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -171,7 +166,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; Modified: trunk/src/mainboard/jetway/pa78vm5/romstage.c ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/jetway/pa78vm5/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -28,10 +28,6 @@ #define FAM10_SCAN_PCI_BUS 0 #define FAM10_ALLOCATE_IO_RANGE 0 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -204,7 +200,7 @@ rs780_early_setup(); sb700_early_setup(); - #if SET_FIDVID == 1 + #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); Modified: trunk/src/mainboard/kontron/kt690/Kconfig ============================================================================== --- trunk/src/mainboard/kontron/kt690/Kconfig Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/kontron/kt690/Kconfig Tue Nov 16 22:25:29 2010 (r6077) @@ -23,6 +23,7 @@ select RAMINIT_SYSINFO select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string Modified: trunk/src/mainboard/kontron/kt690/romstage.c ============================================================================== --- trunk/src/mainboard/kontron/kt690/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/kontron/kt690/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -18,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SET_FIDVID 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif Modified: trunk/src/mainboard/msi/ms7260/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms7260/Kconfig Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/msi/ms7260/Kconfig Tue Nov 16 22:25:29 2010 (r6077) @@ -23,6 +23,7 @@ select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT select K8_ALLOCATE_IO_RANGE + select SET_FIDVID config MAINBOARD_DIR string Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/msi/ms7260/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -28,12 +28,6 @@ #define SET_NB_CFG_54 1 #endif -/* Used by init_cpus and fidvid. */ -#define SET_FIDVID 1 - -/* If we want to wait for core1 done before DQS training, set it to 0. */ -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -201,7 +195,7 @@ /* Set up chains and store link pair for optimization later. */ ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr = rdmsr(0xc0010042); print_debug("begin msr fid, vid "); Modified: trunk/src/mainboard/msi/ms9185/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms9185/Kconfig Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/msi/ms9185/Kconfig Tue Nov 16 22:25:29 2010 (r6077) @@ -22,6 +22,7 @@ select RAMINIT_SYSINFO select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/msi/ms9185/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -25,11 +25,6 @@ #define SET_NB_CFG_54 1 -//used by init_cpus and fidvid -#define SET_FIDVID 1 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -201,7 +196,7 @@ needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; Modified: trunk/src/mainboard/msi/ms9282/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9282/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/msi/ms9282/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -24,12 +24,6 @@ #define SET_NB_CFG_54 1 -// used by init_cpus and fidvid (disabled until someone tests this) -// #define SET_FIDVID 1 -#define SET_FIDVID 0 -// if we want to wait for core1 done before DQS training, set it to 0 -// #define SET_FIDVID_CORE0_ONLY 1 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> Modified: trunk/src/mainboard/msi/ms9652_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/msi/ms9652_fam10/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -27,9 +27,6 @@ #define SET_NB_CFG_54 1 #endif -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -224,7 +221,7 @@ post_code(0x38); -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -23,11 +23,6 @@ #define SET_NB_CFG_54 1 #endif -//used by init_cpus and fidvid -#define SET_FIDVID 0 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -210,7 +205,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; Modified: trunk/src/mainboard/supermicro/h8dme/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/Kconfig Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/supermicro/h8dme/Kconfig Tue Nov 16 22:25:29 2010 (r6077) @@ -24,6 +24,7 @@ select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT select K8_ALLOCATE_IO_RANGE + select SET_FIDVID config MAINBOARD_DIR string Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -20,11 +20,6 @@ #define SET_NB_CFG_54 1 #endif -// used by init_cpus and fidvid -#define SET_FIDVID 1 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -269,7 +264,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; Modified: trunk/src/mainboard/supermicro/h8dmr/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/Kconfig Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/supermicro/h8dmr/Kconfig Tue Nov 16 22:25:29 2010 (r6077) @@ -23,6 +23,7 @@ select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT select K8_ALLOCATE_IO_RANGE + select SET_FIDVID config MAINBOARD_DIR string Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -23,11 +23,6 @@ #define SET_NB_CFG_54 1 #endif -//used by init_cpus and fidvid -#define SET_FIDVID 1 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -198,7 +193,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; msr=rdmsr(0xc0010042); Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -27,9 +27,6 @@ #define SET_NB_CFG_54 1 #endif -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -214,7 +211,7 @@ post_code(0x38); -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); Modified: trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -27,9 +27,6 @@ #define SET_NB_CFG_54 1 #endif -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -256,7 +253,7 @@ post_code(0x38); -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); Modified: trunk/src/mainboard/technexion/tim5690/Kconfig ============================================================================== --- trunk/src/mainboard/technexion/tim5690/Kconfig Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/technexion/tim5690/Kconfig Tue Nov 16 22:25:29 2010 (r6077) @@ -23,6 +23,7 @@ select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string Modified: trunk/src/mainboard/technexion/tim5690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim5690/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/technexion/tim5690/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SET_FIDVID 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif Modified: trunk/src/mainboard/technexion/tim8690/Kconfig ============================================================================== --- trunk/src/mainboard/technexion/tim8690/Kconfig Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/technexion/tim8690/Kconfig Tue Nov 16 22:25:29 2010 (r6077) @@ -22,6 +22,7 @@ select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select SET_FIDVID config MAINBOARD_DIR string Modified: trunk/src/mainboard/technexion/tim8690/romstage.c ============================================================================== --- trunk/src/mainboard/technexion/tim8690/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/technexion/tim8690/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -17,7 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define SET_FIDVID 1 #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/tyan/s2912/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -23,11 +23,6 @@ #define SET_NB_CFG_54 1 #endif -//used by init_cpus and fidvid -#define SET_FIDVID 0 -//if we want to wait for core1 done before DQS training, set it to 0 -#define SET_FIDVID_CORE0_ONLY 1 - #if CONFIG_K8_REV_F_SUPPORT == 1 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 #endif @@ -205,7 +200,7 @@ /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID { msr_t msr; Modified: trunk/src/mainboard/tyan/s2912_fam10/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/romstage.c Tue Nov 16 01:41:17 2010 (r6076) +++ trunk/src/mainboard/tyan/s2912_fam10/romstage.c Tue Nov 16 22:25:29 2010 (r6077) @@ -27,9 +27,6 @@ #define SET_NB_CFG_54 1 #endif -#define SET_FIDVID 1 -#define SET_FIDVID_CORE_RANGE 0 - #include <stdint.h> #include <string.h> #include <device/pci_def.h> @@ -216,7 +213,7 @@ post_code(0x38); -#if SET_FIDVID == 1 +#if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);

1 0

build service results for r6076
by repository service 16 Nov '10

16 Nov '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6076 to the coreboot repository. This caused the following changes: Change Log: back out parts of #6073 Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of intel:d945gclf has been fixed Compilation of intel:eagleheights has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

1 0

[commit] r6076 - in trunk/src/superio/smsc: lpc47m15x smscsuperio
by repository service 16 Nov '10

16 Nov '10

Author: stepan Date: Tue Nov 16 01:41:17 2010 New Revision: 6076 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6076 Log: back out parts of #6073 Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c trunk/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c Modified: trunk/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c ============================================================================== --- trunk/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c Mon Nov 15 22:09:57 2010 (r6075) +++ trunk/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c Tue Nov 16 01:41:17 2010 (r6076) @@ -34,7 +34,7 @@ outb(0xaa, port); } -static void lpc47m15x_enable_serial(device_t dev, u16 iobase) +static inline void lpc47m15x_enable_serial(device_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); Modified: trunk/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c ============================================================================== --- trunk/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c Mon Nov 15 22:09:57 2010 (r6075) +++ trunk/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c Tue Nov 16 01:41:17 2010 (r6076) @@ -33,7 +33,7 @@ * @param dev The device to use. * @param iobase The I/O base of the serial port (usually 0x3f8/0x2f8). */ -static void smscsuperio_enable_serial(device_t dev, u16 iobase) +static inline void smscsuperio_enable_serial(device_t dev, u16 iobase) { u16 port = dev >> 8;

1 0

Re: [coreboot] P4V800D-X need BIOS modification for PCI-E
by Tomasz Czapiewski 15 Nov '10

15 Nov '10

As requested on IRC I'm sending some logs... dmesg from P4V800D-X with inserted both AGP Radeon 9600 and (unrecognized) PCI-E Radeon HD4670: http://pastebin.com/8wx9JYBJ lspci -v -v from P4V800D-X (the same configuration as above): http://pastebin.com/qfbjNZ40 lshw: http://pastebin.com/PTdGwv0f ---------------------------------------------------------- dmesg from P4V800D-X with inserted both AGP Radeon 9600 and PCI-E Radeon X300 (both working configuration): http://pastebin.com/gtc5rvJW lshw: http://pastebin.com/wS7vS0xF lspci -v -v: http://pastebin.com/iRYGTCqL lspci -xxx: http://pastebin.com/Jv338DFR lspci -xxxx: http://pastebin.com/rdjTZtxP ---------------------------------------------------------- In next mail I'll send logs from other working PC with Radeon HD4670 card which didn't work on my P4V800D-X. With Regards, Tom ---------- Forwarded message ---------- Date: Sun, 14 Nov 2010 22:53:06 +0100 (CET) From: Tomasz Czapiewski <xeros(a)irc.pl> To: coreboot(a)coreboot.org Cc: flashrom(a)flashrom.org Subject: P4V800D-X need BIOS modification for PCI-E Hi, I've been told at Phoronix forums few months ago that you can help solve my problem as you really do miracles with BIOS. The problem is that I have Asus P4V800D-X mainboard from few years which has Via PT880Ultra chipset. The mainboard is for Intel Pentium4 with socket 478 and DDR1 and has two graphic slots (AGP x8 and PCI-E 1.0). OT: The MP spec tells it could not handle both cards but I use both Radeons R3xx (AGP RV350 - 9600 and PCI-E RV370 - x300 in multiseat) just fine althrough before doing kernel mode settings on Linux I can see BIOS POST only on one of them but that's not the case... Back to topic... Some time ago I've get PCI-E 2.0 Radeon HD4670 which I wanted to use as a replace for PCI-E 1.0 Radeon X300 and I've saw it runs without problems on different MB but with the same chipset (Asrock 775Dual-VSTA - only PCI-E without AGP, P4/DualCore socket 775, both DDR1 and DDR2) after BIOS upgrade served by Asrock. I've found that the card I've get does couply PCI-E 1.0 power requirements specs so it really should be possible to use it on PCI-E 1.0 MBs. When I put this card in PCI-E slot of my MB BIOS and even Linux after BOOT does not see that anything is put in PCI-E slot (lspci, lshw, etc... does not show anything related to this card). I know that CoreBoot site does not list any of MBs that contain such chipset so I'm still stuck with proprietary BIOS from my MB vendor. As I've said before Asrock did release BIOS updates for it's MB with fixes for Radeon HD2xxx and HD3xxx cards (althrough some people reported that after this BIOS update Radeon HD4670 works, too) but Asus did forget about P4V800D-X users long time ago and haven't released and wont release such fixes. I know it will be very hard but could you look at Asrock 775Dual-VSTA BIOS changes (last BIOSes contain only fixes for Radeon HD3xxx cards) and somekind use it for fix my Asus P4V800D-X BIOS to support such cards? I don't even imagine how would you do this but anyway I've get here to ask for help as you're the only people who could do something like this. Thanks in advance. Asus P4V800D-X spec: http://motherboardland.blogspot.com/2006/01/asus-p4v800d-x-motherboard.html Asus P4V800D-X user guide: ftp://ftp.asus.com.tw/pub/ASUS/mb/sock478/p4v800d-x/e2221_P4V800D-X.pdf Asus P4V800D-X BIOS: http://dlcdnet.asus.com/pub/ASUS/mb/sock478/p4v800d-x/P4V8D704.zip Asrock 775Dual-VSTA spec: http://www.asrock.com/mb/overview.asp?Model=775Dual-vsta Asrock 775Dual-VSTA user guide: http://europe.asrock.com/manual/775Dual-VSTA.pdf Asrock 775Dual-VSTA BIOSes with changelogs: http://www.asrock.com/mb/download.asp?Model=775Dual-VSTA&o=BIOS Btw. I don't have EEPROM/BIOS programmer/flasher and my MB has only one BIOS so if you would do that BIOS modifications will flashing it will be a lot more risky than flashing any other official BIOSes? I don't mind if after flashing for any reason I could get not video or sth that would just not break Linux boot from SATA HDD so I could SSH to my machine and flash original BIOS or any other not so hard to use fallback. I don't want to change MB for the next few years because of financial reasons as I have some hardware/peripherals which use could be problematic on never MBs like these two graphic cards, PCI analog TV card, some RS232 connected hardware, a lot of DDR1 RAM, etc. With Regards, Tom

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build service results for r6075
by repository service 15 Nov '10

15 Nov '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "stepan" checked in revision 6075 to the coreboot repository. This caused the following changes: Change Log: fix random breakage Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Build Log: Compilation of dell:s1850 has been fixed Compilation of getac:p470 has been fixed Compilation of intel:d945gclf is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6075&device=d945gclf&vendo… Compilation of intel:eagleheights is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6075&device=eagleheights&v… Compilation of jetway:pa78vm5 has been fixed Compilation of roda:rk886ex has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r6075 - in trunk: . src/mainboard/getac/p470/acpi src/mainboard/roda/rk886ex/acpi src/superio/fintek/f71863fg src/superio/nsc/pc8374
by repository service 15 Nov '10

15 Nov '10

Author: stepan Date: Mon Nov 15 22:09:57 2010 New Revision: 6075 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6075 Log: fix random breakage Signed-off-by: Stefan Reinauer <stepan(a)coresystems.de> Acked-by: Stefan Reinauer <stepan(a)coresystems.de> Modified: trunk/Makefile trunk/src/mainboard/getac/p470/acpi/superio.asl trunk/src/mainboard/roda/rk886ex/acpi/superio.asl trunk/src/superio/fintek/f71863fg/superio.c trunk/src/superio/nsc/pc8374/superio.c Modified: trunk/Makefile ============================================================================== --- trunk/Makefile Mon Nov 15 20:44:42 2010 (r6074) +++ trunk/Makefile Mon Nov 15 22:09:57 2010 (r6075) @@ -229,7 +229,7 @@ $(obj)/$(1).ramstage.o: src/$(1).asl @printf " IASL $$(subst $(top)/,,$$(@))\n" $(CPP) -D__ACPI__ -P -include $(abspath $(obj)/config.h) -I$(src) -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$(basename $$(a)).asl - iasl -p $$(obj)/$(1) -tc $$(basename $$(a)).asl > $$(basename $$(a)).asl.out + iasl -p $$(obj)/$(1) -tc $$(basename $$(a)).asl mv $$(obj)/$(1).hex $$(basename $$(a)).c $(CC) $$(CFLAGS) $$(if $$(subst dsdt,,$$(basename $$(notdir $(1)))), -DAmlCode=AmlCode_$$(basename $$(notdir $(1)))) -c -o $$@ $$(basename $$(a)).c # keep %.o: %.c rule from catching the temporary .c file after a make clean Modified: trunk/src/mainboard/getac/p470/acpi/superio.asl ============================================================================== --- trunk/src/mainboard/getac/p470/acpi/superio.asl Mon Nov 15 20:44:42 2010 (r6074) +++ trunk/src/mainboard/getac/p470/acpi/superio.asl Mon Nov 15 22:09:57 2010 (r6075) @@ -114,7 +114,7 @@ Method(_CRS, 0) { Name(NONE, ResourceTemplate() { - IO(Decode16, 0x000, 0x000, 0x0, 0x0) + IO(Decode16, 0x000, 0x000, 0x0, 0x1) IRQNoFlags() { } }) @@ -269,7 +269,7 @@ Method(_CRS, 0) { Name(NONE, ResourceTemplate() { - IO(Decode16, 0x000, 0x000, 0x0, 0x0) + IO(Decode16, 0x000, 0x000, 0x0, 0x1) IRQNoFlags() { } }) @@ -423,7 +423,7 @@ Method(_CRS, 0) { Name(NONE, ResourceTemplate() { - IO(Decode16, 0x000, 0x000, 0x0, 0x0) + IO(Decode16, 0x000, 0x000, 0x0, 0x1) IRQNoFlags() { } }) @@ -575,7 +575,7 @@ Method(_CRS, 0) { Name(NONE, ResourceTemplate() { - IO(Decode16, 0x000, 0x000, 0x0, 0x0) + IO(Decode16, 0x000, 0x000, 0x0, 0x1) IRQNoFlags() { } }) Modified: trunk/src/mainboard/roda/rk886ex/acpi/superio.asl ============================================================================== --- trunk/src/mainboard/roda/rk886ex/acpi/superio.asl Mon Nov 15 20:44:42 2010 (r6074) +++ trunk/src/mainboard/roda/rk886ex/acpi/superio.asl Mon Nov 15 22:09:57 2010 (r6075) @@ -116,7 +116,7 @@ Method(_CRS, 0) { Name(NONE, ResourceTemplate() { - IO(Decode16, 0x000, 0x000, 0x0, 0x0) + IO(Decode16, 0x000, 0x000, 0x0, 0x1) IRQNoFlags() { } }) @@ -275,7 +275,7 @@ Method(_CRS, 0) { Name(NONE, ResourceTemplate() { - IO(Decode16, 0x000, 0x000, 0x0, 0x0) + IO(Decode16, 0x000, 0x000, 0x0, 0x1) IRQNoFlags() { } }) Modified: trunk/src/superio/fintek/f71863fg/superio.c ============================================================================== --- trunk/src/superio/fintek/f71863fg/superio.c Mon Nov 15 20:44:42 2010 (r6074) +++ trunk/src/superio/fintek/f71863fg/superio.c Mon Nov 15 22:09:57 2010 (r6075) @@ -101,7 +101,7 @@ { &ops, F71863FG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, { &ops, F71863FG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, { &ops, F71863FG_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, }, - { &ops, F71863FG_GPIO, } + { &ops, F71863FG_GPIO, }, { &ops, F71863FG_VID, PNP_IO0, {0x07f8, 0}, }, { &ops, F71863FG_SPI, }, { &ops, F71863FG_PME, }, Modified: trunk/src/superio/nsc/pc8374/superio.c ============================================================================== --- trunk/src/superio/nsc/pc8374/superio.c Mon Nov 15 20:44:42 2010 (r6074) +++ trunk/src/superio/nsc/pc8374/superio.c Mon Nov 15 22:09:57 2010 (r6075) @@ -33,7 +33,7 @@ static void init(device_t dev) { - struct superio_nsc_pc8374_config *conf = dev�>chip_info; + struct superio_nsc_pc8374_config *conf = dev->chip_info; struct resource *res0; if (!dev->enabled)

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build service results for r6074
by repository service 15 Nov '10

15 Nov '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "oxygene" checked in revision 6074 to the coreboot repository. This caused the following changes: Change Log: Move RCBA defines to northbridge (instead of mainboard) Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Build Log: Compilation of dell:s1850 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6074&device=s1850&vendor=d… Compilation of getac:p470 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6074&device=p470&vendor=ge… Compilation of intel:d945gclf is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6074&device=d945gclf&vendo… Compilation of intel:eagleheights is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6074&device=eagleheights&v… Compilation of jetway:pa78vm5 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6074&device=pa78vm5&vendor… Compilation of roda:rk886ex is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6074&device=rk886ex&vendor… If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot November 2010