coreboot November 2010

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build service results for r6073
by repository service 15 Nov '10

15 Nov '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "uwe" checked in revision 6073 to the coreboot repository. This caused the following changes: Change Log: C and other Super I/O cosmetic fixes. - Random coding style, whitespace and cosmetic fixes. - Consistently use the same spacing and 4-hexdigit port number format in the pnp_dev_info[] arrays. - Drop dead/unused code and less useful comments. - Add missing "(C)" characters and copyright years. - Shorten and simplify some code snippets. - Use u8/u16/etc. everywhere. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Build Log: Compilation of dell:s1850 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6073&device=s1850&vendor=d… Compilation of getac:p470 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6073&device=p470&vendor=ge… Compilation of intel:d945gclf has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6073&device=d945gclf&vendo… Compilation of intel:eagleheights has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6073&device=eagleheights&v… Compilation of jetway:pa78vm5 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6073&device=pa78vm5&vendor… Compilation of roda:rk886ex has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=6073&device=rk886ex&vendor… If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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[commit] r6074 - in trunk/src: mainboard/intel/eagleheights northbridge/intel/i3100
by repository service 15 Nov '10

15 Nov '10

Author: oxygene Date: Mon Nov 15 20:44:42 2010 New Revision: 6074 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6074 Log: Move RCBA defines to northbridge (instead of mainboard) Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/src/mainboard/intel/eagleheights/romstage.c trunk/src/northbridge/intel/i3100/i3100.h Modified: trunk/src/mainboard/intel/eagleheights/romstage.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/romstage.c Mon Nov 15 20:35:14 2010 (r6073) +++ trunk/src/mainboard/intel/eagleheights/romstage.c Mon Nov 15 20:44:42 2010 (r6074) @@ -39,6 +39,7 @@ #include "reset.c" #include "superio/intel/i3100/i3100_early_serial.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" +#include "northbridge/intel/i3100/i3100.h" #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0) @@ -54,10 +55,6 @@ #define SATA_MODE_IDE 0x00 #define SATA_MODE_AHCI 0x01 -/* RCBA registers */ -#define RCBA 0xF0 -#define DEFAULT_RCBA 0xFEA00000 - #define RCBA_RPC 0x0224 /* 32 bit */ #define RCBA_TCTL 0x3000 /* 8 bit */ Modified: trunk/src/northbridge/intel/i3100/i3100.h ============================================================================== --- trunk/src/northbridge/intel/i3100/i3100.h Mon Nov 15 20:35:14 2010 (r6073) +++ trunk/src/northbridge/intel/i3100/i3100.h Mon Nov 15 20:44:42 2010 (r6074) @@ -64,6 +64,8 @@ #define DRC_NOECC_MODE (0 << 20) #define DRC_72BIT_ECC (1 << 20) +#define RCBA 0xF0 +#define DEFAULT_RCBA 0xFEA00000 #ifdef __GNUC__ int bios_reset_detected(void);

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[commit] r6073 - in trunk/src/superio: fintek/f71805f fintek/f71859 fintek/f71863fg fintek/f71872 fintek/f71889 intel/i3100 ite/it8661f ite/it8671f ite/it8673f ite/it8705f ite/it8712f ite/it8716f i...
by repository service 15 Nov '10

15 Nov '10

Author: uwe Date: Mon Nov 15 20:35:14 2010 New Revision: 6073 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6073 Log: C and other Super I/O cosmetic fixes. - Random coding style, whitespace and cosmetic fixes. - Consistently use the same spacing and 4-hexdigit port number format in the pnp_dev_info[] arrays. - Drop dead/unused code and less useful comments. - Add missing "(C)" characters and copyright years. - Shorten and simplify some code snippets. - Use u8/u16/etc. everywhere. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/superio/fintek/f71805f/superio.c trunk/src/superio/fintek/f71859/superio.c trunk/src/superio/fintek/f71863fg/superio.c trunk/src/superio/fintek/f71872/superio.c trunk/src/superio/fintek/f71889/superio.c trunk/src/superio/intel/i3100/superio.c trunk/src/superio/ite/it8661f/superio.c trunk/src/superio/ite/it8671f/superio.c trunk/src/superio/ite/it8673f/superio.c trunk/src/superio/ite/it8705f/superio.c trunk/src/superio/ite/it8712f/superio.c trunk/src/superio/ite/it8716f/superio.c trunk/src/superio/ite/it8718f/superio.c trunk/src/superio/nsc/pc8374/Makefile.inc trunk/src/superio/nsc/pc8374/pc8374_early_init.c trunk/src/superio/nsc/pc8374/superio.c trunk/src/superio/nsc/pc87309/Makefile.inc trunk/src/superio/nsc/pc87309/pc87309_early_serial.c trunk/src/superio/nsc/pc87309/superio.c trunk/src/superio/nsc/pc87351/Makefile.inc trunk/src/superio/nsc/pc87351/pc87351_early_serial.c trunk/src/superio/nsc/pc87351/superio.c trunk/src/superio/nsc/pc87360/Makefile.inc trunk/src/superio/nsc/pc87360/pc87360_early_serial.c trunk/src/superio/nsc/pc87360/superio.c trunk/src/superio/nsc/pc87366/Makefile.inc trunk/src/superio/nsc/pc87366/pc87366_early_serial.c trunk/src/superio/nsc/pc87366/superio.c trunk/src/superio/nsc/pc87417/Makefile.inc trunk/src/superio/nsc/pc87417/pc87417.h trunk/src/superio/nsc/pc87417/pc87417_early_init.c trunk/src/superio/nsc/pc87417/pc87417_early_serial.c trunk/src/superio/nsc/pc87417/superio.c trunk/src/superio/nsc/pc87427/Makefile.inc trunk/src/superio/nsc/pc87427/pc87427_early_init.c trunk/src/superio/nsc/pc87427/superio.c trunk/src/superio/nsc/pc97307/Makefile.inc trunk/src/superio/nsc/pc97307/superio.c trunk/src/superio/nsc/pc97317/Makefile.inc trunk/src/superio/nsc/pc97317/pc97317_early_serial.c trunk/src/superio/nsc/pc97317/superio.c trunk/src/superio/smsc/fdc37m60x/Makefile.inc trunk/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c trunk/src/superio/smsc/fdc37m60x/superio.c trunk/src/superio/smsc/fdc37n972/Makefile.inc trunk/src/superio/smsc/fdc37n972/fdc37n972.c trunk/src/superio/smsc/lpc47b272/Makefile.inc trunk/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c trunk/src/superio/smsc/lpc47b272/superio.c trunk/src/superio/smsc/lpc47b397/Makefile.inc trunk/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c trunk/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c trunk/src/superio/smsc/lpc47b397/superio.c trunk/src/superio/smsc/lpc47m10x/Makefile.inc trunk/src/superio/smsc/lpc47m10x/lpc47m10x.h trunk/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c trunk/src/superio/smsc/lpc47m10x/superio.c trunk/src/superio/smsc/lpc47m15x/Makefile.inc trunk/src/superio/smsc/lpc47m15x/lpc47m15x.h trunk/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c trunk/src/superio/smsc/lpc47m15x/superio.c trunk/src/superio/smsc/lpc47n217/Makefile.inc trunk/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c trunk/src/superio/smsc/lpc47n217/superio.c trunk/src/superio/smsc/lpc47n227/Makefile.inc trunk/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c trunk/src/superio/smsc/lpc47n227/superio.c trunk/src/superio/smsc/sio10n268/Makefile.inc trunk/src/superio/smsc/sio10n268/sio10n268.c trunk/src/superio/smsc/smscsuperio/Makefile.inc trunk/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c trunk/src/superio/smsc/smscsuperio/superio.c trunk/src/superio/via/vt1211/vt1211.c trunk/src/superio/winbond/w83627dhg/superio.c trunk/src/superio/winbond/w83627ehg/superio.c trunk/src/superio/winbond/w83627hf/superio.c trunk/src/superio/winbond/w83627thf/superio.c trunk/src/superio/winbond/w83627thg/superio.c trunk/src/superio/winbond/w83627uhg/superio.c trunk/src/superio/winbond/w83697hf/superio.c trunk/src/superio/winbond/w83977f/superio.c trunk/src/superio/winbond/w83977tf/superio.c Modified: trunk/src/superio/fintek/f71805f/superio.c ============================================================================== --- trunk/src/superio/fintek/f71805f/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/fintek/f71805f/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -90,12 +90,12 @@ }; static struct pnp_info pnp_dev_info[] = { - /* TODO: Some of the 0x7f8 etc. values may not be correct. */ - { &ops, F71805F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, F71805F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, F71805F_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, F71805F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, F71805F_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, }, + /* TODO: Some of the 0x07f8 etc. values may not be correct. */ + { &ops, F71805F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, F71805F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71805F_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71805F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, F71805F_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, { &ops, F71805F_GPIO, PNP_IRQ0, }, { &ops, F71805F_PME, }, }; Modified: trunk/src/superio/fintek/f71859/superio.c ============================================================================== --- trunk/src/superio/fintek/f71859/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/fintek/f71859/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -87,9 +87,8 @@ }; static struct pnp_info pnp_dev_info[] = { - /* TODO: Some of the 0x7f8 etc. values may not be correct. */ - { &ops, F71859_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - + /* TODO: Some of the 0x07f8 etc. values may not be correct. */ + { &ops, F71859_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, }; static void enable_dev(device_t dev) Modified: trunk/src/superio/fintek/f71863fg/superio.c ============================================================================== --- trunk/src/superio/fintek/f71863fg/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/fintek/f71863fg/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -94,15 +94,15 @@ }; static struct pnp_info pnp_dev_info[] = { - /* TODO: Some of the 0x7f8 etc. values may not be correct. */ - { &ops, F71863FG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, }, - { &ops, F71863FG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, F71863FG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, F71863FG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, }, - { &ops, F71863FG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, - { &ops, F71863FG_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, }, - { &ops, F71863FG_GPIO, }, - { &ops, F71863FG_VID, PNP_IO0, { 0x07f8, 0 }, }, + /* TODO: Some of the 0x07f8 etc. values may not be correct. */ + { &ops, F71863FG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, F71863FG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71863FG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71863FG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, F71863FG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, F71863FG_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, }, + { &ops, F71863FG_GPIO, } + { &ops, F71863FG_VID, PNP_IO0, {0x07f8, 0}, }, { &ops, F71863FG_SPI, }, { &ops, F71863FG_PME, }, }; Modified: trunk/src/superio/fintek/f71872/superio.c ============================================================================== --- trunk/src/superio/fintek/f71872/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/fintek/f71872/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -92,15 +92,15 @@ }; static struct pnp_info pnp_dev_info[] = { - /* TODO: Some of the 0x7f8 etc. values may not be correct. */ - { &ops, F71872_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, }, - { &ops, F71872_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, F71872_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, F71872_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, }, - { &ops, F71872_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, - { &ops, F71872_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x07ff, 0 }, }, + /* TODO: Some of the 0x07f8 etc. values may not be correct. */ + { &ops, F71872_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, F71872_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71872_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71872_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, F71872_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, F71872_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, }, { &ops, F71872_GPIO, PNP_IRQ0, }, - { &ops, F71872_VID, PNP_IO0, { 0x0ff8, 0 }, }, + { &ops, F71872_VID, PNP_IO0, {0x0ff8, 0}, }, { &ops, F71872_PM, }, }; Modified: trunk/src/superio/fintek/f71889/superio.c ============================================================================== --- trunk/src/superio/fintek/f71889/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/fintek/f71889/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -93,15 +93,15 @@ }; static struct pnp_info pnp_dev_info[] = { - /* TODO: Some of the 0x7f8 etc. values may not be correct. */ - { &ops, F71889_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, }, - { &ops, F71889_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, F71889_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, F71889_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, }, - { &ops, F71889_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, - { &ops, F71889_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, }, + /* TODO: Some of the 0x07f8 etc. values may not be correct. */ + { &ops, F71889_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, F71889_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71889_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71889_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, F71889_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, F71889_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, }, { &ops, F71889_GPIO, }, - { &ops, F71889_VID, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 }, }, + { &ops, F71889_VID, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, F71889_SPI, }, { &ops, F71889_PME, }, { &ops, F71889_VREF, }, Modified: trunk/src/superio/intel/i3100/superio.c ============================================================================== --- trunk/src/superio/intel/i3100/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/intel/i3100/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -91,8 +91,8 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, I3100_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, I3100_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, I3100_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, I3100_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, }; static void enable_dev(struct device *dev) Modified: trunk/src/superio/ite/it8661f/superio.c ============================================================================== --- trunk/src/superio/ite/it8661f/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/ite/it8661f/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -63,8 +63,8 @@ /* TODO: FDC, PP, IR, GPIO. */ static struct pnp_info pnp_dev_info[] = { - { &ops, IT8661F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, IT8661F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, + { &ops, IT8661F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, IT8661F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, }; static void enable_dev(struct device *dev) Modified: trunk/src/superio/ite/it8671f/superio.c ============================================================================== --- trunk/src/superio/ite/it8671f/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/ite/it8671f/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -65,9 +65,9 @@ /* TODO: FDC, PP, KBCM. */ static struct pnp_info pnp_dev_info[] = { - { &ops, IT8671F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, IT8671F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, - { &ops, IT8671F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, + { &ops, IT8671F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, IT8671F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, + { &ops, IT8671F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, }, }; static void enable_dev(struct device *dev) Modified: trunk/src/superio/ite/it8673f/superio.c ============================================================================== --- trunk/src/superio/ite/it8673f/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/ite/it8673f/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -67,9 +67,9 @@ /* TODO: FDC, PP, FAN, KBCM. */ static struct pnp_info pnp_dev_info[] = { - { &ops, IT8673F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, IT8673F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, - { &ops, IT8673F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, + { &ops, IT8673F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, IT8673F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, + { &ops, IT8673F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, }, }; static void enable_dev(struct device *dev) Modified: trunk/src/superio/ite/it8705f/superio.c ============================================================================== --- trunk/src/superio/ite/it8705f/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/ite/it8705f/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -69,8 +69,8 @@ /* TODO: FDC, PP, EC, GPIO, GAME, IR, MIDI. */ static struct pnp_info pnp_dev_info[] = { - { &ops, IT8705F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, IT8705F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, + { &ops, IT8705F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, IT8705F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, }; static void enable_dev(struct device *dev) Modified: trunk/src/superio/ite/it8712f/superio.c ============================================================================== --- trunk/src/superio/ite/it8712f/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/ite/it8712f/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -112,17 +112,17 @@ }; static struct pnp_info pnp_dev_info[] = { - {&ops, IT8712F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xff8, 0},}, - {&ops, IT8712F_SP1, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, - {&ops, IT8712F_SP2, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, - {&ops, IT8712F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xffc, 0},}, - {&ops, IT8712F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xff8, 0}, {0xff8, 4},}, - {&ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xfff, 0}, {0xfff, 4},}, - {&ops, IT8712F_KBCM, PNP_IRQ0,}, - {&ops, IT8712F_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, {0xfff, 0}, {0xff8, 0}, {0xff8, 0},}, - {&ops, IT8712F_MIDI, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, - {&ops, IT8712F_GAME, PNP_IO0, {0xfff, 0},}, - {&ops, IT8712F_IR, PNP_IO0 | PNP_IRQ0, {0xff8, 0},}, + { &ops, IT8712F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, }, + { &ops, IT8712F_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, IT8712F_SP2, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, IT8712F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ffc, 0}, }, + { &ops, IT8712F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0ff8, 0}, {0x0ff8, 4}, }, + { &ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0fff, 0}, {0x0fff, 4}, }, + { &ops, IT8712F_KBCM, PNP_IRQ0, }, + { &ops, IT8712F_GPIO, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IRQ0, {0x0fff, 0}, {0x0ff8, 0}, {0x0ff8, 0}, }, + { &ops, IT8712F_MIDI, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, IT8712F_GAME, PNP_IO0, {0x0fff, 0}, }, + { &ops, IT8712F_IR, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, }; static void enable_dev(struct device *dev) Modified: trunk/src/superio/ite/it8716f/superio.c ============================================================================== --- trunk/src/superio/ite/it8716f/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/ite/it8716f/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -135,19 +135,17 @@ }; static struct pnp_info pnp_dev_info[] = { - {&ops, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},}, - {&ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},}, - {&ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},}, - {&ops, IT8716F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},}, - {&ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0}, - {0x7f8, 0x4},}, - {&ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0}, - {0x7ff, 0x4},}, - {&ops, IT8716F_KBCM, PNP_IRQ0,}, - {&ops, IT8716F_GPIO, PNP_IO1 | PNP_IO2, {0, 0}, {0x7f8, 0}, {0x7f8, 0},}, - {&ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},}, - {&ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},}, - {&ops, IT8716F_IR,}, + { &ops, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, IT8716F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, }, + { &ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07ff, 4}, }, + { &ops, IT8716F_KBCM, PNP_IRQ0, }, + { &ops, IT8716F_GPIO, PNP_IO1 | PNP_IO2, {0, 0}, {0x07f8, 0}, {0x07f8, 0}, }, + { &ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x07fe, 4}, }, + { &ops, IT8716F_GAME, PNP_IO0, {0x07ff, 0}, }, + { &ops, IT8716F_IR, }, }; static void enable_dev(struct device *dev) Modified: trunk/src/superio/ite/it8718f/superio.c ============================================================================== --- trunk/src/superio/ite/it8718f/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/ite/it8718f/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -69,9 +69,9 @@ /* TODO: FDC, PP, EC, KBCM, IR. */ static struct pnp_info pnp_dev_info[] = { - { &ops, IT8718F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, IT8718F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, - { &ops, IT8718F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, + { &ops, IT8718F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, IT8718F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, + { &ops, IT8718F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, }, }; static void enable_dev(struct device *dev) Modified: trunk/src/superio/nsc/pc8374/Makefile.inc ============================================================================== --- trunk/src/superio/nsc/pc8374/Makefile.inc Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc8374/Makefile.inc Mon Nov 15 20:35:14 2010 (r6073) @@ -19,5 +19,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_NSC_PC8374) += superio.c + Modified: trunk/src/superio/nsc/pc8374/pc8374_early_init.c ============================================================================== --- trunk/src/superio/nsc/pc8374/pc8374_early_init.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc8374/pc8374_early_init.c Mon Nov 15 20:35:14 2010 (r6073) @@ -22,30 +22,31 @@ #include <arch/romcc_io.h> #include "pc8374.h" -/* things that Must Be Done to get this chip working */ -/* Straight from the data book */ -static void pc8374_enable(unsigned iobase, u8 *init) +static void pc8374_enable(u16 iobase, u8 *init) { u8 val, count; + outb(0x29, iobase); - val = inb(iobase+1); + val = inb(iobase + 1); val |= 0x91; - outb(val, iobase+1); - for(count = 0; count < 255; count++) - if (inb(iobase+1) == 0x91) + outb(val, iobase + 1); + + for (count = 0; count < 255; count++) + if (inb(iobase + 1) == 0x91) break; - for(;*init; init++) { + + for (; *init; init++) { outb(*init, iobase); - val = inb(iobase+1); + val = inb(iobase + 1); init++; val &= *init; init++; val |= *init; - outb(val, iobase+1); + outb(val, iobase + 1); } } -static void pc8374_enable_dev(device_t dev, unsigned iobase) +static void pc8374_enable_dev(device_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); Modified: trunk/src/superio/nsc/pc8374/superio.c ============================================================================== --- trunk/src/superio/nsc/pc8374/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc8374/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -33,15 +33,12 @@ static void init(device_t dev) { - struct superio_nsc_pc8374_config *conf; + struct superio_nsc_pc8374_config *conf = dev�>chip_info; struct resource *res0; - /* Wishlist handle well known programming interfaces more - * generically. - */ - if (!dev->enabled) { + + if (!dev->enabled) return; - } - conf = dev->chip_info; + switch(dev->path.pnp.device) { case PC8374_SP1: res0 = find_resource(dev, PNP_IDX_IO0); @@ -66,20 +63,19 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, PC8374_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, }, - { &ops, PC8374_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, - { &ops, PC8374_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, - { &ops, PC8374_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, PC8374_SWC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, - { &ops, PC8374_KBCM, PNP_IRQ0 }, - { &ops, PC8374_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, - { &ops, PC8374_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, + { &ops, PC8374_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, }, + { &ops, PC8374_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0}, }, + { &ops, PC8374_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, + { &ops, PC8374_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, PC8374_SWC, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, }, + { &ops, PC8374_KBCM, PNP_IRQ0, }, + { &ops, PC8374_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, }, + { &ops, PC8374_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, }, }; static void enable_dev(struct device *dev) { - pnp_enable_devices(dev, &ops, - ARRAY_SIZE(pnp_dev_info), pnp_dev_info); + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc8374_ops = { Modified: trunk/src/superio/nsc/pc87309/Makefile.inc ============================================================================== --- trunk/src/superio/nsc/pc87309/Makefile.inc Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc87309/Makefile.inc Mon Nov 15 20:35:14 2010 (r6073) @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_NSC_PC87309) += superio.c + Modified: trunk/src/superio/nsc/pc87309/pc87309_early_serial.c ============================================================================== --- trunk/src/superio/nsc/pc87309/pc87309_early_serial.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc87309/pc87309_early_serial.c Mon Nov 15 20:35:14 2010 (r6073) @@ -21,7 +21,7 @@ #include <arch/romcc_io.h> #include "pc87309.h" -static void pc87309_enable_serial(device_t dev, unsigned int iobase) +static void pc87309_enable_serial(device_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); Modified: trunk/src/superio/nsc/pc87309/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87309/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc87309/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -29,13 +29,12 @@ static void init(device_t dev) { - struct superio_nsc_pc87309_config *conf; + struct superio_nsc_pc87309_config *conf = dev->chip_info; struct resource *res0; - if (!dev->enabled) { + if (!dev->enabled) return; - } - conf = dev->chip_info; + switch (dev->path.pnp.device) { case PC87309_SP1: res0 = find_resource(dev, PNP_IDX_IO0); @@ -52,21 +51,21 @@ } static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = pnp_set_resources, + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, .enable_resources = pnp_enable_resources, - .enable = pnp_enable, - .init = init, + .enable = pnp_enable, + .init = init, }; static struct pnp_info pnp_dev_info[] = { - {&ops, PC87309_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0},}, - {&ops, PC87309_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0},}, - {&ops, PC87309_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x7f8, 0},}, - {&ops, PC87309_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},}, + { &ops, PC87309_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, }, + { &ops, PC87309_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0}, }, + { &ops, PC87309_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, + { &ops, PC87309_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, /* TODO: PM. */ - {&ops, PC87309_KBCM, PNP_IRQ0}, - {&ops, PC87309_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0}, {0x7f8, 0x4},}, + { &ops, PC87309_KBCM, PNP_IRQ0, }, + { &ops, PC87309_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x7f8, 4}, }, }; static void enable_dev(struct device *dev) Modified: trunk/src/superio/nsc/pc87351/Makefile.inc ============================================================================== --- trunk/src/superio/nsc/pc87351/Makefile.inc Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc87351/Makefile.inc Mon Nov 15 20:35:14 2010 (r6073) @@ -19,5 +19,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_NSC_PC87351) += superio.c + Modified: trunk/src/superio/nsc/pc87351/pc87351_early_serial.c ============================================================================== --- trunk/src/superio/nsc/pc87351/pc87351_early_serial.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc87351/pc87351_early_serial.c Mon Nov 15 20:35:14 2010 (r6073) @@ -22,7 +22,7 @@ #include <arch/romcc_io.h> #include "pc87351.h" -static void pc87351_enable_serial(device_t dev, unsigned iobase) +static void pc87351_enable_serial(device_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); Modified: trunk/src/superio/nsc/pc87351/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87351/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc87351/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -19,12 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* - * Richard A Smith - * I derived this code from the pc87360 device and removed the stuff the 87351 - * dosen't do. - */ - #include <arch/io.h> #include <device/device.h> #include <device/pnp.h> @@ -39,15 +33,12 @@ static void init(device_t dev) { - struct superio_nsc_pc87351_config *conf; + struct superio_nsc_pc87351_config *conf = dev->chip_info; struct resource *res0; - /* Wishlist handle well known programming interfaces more - * generically. - */ - if (!dev->enabled) { + + if (!dev->enabled) return; - } - conf = dev->chip_info; + switch(dev->path.pnp.device) { case PC87351_SP1: res0 = find_resource(dev, PNP_IDX_IO0); @@ -72,15 +63,15 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, PC87351_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, }, - { &ops, PC87351_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, - { &ops, PC87351_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, - { &ops, PC87351_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, PC87351_SWC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, - { &ops, PC87351_KBCM, PNP_IRQ0 }, - { &ops, PC87351_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, - { &ops, PC87351_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, - { &ops, PC87351_FSD, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, + { &ops, PC87351_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, }, + { &ops, PC87351_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0}, }, + { &ops, PC87351_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, + { &ops, PC87351_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, PC87351_SWC, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, }, + { &ops, PC87351_KBCM, PNP_IRQ0, }, + { &ops, PC87351_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, }, + { &ops, PC87351_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, }, + { &ops, PC87351_FSD, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, }, }; static void enable_dev(struct device *dev) Modified: trunk/src/superio/nsc/pc87360/Makefile.inc ============================================================================== --- trunk/src/superio/nsc/pc87360/Makefile.inc Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc87360/Makefile.inc Mon Nov 15 20:35:14 2010 (r6073) @@ -19,5 +19,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_NSC_PC87360) += superio.c + Modified: trunk/src/superio/nsc/pc87360/pc87360_early_serial.c ============================================================================== --- trunk/src/superio/nsc/pc87360/pc87360_early_serial.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc87360/pc87360_early_serial.c Mon Nov 15 20:35:14 2010 (r6073) @@ -22,7 +22,7 @@ #include <arch/romcc_io.h> #include "pc87360.h" -static void pc87360_enable_serial(device_t dev, unsigned iobase) +static void pc87360_enable_serial(device_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); Modified: trunk/src/superio/nsc/pc87360/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87360/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc87360/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -33,15 +33,12 @@ static void init(device_t dev) { - struct superio_nsc_pc87360_config *conf; + struct superio_nsc_pc87360_config *conf = dev->chip_info; struct resource *res0; - /* Wishlist handle well known programming interfaces more - * generically. - */ - if (!dev->enabled) { + + if (!dev->enabled) return; - } - conf = dev->chip_info; + switch(dev->path.pnp.device) { case PC87360_SP1: res0 = find_resource(dev, PNP_IDX_IO0); @@ -66,23 +63,22 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, PC87360_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, }, - { &ops, PC87360_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, - { &ops, PC87360_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, - { &ops, PC87360_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, PC87360_SWC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, - { &ops, PC87360_KBCM, PNP_IRQ0 }, - { &ops, PC87360_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, - { &ops, PC87360_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, - { &ops, PC87360_ACB, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, - { &ops, PC87360_FSCM, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, - { &ops, PC87360_WDT, PNP_IO0 | PNP_IRQ0, { 0xfffc, 0 } }, + { &ops, PC87360_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, }, + { &ops, PC87360_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0}, }, + { &ops, PC87360_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, + { &ops, PC87360_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, PC87360_SWC, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, }, + { &ops, PC87360_KBCM, PNP_IRQ0, }, + { &ops, PC87360_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, }, + { &ops, PC87360_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, }, + { &ops, PC87360_ACB, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, }, + { &ops, PC87360_FSCM, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, }, + { &ops, PC87360_WDT, PNP_IO0 | PNP_IRQ0, {0xfffc, 0}, }, }; static void enable_dev(struct device *dev) { - pnp_enable_devices(dev, &ops, - ARRAY_SIZE(pnp_dev_info), pnp_dev_info); + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc87360_ops = { Modified: trunk/src/superio/nsc/pc87366/Makefile.inc ============================================================================== --- trunk/src/superio/nsc/pc87366/Makefile.inc Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc87366/Makefile.inc Mon Nov 15 20:35:14 2010 (r6073) @@ -19,5 +19,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_NSC_PC87366) += superio.c + Modified: trunk/src/superio/nsc/pc87366/pc87366_early_serial.c ============================================================================== --- trunk/src/superio/nsc/pc87366/pc87366_early_serial.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc87366/pc87366_early_serial.c Mon Nov 15 20:35:14 2010 (r6073) @@ -22,7 +22,7 @@ #include <arch/romcc_io.h> #include "pc87366.h" -static void pc87366_enable_serial(device_t dev, unsigned iobase) +static void pc87366_enable_serial(device_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); Modified: trunk/src/superio/nsc/pc87366/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87366/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc87366/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -33,15 +33,12 @@ static void init(device_t dev) { - struct superio_nsc_pc87366_config *conf; + struct superio_nsc_pc87366_config *conf = dev->chip_info; struct resource *res0; - /* Wishlist handle well known programming interfaces more - * generically. - */ - if (!dev->enabled) { + + if (!dev->enabled) return; - } - conf = dev->chip_info; + switch(dev->path.pnp.device) { case PC87366_SP1: res0 = find_resource(dev, PNP_IDX_IO0); @@ -66,17 +63,17 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, PC87366_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, }, - { &ops, PC87366_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, - { &ops, PC87366_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, - { &ops, PC87366_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, PC87366_SWC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, - { &ops, PC87366_KBCM, PNP_IRQ0 }, - { &ops, PC87366_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, - { &ops, PC87366_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, - { &ops, PC87366_ACB, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, - { &ops, PC87366_FSCM, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, - { &ops, PC87366_WDT, PNP_IO0 | PNP_IRQ0, { 0xfffc, 0 } }, + { &ops, PC87366_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, }, + { &ops, PC87366_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0}, }, + { &ops, PC87366_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, + { &ops, PC87366_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, PC87366_SWC, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, }, + { &ops, PC87366_KBCM, PNP_IRQ0, }, + { &ops, PC87366_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, }, + { &ops, PC87366_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, }, + { &ops, PC87366_ACB, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, }, + { &ops, PC87366_FSCM, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, }, + { &ops, PC87366_WDT, PNP_IO0 | PNP_IRQ0, {0xfffc, 0}, }, }; static void enable_dev(struct device *dev) Modified: trunk/src/superio/nsc/pc87417/Makefile.inc ============================================================================== --- trunk/src/superio/nsc/pc87417/Makefile.inc Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc87417/Makefile.inc Mon Nov 15 20:35:14 2010 (r6073) @@ -20,5 +20,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_NSC_PC87417) += superio.c + Modified: trunk/src/superio/nsc/pc87417/pc87417.h ============================================================================== --- trunk/src/superio/nsc/pc87417/pc87417.h Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc87417/pc87417.h Mon Nov 15 20:35:14 2010 (r6073) @@ -3,7 +3,7 @@ * * Copyright (C) 2000 AG Electronics Ltd. * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan by yhlu + * Copyright (C) 2004 Tyan * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -115,7 +115,7 @@ #define PC87417_XWBCNF 0x16 #if defined(__PRE_RAM__) && !defined(__ROMCC__) -void pc87417_enable_serial(device_t dev, unsigned iobase); +void pc87417_enable_serial(device_t dev, u16 iobase); void pc87417_enable_dev(device_t dev); #endif Modified: trunk/src/superio/nsc/pc87417/pc87417_early_init.c ============================================================================== --- trunk/src/superio/nsc/pc87417/pc87417_early_init.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc87417/pc87417_early_init.c Mon Nov 15 20:35:14 2010 (r6073) @@ -3,7 +3,7 @@ * * Copyright (C) 2000 AG Electronics Ltd. * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan by yhlu + * Copyright (C) 2004 Tyan * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,7 +29,7 @@ pnp_set_enable(dev, 0); } -static void pc87417_enable_dev(device_t dev, unsigned iobase) +static void pc87417_enable_dev(device_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); @@ -39,17 +39,16 @@ static void xbus_cfg(device_t dev) { - uint8_t i, data; - uint16_t xbus_index; + u8 i, data; + u16 xbus_index; pnp_set_logical_device(dev); - /* select proper BIOS size (4MB) */ - pnp_write_config(dev, PC87417_XMEMCNF2, (pnp_read_config(dev, PC87417_XMEMCNF2)) | 0x04); + /* Select proper BIOS size (4MB). */ + pnp_write_config(dev, PC87417_XMEMCNF2, + (pnp_read_config(dev, PC87417_XMEMCNF2)) | 0x04); xbus_index = pnp_read_iobase(dev, 0x60); - /* enable writes to devices attached to XCS0 (XBUS Chip Select 0) */ - for (i=0; i<= 0xf; i++) { - outb((i<<4), xbus_index + PC87417_HAP0); - } - return; + /* Enable writes to devices attached to XCS0 (XBUS Chip Select 0). */ + for (i = 0; i <= 0xf; i++) + outb((i << 4), xbus_index + PC87417_HAP0); } Modified: trunk/src/superio/nsc/pc87417/pc87417_early_serial.c ============================================================================== --- trunk/src/superio/nsc/pc87417/pc87417_early_serial.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc87417/pc87417_early_serial.c Mon Nov 15 20:35:14 2010 (r6073) @@ -3,7 +3,7 @@ * * Copyright (C) 2000 AG Electronics Ltd. * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan by yhlu + * Copyright (C) 2004 Tyan * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -23,7 +23,7 @@ #include <arch/romcc_io.h> #include "pc87417.h" -void pc87417_enable_serial(device_t dev, unsigned iobase) +void pc87417_enable_serial(device_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); Modified: trunk/src/superio/nsc/pc87417/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87417/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc87417/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -3,7 +3,7 @@ * * Copyright (C) 2000 AG Electronics Ltd. * Copyright (C) 2003-2004 Linux Networx - * Copyright (C) 2004 Tyan by yhlu + * Copyright (C) 2004 Tyan * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -34,15 +34,12 @@ static void init(device_t dev) { - struct superio_nsc_pc87417_config *conf; + struct superio_nsc_pc87417_config *conf = dev->chip_info; struct resource *res0; - /* Wishlist handle well known programming interfaces more - * generically. - */ - if (!dev->enabled) { + + if (!dev->enabled) return; - } - conf = dev->chip_info; + switch(dev->path.pnp.device) { case PC87417_SP1: res0 = find_resource(dev, PNP_IDX_IO0); @@ -67,16 +64,16 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, PC87417_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, }, - { &ops, PC87417_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x04f8, 0}, }, - { &ops, PC87417_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, - { &ops, PC87417_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, PC87417_SWC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, - { &ops, PC87417_KBCM, PNP_IRQ0 }, - { &ops, PC87417_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, - { &ops, PC87417_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 } }, - { &ops, PC87417_XBUS, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } }, - { &ops, PC87417_RTC, PNP_IO0 | PNP_IO1, { 0xfffe, 0 }, {0xfffe, 0x4} }, + { &ops, PC87417_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, }, + { &ops, PC87417_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x04f8, 0}, }, + { &ops, PC87417_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, + { &ops, PC87417_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, PC87417_SWC, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, }, + { &ops, PC87417_KBCM, PNP_IRQ0, }, + { &ops, PC87417_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, }, + { &ops, PC87417_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, }, + { &ops, PC87417_XBUS, PNP_IO0 | PNP_IRQ0, {0xffe0, 0}, }, + { &ops, PC87417_RTC, PNP_IO0 | PNP_IO1, {0xfffe, 0}, {0xfffe, 4}, }, }; static void enable_dev(struct device *dev) Modified: trunk/src/superio/nsc/pc87427/Makefile.inc ============================================================================== --- trunk/src/superio/nsc/pc87427/Makefile.inc Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc87427/Makefile.inc Mon Nov 15 20:35:14 2010 (r6073) @@ -19,5 +19,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_NSC_PC87427) += superio.c + Modified: trunk/src/superio/nsc/pc87427/pc87427_early_init.c ============================================================================== --- trunk/src/superio/nsc/pc87427/pc87427_early_init.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc87427/pc87427_early_init.c Mon Nov 15 20:35:14 2010 (r6073) @@ -27,26 +27,28 @@ pnp_set_logical_device(dev); pnp_set_enable(dev, 0); } -static void pc87427_enable_dev(device_t dev, unsigned iobase) + +static void pc87427_enable_dev(device_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); pnp_set_enable(dev, 1); } + static void xbus_cfg(device_t dev) { - uint8_t i, data; - uint16_t xbus_index; + u8 i, data; + u16 xbus_index; pnp_set_logical_device(dev); - /* select proper BIOS size (4MB) */ - pnp_write_config(dev, PC87427_XMEMCNF2, (pnp_read_config(dev, PC87427_XMEMCNF2)) | 0x04); + + /* Select proper BIOS size (4MB). */ + pnp_write_config(dev, PC87427_XMEMCNF2, + (pnp_read_config(dev, PC87427_XMEMCNF2)) | 0x04); xbus_index = pnp_read_iobase(dev, 0x60); - /* enable writes to devices attached to XCS0 (XBUS Chip Select 0) */ - for (i=0; i<= 0xf; i++) { - outb((i<<4), xbus_index + PC87427_HAP0); - } - return; + /* Enable writes to devices attached to XCS0 (XBUS Chip Select 0). */ + for (i = 0; i <= 0xf; i++) + outb((i << 4), xbus_index + PC87427_HAP0); } Modified: trunk/src/superio/nsc/pc87427/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87427/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc87427/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -31,15 +31,12 @@ static void init(device_t dev) { - struct superio_nsc_pc87427_config *conf; + struct superio_nsc_pc87427_config *conf = dev->chip_info; struct resource *res0; - /* Wishlist handle well known programming interfaces more - * generically. - */ - if (!dev->enabled) { + + if (!dev->enabled) return; - } - conf = dev->chip_info; + switch(dev->path.pnp.device) { case PC87427_SP1: res0 = find_resource(dev, PNP_IDX_IO0); @@ -64,25 +61,23 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, PC87427_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07fa, 0}, }, - { &ops, PC87427_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, PC87427_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, PC87427_SWC, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0, - { 0xfff0, 0 }, { 0xfffc, 0 }, { 0xfffc, 0 }, { 0xfff8, 0 } }, - { &ops, PC87427_KBCM, PNP_IRQ0 }, - { &ops, PC87427_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, - { &ops, PC87427_GPIO, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } }, - { &ops, PC87427_WDT, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 } }, - { &ops, PC87427_FMC, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } }, - { &ops, PC87427_XBUS, PNP_IO0 | PNP_IRQ0, { 0xffe0, 0 } }, - { &ops, PC87427_RTC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xfffe, 0 }, { 0xfffe, 0 } }, - { &ops, PC87427_MHC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xffe0, 0 }, { 0xffe0, 0 } }, + { &ops, PC87427_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07fa, 0}, }, + { &ops, PC87427_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, PC87427_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, PC87427_SWC, PNP_IO0 | PNP_IO1 | PNP_IO2 | PNP_IO3 | PNP_IRQ0, {0xfff0, 0}, {0xfffc, 0}, {0xfffc, 0}, {0xfff8, 0}, }, + { &ops, PC87427_KBCM, PNP_IRQ0, }, + { &ops, PC87427_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, }, + { &ops, PC87427_GPIO, PNP_IO0 | PNP_IRQ0, {0xffe0, 0}, }, + { &ops, PC87427_WDT, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, }, + { &ops, PC87427_FMC, PNP_IO0 | PNP_IRQ0, {0xffe0, 0}, }, + { &ops, PC87427_XBUS, PNP_IO0 | PNP_IRQ0, {0xffe0, 0}, }, + { &ops, PC87427_RTC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xfffe, 0}, {0xfffe, 0}, }, + { &ops, PC87427_MHC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0xffe0, 0}, {0xffe0, 0}, }, }; static void enable_dev(struct device *dev) { - pnp_enable_devices(dev, &ops, - ARRAY_SIZE(pnp_dev_info), pnp_dev_info); + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc87427_ops = { Modified: trunk/src/superio/nsc/pc97307/Makefile.inc ============================================================================== --- trunk/src/superio/nsc/pc97307/Makefile.inc Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc97307/Makefile.inc Mon Nov 15 20:35:14 2010 (r6073) @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_NSC_PC97307) += superio.c + Modified: trunk/src/superio/nsc/pc97307/superio.c ============================================================================== --- trunk/src/superio/nsc/pc97307/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc97307/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -28,45 +28,37 @@ static void init(device_t dev) { - struct superio_nsc_pc97307_config *conf; + struct superio_nsc_pc97307_config *conf = dev->chip_info; struct resource *res0; + u8 reg8; - if (!dev->enabled) { + if (!dev->enabled) return; - } - conf = dev->chip_info; + switch(dev->path.pnp.device) { case PC97307_SP1: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; - case PC97307_SP2: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com2); break; - case PC97307_KBCK: - /* Enable keyboard */ pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); /* Disable keyboard */ - pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 Mhz */ - pnp_set_enable(dev, 1); /* Enable keyboard */ - + pnp_set_enable(dev, 0); /* Disable keyboard */ + pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 MHz. */ + pnp_set_enable(dev, 1); /* Enable keyboard. */ pc_keyboard_init(&conf->keyboard); break; - case PC97307_FDC: - { - unsigned reg; - /* Set up floppy in PS/2 mode */ + /* Set up floppy in PS/2 mode. */ outb(0x09, SIO_CONFIG_RA); - reg = inb(SIO_CONFIG_RD); - reg = (reg & 0x3F) | 0x40; - outb(reg, SIO_CONFIG_RD); - outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */ + reg8 = inb(SIO_CONFIG_RD); + reg8 = (reg8 & 0x3F) | 0x40; + outb(reg8, SIO_CONFIG_RD); + outb(reg8, SIO_CONFIG_RD); /* Have to write twice to change! */ break; - } default: break; } @@ -81,21 +73,20 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, PC97307_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xffb, 0 }, { 0xffb, 0x4}, }, - { &ops, PC97307_KBCM, PNP_IRQ0 }, - { &ops, PC97307_RTC, PNP_IO0 | PNP_IRQ0, { 0xfffe, 0}, }, - { &ops, PC97307_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0xfffa, 0}, }, - { &ops, PC97307_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x03fc, 0}, }, - { &ops, PC97307_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0xfff8, 0 }, }, - { &ops, PC97307_SP1, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 }, }, - { &ops, PC97307_GPIO, PNP_IO0, { 0xfff8, 0 } }, - { &ops, PC97307_PM, PNP_IO0, { 0xfffe, 0 } }, + { &ops, PC97307_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0ffb, 0}, {0x0ffb, 4}, }, + { &ops, PC97307_KBCM, PNP_IRQ0, }, + { &ops, PC97307_RTC, PNP_IO0 | PNP_IRQ0, {0xfffe, 0}, }, + { &ops, PC97307_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xfffa, 0}, }, + { &ops, PC97307_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x03fc, 0}, }, + { &ops, PC97307_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0xfff8, 0}, }, + { &ops, PC97307_SP1, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, }, + { &ops, PC97307_GPIO, PNP_IO0, {0xfff8, 0}, }, + { &ops, PC97307_PM, PNP_IO0, {0xfffe, 0}, }, }; static void enable_dev(struct device *dev) { - pnp_enable_devices(dev, &ops, - ARRAY_SIZE(pnp_dev_info), pnp_dev_info); + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc97307_ops = { Modified: trunk/src/superio/nsc/pc97317/Makefile.inc ============================================================================== --- trunk/src/superio/nsc/pc97317/Makefile.inc Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc97317/Makefile.inc Mon Nov 15 20:35:14 2010 (r6073) @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_NSC_PC97317) += superio.c + Modified: trunk/src/superio/nsc/pc97317/pc97317_early_serial.c ============================================================================== --- trunk/src/superio/nsc/pc97317/pc97317_early_serial.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc97317/pc97317_early_serial.c Mon Nov 15 20:35:14 2010 (r6073) @@ -24,28 +24,24 @@ #define PM_DEV PNP_DEV(0x2e, PC97317_PM) #define PM_BASE 0xe8 -/* The pc97317 needs clocks to be set up before the serial port will operate */ - -static void pc97317_enable_serial(device_t dev, unsigned iobase) +/* The PC97317 needs clocks to be set up before the serial port will operate. */ +static void pc97317_enable_serial(device_t dev, u16 iobase) { - /* Set base address of power management unit */ - + /* Set base address of power management unit. */ pnp_set_logical_device(PM_DEV); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, PM_BASE); pnp_set_enable(dev, 1); - /* Use on-chip clock multiplier */ - + /* Use on-chip clock multiplier. */ outb(0x03, PM_BASE); outb(inb(PM_BASE + 1) | 0x07, PM_BASE + 1); - /* Wait for the clock to stabilise */ + /* Wait for the clock to stabilise. */ while(!(inb(PM_BASE + 1) & 0x80)) ; - /* Set the base address of the port */ - + /* Set the base address of the port. */ pnp_set_logical_device(dev); pnp_set_enable(dev, 0); pnp_set_iobase(dev, PNP_IDX_IO0, iobase); Modified: trunk/src/superio/nsc/pc97317/superio.c ============================================================================== --- trunk/src/superio/nsc/pc97317/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/nsc/pc97317/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -28,47 +28,28 @@ static void init(device_t dev) { - struct superio_nsc_pc97317_config *conf; + struct superio_nsc_pc97317_config *conf = dev->chip_info; struct resource *res0; - if (!dev->enabled) { + if (!dev->enabled) return; - } - conf = dev->chip_info; + switch(dev->path.pnp.device) { case PC97317_SP1: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; - case PC97317_SP2: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com2); break; - case PC97317_KBCK: - /* Enable keyboard */ pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); /* Disable keyboard */ - pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 Mhz */ - pnp_set_enable(dev, 1); /* Enable keyboard */ - + pnp_set_enable(dev, 0); /* Disable keyboard */ + pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 MHz. */ + pnp_set_enable(dev, 1); /* Enable keyboard */ pc_keyboard_init(&conf->keyboard); break; - -#if 0 - case PC97317_FDC: - { - unsigned reg; - /* Set up floppy in PS/2 mode */ - outb(0x09, SIO_CONFIG_RA); - reg = inb(SIO_CONFIG_RD); - reg = (reg & 0x3F) | 0x40; - outb(reg, SIO_CONFIG_RD); - outb(reg, SIO_CONFIG_RD); /* Have to write twice to change! */ - break; - } -#endif default: break; } @@ -83,21 +64,20 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, PC97317_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0xffb, 0 }, { 0xffb, 0x4}, }, - { &ops, PC97317_KBCM, PNP_IRQ0 }, - { &ops, PC97317_RTC, PNP_IO0 | PNP_IRQ0, { 0xfffe, 0}, }, - { &ops, PC97317_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0xfffa, 0}, }, - { &ops, PC97317_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x03fc, 0}, }, - { &ops, PC97317_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0xfff8, 0 }, }, - { &ops, PC97317_SP1, PNP_IO0 | PNP_IRQ0, { 0xfff8, 0 }, }, - { &ops, PC97317_GPIO, PNP_IO0, { 0xfff8, 0 } }, - { &ops, PC97317_PM, PNP_IO0, { 0xfffe, 0 } }, + { &ops, PC97317_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x0ffb, 0}, {0x0ffb, 4}, }, + { &ops, PC97317_KBCM, PNP_IRQ0, }, + { &ops, PC97317_RTC, PNP_IO0 | PNP_IRQ0, {0xfffe, 0}, }, + { &ops, PC97317_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xfffa, 0}, }, + { &ops, PC97317_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x03fc, 0}, }, + { &ops, PC97317_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0xfff8, 0}, }, + { &ops, PC97317_SP1, PNP_IO0 | PNP_IRQ0, {0xfff8, 0}, }, + { &ops, PC97317_GPIO, PNP_IO0, {0xfff8, 0}, }, + { &ops, PC97317_PM, PNP_IO0, {0xfffe, 0}, }, }; static void enable_dev(struct device *dev) { - pnp_enable_devices(dev, &ops, - ARRAY_SIZE(pnp_dev_info), pnp_dev_info); + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_nsc_pc97317_ops = { Modified: trunk/src/superio/smsc/fdc37m60x/Makefile.inc ============================================================================== --- trunk/src/superio/smsc/fdc37m60x/Makefile.inc Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/fdc37m60x/Makefile.inc Mon Nov 15 20:35:14 2010 (r6073) @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_SMSC_FDC37M60X) += superio.c + Modified: trunk/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c ============================================================================== --- trunk/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/fdc37m60x/fdc37m60x_early_serial.c Mon Nov 15 20:35:14 2010 (r6073) @@ -24,7 +24,7 @@ /* The base address is 0x3f0 or 0x370, depending on the SYSOPT pin. */ #define SIO_BASE 0x3f0 #define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 +#define SIO_DATA (SIO_BASE + 1) /* Global configuration registers. */ #define FDC37M60X_CONFIG_REG_CC 0x02 /* Configure Control. */ @@ -37,7 +37,7 @@ /* The content of FDC37M60X_CONFIG_REG_LDN (index 0x07) must be set to the LDN the register belongs to, before you can access the register. */ -static void fdc37m60x_sio_write(uint8_t ldn, uint8_t index, uint8_t value) +static void fdc37m60x_sio_write(uint8_t ldn, u8 index, u8 value) { outb(FDC37M60X_CONFIG_REG_LDN, SIO_BASE); outb(ldn, SIO_DATA); @@ -46,7 +46,7 @@ } /* Enable the peripheral devices on the FDC37M60X Super I/O chip. */ -static void fdc37m60x_enable_serial(device_t dev, unsigned iobase) +static void fdc37m60x_enable_serial(device_t dev, u16 iobase) { /* (1) Enter the configuration state. */ outb(0x55, FDC37M60X_CONFIGURATION_PORT); Modified: trunk/src/superio/smsc/fdc37m60x/superio.c ============================================================================== --- trunk/src/superio/smsc/fdc37m60x/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/fdc37m60x/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -28,14 +28,11 @@ static void init(device_t dev) { - struct superio_smsc_fdc37m60x_config *conf; + struct superio_smsc_fdc37m60x_config *conf = dev->chip_info; struct resource *res0; - if (!dev->enabled) { + if (!dev->enabled) return; - } - - conf = dev->chip_info; switch (dev->path.pnp.device) { case FDC37M60X_FDC: /* TODO. */ @@ -68,9 +65,9 @@ /* TODO: FDC, PP, AUX. */ static struct pnp_info pnp_dev_info[] = { - { &ops, FDC37M60X_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, FDC37M60X_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, - { &ops, FDC37M60X_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, + { &ops, FDC37M60X_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, FDC37M60X_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, + { &ops, FDC37M60X_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, }, }; static void enable_dev(struct device *dev) Modified: trunk/src/superio/smsc/fdc37n972/Makefile.inc ============================================================================== --- trunk/src/superio/smsc/fdc37n972/Makefile.inc Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/fdc37n972/Makefile.inc Mon Nov 15 20:35:14 2010 (r6073) @@ -18,3 +18,4 @@ ## ramstage-$(CONFIG_SUPERIO_SMSC_FDC37N972) += fdc37n972.c + Modified: trunk/src/superio/smsc/fdc37n972/fdc37n972.c ============================================================================== --- trunk/src/superio/smsc/fdc37n972/fdc37n972.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/fdc37n972/fdc37n972.c Mon Nov 15 20:35:14 2010 (r6073) @@ -27,13 +27,10 @@ static void init(device_t dev) { - struct superio_smsc_fdc37n972_config *conf; + struct superio_smsc_fdc37n972_config *conf = dev->chip_info; - if (!dev->enabled) { + if (!dev->enabled) return; - } - - conf = dev->chip_info; switch (dev->path.pnp.device) { case FDC37N972_FDC: /* TODO. */ @@ -56,9 +53,9 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, FDC37N972_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, FDC37N972_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, { 0x7f8, 0 }, }, - { &ops, FDC37N972_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, + { &ops, FDC37N972_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, FDC37N972_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x07f8, 0}, }, + { &ops, FDC37N972_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, }, }; static void enable_dev(struct device *dev) Modified: trunk/src/superio/smsc/lpc47b272/Makefile.inc ============================================================================== --- trunk/src/superio/smsc/lpc47b272/Makefile.inc Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47b272/Makefile.inc Mon Nov 15 20:35:14 2010 (r6073) @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_SMSC_LPC47B272) += superio.c + Modified: trunk/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c ============================================================================== --- trunk/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47b272/lpc47b272_early_serial.c Mon Nov 15 20:35:14 2010 (r6073) @@ -23,17 +23,15 @@ #include <arch/romcc_io.h> #include "lpc47b272.h" -/** Enable access to the LPC47B272's configuration registers. */ -static inline void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(device_t dev) { - unsigned port = dev>>8; + u16 port = dev >> 8; outb(0x55, port); } -/** Disable access to the LPC47B272's configuration registers. */ static void pnp_exit_conf_state(device_t dev) { - unsigned port = dev>>8; + u16 port = dev >> 8; outb(0xaa, port); } @@ -44,7 +42,7 @@ * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47b272_enable_serial(device_t dev, unsigned iobase) +static void lpc47b272_enable_serial(device_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); Modified: trunk/src/superio/smsc/lpc47b272/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47b272/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47b272/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -45,7 +45,7 @@ static void pnp_enter_conf_state(device_t dev); static void pnp_exit_conf_state(device_t dev); -//static void dump_pnp_device(device_t dev); +// static void dump_pnp_device(device_t dev); struct chip_operations superio_smsc_lpc47b272_ops = { CHIP_NAME("SMSC LPC47B272 Super I/O") @@ -61,12 +61,12 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, LPC47B272_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, LPC47B272_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, LPC47B272_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, LPC47B272_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, LPC47B272_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, - { &ops, LPC47B272_RT, PNP_IO0, { 0x780, 0 }, }, + { &ops, LPC47B272_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, LPC47B272_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, LPC47B272_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, LPC47B272_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, LPC47B272_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, + { &ops, LPC47B272_RT, PNP_IO0, {0x0780, 0}, }, }; /** @@ -105,13 +105,7 @@ { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); - - if(dev->enabled) { - pnp_set_enable(dev, 1); - } - else { - pnp_set_enable(dev, 0); - } + pnp_set_enable(dev, (dev->enabled) ? 1 : 0); pnp_exit_conf_state(dev); } @@ -136,25 +130,21 @@ res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; - case LPC47B272_SP2: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com2); break; - case LPC47B272_KBC: pc_keyboard_init(&conf->keyboard); break; } } -/** Enable access to the LPC47B272's configuration registers. */ static void pnp_enter_conf_state(device_t dev) { outb(0x55, dev->path.pnp.port); } -/** Disable access to the LPC47B272's configuration registers. */ static void pnp_exit_conf_state(device_t dev) { outb(0xaa, dev->path.pnp.port); @@ -170,28 +160,30 @@ */ static void dump_pnp_device(device_t dev) { - int register_index; + int i; print_debug("\n"); - for(register_index = 0; register_index <= LPC47B272_MAX_CONFIG_REGISTER; register_index++) { - uint8_t register_value; + for (i = 0; i <= LPC47B272_MAX_CONFIG_REGISTER; i++) { + u8 register_value; - if ((register_index & 0x0f) == 0) { - print_debug_hex8(register_index); + if ((i & 0x0f) == 0) { + print_debug_hex8(i); print_debug_char(':'); } - /* Skip over 'register' that would cause exit from configuration mode */ - if (register_index == 0xaa) + /* + * Skip over 'register' that would cause exit from + * configuration mode. + */ + if (i == 0xaa) register_value = 0xaa; else - register_value = pnp_read_config(dev, register_index); + register_value = pnp_read_config(dev, i); print_debug_char(' '); print_debug_hex8(register_value); - if ((register_index & 0x0f) == 0x0f) { + if ((i & 0x0f) == 0x0f) print_debug("\n"); - } } print_debug("\n"); Modified: trunk/src/superio/smsc/lpc47b397/Makefile.inc ============================================================================== --- trunk/src/superio/smsc/lpc47b397/Makefile.inc Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47b397/Makefile.inc Mon Nov 15 20:35:14 2010 (r6073) @@ -20,5 +20,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_SMSC_LPC47B397) += superio.c + Modified: trunk/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c ============================================================================== --- trunk/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -20,30 +20,30 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -static void lpc47b397_gpio_offset_out(unsigned iobase, unsigned offset, unsigned value) +static void lpc47b397_gpio_offset_out(u16 iobase, u16 offset, u8 value) { - outb(value,iobase+offset); + outb(value, iobase + offset); } -static unsigned lpc47b397_gpio_offset_in(unsigned iobase, unsigned offset) +static u8 lpc47b397_gpio_offset_in(u16 iobase, u16 offset) { return inb(iobase+offset); } #if 0 -/* for GP60-GP64, GP66-GP85 */ +/* For GP60-GP64, GP66-GP85. */ #define LPC47B397_GPIO_CNTL_INDEX 0x70 #define LPC47B397_GPIO_CNTL_DATA 0x71 -static void lpc47b397_gpio_index_out(unsigned iobase, unsigned index, unsigned value) +static void lpc47b397_gpio_index_out(u16 iobase, u8 index, u8 value) { - outb(index,iobase+LPC47B397_GPIO_CNTL_INDEX); - outb(value, iobase+LPC47B397_GPIO_CNTL_DATA); + outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX); + outb(value, iobase + LPC47B397_GPIO_CNTL_DATA); } -static unsigned lpc47b397_gpio_index_in(unsigned iobase, unsigned index) +static u8 lpc47b397_gpio_index_in(u16 iobase, u8 index) { - outb(index,iobase+LPC47B397_GPIO_CNTL_INDEX); - return inb(iobase+LPC47B397_GPIO_CNTL_DATA); + outb(index, iobase + LPC47B397_GPIO_CNTL_INDEX); + return inb(iobase + LPC47B397_GPIO_CNTL_DATA); } #endif Modified: trunk/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c ============================================================================== --- trunk/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c Mon Nov 15 20:35:14 2010 (r6073) @@ -23,19 +23,19 @@ #include <arch/romcc_io.h> #include "lpc47b397.h" -static inline void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(device_t dev) { - unsigned port = dev>>8; + u16 port = dev >> 8; outb(0x55, port); } static void pnp_exit_conf_state(device_t dev) { - unsigned port = dev>>8; + u16 port = dev >> 8; outb(0xaa, port); } -static void lpc47b397_enable_serial(device_t dev, unsigned iobase) +static void lpc47b397_enable_serial(device_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); Modified: trunk/src/superio/smsc/lpc47b397/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47b397/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47b397/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -37,41 +37,42 @@ { outb(0x55, dev->path.pnp.port); } + static void pnp_exit_conf_state(device_t dev) { outb(0xaa, dev->path.pnp.port); } -static void pnp_write_index(unsigned long port_base, uint8_t reg, uint8_t value) +static void pnp_write_index(u16 port, u8 reg, u8 value) { - outb(reg, port_base); - outb(value, port_base + 1); + outb(reg, port); + outb(value, port + 1); } -static uint8_t pnp_read_index(unsigned long port_base, uint8_t reg) +static u8 pnp_read_index(u16 port, u8 reg) { - outb(reg, port_base); - return inb(port_base + 1); + outb(reg, port); + return inb(port + 1); } static void enable_hwm_smbus(device_t dev) { - /* enable SensorBus register access */ - uint8_t reg, value; - reg = 0xf0; - value = pnp_read_config(dev, reg); - value |= 0x01; - pnp_write_config(dev, reg, value); + /* Enable SensorBus register access. */ + u8 reg8; + + reg8 = pnp_read_config(dev, 0xf0); + reg8 |= (1 << 1); + pnp_write_config(dev, 0xf0, reg8); } static void lpc47b397_init(device_t dev) { - struct superio_smsc_lpc47b397_config *conf; + struct superio_smsc_lpc47b397_config *conf = dev->chip_info; struct resource *res0; - if (!dev->enabled) { + + if (!dev->enabled) return; - } - conf = dev->chip_info; + switch(dev->path.pnp.device) { case LPC47B397_SP1: res0 = find_resource(dev, PNP_IDX_IO0); @@ -91,9 +92,7 @@ { pnp_enter_conf_state(dev); pnp_set_resources(dev); -#if 0 - dump_pnp_device(dev); -#endif + /* dump_pnp_device(dev); */ pnp_exit_conf_state(dev); } @@ -104,14 +103,12 @@ switch(dev->path.pnp.device) { case LPC47B397_HWM: - printk(BIOS_DEBUG, "lpc47b397 SensorBus Register Access enabled\n"); + printk(BIOS_DEBUG, "LPC47B397 SensorBus register access enabled\n"); pnp_set_logical_device(dev); enable_hwm_smbus(dev); break; } -#if 0 - dump_pnp_device(dev); -#endif + /* dump_pnp_device(dev); */ pnp_exit_conf_state(dev); } @@ -119,13 +116,7 @@ { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); - - if(dev->enabled) { - pnp_set_enable(dev, 1); - } - else { - pnp_set_enable(dev, 0); - } + pnp_set_enable(dev, (dev->enabled) ? 1 : 0); pnp_exit_conf_state(dev); } @@ -145,9 +136,9 @@ #define SB_DATA2 0x0e #define SB_DATA3 0x0f -static int lsmbus_read_byte(device_t dev, uint8_t address) +static int lsmbus_read_byte(device_t dev, u8 address) { - unsigned device; + unsigned int device; struct resource *res; int result; @@ -155,24 +146,26 @@ res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0); - pnp_write_index(res->base+HWM_INDEX, 0, device); /* why 0? */ + pnp_write_index(res->base + HWM_INDEX, 0, device); /* Why 0? */ - result = pnp_read_index(res->base+SB_INDEX, address); /* we only read it one byte one time */ + /* We only read it one byte one time. */ + result = pnp_read_index(res->base + SB_INDEX, address); return result; } -static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val) +static int lsmbus_write_byte(device_t dev, u8 address, u8 val) { - unsigned device; + unsigned int device; struct resource *res; device = dev->path.i2c.device; res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0); - pnp_write_index(res->base+HWM_INDEX, 0, device); /* why 0? */ + pnp_write_index(res->base+HWM_INDEX, 0, device); /* Why 0? */ - pnp_write_index(res->base+SB_INDEX, address, val); /* we only write it one byte one time */ + /* We only write it one byte one time. */ + pnp_write_index(res->base+SB_INDEX, address, val); return 0; } @@ -183,6 +176,7 @@ .read_byte = lsmbus_read_byte, .write_byte = lsmbus_write_byte, }; + static struct device_operations ops_hwm = { .read_resources = pnp_read_resources, .set_resources = lpc47b397_pnp_set_resources, @@ -194,13 +188,13 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, LPC47B397_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, - { &ops_hwm, LPC47B397_HWM, PNP_IO0, { 0x7f0, 0 }, }, - { &ops, LPC47B397_RT, PNP_IO0, { 0x780, 0 }, }, + { &ops, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, LPC47B397_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, + { &ops_hwm, LPC47B397_HWM, PNP_IO0, {0x07f0, 0}, }, + { &ops, LPC47B397_RT, PNP_IO0, {0x0780, 0}, }, }; static void enable_dev(struct device *dev) Modified: trunk/src/superio/smsc/lpc47m10x/Makefile.inc ============================================================================== --- trunk/src/superio/smsc/lpc47m10x/Makefile.inc Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47m10x/Makefile.inc Mon Nov 15 20:35:14 2010 (r6073) @@ -22,5 +22,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_SMSC_LPC47M10X) += superio.c + Modified: trunk/src/superio/smsc/lpc47m10x/lpc47m10x.h ============================================================================== --- trunk/src/superio/smsc/lpc47m10x/lpc47m10x.h Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47m10x/lpc47m10x.h Mon Nov 15 20:35:14 2010 (r6073) @@ -28,9 +28,9 @@ #define LPC47M10X2_SP1 4 /* Com1 */ #define LPC47M10X2_SP2 5 /* Com2 */ #define LPC47M10X2_KBC 7 /* Keyboard & Mouse */ -#define LPC47M10X2_GAME 9 /* GAME */ +#define LPC47M10X2_GAME 9 /* GAME */ #define LPC47M10X2_PME 10 /* PME reg*/ -#define LPC47M10X2_MPU 10 /* MPE -- who knows -- reg*/ +#define LPC47M10X2_MPU 10 /* MPE -- who knows -- reg*/ // FIXME #define LPC47M10X2_MAX_CONFIG_REGISTER 0x5F Modified: trunk/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c ============================================================================== --- trunk/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47m10x/lpc47m10x_early_serial.c Mon Nov 15 20:35:14 2010 (r6073) @@ -1,6 +1,5 @@ /* - * lpc47m10x_early_serial.c: Pre-RAM driver for SMSC LPC47M10X2 Super I/O chip - * derived from lpc47n217 + * This file is part of the coreboot project. * * Copyright (C) 2005 Digital Design Corporation * @@ -22,17 +21,15 @@ #include <arch/romcc_io.h> #include "lpc47m10x.h" -/** Enable access to the LPC47M10X2's configuration registers. */ -static inline void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(device_t dev) { - unsigned port = dev>>8; + u16 port = dev >> 8; outb(0x55, port); } -/** Disable access to the LPC47M10X2's configuration registers. */ static void pnp_exit_conf_state(device_t dev) { - unsigned port = dev>>8; + u16 port = dev >> 8; outb(0xaa, port); } @@ -43,7 +40,7 @@ * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47m10x_enable_serial(device_t dev, unsigned iobase) +static void lpc47m10x_enable_serial(device_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); Modified: trunk/src/superio/smsc/lpc47m10x/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47m10x/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47m10x/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -1,11 +1,11 @@ /* - * superio.c: RAM driver for SMSC LPC47M10X2 Super I/O chip + * This file is part of the coreboot project. * - * Copyright 2000 AG Electronics Ltd. - * Copyright 2003-2004 Linux Networx - * Copyright 2004 Tyan + * Copyright (C) 2000 AG Electronics Ltd. + * Copyright (C) 2003-2004 Linux Networx + * Copyright (C) 2004 Tyan * Copyright (C) 2005 Digital Design Corporation - * Copyright (C) Ron Minnich, LANL + * Copyright (C) 2006 Ron Minnich, LANL * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -44,7 +44,7 @@ static void pnp_enter_conf_state(device_t dev); static void pnp_exit_conf_state(device_t dev); -//static void dump_pnp_device(device_t dev); +// static void dump_pnp_device(device_t dev); struct chip_operations superio_smsc_lpc47m10x_ops = { CHIP_NAME("SMSC LPC47M10x Super I/O") @@ -60,11 +60,11 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, LPC47M10X2_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, LPC47M10X2_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, LPC47M10X2_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, LPC47M10X2_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, LPC47M10X2_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, + { &ops, LPC47M10X2_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, LPC47M10X2_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, LPC47M10X2_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, LPC47M10X2_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, LPC47M10X2_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, }; /** @@ -103,13 +103,7 @@ { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); - - if(dev->enabled) { - pnp_set_enable(dev, 1); - } - else { - pnp_set_enable(dev, 0); - } + pnp_set_enable(dev, (dev->enabled) ? 1 : 0); pnp_exit_conf_state(dev); } @@ -134,25 +128,21 @@ res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; - case LPC47M10X2_SP2: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com2); break; - case LPC47M10X2_KBC: pc_keyboard_init(&conf->keyboard); break; } } -/** Enable access to the LPC47M10X2's configuration registers. */ static void pnp_enter_conf_state(device_t dev) { outb(0x55, dev->path.pnp.port); } -/** Disable access to the LPC47M10X2's configuration registers. */ static void pnp_exit_conf_state(device_t dev) { outb(0xaa, dev->path.pnp.port); @@ -168,30 +158,32 @@ */ static void dump_pnp_device(device_t dev) { - int register_index; + int i; print_debug("\n"); - for(register_index = 0; register_index <= LPC47M10X2_MAX_CONFIG_REGISTER; register_index++) { - uint8_t register_value; + for (i = 0; i <= LPC47M10X2_MAX_CONFIG_REGISTER; i++) { + u8 register_value; - if ((register_index & 0x0f) == 0) { - print_debug_hex8(register_index); + if ((i & 0x0f) == 0) { + print_debug_hex8(i); print_debug_char(':'); } - /* Skip over 'register' that would cause exit from configuration mode */ - if (register_index == 0xaa) + /* + * Skip over 'register' that would cause exit from + * configuration mode. + */ + if (i == 0xaa) register_value = 0xaa; else - register_value = pnp_read_config(dev, register_index); + register_value = pnp_read_config(dev, i); print_debug_char(' '); print_debug_hex8(register_value); - if ((register_index & 0x0f) == 0x0f) { + if ((i & 0x0f) == 0x0f) print_debug("\n"); - } } - print_debug("\n"); + print_debug("\n"); } #endif Modified: trunk/src/superio/smsc/lpc47m15x/Makefile.inc ============================================================================== --- trunk/src/superio/smsc/lpc47m15x/Makefile.inc Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47m15x/Makefile.inc Mon Nov 15 20:35:14 2010 (r6073) @@ -17,5 +17,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_SMSC_LPC47M15X) += superio.c + Modified: trunk/src/superio/smsc/lpc47m15x/lpc47m15x.h ============================================================================== --- trunk/src/superio/smsc/lpc47m15x/lpc47m15x.h Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47m15x/lpc47m15x.h Mon Nov 15 20:35:14 2010 (r6073) @@ -25,7 +25,7 @@ #define LPC47M15X_SP1 4 /* Com1 */ #define LPC47M15X_SP2 5 /* Com2 */ #define LPC47M15X_KBC 7 /* Keyboard & Mouse */ -#define LPC47M15X_GAME 9 /* GAME */ +#define LPC47M15X_GAME 9 /* GAME */ #define LPC47M15X_PME 10 /* PME reg*/ #define LPC47M15X_MPU 11 /* MPE -- who knows -- reg*/ Modified: trunk/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c ============================================================================== --- trunk/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c Mon Nov 15 20:35:14 2010 (r6073) @@ -22,19 +22,19 @@ #include <arch/romcc_io.h> #include "lpc47m15x.h" -static inline void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(device_t dev) { - unsigned port = dev>>8; + u16 port = dev >> 8; outb(0x55, port); } static void pnp_exit_conf_state(device_t dev) { - unsigned port = dev>>8; + u16 port = dev >> 8; outb(0xaa, port); } -static inline void lpc47m15x_enable_serial(device_t dev, unsigned iobase) +static void lpc47m15x_enable_serial(device_t dev, u16 iobase) { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); Modified: trunk/src/superio/smsc/lpc47m15x/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47m15x/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47m15x/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -56,16 +56,17 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, LPC47M15X_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, LPC47M15X_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, LPC47M15X_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, LPC47M15X_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, LPC47M15X_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, + { &ops, LPC47M15X_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, LPC47M15X_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, LPC47M15X_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, LPC47M15X_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, LPC47M15X_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, }; static void enable_dev(device_t dev) { - pnp_enable_devices(dev, &pnp_ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); + pnp_enable_devices(dev, &pnp_ops, + ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } static void lpc47m15x_pnp_set_resources(device_t dev) @@ -86,13 +87,7 @@ { pnp_enter_conf_state(dev); pnp_set_logical_device(dev); - - if(dev->enabled) { - pnp_set_enable(dev, 1); - } - else { - pnp_set_enable(dev, 0); - } + pnp_set_enable(dev, (dev->enabled) ? 1 : 0); pnp_exit_conf_state(dev); } @@ -109,12 +104,10 @@ res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; - case LPC47M15X_SP2: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com2); break; - case LPC47M15X_KBC: pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/smsc/lpc47n217/Makefile.inc ============================================================================== --- trunk/src/superio/smsc/lpc47n217/Makefile.inc Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47n217/Makefile.inc Mon Nov 15 20:35:14 2010 (r6073) @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_SMSC_LPC47N217) += superio.c + Modified: trunk/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c ============================================================================== --- trunk/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47n217/lpc47n217_early_serial.c Mon Nov 15 20:35:14 2010 (r6073) @@ -24,17 +24,15 @@ #include <assert.h> #include "lpc47n217.h" -/** Enable access to the LPC47N217's configuration registers. */ -static inline void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(device_t dev) { - unsigned port = dev>>8; + u16 port = dev >> 8; outb(0x55, port); } -/** Disable access to the LPC47N217's configuration registers. */ static void pnp_exit_conf_state(device_t dev) { - unsigned port = dev>>8; + u16 port = dev >> 8; outb(0xaa, port); } @@ -44,24 +42,21 @@ * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Base I/O port for the logical device. */ -void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase) +void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) { - /* LPC47N217 requires base ports to be a multiple of 4 */ + /* LPC47N217 requires base ports to be a multiple of 4. */ ASSERT(!(iobase & 0x3)); switch(dev & 0xFF) { case LPC47N217_PP: pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff); break; - case LPC47N217_SP1: pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff); break; - case LPC47N217_SP2: pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff); break; - default: break; } @@ -81,37 +76,29 @@ */ void lpc47n217_pnp_set_enable(device_t dev, int enable) { - uint8_t power_register = 0; - uint8_t power_mask = 0; - uint8_t current_power; - uint8_t new_power; + u8 power_register = 0, power_mask = 0, current_power, new_power; switch(dev & 0xFF) { case LPC47N217_PP: power_register = 0x01; power_mask = 0x04; break; - case LPC47N217_SP1: power_register = 0x02; power_mask = 0x08; break; - case LPC47N217_SP2: power_register = 0x02; power_mask = 0x80; break; - default: return; } current_power = pnp_read_config(dev, power_register); - new_power = current_power & ~power_mask; /* disable by default */ - + new_power = current_power & ~power_mask; /* Disable by default. */ if (enable) - new_power |= power_mask; /* Enable */ - + new_power |= power_mask; /* Enable. */ pnp_write_config(dev, power_register, new_power); } @@ -122,7 +109,7 @@ * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47n217_enable_serial(device_t dev, unsigned iobase) +static void lpc47n217_enable_serial(device_t dev, u16 iobase) { /* * NOTE: Cannot use pnp_set_XXX() here because they assume chip Modified: trunk/src/superio/smsc/lpc47n217/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47n217/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47n217/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -22,7 +22,6 @@ */ /* RAM-based driver for SMSC LPC47N217 Super I/O chip. */ -/* Based on coreboot code for SMSC 47B397. */ #include <arch/io.h> #include <device/device.h> @@ -43,13 +42,11 @@ static void lpc47n217_pnp_enable_resources(device_t dev); static void lpc47n217_pnp_enable(device_t dev); static void lpc47n217_init(device_t dev); - static void lpc47n217_pnp_set_resource(device_t dev, struct resource *resource); -static void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase); -static void lpc47n217_pnp_set_drq(device_t dev, unsigned drq); -static void lpc47n217_pnp_set_irq(device_t dev, unsigned irq); +static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase); +static void lpc47n217_pnp_set_drq(device_t dev, u8 drq); +static void lpc47n217_pnp_set_irq(device_t dev, u8 irq); static void lpc47n217_pnp_set_enable(device_t dev, int enable); - static void pnp_enter_conf_state(device_t dev); static void pnp_exit_conf_state(device_t dev); @@ -67,9 +64,9 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, } + { &ops, LPC47N217_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, LPC47N217_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, LPC47N217_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, } }; /** @@ -88,6 +85,9 @@ * Configure the specified Super I/O device with the resources (I/O space, * etc.) that have been allocate for it. * + * NOTE: Cannot use pnp_set_resources() here because it assumes chip + * support for logical devices, which the LPC47N217 doesn't have. + * * @param dev Pointer to structure describing a Super I/O device. */ static void lpc47n217_pnp_set_resources(device_t dev) @@ -95,46 +95,31 @@ struct resource *res; pnp_enter_conf_state(dev); - - /* NOTE: Cannot use pnp_set_resources() here because it assumes chip - * support for logical devices, which the LPC47N217 doesn't have - */ - for(res = dev->resource_list; res; res = res->next) + for (res = dev->resource_list; res; res = res->next) lpc47n217_pnp_set_resource(dev, res); - /* dump_pnp_device(dev); */ - pnp_exit_conf_state(dev); } +/* + * NOTE: Cannot use pnp_enable_resources() here because it assumes chip + * support for logical devices, which the LPC47N217 doesn't have. + */ static void lpc47n217_pnp_enable_resources(device_t dev) { pnp_enter_conf_state(dev); - - /* - * NOTE: Cannot use pnp_enable_resources() here because it assumes chip - * support for logical devices, which the LPC47N217 doesn't have. - */ lpc47n217_pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); } +/* + * NOTE: Cannot use pnp_set_enable() here because it assumes chip + * support for logical devices, which the LPC47N217 doesn't have. + */ static void lpc47n217_pnp_enable(device_t dev) { pnp_enter_conf_state(dev); - - /* - * NOTE: Cannot use pnp_set_enable() here because it assumes chip - * support for logical devices, which the LPC47N217 doesn't have. - */ - if(dev->enabled) { - lpc47n217_pnp_set_enable(dev, 1); - } - else { - lpc47n217_pnp_set_enable(dev, 0); - } - + lpc47n217_pnp_set_enable(dev, (dev->enabled) ? 1 : 0); pnp_exit_conf_state(dev); } @@ -159,7 +144,6 @@ res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; - case LPC47N217_SP2: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com2); @@ -171,27 +155,25 @@ { if (!(resource->flags & IORESOURCE_ASSIGNED)) { printk(BIOS_ERR, "ERROR: %s %02x not allocated\n", - dev_path(dev), resource->index); + dev_path(dev), resource->index); return; } - /* Now store the resource */ + /* Now store the resource. */ + /* * NOTE: Cannot use pnp_set_XXX() here because they assume chip * support for logical devices, which the LPC47N217 doesn't have. */ if (resource->flags & IORESOURCE_IO) { lpc47n217_pnp_set_iobase(dev, resource->base); - } - else if (resource->flags & IORESOURCE_DRQ) { + } else if (resource->flags & IORESOURCE_DRQ) { lpc47n217_pnp_set_drq(dev, resource->base); - } - else if (resource->flags & IORESOURCE_IRQ) { + } else if (resource->flags & IORESOURCE_IRQ) { lpc47n217_pnp_set_irq(dev, resource->base); - } - else { + } else { printk(BIOS_ERR, "ERROR: %s %02x unknown resource type\n", - dev_path(dev), resource->index); + dev_path(dev), resource->index); return; } resource->flags |= IORESOURCE_STORED; @@ -199,7 +181,7 @@ report_resource_stored(dev, resource, ""); } -static void lpc47n217_pnp_set_iobase(device_t dev, unsigned iobase) +static void lpc47n217_pnp_set_iobase(device_t dev, u16 iobase) { ASSERT(!(iobase & 0x3)); @@ -207,30 +189,28 @@ case LPC47N217_PP: pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff); break; - case LPC47N217_SP1: pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff); break; - case LPC47N217_SP2: pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff); break; - default: BUG(); break; } } -static void lpc47n217_pnp_set_drq(device_t dev, unsigned drq) +static void lpc47n217_pnp_set_drq(device_t dev, u8 drq) { - if (dev->path.pnp.device == LPC47N217_PP) { - const uint8_t PP_DMA_MASK = 0x0F; - const uint8_t PP_DMA_SELECTION_REGISTER = 0x26; - uint8_t current_config = pnp_read_config(dev, PP_DMA_SELECTION_REGISTER); - uint8_t new_config; + const u8 PP_DMA_MASK = 0x0F; + const u8 PP_DMA_SELECTION_REGISTER = 0x26; + u8 current_config, new_config; - ASSERT(!(drq & ~PP_DMA_MASK)); /* DRQ out of range?? */ + if (dev->path.pnp.device == LPC47N217_PP) { + current_config = pnp_read_config(dev, + PP_DMA_SELECTION_REGISTER); + ASSERT(!(drq & ~PP_DMA_MASK)); /* DRQ out of range? */ new_config = (current_config & ~PP_DMA_MASK) | drq; pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config); } else { @@ -238,36 +218,31 @@ } } -static void lpc47n217_pnp_set_irq(device_t dev, unsigned irq) +static void lpc47n217_pnp_set_irq(device_t dev, u8 irq) { - uint8_t irq_config_register = 0; - uint8_t irq_config_mask = 0; - uint8_t current_config; - uint8_t new_config; + u8 irq_config_register = 0, irq_config_mask = 0; + u8 current_config, new_config; switch(dev->path.pnp.device) { case LPC47N217_PP: irq_config_register = 0x27; irq_config_mask = 0x0F; break; - case LPC47N217_SP1: irq_config_register = 0x28; irq_config_mask = 0xF0; irq <<= 4; break; - case LPC47N217_SP2: irq_config_register = 0x28; irq_config_mask = 0x0F; break; - default: BUG(); return; } - ASSERT(!(irq & ~irq_config_mask)); /* IRQ out of range?? */ + ASSERT(!(irq & ~irq_config_mask)); /* IRQ out of range? */ current_config = pnp_read_config(dev, irq_config_register); new_config = (current_config & ~irq_config_mask) | irq; @@ -276,54 +251,44 @@ static void lpc47n217_pnp_set_enable(device_t dev, int enable) { - uint8_t power_register = 0; - uint8_t power_mask = 0; - uint8_t current_power; - uint8_t new_power; + u8 power_register = 0, power_mask = 0, current_power, new_power; switch(dev->path.pnp.device) { case LPC47N217_PP: power_register = 0x01; power_mask = 0x04; break; - case LPC47N217_SP1: power_register = 0x02; power_mask = 0x08; break; - case LPC47N217_SP2: power_register = 0x02; power_mask = 0x80; break; - default: BUG(); return; } current_power = pnp_read_config(dev, power_register); - new_power = current_power & ~power_mask; /* disable by default */ - + new_power = current_power & ~power_mask; /* Disable by default. */ if (enable) { - struct resource* ioport_resource = find_resource(dev, PNP_IDX_IO0); + struct resource* ioport_resource; + ioport_resource = find_resource(dev, PNP_IDX_IO0); lpc47n217_pnp_set_iobase(dev, ioport_resource->base); - - new_power |= power_mask; /* Enable */ - + new_power |= power_mask; /* Enable. */ } else { lpc47n217_pnp_set_iobase(dev, 0); } pnp_write_config(dev, power_register, new_power); } -/** Enable access to the LPC47N217's configuration registers. */ static void pnp_enter_conf_state(device_t dev) { outb(0x55, dev->path.pnp.port); } -/** Disable access to the LPC47N217's configuration registers. */ static void pnp_exit_conf_state(device_t dev) { outb(0xaa, dev->path.pnp.port); @@ -339,30 +304,32 @@ */ static void dump_pnp_device(device_t dev) { - int register_index; + int i; print_debug("\n"); - for(register_index = 0; register_index <= LPC47N217_MAX_CONFIG_REGISTER; register_index++) { - uint8_t register_value; + for (i = 0; i <= LPC47N217_MAX_CONFIG_REGISTER; i++) { + u8 register_value; - if ((register_index & 0x0f) == 0) { - print_debug_hex8(register_index); + if ((i & 0x0f) == 0) { + print_debug_hex8(i); print_debug_char(':'); } - /* Skip over 'register' that would cause exit from configuration mode */ - if (register_index == 0xaa) + /* + * Skip over 'register' that would cause exit from + * configuration mode. + */ + if (i == 0xaa) register_value = 0xaa; else - register_value = pnp_read_config(dev, register_index); + register_value = pnp_read_config(dev, i); print_debug_char(' '); print_debug_hex8(register_value); - if ((register_index & 0x0f) == 0x0f) { + if ((i & 0x0f) == 0x0f) print_debug("\n"); - } } - print_debug("\n"); + print_debug("\n"); } #endif Modified: trunk/src/superio/smsc/lpc47n227/Makefile.inc ============================================================================== --- trunk/src/superio/smsc/lpc47n227/Makefile.inc Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47n227/Makefile.inc Mon Nov 15 20:35:14 2010 (r6073) @@ -18,3 +18,4 @@ ## ramstage-$(CONFIG_SUPERIO_SMSC_LPC47N227) += superio.c + Modified: trunk/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c ============================================================================== --- trunk/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47n227/lpc47n227_early_serial.c Mon Nov 15 20:35:14 2010 (r6073) @@ -23,25 +23,15 @@ #include <arch/romcc_io.h> #include "lpc47n227.h" -/** - * Enable access to the LPC47N227's configuration registers. - * - * @param dev High 8 bits = Super I/O port. - */ -static inline void pnp_enter_conf_state(device_t dev) +static void pnp_enter_conf_state(device_t dev) { - unsigned port = dev >> 8; + u16 port = dev >> 8; outb(0x55, port); } -/** - * Disable access to the LPC47N227's configuration registers. - * - * @param dev High 8 bits = Super I/O port. - */ static void pnp_exit_conf_state(device_t dev) { - unsigned port = dev >> 8; + u16 port = dev >> 8; outb(0xaa, port); } @@ -51,24 +41,21 @@ * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Base I/O port for the logical device. */ -void lpc47n227_pnp_set_iobase(device_t dev, unsigned iobase) +void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) { - // LPC47N227 requires base ports to be a multiple of 4 + /* LPC47N227 requires base ports to be a multiple of 4. */ ASSERT(!(iobase & 0x3)); switch (dev & 0xFF) { case LPC47N227_PP: pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff); break; - case LPC47N227_SP1: pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff); break; - case LPC47N227_SP2: pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff); break; - default: break; } @@ -88,37 +75,29 @@ */ void lpc47n227_pnp_set_enable(device_t dev, int enable) { - uint8_t power_register = 0; - uint8_t power_mask = 0; - uint8_t current_power; - uint8_t new_power; + u8 power_register = 0, power_mask = 0, current_power, new_power; switch (dev & 0xFF) { case LPC47N227_PP: power_register = 0x01; power_mask = 0x04; break; - case LPC47N227_SP1: power_register = 0x02; power_mask = 0x08; break; - case LPC47N227_SP2: power_register = 0x02; power_mask = 0x80; break; - default: return; } current_power = pnp_read_config(dev, power_register); - new_power = current_power & ~power_mask; // disable by default - + new_power = current_power & ~power_mask; /* Disable by default. */ if (enable) - new_power |= power_mask; // Enable - + new_power |= power_mask; /* Enable. */ pnp_write_config(dev, power_register, new_power); } @@ -129,7 +108,7 @@ * @param dev High 8 bits = Super I/O port, low 8 bits = logical device number. * @param iobase Processor I/O port address to assign to this serial device. */ -static void lpc47n227_enable_serial(device_t dev, unsigned iobase) +static void lpc47n227_enable_serial(device_t dev, u16 iobase) { /* * NOTE: Cannot use pnp_set_XXX() here because they assume chip Modified: trunk/src/superio/smsc/lpc47n227/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47n227/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/lpc47n227/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -33,41 +33,38 @@ #include "chip.h" #include "lpc47n227.h" -// Forward declarations +/* Forward declarations. */ static void enable_dev(device_t dev); void lpc47n227_pnp_set_resources(device_t dev); void lpc47n227_pnp_enable_resources(device_t dev); void lpc47n227_pnp_enable(device_t dev); static void lpc47n227_init(device_t dev); - static void lpc47n227_pnp_set_resource(device_t dev, struct resource *resource); -void lpc47n227_pnp_set_iobase(device_t dev, unsigned iobase); -void lpc47n227_pnp_set_drq(device_t dev, unsigned drq); -void lpc47n227_pnp_set_irq(device_t dev, unsigned irq); +void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase); +void lpc47n227_pnp_set_drq(device_t dev, u8 drq); +void lpc47n227_pnp_set_irq(device_t dev, u8 irq); void lpc47n227_pnp_set_enable(device_t dev, int enable); - static void pnp_enter_conf_state(device_t dev); static void pnp_exit_conf_state(device_t dev); struct chip_operations superio_smsc_lpc47n227_ops = { CHIP_NAME("SMSC LPC47N227 Super I/O") - .enable_dev = enable_dev, + .enable_dev = enable_dev, }; static struct device_operations ops = { - .read_resources = pnp_read_resources, - .set_resources = lpc47n227_pnp_set_resources, + .read_resources = pnp_read_resources, + .set_resources = lpc47n227_pnp_set_resources, .enable_resources = lpc47n227_pnp_enable_resources, - .enable = lpc47n227_pnp_enable, - .init = lpc47n227_init, + .enable = lpc47n227_pnp_enable, + .init = lpc47n227_init, }; static struct pnp_info pnp_dev_info[] = { - {&ops, LPC47N227_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},}, - {&ops, LPC47N227_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},}, - {&ops, LPC47N227_SP2, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},}, - {&ops, LPC47N227_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0}, - {0x7f8, 0x4},} + { &ops, LPC47N227_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, LPC47N227_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, LPC47N227_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, LPC47N227_KBDC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07f8, 0}, {0x07f8, 4}, }, }; /** @@ -86,6 +83,9 @@ * Configure the specified Super I/O device with the resources (I/O space, * etc.) that have been allocate for it. * + * NOTE: Cannot use pnp_set_resources() here because it assumes chip + * support for logical devices, which the LPC47N227 doesn't have. + * * @param dev Pointer to structure describing a Super I/O device. */ void lpc47n227_pnp_set_resources(device_t dev) @@ -93,44 +93,30 @@ struct resource *res; pnp_enter_conf_state(dev); - - /* - * NOTE: Cannot use pnp_set_resources() here because it assumes chip - * support for logical devices, which the LPC47N227 doesn't have. - */ for (res = dev->resource_list; res; res = res->next) lpc47n227_pnp_set_resource(dev, res); - pnp_exit_conf_state(dev); } +/* + * NOTE: Cannot use pnp_enable_resources() here because it assumes chip + * support for logical devices, which the LPC47N227 doesn't have. + */ void lpc47n227_pnp_enable_resources(device_t dev) { pnp_enter_conf_state(dev); - - /* - * NOTE: Cannot use pnp_enable_resources() here because it assumes chip - * support for logical devices, which the LPC47N227 doesn't have. - */ lpc47n227_pnp_set_enable(dev, 1); - pnp_exit_conf_state(dev); } +/* + * NOTE: Cannot use pnp_set_enable() here because it assumes chip + * support for logical devices, which the LPC47N227 doesn't have. + */ void lpc47n227_pnp_enable(device_t dev) { pnp_enter_conf_state(dev); - - /* - * NOTE: Cannot use pnp_set_enable() here because it assumes chip - * support for logical devices, which the LPC47N227 doesn't have. - */ - if (dev->enabled) { - lpc47n227_pnp_set_enable(dev, 1); - } else { - lpc47n227_pnp_set_enable(dev, 0); - } - + lpc47n227_pnp_set_enable(dev, (dev->enabled) ? 1 : 0); pnp_exit_conf_state(dev); } @@ -155,12 +141,10 @@ res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); break; - case LPC47N227_SP2: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com2); break; - case LPC47N227_KBDC: printk(BIOS_DEBUG, "LPC47N227: Initializing keyboard.\n"); pc_keyboard_init(&conf->keyboard); @@ -172,11 +156,11 @@ { if (!(resource->flags & IORESOURCE_ASSIGNED)) { printk(BIOS_ERR, "ERROR: %s %02lx not allocated\n", - dev_path(dev), resource->index); + dev_path(dev), resource->index); return; } - /* Now store the resource */ + /* Now store the resource. */ /* * NOTE: Cannot use pnp_set_XXX() here because they assume chip * support for logical devices, which the LPC47N227 doesn't have. @@ -189,7 +173,7 @@ lpc47n227_pnp_set_irq(dev, resource->base); } else { printk(BIOS_ERR, "ERROR: %s %02lx unknown resource type\n", - dev_path(dev), resource->index); + dev_path(dev), resource->index); return; } resource->flags |= IORESOURCE_STORED; @@ -197,7 +181,7 @@ report_resource_stored(dev, resource, ""); } -void lpc47n227_pnp_set_iobase(device_t dev, unsigned iobase) +void lpc47n227_pnp_set_iobase(device_t dev, u16 iobase) { ASSERT(!(iobase & 0x3)); @@ -205,33 +189,29 @@ case LPC47N227_PP: pnp_write_config(dev, 0x23, (iobase >> 2) & 0xff); break; - case LPC47N227_SP1: pnp_write_config(dev, 0x24, (iobase >> 2) & 0xff); break; - case LPC47N227_SP2: pnp_write_config(dev, 0x25, (iobase >> 2) & 0xff); break; - case LPC47N227_KBDC: break; - default: BUG(); break; } } -void lpc47n227_pnp_set_drq(device_t dev, unsigned drq) +void lpc47n227_pnp_set_drq(device_t dev, u8 drq) { - if (dev->path.pnp.device == LPC47N227_PP) { - const uint8_t PP_DMA_MASK = 0x0F; - const uint8_t PP_DMA_SELECTION_REGISTER = 0x26; - uint8_t current_config = - pnp_read_config(dev, PP_DMA_SELECTION_REGISTER); - uint8_t new_config; + const u8 PP_DMA_MASK = 0x0F; + const u8 PP_DMA_SELECTION_REGISTER = 0x26; + u8 current_config, new_config; + if (dev->path.pnp.device == LPC47N227_PP) { + current_config = pnp_read_config(dev, + PP_DMA_SELECTION_REGISTER); ASSERT(!(drq & ~PP_DMA_MASK)); // DRQ out of range?? new_config = (current_config & ~PP_DMA_MASK) | drq; pnp_write_config(dev, PP_DMA_SELECTION_REGISTER, new_config); @@ -240,33 +220,27 @@ } } -void lpc47n227_pnp_set_irq(device_t dev, unsigned irq) +void lpc47n227_pnp_set_irq(device_t dev, u8 irq) { - uint8_t irq_config_register = 0; - uint8_t irq_config_mask = 0; - uint8_t current_config; - uint8_t new_config; + u8 irq_config_register = 0, irq_config_mask = 0; + u8 current_config, new_config; switch (dev->path.pnp.device) { case LPC47N227_PP: irq_config_register = 0x27; irq_config_mask = 0x0F; break; - case LPC47N227_SP1: irq_config_register = 0x28; irq_config_mask = 0xF0; irq <<= 4; break; - case LPC47N227_SP2: irq_config_register = 0x28; irq_config_mask = 0x0F; break; - case LPC47N227_KBDC: break; - default: BUG(); return; @@ -279,58 +253,46 @@ void lpc47n227_pnp_set_enable(device_t dev, int enable) { - uint8_t power_register = 0; - uint8_t power_mask = 0; - uint8_t current_power; - uint8_t new_power; + u8 power_register = 0, power_mask = 0, current_power, new_power; switch (dev->path.pnp.device) { case LPC47N227_PP: power_register = 0x01; power_mask = 0x04; break; - case LPC47N227_SP1: power_register = 0x02; power_mask = 0x08; break; - case LPC47N227_SP2: power_register = 0x02; power_mask = 0x80; break; - case LPC47N227_KBDC: break; - default: BUG(); return; } current_power = pnp_read_config(dev, power_register); - new_power = current_power & ~power_mask; // disable by default - + new_power = current_power & ~power_mask; /* Disable by default. */ if (enable) { - struct resource *ioport_resource = - find_resource(dev, PNP_IDX_IO0); + struct resource *ioport_resource; + ioport_resource = find_resource(dev, PNP_IDX_IO0); lpc47n227_pnp_set_iobase(dev, ioport_resource->base); - - new_power |= power_mask; // Enable - + new_power |= power_mask; /* Enable. */ } else { lpc47n227_pnp_set_iobase(dev, 0); } pnp_write_config(dev, power_register, new_power); } -/** Enable access to the LPC47N227's configuration registers. */ static void pnp_enter_conf_state(device_t dev) { outb(0x55, dev->path.pnp.port); } -/** Disable access to the LPC47N227's configuration registers. */ static void pnp_exit_conf_state(device_t dev) { outb(0xaa, dev->path.pnp.port); Modified: trunk/src/superio/smsc/sio10n268/Makefile.inc ============================================================================== --- trunk/src/superio/smsc/sio10n268/Makefile.inc Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/sio10n268/Makefile.inc Mon Nov 15 20:35:14 2010 (r6073) @@ -18,3 +18,4 @@ ## ramstage-$(CONFIG_SUPERIO_SMSC_SIO10N268) += sio10n268.c + Modified: trunk/src/superio/smsc/sio10n268/sio10n268.c ============================================================================== --- trunk/src/superio/smsc/sio10n268/sio10n268.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/sio10n268/sio10n268.c Mon Nov 15 20:35:14 2010 (r6073) @@ -27,13 +27,10 @@ static void init(device_t dev) { - struct superio_smsc_sio10n268_config *conf; + struct superio_smsc_sio10n268_config *conf = dev->chip_info; - if (!dev->enabled) { + if (!dev->enabled) return; - } - - conf = dev->chip_info; switch (dev->path.pnp.device) { case SIO10N268_FDC: /* TODO. */ @@ -58,7 +55,7 @@ /* TODO: FDC, PP, AUX. */ static struct pnp_info pnp_dev_info[] = { - { &ops, SIO10N268_KBDC, PNP_IO0 | PNP_IO1, { 0x7f8, 0 }, { 0x7f8, 0x4}, }, + { &ops, SIO10N268_KBDC, PNP_IO0 | PNP_IO1, {0x07f8, 0}, {0x07f8, 4}, }, }; static void enable_dev(struct device *dev) Modified: trunk/src/superio/smsc/smscsuperio/Makefile.inc ============================================================================== --- trunk/src/superio/smsc/smscsuperio/Makefile.inc Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/smscsuperio/Makefile.inc Mon Nov 15 20:35:14 2010 (r6073) @@ -19,3 +19,4 @@ ## ramstage-$(CONFIG_SUPERIO_SMSC_SMSCSUPERIO) += superio.c + Modified: trunk/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c ============================================================================== --- trunk/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c Mon Nov 15 20:35:14 2010 (r6073) @@ -33,9 +33,9 @@ * @param dev The device to use. * @param iobase The I/O base of the serial port (usually 0x3f8/0x2f8). */ -static inline void smscsuperio_enable_serial(device_t dev, uint16_t iobase) +static void smscsuperio_enable_serial(device_t dev, u16 iobase) { - uint16_t port = dev >> 8; + u16 port = dev >> 8; outb(0x55, port); /* Enter the configuration state. */ pnp_set_logical_device(dev); Modified: trunk/src/superio/smsc/smscsuperio/superio.c ============================================================================== --- trunk/src/superio/smsc/smscsuperio/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/smsc/smscsuperio/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -70,8 +70,8 @@ /* Static variables for the Super I/O device ID and revision. */ static int first_time = 1; -static uint8_t superio_id = 0; -static uint8_t superio_rev = 0; +static u8 superio_id = 0; +static u8 superio_rev = 0; /** * A list of all possible logical devices which may be supported by at least @@ -117,7 +117,7 @@ * The result would be that the init code would be executed twice! */ static const struct logical_devices { - uint8_t superio_id; + u8 superio_id; int devs[MAX_LOGICAL_DEVICES]; } logical_device_table[] = { /* Chip FDC PP SP1 SP2 RTC KBC AUX XBUS HWM GAME PME MPU RT ACPI SMB */ @@ -150,7 +150,7 @@ * * @param dev The device to use. */ -static inline void smsc_pnp_enter_conf_state(device_t dev) +static void smsc_pnp_enter_conf_state(device_t dev) { outb(0x55, dev->path.pnp.port); } @@ -162,7 +162,7 @@ * * @param dev The device to use. */ -static inline void smsc_pnp_exit_conf_state(device_t dev) +static void smsc_pnp_exit_conf_state(device_t dev) { outb(0xaa, dev->path.pnp.port); } @@ -260,20 +260,19 @@ * TODO: FDC, PP, SP1, SP2, and KBC should work, the rest probably not (yet). */ static struct pnp_info pnp_dev_info[] = { - { &ops, LD_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, }, - { &ops, LD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, }, - { &ops, LD_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, LD_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, LD_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, LD_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, LD_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, LD_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, LD_RTC, }, - { &ops, LD_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, - { 0x7ff, 4 },}, + { &ops, LD_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, { &ops, LD_AUX, }, { &ops, LD_XBUS, }, - { &ops, LD_HWM, PNP_IO0, { 0x7f0, 0 }, }, + { &ops, LD_HWM, PNP_IO0, {0x07f0, 0}, }, { &ops, LD_GAME, }, { &ops, LD_PME, }, { &ops, LD_MPU401, }, - { &ops, LD_RT, PNP_IO0, { 0x780, 0 }, }, + { &ops, LD_RT, PNP_IO0, {0x0780, 0}, }, { &ops, LD_ACPI, }, { &ops, LD_SMB, }, }; @@ -291,7 +290,7 @@ { int i, j, fn; int tmp[MAX_LOGICAL_DEVICES]; - uint8_t test7; + u8 test7; if (first_time) { /* Read the device ID and revision of the Super I/O chip. */ @@ -302,21 +301,23 @@ /* TODO: Error handling? */ - printk(BIOS_INFO, "Found SMSC Super I/O (ID=0x%02x, rev=0x%02x)\n", - superio_id, superio_rev); + printk(BIOS_INFO, "Found SMSC Super I/O (ID=0x%02x, " + "rev=0x%02x)\n", superio_id, superio_rev); first_time = 0; - if(superio_id == LPC47M172) { - /* Do not use the default logical device number - * but instead the standard smsc registers set - */ - - /* TEST7 configuration register (0x29) - * bit 0 : LD_NUM (0 = new, 1 = std smsc) - */ - test7 = pnp_read_config(dev, DEVICE_TEST7_REG); - test7 |= 1; - pnp_write_config(dev, DEVICE_TEST7_REG, test7); + if (superio_id == LPC47M172) { + /* + * Do not use the default logical device number but + * instead the standard SMSC registers set. + */ + + /* + * TEST7 configuration register (0x29) + * Bit 0: LD_NUM (0 = new, 1 = std SMSC) + */ + test7 = pnp_read_config(dev, DEVICE_TEST7_REG); + test7 |= (1 << 0); + pnp_write_config(dev, DEVICE_TEST7_REG, test7); } } @@ -333,7 +334,8 @@ for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++) tmp[j] = pnp_dev_info[j].function; - /* Replace the LD_FOO markers in pnp_dev_info[] with + /* + * Replace the LD_FOO markers in pnp_dev_info[] with * the real logical device IDs of this Super I/O chip. */ for (j = 0; j < ARRAY_SIZE(pnp_dev_info); j++) { Modified: trunk/src/superio/via/vt1211/vt1211.c ============================================================================== --- trunk/src/superio/via/vt1211/vt1211.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/via/vt1211/vt1211.c Mon Nov 15 20:35:14 2010 (r6073) @@ -205,17 +205,17 @@ /* TODO: Check if 0x07f8 is correct for FDC/PP/SP1/SP2, the rest is correct. */ static struct pnp_info pnp_dev_info[] = { - { &ops, VT1211_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, }, - { &ops, VT1211_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, }, - { &ops, VT1211_SP1, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 }, }, - { &ops, VT1211_SP2, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 }, }, - { &ops, VT1211_MIDI, PNP_IO0 | PNP_IRQ0, { 0xfffc, 0 }, }, - { &ops, VT1211_GAME, PNP_IO0, { 0xfff8, 0 }, }, - { &ops, VT1211_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, - { &ops, VT1211_WDG, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, - { &ops, VT1211_WUC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, - { &ops, VT1211_HWM, PNP_IO0 | PNP_IRQ0, { 0xff00, 0 }, }, - { &ops, VT1211_FIR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0xff00, 0 }, }, + { &ops, VT1211_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, VT1211_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, VT1211_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, VT1211_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, VT1211_MIDI, PNP_IO0 | PNP_IRQ0, {0xfffc, 0}, }, + { &ops, VT1211_GAME, PNP_IO0, {0xfff8, 0}, }, + { &ops, VT1211_GPIO, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, }, + { &ops, VT1211_WDG, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, }, + { &ops, VT1211_WUC, PNP_IO0 | PNP_IRQ0, {0xfff0, 0}, }, + { &ops, VT1211_HWM, PNP_IO0 | PNP_IRQ0, {0xff00, 0}, }, + { &ops, VT1211_FIR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0xff00, 0}, }, { &ops, VT1211_ROM, }, }; Modified: trunk/src/superio/winbond/w83627dhg/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627dhg/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/winbond/w83627dhg/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -94,18 +94,18 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, W83627DHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x0ff8, 0}, }, - { &ops, W83627DHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x0ff8, 0}, }, - { &ops, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, - { &ops, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, - { &ops, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0xfff, 0 }, { 0xfff, 0x4}, }, + { &ops, W83627DHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, }, + { &ops, W83627DHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x0ff8, 0}, }, + { &ops, W83627DHG_SP1, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, W83627DHG_SP2, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, W83627DHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x0fff, 0}, {0x0fff, 4}, }, /* the next line makes coreboot hang in pnp_enable_devices() */ /* { &ops, W83627DHG_SPI, PNP_IO1, { 0xff8, 0 }, }, */ { &ops, W83627DHG_GPIO6, }, { &ops, W83627DHG_WDTO_PLED, }, { &ops, W83627DHG_GPIO2345, }, { &ops, W83627DHG_ACPI, }, - { &ops, W83627DHG_HWM, PNP_IO0 | PNP_IRQ0, { 0xffe, 0 }, }, + { &ops, W83627DHG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ffe, 0}, }, { &ops, W83627DHG_PECI_SST, }, }; Modified: trunk/src/superio/winbond/w83627ehg/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627ehg/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/winbond/w83627ehg/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -178,17 +178,17 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, W83627EHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83627EHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, - { &ops, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, W83627EHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83627EHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83627EHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83627EHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83627EHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, + { &ops, W83627EHG_SFI, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, W83627EHG_WDTO_PLED, }, { &ops, W83627EHG_ACPI, }, - { &ops, W83627EHG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, - { &ops, W83627EHG_GAME, PNP_IO0, { 0x7ff, 0 }, }, - { &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 } , {0x7fe, 0x4}, }, + { &ops, W83627EHG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, W83627EHG_GAME, PNP_IO0, {0x07ff, 0}, }, + { &ops, W83627EHG_MIDI, PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, }, { &ops, W83627EHG_GPIO1, }, { &ops, W83627EHG_GPIO2, }, { &ops, W83627EHG_GPIO3, }, Modified: trunk/src/superio/winbond/w83627hf/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627hf/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/winbond/w83627hf/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -197,17 +197,17 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, - { &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, }, + { &ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, + { &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, }, { &ops, W83627HF_GPIO2, }, { &ops, W83627HF_GPIO3, }, { &ops, W83627HF_ACPI, }, - { &ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, + { &ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, }; static void enable_dev(struct device *dev) Modified: trunk/src/superio/winbond/w83627thf/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627thf/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/winbond/w83627thf/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -96,17 +96,17 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, W83627THF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83627THF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83627THF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627THF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627THF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, - { &ops, W83627THF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627THF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} }, - /* { W83627THF_GPIO2,}, */ - /* { W83627THF_GPIO3,}, */ - { &ops, W83627THF_ACPI, PNP_IRQ0, }, - { &ops, W83627THF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } }, + { &ops, W83627THF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83627THF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83627THF_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83627THF_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83627THF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, + { &ops, W83627THF_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83627THF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, }, + /* { W83627THF_GPIO2, }, */ + /* { W83627THF_GPIO3, }, */ + { &ops, W83627THF_ACPI, PNP_IRQ0, }, + { &ops, W83627THF_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, }; static void enable_dev(device_t dev) Modified: trunk/src/superio/winbond/w83627thg/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627thg/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/winbond/w83627thg/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -95,16 +95,16 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC1, { 0x7f8, 0 }, }, - { &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, - { &ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} }, - { &ops, W83627THG_GPIO2,}, + { &ops, W83627THG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83627THG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83627THG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83627THG_SP2, PNP_IO0 | PNP_IRQ0 | PNP_MSC1, {0x07f8, 0}, }, + { &ops, W83627THG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1 | PNP_MSC0, {0x07ff, 0}, {0x07ff, 4}, }, + { &ops, W83627THG_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, }, + { &ops, W83627THG_GPIO2, }, { &ops, W83627THG_GPIO3, PNP_EN | PNP_MSC0 | PNP_MSC1, }, - { &ops, W83627THG_ACPI, PNP_IRQ0, }, - { &ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } }, + { &ops, W83627THG_ACPI, PNP_IRQ0, }, + { &ops, W83627THG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, }; static void enable_dev(device_t dev) Modified: trunk/src/superio/winbond/w83627uhg/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627uhg/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/winbond/w83627uhg/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -145,21 +145,21 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, W83627UHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83627UHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83627UHG_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627UHG_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627UHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, - { &ops, W83627UHG_SP3, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, W83627UHG_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83627UHG_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83627UHG_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83627UHG_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83627UHG_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, + { &ops, W83627UHG_SP3, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, { &ops, W83627UHG_GPIO3_4, }, { &ops, W83627UHG_WDTO_PLED_GPIO5_6, }, - { &ops, W83627UHG_GPIO1_2,}, - { &ops, W83627UHG_ACPI, PNP_IRQ0, }, - { &ops, W83627UHG_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 } }, - { &ops, W83627UHG_PECI_SST,}, - { &ops, W83627UHG_SP4, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627UHG_SP5, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83627UHG_SP6, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, W83627UHG_GPIO1_2, }, + { &ops, W83627UHG_ACPI, PNP_IRQ0, }, + { &ops, W83627UHG_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, + { &ops, W83627UHG_PECI_SST, }, + { &ops, W83627UHG_SP4, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83627UHG_SP5, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83627UHG_SP6, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, }; static void enable_dev(device_t dev) Modified: trunk/src/superio/winbond/w83697hf/superio.c ============================================================================== --- trunk/src/superio/winbond/w83697hf/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/winbond/w83697hf/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -95,16 +95,16 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, W83697HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83697HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83697HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83697HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83697HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83697HF_GAME_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 0x4}, }, + { &ops, W83697HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83697HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83697HF_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83697HF_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83697HF_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83697HF_GAME_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, }, { &ops, W83697HF_MIDI_GPIO5, }, { &ops, W83697HF_GPIO234, }, { &ops, W83697HF_ACPI, }, - { &ops, W83697HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, }, + { &ops, W83697HF_HWM, PNP_IO0 | PNP_IRQ0, {0x0ff8, 0}, }, }; static void enable_dev(struct device *dev) Modified: trunk/src/superio/winbond/w83977f/superio.c ============================================================================== --- trunk/src/superio/winbond/w83977f/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/winbond/w83977f/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -94,15 +94,15 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, W83977F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x7f8, 0 }, }, - { &ops, W83977F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x7f8, 0 }, }, - { &ops, W83977F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83977F_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83977F_RTC, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83977F_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7f8, 0 }, { 0x7f8, 0x0}, }, - { &ops, W83977F_IR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83977F_GPIO1, PNP_IO0, { 0x7f8, 0 }, }, - { &ops, W83977F_GPIO2, PNP_IO0, { 0x7f8, 0 }, }, + { &ops, W83977F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83977F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83977F_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83977F_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83977F_RTC, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83977F_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07f8, 0}, {0x07f8, 0}, }, + { &ops, W83977F_IR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83977F_GPIO1, PNP_IO0, {0x07f8, 0}, }, + { &ops, W83977F_GPIO2, PNP_IO0, {0x07f8, 0}, }, }; static void enable_dev(device_t dev) Modified: trunk/src/superio/winbond/w83977tf/superio.c ============================================================================== --- trunk/src/superio/winbond/w83977tf/superio.c Sun Nov 14 22:48:14 2010 (r6072) +++ trunk/src/superio/winbond/w83977tf/superio.c Mon Nov 15 20:35:14 2010 (r6073) @@ -96,14 +96,14 @@ }; static struct pnp_info pnp_dev_info[] = { - { &ops, W83977TF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83977TF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, W83977TF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83977TF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83977TF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, - { &ops, W83977TF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, - { &ops, W83977TF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, { 0x7ff, 0 }, {0x7fe, 4} }, - { &ops, W83977TF_ACPI, PNP_IRQ0, }, + { &ops, W83977TF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83977TF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, W83977TF_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83977TF_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83977TF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, {0x07ff, 4}, }, + { &ops, W83977TF_CIR, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, W83977TF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x07ff, 0}, {0x07fe, 4}, }, + { &ops, W83977TF_ACPI, PNP_IRQ0, }, }; static void enable_dev(device_t dev)

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SATA/IDE failed under 64bit linux
by Liu Tao 15 Nov '10

15 Nov '10

Hello all, I'm using coreboot4 + seabios to boot a K8/RS780/SB710 based board, my SATA disk and DVD-drive connects to SB710's SATA0/SATA1 port. Now the board can boot Ubuntu-10.10-i386 and FedoraCore-13-i686, and everything seems ok, but with 64bit linux OS, including SUSE11-X86_64/ RHEL5.5-X86-64/ Ubuntu-10.10-X86_64, the SATA drive cannot be recognized, the kernel reports "qc time out" during SATA disk scanning, and randomly crashes during this process. I checked the mptable and confirmed the IRQ of ahci is correct. With pci=nomsi parameter, the 32bit kernel boots and works fine, 64bit kernel uses the same irq number and can't detect SATA disk correctly. Without pci=nomsi, 32/64 bit kernel may use different MSI irq number, but the result is same, 32bit ok and 64bit fail. Later I tried to install 64bit linux with IDE harddisk/DVD, seabios successfully boots the installation DVD, but linux can't find any CD-ROM & harddisk. The installation script can eject the DVD-drive, but it can't find the device file to mount and reports no CDROM detected, so the installation can't continue. I think maybe something is wrong with ACPI or other tables bios provides to linux kernel? I'm not familia with the bios/kernel interaction, does anyone has any suggestions on the problem? Thanks very much! -- Regards, Liu Tao

3 3

a question about the file, coreboot_ram
by ali hagigat 15 Nov '10

15 Nov '10

We know that coreboot_ram is written in ROM. So how its linker file(src/arch/i386/coreboot_ram.ld), shows some text and data sections above CONFIG_RAMBASE(like above 1MB) in RAM?

2 1

Trac reminder: list of new ticket(s)
by coreboot tracker 15 Nov '10

15 Nov '10

1 0

P4V800D-X need BIOS modification for PCI-E
by Tomasz Czapiewski 14 Nov '10

14 Nov '10

Hi, I've been told at Phoronix forums few months ago that you can help solve my problem as you really do miracles with BIOS. The problem is that I have Asus P4V800D-X mainboard from few years which has Via PT880Ultra chipset. The mainboard is for Intel Pentium4 with socket 478 and DDR1 and has two graphic slots (AGP x8 and PCI-E 1.0). OT: The MP spec tells it could not handle both cards but I use both Radeons R3xx (AGP RV350 - 9600 and PCI-E RV370 - x300 in multiseat) just fine althrough before doing kernel mode settings on Linux I can see BIOS POST only on one of them but that's not the case... Back to topic... Some time ago I've get PCI-E 2.0 Radeon HD4670 which I wanted to use as a replace for PCI-E 1.0 Radeon X300 and I've saw it runs without problems on different MB but with the same chipset (Asrock 775Dual-VSTA - only PCI-E without AGP, P4/DualCore socket 775, both DDR1 and DDR2) after BIOS upgrade served by Asrock. I've found that the card I've get does couply PCI-E 1.0 power requirements specs so it really should be possible to use it on PCI-E 1.0 MBs. When I put this card in PCI-E slot of my MB BIOS and even Linux after BOOT does not see that anything is put in PCI-E slot (lspci, lshw, etc... does not show anything related to this card). I know that CoreBoot site does not list any of MBs that contain such chipset so I'm still stuck with proprietary BIOS from my MB vendor. As I've said before Asrock did release BIOS updates for it's MB with fixes for Radeon HD2xxx and HD3xxx cards (althrough some people reported that after this BIOS update Radeon HD4670 works, too) but Asus did forget about P4V800D-X users long time ago and haven't released and wont release such fixes. I know it will be very hard but could you look at Asrock 775Dual-VSTA BIOS changes (last BIOSes contain only fixes for Radeon HD3xxx cards) and somekind use it for fix my Asus P4V800D-X BIOS to support such cards? I don't even imagine how would you do this but anyway I've get here to ask for help as you're the only people who could do something like this. Thanks in advance. Asus P4V800D-X spec: http://motherboardland.blogspot.com/2006/01/asus-p4v800d-x-motherboard.html Asus P4V800D-X user guide: ftp://ftp.asus.com.tw/pub/ASUS/mb/sock478/p4v800d-x/e2221_P4V800D-X.pdf Asus P4V800D-X BIOS: http://dlcdnet.asus.com/pub/ASUS/mb/sock478/p4v800d-x/P4V8D704.zip Asrock 775Dual-VSTA spec: http://www.asrock.com/mb/overview.asp?Model=775Dual-vsta Asrock 775Dual-VSTA user guide: http://europe.asrock.com/manual/775Dual-VSTA.pdf Asrock 775Dual-VSTA BIOSes with changelogs: http://www.asrock.com/mb/download.asp?Model=775Dual-VSTA&o=BIOS Btw. I don't have EEPROM/BIOS programmer/flasher and my MB has only one BIOS so if you would do that BIOS modifications will flashing it will be a lot more risky than flashing any other official BIOSes? I don't mind if after flashing for any reason I could get not video or sth that would just not break Linux boot from SATA HDD so I could SSH to my machine and flash original BIOS or any other not so hard to use fallback. I don't want to change MB for the next few years because of financial reasons as I have some hardware/peripherals which use could be problematic on never MBs like these two graphic cards, PCI analog TV card, some RS232 connected hardware, a lot of DDR1 RAM, etc. With Regards, Tom

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[commit] r6072 - in trunk/src: mainboard/asus mainboard/asus/a8v-e_deluxe southbridge/via/k8t890
by repository service 14 Nov '10

14 Nov '10

Author: uwe Date: Sun Nov 14 22:48:14 2010 New Revision: 6072 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6072 Log: Add a target for the ASUS A8V-E Deluxe (trivial). For now this is a plain copy of the ASUS A8V-E SE target, I reported that most of the code also works (sort of) for the ASUS A8V-E Deluxe a long while ago, see http://www.coreboot.org/pipermail/coreboot/2008-March/031866.html http://www.coreboot.org/ASUS_A8V-E_Deluxe There will be a bunch of changes necessary though (devicetree.cb, mptable.c, ACPI, etc) which do not apply to the A8V-E SE, so we need an extra target. Also: Increase ID_SECTION_OFFSET on the VIA K8T890/K8M890 southbridge, as otherwise there will be build errors if the MAINBOARD_PART_NUMBER string gets too long (as is the case for "A8V-E Deluxe"). The error is: ld: section .id loaded at [00000000ffffffd2,00000000ffffffef] overlaps section .romstrap loaded at [00000000ffffff80,00000000ffffffd3] (both with stock Debian gcc and with xgcc) Increase ID_SECTION_OFFSET (default 0x10) to 0x80 as other southbridges do. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/src/mainboard/asus/a8v-e_deluxe/ - copied from r6071, trunk/src/mainboard/asus/a8v-e_se/ Modified: trunk/src/mainboard/asus/Kconfig trunk/src/mainboard/asus/a8v-e_deluxe/Kconfig trunk/src/mainboard/asus/a8v-e_deluxe/mainboard.c trunk/src/mainboard/asus/a8v-e_deluxe/mptable.c trunk/src/southbridge/via/k8t890/Kconfig Modified: trunk/src/mainboard/asus/Kconfig ============================================================================== --- trunk/src/mainboard/asus/Kconfig Sun Nov 14 21:10:11 2010 (r6071) +++ trunk/src/mainboard/asus/Kconfig Sun Nov 14 22:48:14 2010 (r6072) @@ -25,6 +25,8 @@ bool "A8N-E" config BOARD_ASUS_A8V_E_SE bool "A8V-E SE" +config BOARD_ASUS_A8V_E_DELUXE + bool "A8V-E Deluxe" config BOARD_ASUS_M2V bool "M2V" config BOARD_ASUS_M2V_MX_SE @@ -52,6 +54,7 @@ source "src/mainboard/asus/a8n_e/Kconfig" source "src/mainboard/asus/a8v-e_se/Kconfig" +source "src/mainboard/asus/a8v-e_deluxe/Kconfig" source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" source "src/mainboard/asus/m4a785-m/Kconfig" Modified: trunk/src/mainboard/asus/a8v-e_deluxe/Kconfig ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/Kconfig Sun Nov 14 21:10:11 2010 (r6071) +++ trunk/src/mainboard/asus/a8v-e_deluxe/Kconfig Sun Nov 14 22:48:14 2010 (r6072) @@ -1,4 +1,4 @@ -if BOARD_ASUS_A8V_E_SE +if BOARD_ASUS_A8V_E_DELUXE config BOARD_SPECIFIC_OPTIONS # dummy def_bool y @@ -20,7 +20,7 @@ config MAINBOARD_DIR string - default asus/a8v-e_se + default asus/a8v-e_deluxe config DCACHE_RAM_BASE hex @@ -44,7 +44,7 @@ config MAINBOARD_PART_NUMBER string - default "A8V-E SE" + default "A8V-E Deluxe" config HW_MEM_HOLE_SIZEK hex @@ -74,4 +74,4 @@ hex default 0x1043 -endif # BOARD_ASUS_A8V_E_SE +endif # BOARD_ASUS_A8V_E_DELUXE Modified: trunk/src/mainboard/asus/a8v-e_deluxe/mainboard.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/mainboard.c Sun Nov 14 21:10:11 2010 (r6071) +++ trunk/src/mainboard/asus/a8v-e_deluxe/mainboard.c Sun Nov 14 22:48:14 2010 (r6072) @@ -24,5 +24,5 @@ #include "chip.h" struct chip_operations mainboard_ops = { - CHIP_NAME("ASUS A8V-E SE Mainboard") + CHIP_NAME("ASUS A8V-E Deluxe Mainboard") }; Modified: trunk/src/mainboard/asus/a8v-e_deluxe/mptable.c ============================================================================== --- trunk/src/mainboard/asus/a8v-e_se/mptable.c Sun Nov 14 21:10:11 2010 (r6071) +++ trunk/src/mainboard/asus/a8v-e_deluxe/mptable.c Sun Nov 14 22:48:14 2010 (r6072) @@ -31,7 +31,7 @@ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - mptable_init(mc, "A8V-E SE ", LAPIC_ADDR); + mptable_init(mc, "A8V-E Deluxe", LAPIC_ADDR); smp_write_processors(mc); Modified: trunk/src/southbridge/via/k8t890/Kconfig ============================================================================== --- trunk/src/southbridge/via/k8t890/Kconfig Sun Nov 14 21:10:11 2010 (r6071) +++ trunk/src/southbridge/via/k8t890/Kconfig Sun Nov 14 22:48:14 2010 (r6072) @@ -37,3 +37,8 @@ default 256 if K8M890_VIDEO_MB_256MB default -1 if K8M890_VIDEO_MB_CMOS depends on SOUTHBRIDGE_VIA_K8M890_VGA_EN + +config ID_SECTION_OFFSET + hex + default 0x80 if SOUTHBRIDGE_VIA_K8M890 || SOUTHBRIDGE_VIA_K8T890 +

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[commit] r6071 - in trunk/src/mainboard: asus/a8n_e gigabyte/m57sli msi/ms7135 msi/ms7260 msi/ms9282 msi/ms9652_fam10 nvidia/l1_2pvv sunw/ultra40 supermicro/h8dme supermicro/h8dmr supermicro/h8dmr_...
by repository service 14 Nov '10

14 Nov '10

Author: uwe Date: Sun Nov 14 21:10:11 2010 New Revision: 6071 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6071 Log: CK804/MCP55 devicetree.cb cosmetic and indentation fixes. Add a few more comments for the entries, and also change the devicetree.cb files to the more compact and better readable variant with indentation level of 2 spaces (instead of random mix of tabs and spaces). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/asus/a8n_e/devicetree.cb trunk/src/mainboard/gigabyte/m57sli/devicetree.cb trunk/src/mainboard/msi/ms7135/devicetree.cb trunk/src/mainboard/msi/ms7260/devicetree.cb trunk/src/mainboard/msi/ms9282/devicetree.cb trunk/src/mainboard/msi/ms9652_fam10/devicetree.cb trunk/src/mainboard/nvidia/l1_2pvv/devicetree.cb trunk/src/mainboard/sunw/ultra40/devicetree.cb trunk/src/mainboard/supermicro/h8dme/devicetree.cb trunk/src/mainboard/supermicro/h8dmr/devicetree.cb trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb trunk/src/mainboard/supermicro/h8qme_fam10/devicetree.cb trunk/src/mainboard/tyan/s2891/devicetree.cb trunk/src/mainboard/tyan/s2892/devicetree.cb trunk/src/mainboard/tyan/s2895/devicetree.cb trunk/src/mainboard/tyan/s2912/devicetree.cb trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb Modified: trunk/src/mainboard/asus/a8n_e/devicetree.cb ============================================================================== --- trunk/src/mainboard/asus/a8n_e/devicetree.cb Sun Nov 14 15:39:29 2010 (r6070) +++ trunk/src/mainboard/asus/a8n_e/devicetree.cb Sun Nov 14 21:10:11 2010 (r6071) @@ -1,14 +1,13 @@ chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_939 # Socket 939 CPU - device lapic 0 on end # APIC + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_939 # CPU socket + device lapic 0 on end # Local APIC of the CPU end end device pci_domain 0 on # PCI domain - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 chip southbridge/nvidia/ck804 # Southbridge device pci 0.0 on end # HT device pci 1.0 on # LPC @@ -62,7 +61,7 @@ io 0xc8 = 0x0000 io 0xca = 0x0500 end - device pnp 2e.8 on # Midi port + device pnp 2e.8 on # MIDI port io 0x60 = 0x300 irq 0x70 = 10 end @@ -76,28 +75,28 @@ end end device pci 1.1 on # SM 0 - # chip drivers/generic/generic #dimm 0-0-0 + # chip drivers/generic/generic # DIMM 0-0-0 # device i2c 50 on end # end - # chip drivers/generic/generic #dimm 0-0-1 + # chip drivers/generic/generic # DIMM 0-0-1 # device i2c 51 on end # end - # chip drivers/generic/generic #dimm 0-1-0 + # chip drivers/generic/generic # DIMM 0-1-0 # device i2c 52 on end # end - # chip drivers/generic/generic #dimm 0-1-1 + # chip drivers/generic/generic # DIMM 0-1-1 # device i2c 53 on end # end - # chip drivers/generic/generic #dimm 1-0-0 + # chip drivers/generic/generic # DIMM 1-0-0 # device i2c 54 on end # end - # chip drivers/generic/generic #dimm 1-0-1 + # chip drivers/generic/generic # DIMM 1-0-1 # device i2c 55 on end # end - # chip drivers/generic/generic #dimm 1-1-0 + # chip drivers/generic/generic # DIMM 1-1-0 # device i2c 56 on end # end - # chip drivers/generic/generic #dimm 1-1-1 + # chip drivers/generic/generic # DIMM 1-1-1 # device i2c 57 on end # end end @@ -118,6 +117,7 @@ register "ide1_enable" = "1" register "sata0_enable" = "1" register "sata1_enable" = "1" + # TODO # register "mac_eeprom_smbus" = "3" # register "mac_eeprom_addr" = "0x51" end Modified: trunk/src/mainboard/gigabyte/m57sli/devicetree.cb ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/devicetree.cb Sun Nov 14 15:39:29 2010 (r6070) +++ trunk/src/mainboard/gigabyte/m57sli/devicetree.cb Sun Nov 14 21:10:11 2010 (r6071) @@ -1,174 +1,177 @@ -chip northbridge/amd/amdk8/root_complex - device lapic_cluster 0 on - chip cpu/amd/socket_AM2 - device lapic 0 on end - end +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_AM2 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end +end +device pci_domain 0 on # PCI domain + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/ite/it8716f # Super I/O + device pnp 2e.0 on # Floppy and any LDN + # Watchdog from CLKIN (24 MHz) + irq 0x23 = 0x11 + # Serial Flash (SPI only) + # 0x24 = 0x1a + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Embedded controller + io 0x60 = 0x290 + io 0x62 = 0x230 + irq 0x70 = 9 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO, SPI flash + # Pin 84 is not GP10 + irq 0x25 = 0x0 + # Pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 + irq 0x26 = 0x43 + # Pin 13 is GP35 + irq 0x27 = 0x20 + # Pin 70 is not GP46 + # irq 0x28 = 0x0 + # Pin 6,3,128,127,126 is GP63,64,65,66,67 + irq 0x29 = 0x81 + # Enable FAN_CTL/FAN_TAC set to 5 (pin 21, 23), + # enable FAN_CTL/FAN_TAC set to 4 (pin 20, 22), + # pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal + # voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal + # voltage divider for VCC5V + # irq 0x2c = 0x1f + # Simple I/O base + io 0x62 = 0x800 + # Serial Flash I/O (SPI only) + io 0x64 = 0x820 + # Watchdog force timeout (parallel flash only) + # irq 0x71 = 0x1 + # No WDT interrupt + irq 0x72 = 0x0 + # GPIO pin set 1 disable internal pullup + irq 0xb8 = 0x0 + # GPIO pin set 5 enable internal pullup + irq 0xbc = 0x01 + # SIO pin set 1 alternate function + # irq 0xc0 = 0x0 + # SIO pin set 2 mixed function + irq 0xc1 = 0x43 + # SIO pin set 3 mixed function + irq 0xc2 = 0x20 + # SIO pin set 4 alternate function + # irq 0xc3 = 0x0 + # SIO pin set 1 input mode + # irq 0xc8 = 0x0 + # SIO pin set 2 input mode + irq 0xc9 = 0x0 + # SIO pin set 4 input mode + # irq 0xcb = 0x0 + # Generate SMI# on EC IRQ + # irq 0xf0 = 0x10 + # SMI# level trigger + # irq 0xf1 = 0x40 + # HWMON alert beep pin location + irq 0xf6 = 0x28 + end + device pnp 2e.8 off # MIDI + io 0x60 = 0x300 + irq 0x70 = 10 + end + device pnp 2e.9 off # Game port + io 0x60 = 0x220 + end + device pnp 2e.a off end # Consumer IR + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on end # PCI + device pci 6.1 on end # AUDIO + device pci 8.0 on end # NIC + device pci 9.0 off end # N/A + device pci a.0 on end # PCI E 5 + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.0 on end # Link 1 + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end + # chip drivers/generic/debug + # device pnp 0.0 off end # chip name + # device pnp 0.1 on end # pci_regs_all + # device pnp 0.2 on end # mem + # device pnp 0.3 off end # cpuid + # device pnp 0.4 on end # smbus_regs_all + # device pnp 0.5 off end # dual core msr + # device pnp 0.6 off end # cache size + # device pnp 0.7 off end # tsc + # device pnp 0.8 off end # io + # device pnp 0.9 off end # io + # end end -device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/ite/it8716f - # Floppy and any LDN - device pnp 2e.0 on - # Watchdog from CLKIN, CLKIN = 24 MHz - irq 0x23 = 0x11 - # Serial Flash (SPI only) - #0x24 = 0x1a - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.2 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.3 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # EC - io 0x60 = 0x290 - io 0x62 = 0x230 - irq 0x70 = 9 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - end - device pnp 2e.6 on # Mouse - irq 0x70 = 12 - end - device pnp 2e.7 on # GPIO, SPI flash - # pin 84 is not GP10 - irq 0x25 = 0x0 - # pin 21 is GP26, pin 26 is GP21, pin 27 is GP20 - irq 0x26 = 0x43 - # pin 13 is GP35 - irq 0x27 = 0x20 - # pin 70 is not GP46 - #irq 0x28 = 0x0 - # pin 6,3,128,127,126 is GP63,64,65,66,67 - irq 0x29 = 0x81 - # Enable FAN_CTL/FAN_TAC set to 5 (pin 21,23), enable FAN_CTL/FAN_TAC set to 4 (pin 20,22), pin 48 is PCIRST5#, pin91 is PCIRSTIN#, VIN7 is internal voltage divider for VCCH5V, pin 95 is ATXPG, VIN3 is internal voltage divider for VCC5V - #irq 0x2c = 0x1f - # Simple I/O base - io 0x62 = 0x800 - # Serial Flash I/O (SPI only) - io 0x64 = 0x820 - # watch dog force timeout (parallel flash only) - #irq 0x71 = 0x1 - # No WDT interrupt - irq 0x72 = 0x0 - # GPIO pin set 1 disable internal pullup - irq 0xb8 = 0x0 - # GPIO pin set 5 enable internal pullup - irq 0xbc = 0x01 - # SIO pin set 1 alternate function - #irq 0xc0 = 0x0 - # SIO pin set 2 mixed function - irq 0xc1 = 0x43 - # SIO pin set 3 mixed function - irq 0xc2 = 0x20 - # SIO pin set 4 alternate function - #irq 0xc3 = 0x0 - # SIO pin set 1 input mode - #irq 0xc8 = 0x0 - # SIO pin set 2 input mode - irq 0xc9 = 0x0 - # SIO pin set 4 input mode - #irq 0xcb = 0x0 - # Generate SMI# on EC IRQ - #irq 0xf0 = 0x10 - # SMI# level trigger - #irq 0xf1 = 0x40 - # HWMON alert beep pin location - irq 0xf6 = 0x28 - end - device pnp 2e.8 off # MIDI - io 0x60 = 0x300 - irq 0x70 = 10 - end - device pnp 2e.9 off # GAME - io 0x60 = 0x220 - end - device pnp 2e.a off end # CIR - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 on end # AUDIO - device pci 8.0 on end # NIC - device pci 9.0 off end # N/A - device pci a.0 on end # PCI E 5 - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end #device pci 18.0 - device pci 18.0 on end # Link 1 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # mc0 - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 on end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 off end # io -# end -end #root_complex Modified: trunk/src/mainboard/msi/ms7135/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms7135/devicetree.cb Sun Nov 14 15:39:29 2010 (r6070) +++ trunk/src/mainboard/msi/ms7135/devicetree.cb Sun Nov 14 21:10:11 2010 (r6071) @@ -1,14 +1,13 @@ chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_754 # Socket 754 CPU - device lapic 0 on end # APIC + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_754 # CPU socket + device lapic 0 on end # Local APIC of the CPU end end device pci_domain 0 on # PCI domain - chip northbridge/amd/amdk8 # mc0 - device pci 18.0 on # Northbridge - # Devices on link 0, link 0 == LDT 0 + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 chip southbridge/nvidia/ck804 # Southbridge device pci 0.0 on end # HT device pci 1.0 on # LPC @@ -52,14 +51,14 @@ device pci 2.0 on end # USB 1.1 device pci 2.1 on end # USB 2 device pci 4.0 on end # Onboard audio (ACI) - device pci 4.1 off end # Onboard modem (MCI) -- not wired out + device pci 4.1 off end # Onboard modem (MCI), N/A device pci 6.0 on end # IDE device pci 7.0 on end # SATA 1 device pci 8.0 on end # SATA 0 device pci 9.0 on end # PCI device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 -- not wired out - device pci c.0 off end # PCI E 2 -- not wired out + device pci b.0 off end # PCI E 3 (N/A) + device pci c.0 off end # PCI E 2 (N/A) device pci d.0 on end # PCI E 1 device pci e.0 on end # PCI E 0 register "ide0_enable" = "1" Modified: trunk/src/mainboard/msi/ms7260/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms7260/devicetree.cb Sun Nov 14 15:39:29 2010 (r6070) +++ trunk/src/mainboard/msi/ms7260/devicetree.cb Sun Nov 14 21:10:11 2010 (r6071) @@ -1,13 +1,12 @@ chip northbridge/amd/amdk8/root_complex # Root complex - device lapic_cluster 0 on # APIC cluster - chip cpu/amd/socket_AM2 # CPU - device lapic 0 on end # APIC + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_AM2 # CPU socket + device lapic 0 on end # Local APIC of the CPU end end device pci_domain 0 on # PCI domain - chip northbridge/amd/amdk8 # Northbridge / mc0 - device pci 18.0 on - # Devices on link 0, link 0 == LDT 0 + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 chip southbridge/nvidia/mcp55 # Southbridge device pci 0.0 on end # HT device pci 1.0 on # LPC @@ -83,19 +82,19 @@ end # TODO: Check if the stuff below is correct / needed. device pci 1.1 on # SM 1 - # PCI device SMBus address will depend on addon PCI device, - # do we need to scan_smbus_bus? - - # chip drivers/generic/generic # PCIXA Slot1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 # device i2c 50 on end # end - # chip drivers/generic/generic # PCIXB Slot1 + # chip drivers/generic/generic # PCIXB slot 1 # device i2c 51 on end # end - # chip drivers/generic/generic # PCIXB Slot2 + # chip drivers/generic/generic # PCIXB slot 2 # device i2c 52 on end # end - # chip drivers/generic/generic # PCI Slot1 + # chip drivers/generic/generic # PCI slot 1 # device i2c 53 on end # end # chip drivers/generic/generic # Master MCP55 PCI-E @@ -128,7 +127,8 @@ register "sata0_enable" = "1" register "sata1_enable" = "1" # TODO: Check the two lines below. - register "mac_eeprom_smbus" = "3" # 1: SMBus under 2e.8, 2: SM0 3: SM1 + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" register "mac_eeprom_addr" = "0x51" end end @@ -139,19 +139,17 @@ device pci 18.3 on end end end - -# TODO -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 on end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 off end # io -# end - + # TODO + # chip drivers/generic/debug + # device pnp 0.0 off end # chip name + # device pnp 0.1 on end # pci_regs_all + # device pnp 0.2 on end # mem + # device pnp 0.3 off end # cpuid + # device pnp 0.4 on end # smbus_regs_all + # device pnp 0.5 off end # dual core msr + # device pnp 0.6 off end # cache size + # device pnp 0.7 off end # tsc + # device pnp 0.8 off end # io + # device pnp 0.9 off end # io + # end end Modified: trunk/src/mainboard/msi/ms9282/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms9282/devicetree.cb Sun Nov 14 15:39:29 2010 (r6070) +++ trunk/src/mainboard/msi/ms9282/devicetree.cb Sun Nov 14 21:10:11 2010 (r6071) @@ -1,181 +1,176 @@ -chip northbridge/amd/amdk8/root_complex - device lapic_cluster 0 on - chip cpu/amd/socket_F - device lapic 0 on end +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # Serial flash + io 0x60 = 0x100 + end + device pnp 2e.7 off # Game port, MIDI, GPIO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO2, GPIO3, GPIO4, GPIO5 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/i2c/i2cmux2 # PCA9554 SMBus mux + device i2c 70 on # 0 pca9554 1 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 57 on end + end + end + device i2c 70 on # 0 pca9554 2 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 57 on end + end + end + end + end + device pci 1.1 on # SM 1 + chip drivers/i2c/i2cmux2 # pca9554 SMBus mux + device i2c 72 on # PCA9554 channel 1 + chip drivers/i2c/adm1027 # HWM ADT7476 1 + device i2c 2e on end + end + end + device i2c 72 on # PCA9545 channel 2 + chip drivers/i2c/adm1027 # HWM ADT7463 + device i2c 2e on end + end + end + device i2c 72 on end # PCA9545 channel 3 + device i2c 72 on # PCA9545 channel 4 + chip drivers/i2c/adm1027 # HWM ADT7476 2 + device i2c 2e on end + end + end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # P2P + device pci 4.0 on end + end + device pci 7.0 on end # reserve + device pci 8.0 on end # MAC0 + device pci 9.0 on end # MAC1 + device pci a.0 on + device pci 0.0 on + device pci 4.0 on end # PCI-E LAN1 + device pci 4.1 on end # PCI-E LAN2 + end + end # 0x376 + device pci b.0 on end # PCI E 0x374 + device pci c.0 on end + device pci d.0 on # SAS + device pci 0.0 on end + end # PCI E 1 0x378 + device pci e.0 on end # PCI E 0 0x375 + device pci f.0 on end # PCI E 0x377, PCI-E slot + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" end - - device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SERIAL_FALSH - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO2_GPIO3_GPIO4_GPIO5 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/i2c/i2cmux2 # pca9554 smbus mux - device i2c 70 on #0 pca9554 1 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 0-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 57 on end - end - end - device i2c 70 on #0 pca9554 2 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 0-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 57 on end - end - end - end - end - device pci 1.1 on # SM 1 - chip drivers/i2c/i2cmux2 # pca9554 smbus mux - device i2c 72 on #pca9554 channle1 - chip drivers/i2c/adm1027 #HWM ADT7476 1 - device i2c 2e on end - end - end - device i2c 72 on #pca9545 channel 2 - chip drivers/i2c/adm1027 #HWM ADT7463 - device i2c 2e on end - end - end - device i2c 72 on end #pca9545 channel 3 - device i2c 72 on #pca9545 channel 4 - chip drivers/i2c/adm1027 #HWM ADT7476 2 - device i2c 2e on end - end - end - end - end - - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on #P2P - device pci 4.0 on end - end # P2P - device pci 7.0 on end # reserve - device pci 8.0 on end # MAC0 - device pci 9.0 on end # MAC1 - device pci a.0 on - device pci 0.0 on - device pci 4.0 on end #pci_E lan1 - device pci 4.1 on end #pci_E lan2 - end - end # 0x376 - device pci b.0 on end # PCI E 0x374 - device pci c.0 on end - device pci d.0 on #SAS - device pci 0.0 on end - end # PCI E 1 0x378 - device pci e.0 on end # PCI E 0 0x375 - device pci f.0 on end #PCI E 0x377 pci_E slot - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - end - end # device pci 18.0 - device pci 18.0 on end # Link 1 - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #mc0 - - end # pci_domain - -# chip drivers/generic/debug -# device pnp 0.0 off end -# device pnp 0.1 off end -# device pnp 0.2 off end -# device pnp 0.3 off end -# device pnp 0.4 off end -# device pnp 0.5 on end -# end -end # root_complex + end + device pci 18.0 on end # Link 1 + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end + # chip drivers/generic/debug + # device pnp 0.0 off end + # device pnp 0.1 off end + # device pnp 0.2 off end + # device pnp 0.3 off end + # device pnp 0.4 off end + # device pnp 0.5 on end + # end +end Modified: trunk/src/mainboard/msi/ms9652_fam10/devicetree.cb ============================================================================== --- trunk/src/mainboard/msi/ms9652_fam10/devicetree.cb Sun Nov 14 15:39:29 2010 (r6070) +++ trunk/src/mainboard/msi/ms9652_fam10/devicetree.cb Sun Nov 14 21:10:11 2010 (r6071) @@ -21,152 +21,153 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -chip northbridge/amd/amdfam10/root_complex - device lapic_cluster 0 on - chip cpu/amd/socket_F_1207 - device lapic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdfam10 #mc0 - device pci 18.0 on # SB on HT link 0.0 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SERIAL_FLASH - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO2_GPIO3_GPIO4_GPIO5 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - device pnp 2e.106 off # Serial flash - io 0x60 = 0x100 - end - device pnp 2e.207 on # MIDI - io 0x62 = 0x330 - irq 0x70 = 0xa - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # SM - device pci 1.1 on # SM 1 -#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# chip drivers/generic/generic #PCIXA Slot1 -# device i2c 50 on end -# end -# chip drivers/generic/generic #PCIXB Slot1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #PCIXB Slot2 -# device i2c 52 on end -# end -# chip drivers/generic/generic #PCI Slot1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #Master MCP55 PCI-E -# device i2c 54 on end -# end -# chip drivers/generic/generic #Slave MCP55 PCI-E -# device i2c 55 on end -# end -# chip drivers/generic/generic #MAC EEPROM -# device i2c 51 on end -# end - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.0 on end # HT 1.0 - device pci 18.0 on end # HT 2.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end # mc0 - - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 on end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 off end # io -# end -end #root_complex +chip northbridge/amd/amdfam10/root_complex # Root complex + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + device pci 18.0 on # Link 0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # Serial flash + io 0x60 = 0x100 + end + device pnp 2e.7 off # Game port, MIDI, GPIO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO2, GPIO3, GPIO4, GPIO5 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + device pnp 2e.106 off # Serial flash + io 0x60 = 0x100 + end + device pnp 2e.207 on # MIDI + io 0x62 = 0x330 + irq 0x70 = 0xa + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + # chip drivers/generic/generic # MAC EEPROM + # device i2c 51 on end + # end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.0 on end # HT 1.0 + device pci 18.0 on end # HT 2.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end + end + # chip drivers/generic/debug + # device pnp 0.0 off end # chip name + # device pnp 0.1 on end # pci_regs_all + # device pnp 0.2 on end # mem + # device pnp 0.3 off end # cpuid + # device pnp 0.4 on end # smbus_regs_all + # device pnp 0.5 off end # dual core msr + # device pnp 0.6 off end # cache size + # device pnp 0.7 off end # tsc + # device pnp 0.8 off end # io + # device pnp 0.9 off end # io + # end +end Modified: trunk/src/mainboard/nvidia/l1_2pvv/devicetree.cb ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/devicetree.cb Sun Nov 14 15:39:29 2010 (r6070) +++ trunk/src/mainboard/nvidia/l1_2pvv/devicetree.cb Sun Nov 14 21:10:11 2010 (r6071) @@ -1,178 +1,177 @@ -chip northbridge/amd/amdk8/root_complex - device lapic_cluster 0 on - chip cpu/amd/socket_F - device lapic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # SM - device pci 1.1 on # SM 1 -#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# chip drivers/generic/generic #PCIXA Slot1 -# device i2c 50 on end -# end -# chip drivers/generic/generic #PCIXB Slot1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #PCIXB Slot2 -# device i2c 52 on end -# end -# chip drivers/generic/generic #PCI Slot1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #Master MCP55 PCI-E -# device i2c 54 on end -# end -# chip drivers/generic/generic #Slave MCP55 PCI-E -# device i2c 55 on end -# end - chip drivers/generic/generic #MAC EEPROM - device i2c 51 on end - end - - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.0 on end # Link 1 - device pci 18.0 on - # devices on link 2, link 2 == LDT 2 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on end # LPC - device pci 1.1 on end # SM 0 - device pci 2.0 off end # USB 1.1 - device pci 2.1 off end # USB 2 - device pci 4.0 off end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 off end # PCI - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # mc0 - - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 on end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 off end # io -# end -end #root_complex +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, Game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on end # PCI + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.0 on end # Link 1 + device pci 18.0 on # Link 2 == LDT 2 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on end # LPC + device pci 1.1 on end # SM 0 + device pci 2.0 off end # USB 1.1 + device pci 2.1 off end # USB 2 + device pci 4.0 off end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 off end # PCI + device pci 6.1 off end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end + # chip drivers/generic/debug + # device pnp 0.0 off end # chip name + # device pnp 0.1 on end # pci_regs_all + # device pnp 0.2 on end # mem + # device pnp 0.3 off end # cpuid + # device pnp 0.4 on end # smbus_regs_all + # device pnp 0.5 off end # dual core msr + # device pnp 0.6 off end # cache size + # device pnp 0.7 off end # tsc + # device pnp 0.8 off end # io + # device pnp 0.9 off end # io + # end +end Modified: trunk/src/mainboard/sunw/ultra40/devicetree.cb ============================================================================== --- trunk/src/mainboard/sunw/ultra40/devicetree.cb Sun Nov 14 15:39:29 2010 (r6070) +++ trunk/src/mainboard/sunw/ultra40/devicetree.cb Sun Nov 14 21:10:11 2010 (r6071) @@ -1,152 +1,150 @@ -chip northbridge/amd/amdk8/root_complex - device lapic_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_940 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on end + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/smsc/lpc47m10x # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 off # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master CK804 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave CK804 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # ACI + device pci 4.1 off end # MCI + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on end # PCI + device pci a.0 on end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 off end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" end - device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on end # link 0 - device pci 18.0 on # link1 - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/ck804 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/smsc/lpc47m10x - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 off # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # SM - device pci 1.1 on # SM 1 -#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# chip drivers/generic/generic #PCIXA Slot1 -# device i2c 50 on end -# end -# chip drivers/generic/generic #PCIXB Slot1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #PCIXB Slot2 -# device i2c 52 on end -# end -# chip drivers/generic/generic #PCI Slot1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #Master CK804 PCI-E -# device i2c 54 on end -# end -# chip drivers/generic/generic #Slave CK804 PCI-E -# device i2c 55 on end -# end - chip drivers/generic/generic #MAC EEPROM - device i2c 51 on end - end - - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # ACI - device pci 4.1 off end # MCI - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 off end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.0 on end # link 2 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # mc0 - - chip northbridge/amd/amdk8 - device pci 19.0 on end # link 0 - device pci 19.0 on - # devices on link 1, link 1 == LDT 1 - chip southbridge/nvidia/ck804 - device pci 0.0 on end # HT - device pci 1.0 on end # LPC - device pci 1.1 off end # SM - device pci 2.0 off end # USB 1.1 - device pci 2.1 off end # USB 2 - device pci 4.0 off end # ACI - device pci 4.1 off end # MCI - device pci 6.0 off end # IDE - device pci 7.0 off end # SATA 1 - device pci 8.0 off end # SATA 0 - device pci 9.0 off end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 off end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end - end # device pci 19.0 - - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end - end # PCI domain - -end #root_complex + end + device pci 18.0 on end # Link 2 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 19.0 on end # Link 0 + device pci 19.0 on # Link 1 == LDT 1 + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on end # LPC + device pci 1.1 off end # SM + device pci 2.0 off end # USB 1.1 + device pci 2.1 off end # USB 2 + device pci 4.0 off end # ACI + device pci 4.1 off end # MCI + device pci 6.0 off end # IDE + device pci 7.0 off end # SATA 1 + device pci 8.0 off end # SATA 0 + device pci 9.0 off end # PCI + device pci a.0 on end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 off end # PCI E 1 + device pci e.0 on end # PCI E 0 + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + end + end +end Modified: trunk/src/mainboard/supermicro/h8dme/devicetree.cb ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/devicetree.cb Sun Nov 14 15:39:29 2010 (r6070) +++ trunk/src/mainboard/supermicro/h8dme/devicetree.cb Sun Nov 14 21:10:11 2010 (r6071) @@ -1,139 +1,137 @@ -chip northbridge/amd/amdk8/root_complex - device lapic_cluster 0 on - chip cpu/amd/socket_F - device lapic 0 on end - end +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/i2c/i2cmux2 + device i2c 48 off end + device i2c 49 off end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # PCI + device pci 6.0 on end + end + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on # PCI E 5 + device pci 0.0 on end # NEC PCI-X + device pci 0.1 on # NEC PCI-X + device pci 4.0 on end # SCSI + device pci 4.1 on end # SCSI + end + end + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" end - device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/i2c/i2cmux2 - device i2c 48 off end - device i2c 49 off end - end - end # SM - device pci 1.1 on # SM 1 -#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# chip drivers/generic/generic #PCIXA Slot1 -# device i2c 50 on end -# end -# chip drivers/generic/generic #PCIXB Slot1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #PCIXB Slot2 -# device i2c 52 on end -# end -# chip drivers/generic/generic #PCI Slot1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #Master MCP55 PCI-E -# device i2c 54 on end -# end -# chip drivers/generic/generic #Slave MCP55 PCI-E -# device i2c 55 on end -# end - chip drivers/generic/generic #MAC EEPROM - device i2c 51 on end - end - - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 6.0 on end - end - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on # PCI E 5 - device pci 0.0 on #nec pci-x - end - device pci 0.1 on #nec pci-x - device pci 4.0 on end #scsi - device pci 4.1 on end #scsi - end - end - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # mc0 - - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 on end # io -# end -end #root_complex + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end + # chip drivers/generic/debug + # device pnp 0.0 off end # chip name + # device pnp 0.1 on end # pci_regs_all + # device pnp 0.2 off end # mem + # device pnp 0.3 off end # cpuid + # device pnp 0.4 on end # smbus_regs_all + # device pnp 0.5 off end # dual core msr + # device pnp 0.6 off end # cache size + # device pnp 0.7 off end # tsc + # device pnp 0.8 off end # io + # device pnp 0.9 on end # io + # end +end Modified: trunk/src/mainboard/supermicro/h8dmr/devicetree.cb ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/devicetree.cb Sun Nov 14 15:39:29 2010 (r6070) +++ trunk/src/mainboard/supermicro/h8dmr/devicetree.cb Sun Nov 14 21:10:11 2010 (r6071) @@ -1,159 +1,157 @@ -chip northbridge/amd/amdk8/root_complex - device lapic_cluster 0 on - chip cpu/amd/socket_F - device lapic 0 on end - end +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # PCI + device pci 6.0 on end + end + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on # PCI E 5 + device pci 0.0 on end # NEC PCI-X + device pci 0.1 on # NEC PCI-X + device pci 4.0 on end # SCSI + device pci 4.1 on end # SCSI + end + end + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" end - device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # SM - device pci 1.1 on # SM 1 -#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# chip drivers/generic/generic #PCIXA Slot1 -# device i2c 50 on end -# end -# chip drivers/generic/generic #PCIXB Slot1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #PCIXB Slot2 -# device i2c 52 on end -# end -# chip drivers/generic/generic #PCI Slot1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #Master MCP55 PCI-E -# device i2c 54 on end -# end -# chip drivers/generic/generic #Slave MCP55 PCI-E -# device i2c 55 on end -# end - chip drivers/generic/generic #MAC EEPROM - device i2c 51 on end - end - - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 6.0 on end - end - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on # PCI E 5 - device pci 0.0 on #nec pci-x - end - device pci 0.1 on #nec pci-x - device pci 4.0 on end #scsi - device pci 4.1 on end #scsi - end - end - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # mc0 - - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 on end # io -# end -end #root_complex + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end + # chip drivers/generic/debug + # device pnp 0.0 off end # chip name + # device pnp 0.1 on end # pci_regs_all + # device pnp 0.2 off end # mem + # device pnp 0.3 off end # cpuid + # device pnp 0.4 on end # smbus_regs_all + # device pnp 0.5 off end # dual core msr + # device pnp 0.6 off end # cache size + # device pnp 0.7 off end # tsc + # device pnp 0.8 off end # io + # device pnp 0.9 on end # io + # end +end Modified: trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb Sun Nov 14 15:39:29 2010 (r6070) +++ trunk/src/mainboard/supermicro/h8dmr_fam10/devicetree.cb Sun Nov 14 21:10:11 2010 (r6071) @@ -1,165 +1,163 @@ -chip northbridge/amd/amdfam10/root_complex - device lapic_cluster 0 on - chip cpu/amd/socket_F_1207 - device lapic 0 on end - end +chip northbridge/amd/amdfam10/root_complex # Root complex + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # SB on link 2.0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # PCI + device pci 6.0 on end + end + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on # PCI E 5 + device pci 0.0 on end # NEC PCI-X + device pci 0.1 on # NEC PCI-X + device pci 4.0 on end # SCSI + device pci 4.1 on end # SCSI + end + end + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" end - device pci_domain 0 on - chip northbridge/amd/amdfam10 #mc0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on - # SB on link 2.0 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # SM - device pci 1.1 on # SM 1 -#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# chip drivers/generic/generic #PCIXA Slot1 -# device i2c 50 on end -# end -# chip drivers/generic/generic #PCIXB Slot1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #PCIXB Slot2 -# device i2c 52 on end -# end -# chip drivers/generic/generic #PCI Slot1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #Master MCP55 PCI-E -# device i2c 54 on end -# end -# chip drivers/generic/generic #Slave MCP55 PCI-E -# device i2c 55 on end -# end - chip drivers/generic/generic #MAC EEPROM - device i2c 51 on end - end - - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on # PCI - device pci 6.0 on end - end - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on # PCI E 5 - device pci 0.0 on #nec pci-x - end - device pci 0.1 on #nec pci-x - device pci 4.0 on end #scsi - device pci 4.1 on end #scsi - end - end - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - end # mc0 - - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 on end # io -# end -end #root_complex + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + device pci 19.4 on end + end + end + # chip drivers/generic/debug + # device pnp 0.0 off end # chip name + # device pnp 0.1 on end # pci_regs_all + # device pnp 0.2 off end # mem + # device pnp 0.3 off end # cpuid + # device pnp 0.4 on end # smbus_regs_all + # device pnp 0.5 off end # dual core msr + # device pnp 0.6 off end # cache size + # device pnp 0.7 off end # tsc + # device pnp 0.8 off end # io + # device pnp 0.9 on end # io + # end +end Modified: trunk/src/mainboard/supermicro/h8qme_fam10/devicetree.cb ============================================================================== --- trunk/src/mainboard/supermicro/h8qme_fam10/devicetree.cb Sun Nov 14 15:39:29 2010 (r6070) +++ trunk/src/mainboard/supermicro/h8qme_fam10/devicetree.cb Sun Nov 14 21:10:11 2010 (r6071) @@ -1,128 +1,126 @@ -chip northbridge/amd/amdfam10/root_complex - device lapic_cluster 0 on - chip cpu/amd/socket_F_1207 - device lapic 0 on end - end +chip northbridge/amd/amdfam10/root_complex # Root complex + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # SB on link 2 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.1 off end # AZA + device pci 7.0 on + device pci 1.0 on end + end + device pci 8.0 off end + device pci 9.0 off end + device pci a.0 on end # PCI E 5 + device pci b.0 on end # PCI E 4 + device pci c.0 on end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" end - device pci_domain 0 on - chip northbridge/amd/amdfam10 #mc0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on - # SB on link 2.0 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on end - device pci 1.1 on # SM 1 -#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# - chip drivers/generic/generic #MAC EEPROM - device i2c 51 on end - end - - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.1 off end # AZA - device pci 7.0 on - device pci 1.0 on end - end - device pci 8.0 off end - device pci 9.0 off end - device pci a.0 on end # PCI E 5 - device pci b.0 on end # PCI E 4 - device pci c.0 on end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on - chip southbridge/amd/amd8132 - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on - device pci 3.0 on end - device pci 3.1 on end - end - device pci 1.1 on end - end #amd8132 - end #device pci 19.0 - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - device pci 19.4 on end - end # mc0 - - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 on end # io -# end -end #root_complex + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 19.0 on end + device pci 19.0 on end + device pci 19.0 on + chip southbridge/amd/amd8132 + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on + device pci 3.0 on end + device pci 3.1 on end + end + device pci 1.1 on end + end + end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + device pci 19.4 on end + end + end + # chip drivers/generic/debug + # device pnp 0.0 off end # chip name + # device pnp 0.1 on end # pci_regs_all + # device pnp 0.2 off end # mem + # device pnp 0.3 off end # cpuid + # device pnp 0.4 on end # smbus_regs_all + # device pnp 0.5 off end # dual core msr + # device pnp 0.6 off end # cache size + # device pnp 0.7 off end # tsc + # device pnp 0.8 off end # io + # device pnp 0.9 on end # io + # end +end Modified: trunk/src/mainboard/tyan/s2891/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s2891/devicetree.cb Sun Nov 14 15:39:29 2010 (r6070) +++ trunk/src/mainboard/tyan/s2891/devicetree.cb Sun Nov 14 21:10:11 2010 (r6071) @@ -1,152 +1,147 @@ -chip northbridge/amd/amdk8/root_complex - device lapic_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/ck804 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b off # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 -# chip drivers/generic/generic #dimm 0-0-0 -# device i2c 50 on end -# end -# chip drivers/generic/generic #dimm 0-0-1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #dimm 0-1-0 -# device i2c 52 on end -# end -# chip drivers/generic/generic #dimm 0-1-1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #dimm 1-0-0 -# device i2c 54 on end -# end -# chip drivers/generic/generic #dimm 1-0-1 -# device i2c 55 on end -# end -# chip drivers/generic/generic #dimm 1-1-0 -# device i2c 56 on end -# end -# chip drivers/generic/generic #dimm 1-1-1 -# device i2c 57 on end -# end - end # SM -# device pci 1.1 on # SM 1 -# chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 -# device i2c 2d on end -# end -# chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 -# device i2c 2e on end -# end -# chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN -# device i2c 2a on end -# end -# chip drivers/generic/generic # Winbond HWM 0x92 -# device i2c 49 on end -# end -# chip drivers/generic/generic # Winbond HWM 0x94 -# device i2c 4a on end -# end -# end #SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 off end # ACI - device pci 4.1 off end # MCI - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on # PCI - # chip drivers/ati/ragexl - device pci 7.0 on end - end - device pci a.0 off end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - end - end # device pci 18.0 - device pci 18.0 on end # Link 1 - device pci 18.0 on - # devices on link 2, link 2 == LDT 2 - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on - device pci 9.0 on end - device pci 9.1 on end - end - device pci 1.1 on end - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #mc0 - - end # pci_domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 off end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 off end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 on end # hard_reset -# end -end # root_complex +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_940 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # Consumer IR + io 0x60 = 0x100 + end + device pnp 2e.7 off # Game port, MIDI, GPIO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b off # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + # chip drivers/generic/generic # DIMM 0-0-0 + # device i2c 50 on end + # end + # chip drivers/generic/generic # DIMM 0-0-1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # DIMM 0-1-0 + # device i2c 52 on end + # end + # chip drivers/generic/generic # DIMM 0-1-1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # DIMM 1-0-0 + # device i2c 54 on end + # end + # chip drivers/generic/generic # DIMM 1-0-1 + # device i2c 55 on end + # end + # chip drivers/generic/generic # DIMM 1-1-0 + # device i2c 56 on end + # end + # chip drivers/generic/generic # DIMM 1-1-1 + # device i2c 57 on end + # end + end + # device pci 1.1 on # SM 1 + # chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 + # device i2c 2d on end + # end + # chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 + # device i2c 2e on end + # end + # chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN + # device i2c 2a on end + # end + # chip drivers/generic/generic # Winbond HWM 0x92 + # device i2c 49 on end + # end + # chip drivers/generic/generic # Winbond HWM 0x94 + # device i2c 4a on end + # end + # end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 off end # ACI + device pci 4.1 off end # MCI + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on # PCI + # chip drivers/ati/ragexl + device pci 7.0 on end + end + device pci a.0 off end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 on end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end + end + device pci 18.0 on end # Link 1 + device pci 18.0 on # Link 2 == LDT 2 + chip southbridge/amd/amd8131 # Southbridge + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on + device pci 9.0 on end + device pci 9.1 on end + end + device pci 1.1 on end + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end + # chip drivers/generic/debug + # device pnp 0.0 off end # chip name + # device pnp 0.1 off end # pci_regs_all + # device pnp 0.2 off end # mem + # device pnp 0.3 off end # cpuid + # device pnp 0.4 off end # smbus_regs_all + # device pnp 0.5 off end # dual core msr + # device pnp 0.6 off end # cache size + # device pnp 0.7 off end # tsc + # device pnp 0.8 on end # hard_reset + # end +end Modified: trunk/src/mainboard/tyan/s2892/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s2892/devicetree.cb Sun Nov 14 15:39:29 2010 (r6070) +++ trunk/src/mainboard/tyan/s2892/devicetree.cb Sun Nov 14 21:10:11 2010 (r6071) @@ -1,152 +1,147 @@ -chip northbridge/amd/amdk8/root_complex - device lapic_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/ck804 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 3 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # CIR - io 0x60 = 0x100 - end - device pnp 2e.7 off # GAME_MIDI_GIPO1 - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # GPIO2 - device pnp 2e.9 off end # GPIO3 - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # SM - device pci 1.1 on # SM 1 - chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 - device i2c 2d on end - end - chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 - device i2c 2e on end - end - chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN - device i2c 2a on end - end - chip drivers/generic/generic # Winbond HWM 0x92 - device i2c 49 on end - end - chip drivers/generic/generic # Winbond HWM 0x94 - device i2c 4a on end - end - end #SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 off end # ACI - device pci 4.1 off end # MCI - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on # PCI - # chip drivers/ati/ragexl - device pci 6.0 on end - # end - device pci 8.0 on end - end - device pci a.0 off end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 on end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - end - end # device pci 18.0 - device pci 18.0 on end # Link 1 - device pci 18.0 on - # devices on link 2, link 2 == LDT 2 - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on - device pci 9.0 on end # broadcom 5704 - device pci 9.1 on end - end - device pci 1.1 on end - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #mc0 - - end # pci_domain - -# chip drivers/generic/debug -# device pnp 0.0 off end -# device pnp 0.1 off end -# device pnp 0.2 off end -# device pnp 0.3 off end -# device pnp 0.4 off end -# device pnp 0.5 on end -# end -end # root_complex +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_940 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # Consumer IR + io 0x60 = 0x100 + end + device pnp 2e.7 off # Game port, MIDI, GPIO1 + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # GPIO2 + device pnp 2e.9 off end # GPIO3 + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + chip drivers/i2c/adm1027 # ADT7463A CPU0 temp, SYS FAN 2/3/4 + device i2c 2d on end + end + chip drivers/i2c/adm1027 # ADT7463A CPU1 temp, CPU0/1 FAN , SYS FAN 1/5 + device i2c 2e on end + end + chip drivers/generic/generic # Winbond HWM 0x54 CPU0/1 VRM temp, SYSFAN 6/7, SB FAN + device i2c 2a on end + end + chip drivers/generic/generic # Winbond HWM 0x92 + device i2c 49 on end + end + chip drivers/generic/generic # Winbond HWM 0x94 + device i2c 4a on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 off end # ACI + device pci 4.1 off end # MCI + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on # PCI + # chip drivers/ati/ragexl + device pci 6.0 on end + # end + device pci 8.0 on end + end + device pci a.0 off end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 on end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + end + end + device pci 18.0 on end # Link 1 + device pci 18.0 on # Link 2 == LDT 2 + chip southbridge/amd/amd8131 # Southbridge + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on + device pci 9.0 on end # Broadcom 5704 + device pci 9.1 on end + end + device pci 1.1 on end + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end + # chip drivers/generic/debug + # device pnp 0.0 off end + # device pnp 0.1 off end + # device pnp 0.2 off end + # device pnp 0.3 off end + # device pnp 0.4 off end + # device pnp 0.5 on end + # end +end Modified: trunk/src/mainboard/tyan/s2895/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s2895/devicetree.cb Sun Nov 14 15:39:29 2010 (r6070) +++ trunk/src/mainboard/tyan/s2895/devicetree.cb Sun Nov 14 21:10:11 2010 (r6071) @@ -1,168 +1,162 @@ -chip northbridge/amd/amdk8/root_complex - device lapic_cluster 0 on - chip cpu/amd/socket_940 - device lapic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on # northbridge - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/ck804 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/smsc/lpc47b397 - device pnp 2e.0 on # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.3 on # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - drq 0x74 = 4 - end - device pnp 2e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.5 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.7 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.8 on # HW Monitor - io 0x60 = 0x480 - chip drivers/generic/generic # LM95221 CPU temp - device i2c 2b on end - end - chip drivers/generic/generic # EMCT03 - device i2c 54 on end - end - end - device pnp 2e.a on # RT - io 0x60 = 0x400 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # SM - device pci 1.1 on # SM 1 - chip drivers/generic/generic #MAC EEPROM - device i2c 51 on end - end - - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # ACI - device pci 4.1 off end # MCI - device pci 6.0 on end # IDE - device pci 7.0 on end # SATA 1 - device pci 8.0 on end # SATA 0 - device pci 9.0 on end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 off end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "ide1_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.0 on end # Link 1 - device pci 18.0 on - # devices on link 2, link 2 == LDT 2 - chip southbridge/amd/amd8131 - # the on/off keyword is mandatory - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on - device pci 6.0 on end # lsi scsi - device pci 6.1 on end - end - device pci 1.1 on end - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end #mc0 - - chip northbridge/amd/amdk8 - device pci 19.0 on # northbridge - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/ck804 - device pci 0.0 on end # HT - device pci 1.0 on end # LPC - device pci 1.1 off end # SM - device pci 2.0 off end # USB 1.1 - device pci 2.1 off end # USB 2 - device pci 4.0 off end # ACI - device pci 4.1 off end # MCI - device pci 6.0 off end # IDE - device pci 7.0 off end # SATA 1 - device pci 8.0 off end # SATA 0 - device pci 9.0 off end # PCI - device pci a.0 on end # NIC - device pci b.0 off end # PCI E 3 - device pci c.0 off end # PCI E 2 - device pci d.0 off end # PCI E 1 - device pci e.0 on end # PCI E 0 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end - end # device pci 19.0 - - device pci 19.0 on end - device pci 19.0 on end - device pci 19.1 on end - device pci 19.2 on end - device pci 19.3 on end - end - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 off end # pci_regs_all -# device pnp 0.2 off end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# end -end # root_complex +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_940 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/smsc/lpc47b397 # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 4 + end + device pnp 2e.4 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.5 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.7 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.8 on # Hardware monitor + io 0x60 = 0x480 + chip drivers/generic/generic # LM95221 CPU temp + device i2c 2b on end + end + chip drivers/generic/generic # EMCT03 + device i2c 54 on end + end + end + device pnp 2e.a on # RT + io 0x60 = 0x400 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # ACI + device pci 4.1 off end # MCI + device pci 6.0 on end # IDE + device pci 7.0 on end # SATA 1 + device pci 8.0 on end # SATA 0 + device pci 9.0 on end # PCI + device pci a.0 on end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 off end # PCI E 1 + device pci e.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "ide1_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.0 on end # Link 1 + device pci 18.0 on # Link 2 == LDT 2 + chip southbridge/amd/amd8131 # Southbridge + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on + device pci 6.0 on end # LSI SCSI + device pci 6.1 on end + end + device pci 1.1 on end + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 19.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/ck804 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on end # LPC + device pci 1.1 off end # SM + device pci 2.0 off end # USB 1.1 + device pci 2.1 off end # USB 2 + device pci 4.0 off end # ACI + device pci 4.1 off end # MCI + device pci 6.0 off end # IDE + device pci 7.0 off end # SATA 1 + device pci 8.0 off end # SATA 0 + device pci 9.0 off end # PCI + device pci a.0 on end # NIC + device pci b.0 off end # PCI E 3 + device pci c.0 off end # PCI E 2 + device pci d.0 off end # PCI E 1 + device pci e.0 on end # PCI E 0 + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 19.0 on end + device pci 19.0 on end + device pci 19.1 on end + device pci 19.2 on end + device pci 19.3 on end + end + end + # chip drivers/generic/debug + # device pnp 0.0 off end # chip name + # device pnp 0.1 off end # pci_regs_all + # device pnp 0.2 off end # mem + # device pnp 0.3 off end # cpuid + # device pnp 0.4 on end # smbus_regs_all + # device pnp 0.5 off end # dual core msr + # device pnp 0.6 off end # cache size + # device pnp 0.7 off end # tsc + # end +end Modified: trunk/src/mainboard/tyan/s2912/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s2912/devicetree.cb Sun Nov 14 15:39:29 2010 (r6070) +++ trunk/src/mainboard/tyan/s2912/devicetree.cb Sun Nov 14 21:10:11 2010 (r6071) @@ -1,150 +1,149 @@ -chip northbridge/amd/amdk8/root_complex - device lapic_cluster 0 on - chip cpu/amd/socket_F - device lapic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdk8 #mc0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on - # devices on link 0, link 0 == LDT 0 - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # SM - device pci 1.1 on # SM 1 -#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# chip drivers/generic/generic #PCIXA Slot1 -# device i2c 50 on end -# end -# chip drivers/generic/generic #PCIXB Slot1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #PCIXB Slot2 -# device i2c 52 on end -# end -# chip drivers/generic/generic #PCI Slot1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #Master MCP55 PCI-E -# device i2c 54 on end -# end -# chip drivers/generic/generic #Slave MCP55 PCI-E -# device i2c 55 on end -# end - chip drivers/generic/generic #MAC EEPROM - device i2c 51 on end - end - - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end # mc0 - - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 on end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 off end # io -# end -end #root_complex +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on end # PCI + device pci 6.1 off end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end + # chip drivers/generic/debug + # device pnp 0.0 off end # chip name + # device pnp 0.1 on end # pci_regs_all + # device pnp 0.2 on end # mem + # device pnp 0.3 off end # cpuid + # device pnp 0.4 on end # smbus_regs_all + # device pnp 0.5 off end # dual core msr + # device pnp 0.6 off end # cache size + # device pnp 0.7 off end # tsc + # device pnp 0.8 off end # io + # device pnp 0.9 off end # io + # end +end Modified: trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb ============================================================================== --- trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb Sun Nov 14 15:39:29 2010 (r6070) +++ trunk/src/mainboard/tyan/s2912_fam10/devicetree.cb Sun Nov 14 21:10:11 2010 (r6071) @@ -1,153 +1,152 @@ -chip northbridge/amd/amdfam10/root_complex - device lapic_cluster 0 on - chip cpu/amd/socket_F_1207 - device lapic 0 on end - end - end - device pci_domain 0 on - chip northbridge/amd/amdfam10 #mc0 - device pci 18.0 on end - device pci 18.0 on end - device pci 18.0 on - # SB on link 2.0. - chip southbridge/nvidia/mcp55 - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627hf - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel Port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # Keyboard - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.6 off # SFI - io 0x62 = 0x100 - end - device pnp 2e.7 off # GPIO_GAME_MIDI - io 0x60 = 0x220 - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.8 off end # WDTO_PLED - device pnp 2e.9 off end # GPIO_SUSLED - device pnp 2e.a off end # ACPI - device pnp 2e.b on # HW Monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic #dimm 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic #dimm 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic #dimm 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic #dimm 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic #dimm 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic #dimm 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic #dimm 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic #dimm 1-1-1 - device i2c 57 on end - end - end # SM - device pci 1.1 on # SM 1 -#PCI device smbus address will depend on addon pci device, do we need to scan_smbus_bus? -# chip drivers/generic/generic #PCIXA Slot1 -# device i2c 50 on end -# end -# chip drivers/generic/generic #PCIXB Slot1 -# device i2c 51 on end -# end -# chip drivers/generic/generic #PCIXB Slot2 -# device i2c 52 on end -# end -# chip drivers/generic/generic #PCI Slot1 -# device i2c 53 on end -# end -# chip drivers/generic/generic #Master MCP55 PCI-E -# device i2c 54 on end -# end -# chip drivers/generic/generic #Slave MCP55 PCI-E -# device i2c 55 on end -# end - chip drivers/generic/generic #MAC EEPROM - device i2c 51 on end - end - - end # SM - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on - device pci 4.0 on end - end # PCI - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - register "mac_eeprom_smbus" = "3" # 1: smbus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_addr" = "0x51" - end - end # device pci 18.0 - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - end # mc0 - - end # PCI domain - -# chip drivers/generic/debug -# device pnp 0.0 off end # chip name -# device pnp 0.1 on end # pci_regs_all -# device pnp 0.2 on end # mem -# device pnp 0.3 off end # cpuid -# device pnp 0.4 on end # smbus_regs_all -# device pnp 0.5 off end # dual core msr -# device pnp 0.6 off end # cache size -# device pnp 0.7 off end # tsc -# device pnp 0.8 off end # io -# device pnp 0.9 off end # io -# end -end #root_complex +chip northbridge/amd/amdfam10/root_complex # Root complex + device lapic_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F_1207 # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdfam10 # Northbridge / RAM controller + device pci 18.0 on end + device pci 18.0 on end + device pci 18.0 on # SB on link 2 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627hf # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off # SFI + io 0x62 = 0x100 + end + device pnp 2e.7 off # GPIO, game port, MIDI + io 0x60 = 0x220 + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.8 off end # WDTO PLED + device pnp 2e.9 off end # GPIO SUSLED + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on # PCI + device pci 4.0 on end + end + device pci 6.1 off end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + end + end + # chip drivers/generic/debug + # device pnp 0.0 off end # chip name + # device pnp 0.1 on end # pci_regs_all + # device pnp 0.2 on end # mem + # device pnp 0.3 off end # cpuid + # device pnp 0.4 on end # smbus_regs_all + # device pnp 0.5 off end # dual core msr + # device pnp 0.6 off end # cache size + # device pnp 0.7 off end # tsc + # device pnp 0.8 off end # io + # device pnp 0.9 off end # io + # end +end

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build service results for r6070
by repository service 14 Nov '10

14 Nov '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "ruik" checked in revision 6070 to the coreboot repository. This caused the following changes: Change Log: Return 0, (as for 40pin cable if SB not found) Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Build Log: Compilation of asus:m2v has been fixed If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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coreboot November 2010