coreboot November 2010

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[patch] Fintek F71872
by Jonathan A. Kollasch 11 Nov '10

11 Nov '10

Add support for Fintek F71872 superio. Signed-off-by: Jonathan Kollasch <jakllsch(a)kollasch.net> ---

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[PATCH] Avoid hang when 4GB or more DRAM is installed on AMD RS780 UMA systems
by Scott Duplichan 11 Nov '10

11 Nov '10

Avoid hang when 4GB or more DRAM is installed on AMD RS780 UMA systems. -- When building for UMA, reduce the limit for DRAM below 4GB from E0000000 to C0000000. This is needed to accomodate the UMA frame buffer. -- Correct problem where msr C0010010 bits 21 and 22 (MtrrTom2En and Tom2ForceMemTypeWB) are not set consistently across cores. -- Enable TOM2 only if DRAM is present above 4GB. -- Use AMD Tom2ForceMemTypeWB feature to avoid the need for variable MTRR ranges above 4GB. -- Split function x86_setup_var_mtrrs into standard and AMD versions. The AMD version of the function relies on Tom2ForceMemTypeWB for making DRAM above 4GB type WB. The AMD version also incorporates a change to avoid an unexpected variable MTRR range when using UMA graphics. -- Improve white space consistency for mtrr.c by using tabs in place of spaces. Tested on kino-780am2-fam10 with 2GB and 4GB. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Index: src/cpu/amd/mtrr/amd_mtrr.c =================================================================== --- src/cpu/amd/mtrr/amd_mtrr.c (revision 6056) +++ src/cpu/amd/mtrr/amd_mtrr.c (working copy) @@ -107,14 +107,14 @@ unsigned long address_bits; struct mem_state state; unsigned long i; - msr_t msr; + msr_t msr, sys_cfg; /* Enable the access to AMD RdDram and WrDram extension bits */ disable_cache(); - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr); + sys_cfg = rdmsr(SYSCFG_MSR); + sys_cfg.lo |= SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, sys_cfg); enable_cache(); printk(BIOS_DEBUG, "\n"); @@ -148,11 +148,18 @@ msr.lo = state.mmio_basek << 10; wrmsr(TOP_MEM, msr); + // assume no DRAM above 4GB + sys_cfg.lo &= ~SYSCFG_MSR_TOM2En; + sys_cfg.lo &= ~SYSCFG_MSR_TOM2WB; if(state.tomk > (4*1024*1024)) { /* Setup TOP_MEM2 */ msr.hi = state.tomk >> 22; msr.lo = state.tomk << 10; wrmsr(TOP_MEM2, msr); + // enable tom2 + sys_cfg.lo |= SYSCFG_MSR_TOM2En; + // Make DRAM above 4GB WB without using any variable MTRR ranges + sys_cfg.lo |= SYSCFG_MSR_TOM2WB; } /* zero the IORR's before we enable to prevent @@ -167,10 +174,9 @@ * Enable the RdMem and WrMem bits in the fixed mtrrs. * Disable access to the RdMem and WrMem in the fixed mtrr. */ - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_TOM2En; - msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYSCFG_MSR, msr); + sys_cfg.lo |= SYSCFG_MSR_MtrrVarDramEn | SYSCFG_MSR_MtrrFixDramEn; + sys_cfg.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; + wrmsr(SYSCFG_MSR, sys_cfg); enable_fixed_mtrr(); @@ -186,5 +192,5 @@ /* Now that I have mapped what is memory and what is not * Setup the mtrrs so we can cache the memory. */ - x86_setup_var_mtrrs(address_bits); + amd_setup_var_mtrrs(address_bits); } Index: src/cpu/x86/mtrr/mtrr.c =================================================================== --- src/cpu/x86/mtrr/mtrr.c (revision 6056) +++ src/cpu/x86/mtrr/mtrr.c (working copy) @@ -364,31 +364,30 @@ void x86_setup_fixed_mtrrs(void) { - /* Try this the simple way of incrementally adding together - * mtrrs. If this doesn't work out we can get smart again - * and clear out the mtrrs. - */ + /* Try this the simple way of incrementally adding together + * mtrrs. If this doesn't work out we can get smart again + * and clear out the mtrrs. + */ - printk(BIOS_DEBUG, "\n"); - /* Initialized the fixed_mtrrs to uncached */ - printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: UC\n", - 0, NUM_FIXED_RANGES); - set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE); + printk(BIOS_DEBUG, "\n"); + /* Initialized the fixed_mtrrs to uncached */ + printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: UC\n", + 0, NUM_FIXED_RANGES); + set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE); - /* Now see which of the fixed mtrrs cover ram. - */ - search_global_resources( + /* Now see which of the fixed mtrrs cover ram. */ + search_global_resources( IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, set_fixed_mtrr_resource, NULL); - printk(BIOS_DEBUG, "DONE fixed MTRRs\n"); + printk(BIOS_DEBUG, "DONE fixed MTRRs\n"); - /* enable fixed MTRR */ - printk(BIOS_SPEW, "call enable_fixed_mtrr()\n"); - enable_fixed_mtrr(); + /* enable fixed MTRR */ + printk(BIOS_SPEW, "call enable_fixed_mtrr()\n"); + enable_fixed_mtrr(); } -void x86_setup_var_mtrrs(unsigned address_bits) +static void x86_setup_var_mtrrs(unsigned address_bits) /* this routine needs to know how many address bits a given processor * supports. CPUs get grumpy when you set too many bits in * their mtrr registers :( I would generically call cpuid here @@ -449,6 +448,64 @@ post_code(0x6A); } + +void amd_setup_var_mtrrs(unsigned address_bits) +/* this routine needs to know how many address bits a given processor + * supports. CPUs get grumpy when you set too many bits in + * their mtrr registers :( I would generically call cpuid here + * and find out how many physically supported but some cpus are + * buggy, and report more bits then they actually support. + */ +{ + /* Try this the simple way of incrementally adding together + * mtrrs. If this doesn't work out we can get smart again + * and clear out the mtrrs. + */ + struct var_mtrr_state var_state; + + /* Cache as many memory areas as possible */ + /* FIXME is there an algorithm for computing the optimal set of mtrrs? + * In some cases it is definitely possible to do better. + */ + + var_state.range_startk = 0; + var_state.range_sizek = 0; + var_state.hole_startk = 0; + var_state.hole_sizek = 0; + var_state.reg = 0; + var_state.address_bits = address_bits; + + search_global_resources( + IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE, + set_var_mtrr_resource, &var_state); + + if (var_state.range_sizek >= 0x100000000ull / 1024 && var_state.range_startk == 0) + { + // no variable MTRR range is needed for WB from 4GB-TOM2 + // because Tom2ForceMemTypeWB will be used for this purpose. + var_state.range_sizek = var_state.hole_startk; + } + +#if (CONFIG_GFXUMA == 1) /* UMA or SP. */ + // For now we assume the UMA space is at the end of memory below 4GB + // Reduce the dram wb mtrr range so that it does not cover the uma at the end + var_state.range_sizek -= (uma_memory_size >> 10); +#endif + /* Write the last range */ + var_state.reg = range_to_mtrr(var_state.reg, var_state.range_startk, + var_state.range_sizek, 0, MTRR_TYPE_WRBACK, var_state.address_bits); + printk(BIOS_DEBUG, "DONE variable MTRRs\n"); + printk(BIOS_DEBUG, "Clear out the extra MTRR's\n"); + /* Clear out the extra MTRR's */ + while(var_state.reg < MTRRS) { + set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits); + } + printk(BIOS_SPEW, "call enable_var_mtrr()\n"); + enable_var_mtrr(); + printk(BIOS_SPEW, "Leave %s\n", __func__); + post_code(0x6A); +} + void x86_setup_mtrrs(unsigned address_bits) { x86_setup_fixed_mtrrs(); Index: src/include/cpu/amd/mtrr.h =================================================================== --- src/include/cpu/amd/mtrr.h (revision 6056) +++ src/include/cpu/amd/mtrr.h (working copy) @@ -8,6 +8,7 @@ #define MTRR_WRITE_MEM (1 << 3) #define SYSCFG_MSR 0xC0010010 +#define SYSCFG_MSR_TOM2WB (1 << 22) #define SYSCFG_MSR_TOM2En (1 << 21) #define SYSCFG_MSR_MtrrVarDramEn (1 << 20) #define SYSCFG_MSR_MtrrFixDramModEn (1 << 19) Index: src/include/cpu/x86/mtrr.h =================================================================== --- src/include/cpu/x86/mtrr.h (revision 6056) +++ src/include/cpu/x86/mtrr.h (working copy) @@ -37,7 +37,7 @@ #if !defined (ASSEMBLY) && !defined(__PRE_RAM__) #include <device/device.h> void enable_fixed_mtrr(void); -void x86_setup_var_mtrrs(unsigned address_bits); +void amd_setup_var_mtrrs(unsigned address_bits); void x86_setup_mtrrs(unsigned address_bits); int x86_mtrr_check(void); void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res); Index: src/northbridge/amd/amdmct/wrappers/mcti.h =================================================================== --- src/northbridge/amd/amdmct/wrappers/mcti.h (revision 6056) +++ src/northbridge/amd/amdmct/wrappers/mcti.h (working copy) @@ -42,11 +42,12 @@ //#define SYSTEM_TYPE MOBILE #endif -/*---------------------------------------------------------------------------- -COMMENT OUT ALL BUT 1 -----------------------------------------------------------------------------*/ +/*--------------------------------------------------------------------------*/ +#if (CONFIG_GFXUMA) +#define UMA_SUPPORT 1 /*Supported */ +#else #define UMA_SUPPORT 0 /*Not supported */ -//#define UMA_SUPPORT 1 /*Supported */ +#endif /*---------------------------------------------------------------------------- UPDATE AS NEEDED Index: src/northbridge/amd/amdmct/wrappers/mcti_d.c =================================================================== --- src/northbridge/amd/amdmct/wrappers/mcti_d.c (revision 6056) +++ src/northbridge/amd/amdmct/wrappers/mcti_d.c (working copy) @@ -132,13 +132,17 @@ //val = 1; /* enable */ break; case NV_BottomIO: +#if (UMA_SUPPORT == 0) val = 0xE0; /* address bits [31:24] */ +#elif (UMA_SUPPORT == 1) + val = 0xC0; /* address bits [31:24] */ +#endif break; case NV_BottomUMA: #if (UMA_SUPPORT == 0) val = 0xE0; /* address bits [31:24] */ #elif (UMA_SUPPORT == 1) - val = 0xB0; /* address bits [31:24] */ + val = 0xC0; /* address bits [31:24] */ #endif break; case NV_ECC:

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Re: [coreboot] coreboot Digest, Vol 69, Issue 62
by Fengwei Zhang 11 Nov '10

11 Nov '10

Hi , I think the registers offsets of ICH7 are different from VT8237r, right? we need to use the data sheet of VT8237r. I also tested your code, it cannot boot. In addition, thank you guys for help me out yesterday, and I solved the problem. I should put the smm handler code at 0xa8000(even implementation of ICH4 and ICH7 put the smm handler at 0xa0000, but the entry point is still at (0xa8000 - LAPICID * 0x400), and they used a jumptable. ). Anyway, thank you guys (especially Rudolf's patch) pointed out that and helping me fixed the problem. Best, Fengwei On 11/11/2010 04:29 AM, coreboot-request(a)coreboot.org wrote: > Message: 8 > Date: Thu, 11 Nov 2010 10:29:26 +0100 > From: Stefan Reinauer<stepan(a)coreboot.org> > To:coreboot@coreboot.org > Subject: [coreboot] SMM on K8 > Message-ID:<20101111092926.GB29795(a)coreboot.org> > Content-Type: text/plain; charset="us-ascii" > > First shot, untested > > >

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[commit] r6063 - in trunk/src/superio: fintek/f71889 ite/it8671f ite/it8673f ite/it8705f ite/it8712f ite/it8716f ite/it8718f nsc/pc8374 nsc/pc87309 nsc/pc87351 nsc/pc87360 nsc/pc87366 nsc/pc87417 n...
by repository service 11 Nov '10

11 Nov '10

Author: uwe Date: Thu Nov 11 14:14:55 2010 New Revision: 6063 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6063 Log: Remove superfluous Super I/O res0/res1 lines. The pc_keyboard_init() function no longer takes any base addresses since r5152 (passed in via res0/res1 variables previously), so drop them. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/src/superio/fintek/f71889/superio.c trunk/src/superio/ite/it8671f/superio.c trunk/src/superio/ite/it8673f/superio.c trunk/src/superio/ite/it8705f/superio.c trunk/src/superio/ite/it8712f/superio.c trunk/src/superio/ite/it8716f/superio.c trunk/src/superio/ite/it8718f/superio.c trunk/src/superio/nsc/pc8374/superio.c trunk/src/superio/nsc/pc87309/superio.c trunk/src/superio/nsc/pc87351/superio.c trunk/src/superio/nsc/pc87360/superio.c trunk/src/superio/nsc/pc87366/superio.c trunk/src/superio/nsc/pc87417/superio.c trunk/src/superio/nsc/pc87427/superio.c trunk/src/superio/nsc/pc97307/superio.c trunk/src/superio/nsc/pc97317/superio.c trunk/src/superio/smsc/fdc37m60x/superio.c trunk/src/superio/smsc/lpc47b272/superio.c trunk/src/superio/smsc/lpc47b397/superio.c trunk/src/superio/smsc/lpc47m10x/superio.c trunk/src/superio/smsc/lpc47m15x/superio.c trunk/src/superio/smsc/smscsuperio/superio.c trunk/src/superio/winbond/w83627dhg/superio.c trunk/src/superio/winbond/w83627ehg/superio.c trunk/src/superio/winbond/w83627hf/superio.c trunk/src/superio/winbond/w83627thf/superio.c trunk/src/superio/winbond/w83627thg/superio.c trunk/src/superio/winbond/w83627uhg/superio.c trunk/src/superio/winbond/w83977f/superio.c trunk/src/superio/winbond/w83977tf/superio.c Modified: trunk/src/superio/fintek/f71889/superio.c ============================================================================== --- trunk/src/superio/fintek/f71889/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/fintek/f71889/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -57,7 +57,6 @@ init_uart8250(res0->base, &conf->com2); break; case F71889_KBC: - res0 = find_resource(dev, PNP_IDX_IO0); pc_keyboard_init(&conf->keyboard); break; } Modified: trunk/src/superio/ite/it8671f/superio.c ============================================================================== --- trunk/src/superio/ite/it8671f/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/ite/it8671f/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -29,7 +29,7 @@ static void init(device_t dev) { struct superio_ite_it8671f_config *conf = dev->chip_info; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) return; @@ -48,8 +48,6 @@ case IT8671F_PP: /* TODO. */ break; case IT8671F_KBCK: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; case IT8671F_KBCM: /* TODO. */ Modified: trunk/src/superio/ite/it8673f/superio.c ============================================================================== --- trunk/src/superio/ite/it8673f/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/ite/it8673f/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -29,7 +29,7 @@ static void init(device_t dev) { struct superio_ite_it8673f_config *conf = dev->chip_info; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) return; @@ -50,8 +50,6 @@ case IT8673F_FAN: /* TODO. */ break; case IT8673F_KBCK: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; case IT8673F_KBCM: /* TODO. */ Modified: trunk/src/superio/ite/it8705f/superio.c ============================================================================== --- trunk/src/superio/ite/it8705f/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/ite/it8705f/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -28,7 +28,7 @@ static void init(device_t dev) { struct superio_ite_it8705f_config *conf = dev->chip_info; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) return; Modified: trunk/src/superio/ite/it8712f/superio.c ============================================================================== --- trunk/src/superio/ite/it8712f/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/ite/it8712f/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -46,7 +46,7 @@ static void it8712f_init(device_t dev) { struct superio_ite_it8712f_config *conf = dev->chip_info; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) return; @@ -67,8 +67,6 @@ case IT8712F_EC: /* TODO. */ break; case IT8712F_KBCK: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); set_kbc_ps2_mode(); pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/ite/it8716f/superio.c ============================================================================== --- trunk/src/superio/ite/it8716f/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/ite/it8716f/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -78,7 +78,7 @@ static void it8716f_init(device_t dev) { struct superio_ite_it8716f_config *conf = dev->chip_info; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) return; @@ -99,8 +99,6 @@ init_ec(res0->base + EC_INDEX_PORT); break; case IT8716F_KBCK: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; } Modified: trunk/src/superio/ite/it8718f/superio.c ============================================================================== --- trunk/src/superio/ite/it8718f/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/ite/it8718f/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -29,7 +29,7 @@ static void init(device_t dev) { struct superio_ite_it8718f_config *conf = dev->chip_info; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) return; @@ -50,8 +50,6 @@ case IT8718F_EC: /* TODO. */ break; case IT8718F_KBCK: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; case IT8718F_KBCM: /* TODO. */ Modified: trunk/src/superio/nsc/pc8374/superio.c ============================================================================== --- trunk/src/superio/nsc/pc8374/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/nsc/pc8374/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -34,7 +34,7 @@ static void init(device_t dev) { struct superio_nsc_pc8374_config *conf; - struct resource *res0, *res1; + struct resource *res0; /* Wishlist handle well known programming interfaces more * generically. */ @@ -52,8 +52,6 @@ init_uart8250(res0->base, &conf->com2); break; case PC8374_KBCK: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; } Modified: trunk/src/superio/nsc/pc87309/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87309/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/nsc/pc87309/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -30,7 +30,7 @@ static void init(device_t dev) { struct superio_nsc_pc87309_config *conf; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) { return; @@ -46,8 +46,6 @@ init_uart8250(res0->base, &conf->com2); break; case PC87309_KBCK: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; } Modified: trunk/src/superio/nsc/pc87351/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87351/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/nsc/pc87351/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -40,7 +40,7 @@ static void init(device_t dev) { struct superio_nsc_pc87351_config *conf; - struct resource *res0, *res1; + struct resource *res0; /* Wishlist handle well known programming interfaces more * generically. */ @@ -58,8 +58,6 @@ init_uart8250(res0->base, &conf->com2); break; case PC87351_KBCK: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; } Modified: trunk/src/superio/nsc/pc87360/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87360/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/nsc/pc87360/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -34,7 +34,7 @@ static void init(device_t dev) { struct superio_nsc_pc87360_config *conf; - struct resource *res0, *res1; + struct resource *res0; /* Wishlist handle well known programming interfaces more * generically. */ @@ -52,8 +52,6 @@ init_uart8250(res0->base, &conf->com2); break; case PC87360_KBCK: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; } Modified: trunk/src/superio/nsc/pc87366/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87366/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/nsc/pc87366/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -34,7 +34,7 @@ static void init(device_t dev) { struct superio_nsc_pc87366_config *conf; - struct resource *res0, *res1; + struct resource *res0; /* Wishlist handle well known programming interfaces more * generically. */ @@ -52,8 +52,6 @@ init_uart8250(res0->base, &conf->com2); break; case PC87366_KBCK: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; } Modified: trunk/src/superio/nsc/pc87417/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87417/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/nsc/pc87417/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -35,7 +35,7 @@ static void init(device_t dev) { struct superio_nsc_pc87417_config *conf; - struct resource *res0, *res1; + struct resource *res0; /* Wishlist handle well known programming interfaces more * generically. */ @@ -53,8 +53,6 @@ init_uart8250(res0->base, &conf->com2); break; case PC87417_KBCK: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; } Modified: trunk/src/superio/nsc/pc87427/superio.c ============================================================================== --- trunk/src/superio/nsc/pc87427/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/nsc/pc87427/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -32,7 +32,7 @@ static void init(device_t dev) { struct superio_nsc_pc87427_config *conf; - struct resource *res0, *res1; + struct resource *res0; /* Wishlist handle well known programming interfaces more * generically. */ @@ -50,8 +50,6 @@ init_uart8250(res0->base, &conf->com2); break; case PC87427_KBCK: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; } Modified: trunk/src/superio/nsc/pc97307/superio.c ============================================================================== --- trunk/src/superio/nsc/pc97307/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/nsc/pc97307/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -29,7 +29,7 @@ static void init(device_t dev) { struct superio_nsc_pc97307_config *conf; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) { return; @@ -53,8 +53,6 @@ pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 Mhz */ pnp_set_enable(dev, 1); /* Enable keyboard */ - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/nsc/pc97317/superio.c ============================================================================== --- trunk/src/superio/nsc/pc97317/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/nsc/pc97317/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -29,7 +29,7 @@ static void init(device_t dev) { struct superio_nsc_pc97317_config *conf; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) { return; @@ -53,8 +53,6 @@ pnp_write_config(dev, 0xf0, 0x40); /* Set KBC clock to 8 Mhz */ pnp_set_enable(dev, 1); /* Enable keyboard */ - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; Modified: trunk/src/superio/smsc/fdc37m60x/superio.c ============================================================================== --- trunk/src/superio/smsc/fdc37m60x/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/smsc/fdc37m60x/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -29,7 +29,7 @@ static void init(device_t dev) { struct superio_smsc_fdc37m60x_config *conf; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) { return; @@ -51,8 +51,6 @@ init_uart8250(res0->base, &conf->com2); break; case FDC37M60X_KBCK: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; case FDC37M60X_AUX: /* TODO. */ Modified: trunk/src/superio/smsc/lpc47b272/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47b272/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/smsc/lpc47b272/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -126,7 +126,7 @@ static void lpc47b272_init(device_t dev) { struct superio_smsc_lpc47b272_config *conf = dev->chip_info; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) return; @@ -143,8 +143,6 @@ break; case LPC47B272_KBC: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; } Modified: trunk/src/superio/smsc/lpc47b397/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47b397/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/smsc/lpc47b397/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -67,7 +67,7 @@ static void lpc47b397_init(device_t dev) { struct superio_smsc_lpc47b397_config *conf; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) { return; } @@ -82,8 +82,6 @@ init_uart8250(res0->base, &conf->com2); break; case LPC47B397_KBC: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; } Modified: trunk/src/superio/smsc/lpc47m10x/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47m10x/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/smsc/lpc47m10x/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -124,7 +124,7 @@ static void lpc47m10x_init(device_t dev) { struct superio_smsc_lpc47m10x_config *conf = dev->chip_info; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) return; @@ -141,8 +141,6 @@ break; case LPC47M10X2_KBC: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; } Modified: trunk/src/superio/smsc/lpc47m15x/superio.c ============================================================================== --- trunk/src/superio/smsc/lpc47m15x/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/smsc/lpc47m15x/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -99,7 +99,7 @@ static void lpc47m15x_init(device_t dev) { struct superio_smsc_lpc47m15x_config *conf = dev->chip_info; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) return; @@ -116,8 +116,6 @@ break; case LPC47M15X_KBC: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; } Modified: trunk/src/superio/smsc/smscsuperio/superio.c ============================================================================== --- trunk/src/superio/smsc/smscsuperio/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/smsc/smscsuperio/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -205,7 +205,7 @@ static void smsc_init(device_t dev) { struct superio_smsc_smscsuperio_config *conf = dev->chip_info; - struct resource *res0, *res1; + struct resource *res0; int i, ld; /* Do not initialize disabled devices. */ @@ -230,8 +230,6 @@ res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com2); } else if (ld == logical_device_table[i].devs[LD_KBC]) { - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); } } Modified: trunk/src/superio/winbond/w83627dhg/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627dhg/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/winbond/w83627dhg/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -40,7 +40,7 @@ static void w83627dhg_init(device_t dev) { struct superio_winbond_w83627dhg_config *conf = dev->chip_info; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) return; @@ -55,8 +55,6 @@ init_uart8250(res0->base, &conf->com2); break; case W83627DHG_KBC: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; } Modified: trunk/src/superio/winbond/w83627ehg/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627ehg/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/winbond/w83627ehg/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -108,7 +108,7 @@ static void w83627ehg_init(device_t dev) { struct superio_winbond_w83627ehg_config *conf = dev->chip_info; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) return; @@ -123,8 +123,6 @@ init_uart8250(res0->base, &conf->com2); break; case W83627EHG_KBC: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; case W83627EHG_HWM: Modified: trunk/src/superio/winbond/w83627hf/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627hf/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/winbond/w83627hf/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -129,7 +129,7 @@ static void w83627hf_init(device_t dev) { struct superio_winbond_w83627hf_config *conf = dev->chip_info; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) return; @@ -144,8 +144,6 @@ init_uart8250(res0->base, &conf->com2); break; case W83627HF_KBC: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; case W83627HF_HWM: Modified: trunk/src/superio/winbond/w83627thf/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627thf/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/winbond/w83627thf/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -46,7 +46,7 @@ static void w83627thf_init(device_t dev) { struct superio_winbond_w83627thf_config *conf = dev->chip_info; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) return; @@ -61,8 +61,6 @@ init_uart8250(res0->base, &conf->com2); break; case W83627THF_KBC: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; } Modified: trunk/src/superio/winbond/w83627thg/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627thg/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/winbond/w83627thg/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -45,7 +45,7 @@ static void w83627thg_init(device_t dev) { struct superio_winbond_w83627thg_config *conf = dev->chip_info; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) return; @@ -60,8 +60,6 @@ init_uart8250(res0->base, &conf->com2); break; case W83627THG_KBC: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; } Modified: trunk/src/superio/winbond/w83627uhg/superio.c ============================================================================== --- trunk/src/superio/winbond/w83627uhg/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/winbond/w83627uhg/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -73,7 +73,7 @@ static void w83627uhg_init(device_t dev) { struct superio_winbond_w83627uhg_config *conf = dev->chip_info; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) return; @@ -110,8 +110,6 @@ init_uart8250(res0->base, &conf->com6); break; case W83627UHG_KBC: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; } Modified: trunk/src/superio/winbond/w83977f/superio.c ============================================================================== --- trunk/src/superio/winbond/w83977f/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/winbond/w83977f/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -44,7 +44,7 @@ static void w83977f_init(device_t dev) { struct superio_winbond_w83977f_config *conf = dev->chip_info; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) return; @@ -59,8 +59,6 @@ init_uart8250(res0->base, &conf->com2); break; case W83977F_KBC: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; } Modified: trunk/src/superio/winbond/w83977tf/superio.c ============================================================================== --- trunk/src/superio/winbond/w83977tf/superio.c Thu Nov 11 06:12:01 2010 (r6062) +++ trunk/src/superio/winbond/w83977tf/superio.c Thu Nov 11 14:14:55 2010 (r6063) @@ -46,7 +46,7 @@ static void w83977tf_init(device_t dev) { struct superio_winbond_w83977tf_config *conf = dev->chip_info; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) return; @@ -61,8 +61,6 @@ init_uart8250(res0->base, &conf->com2); break; case W83977TF_KBC: - res0 = find_resource(dev, PNP_IDX_IO0); - res1 = find_resource(dev, PNP_IDX_IO1); pc_keyboard_init(&conf->keyboard); break; }

1 0

[commit] r6062 - trunk/src/southbridge/via/vt8237r
by repository service 11 Nov '10

11 Nov '10

Author: stuge Date: Thu Nov 11 06:12:01 2010 New Revision: 6062 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6062 Log: Add VT8237A id to src/southbridge/via/vt8237r/bootblock.c I missed this one since it was working anyway, since "The LPC BIOS ROM is always accessed when ISA addresses FFF80000-FFFFFFFF and 000F0000-000FFFFF are decoded" (VT8237R datasheet) And the rom I use for testing is smaller than this 512KB default range. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/southbridge/via/vt8237r/bootblock.c Modified: trunk/src/southbridge/via/vt8237r/bootblock.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/bootblock.c Thu Nov 11 06:08:33 2010 (r6061) +++ trunk/src/southbridge/via/vt8237r/bootblock.c Thu Nov 11 06:12:01 2010 (r6062) @@ -38,8 +38,14 @@ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); - if (dev == PCI_DEV_INVALID) - return; + if (dev == PCI_DEV_INVALID) { + /* Power management controller */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237A_LPC), 0); + + if (dev == PCI_DEV_INVALID) + return; + } } pci_write_config8(dev, 0x41, 0x7f);

1 0

[commit] r6061 - in trunk/src: include/device southbridge/via/vt8237r
by repository service 11 Nov '10

11 Nov '10

Author: stuge Date: Thu Nov 11 06:08:33 2010 New Revision: 6061 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6061 Log: Add pci id and ops for VT8237A SATA controller Needed to change class from raid to ide so seabios can boot from it. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/include/device/pci_ids.h trunk/src/southbridge/via/vt8237r/vt8237r_sata.c Modified: trunk/src/include/device/pci_ids.h ============================================================================== --- trunk/src/include/device/pci_ids.h Wed Nov 10 23:09:42 2010 (r6060) +++ trunk/src/include/device/pci_ids.h Thu Nov 11 06:08:33 2010 (r6061) @@ -1229,6 +1229,7 @@ #define PCI_DEVICE_ID_VIA_VT8237A_LPC 0x3337 #define PCI_DEVICE_ID_VIA_VT8237S_LPC 0x3372 #define PCI_DEVICE_ID_VIA_VT8237_SATA 0x5372 +#define PCI_DEVICE_ID_VIA_VT8237A_SATA 0x0591 #define PCI_DEVICE_ID_VIA_VT8237_VLINK 0x287e #define PCI_DEVICE_ID_VIA_VT8237R_UHCI 0x3038 #define PCI_DEVICE_ID_VIA_VT8237R_EHCI 0x3104 Modified: trunk/src/southbridge/via/vt8237r/vt8237r_sata.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r_sata.c Wed Nov 10 23:09:42 2010 (r6060) +++ trunk/src/southbridge/via/vt8237r/vt8237r_sata.c Thu Nov 11 06:08:33 2010 (r6061) @@ -119,6 +119,12 @@ .device = PCI_DEVICE_ID_VIA_VT8237_SATA, }; +static const struct pci_driver northbridge_driver_i_a __pci_driver = { + .ops = &sata_i_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237A_SATA, +}; + static const struct pci_driver northbridge_driver_i __pci_driver = { .ops = &sata_i_ops, .vendor = PCI_VENDOR_ID_VIA,

1 0

[commit] r6060 - trunk/src/mainboard/asus/m2v
by repository service 10 Nov '10

10 Nov '10

Author: uwe Date: Wed Nov 10 23:09:42 2010 New Revision: 6060 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6060 Log: Use the new mptable_write_buses() on the ASUS M2V. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/asus/m2v/mptable.c Modified: trunk/src/mainboard/asus/m2v/mptable.c ============================================================================== --- trunk/src/mainboard/asus/m2v/mptable.c Wed Nov 10 20:08:52 2010 (r6059) +++ trunk/src/mainboard/asus/m2v/mptable.c Wed Nov 10 23:09:42 2010 (r6060) @@ -38,24 +38,14 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - int bus_isa = 42; + int bus_isa; mc = (void*)(((char *)v) + SMP_FLOATING_TABLE_LEN); mptable_init(mc, "M2V ", LAPIC_ADDR); smp_write_processors(mc); - - /* Bus: Bus ID Type */ - smp_write_bus(mc, 0, "PCI "); /* root bus */ - smp_write_bus(mc, 1, "PCI "); /* agp? */ - smp_write_bus(mc, 2, "PCI "); /* pcie x16 */ - smp_write_bus(mc, 3, "PCI "); /* pcie x1 */ - smp_write_bus(mc, 4, "PCI "); /* pcie x1 */ - smp_write_bus(mc, 5, "PCI "); /* pcie x1 */ - smp_write_bus(mc, 6, "PCI "); /* azalia audio */ - smp_write_bus(mc, 7, "PCI "); /* pci */ - smp_write_bus(mc, bus_isa, "ISA "); + mptable_write_buses(mc, NULL, &bus_isa); /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x3, IO_APIC_ADDR);

1 0

[patch 00/16] ASUS M2V support (v3)
by Tobias Diedrich 10 Nov '10

10 Nov '10

Updated patch series for ASUS M2V support. I've tried breaking it up a bit more. -- Tobias PGP: http://8ef7ddba.uguu.de

5 38

[commit] r6059 - trunk/src/mainboard/asus/m2v
by repository service 10 Nov '10

10 Nov '10

Author: uwe Date: Wed Nov 10 20:08:52 2010 New Revision: 6059 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6059 Log: Add mptable for ASUS M2V. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/src/mainboard/asus/m2v/mptable.c Modified: trunk/src/mainboard/asus/m2v/Kconfig Modified: trunk/src/mainboard/asus/m2v/Kconfig ============================================================================== --- trunk/src/mainboard/asus/m2v/Kconfig Wed Nov 10 19:22:11 2010 (r6058) +++ trunk/src/mainboard/asus/m2v/Kconfig Wed Nov 10 20:08:52 2010 (r6059) @@ -19,6 +19,7 @@ select TINY_BOOTBLOCK select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES + select HAVE_MP_TABLE config MAINBOARD_DIR string Added: trunk/src/mainboard/asus/m2v/mptable.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/m2v/mptable.c Wed Nov 10 20:08:52 2010 (r6059) @@ -0,0 +1,162 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <stdint.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" + +static void smp_write_intsrc_pci(struct mp_config_table *mc, + unsigned char srcbus, unsigned char srcbusirq, + unsigned char dstapic, unsigned char dstirq) +{ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + srcbus, srcbusirq, dstapic, dstirq); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa = 42; + + mc = (void*)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, "M2V ", LAPIC_ADDR); + + smp_write_processors(mc); + + /* Bus: Bus ID Type */ + smp_write_bus(mc, 0, "PCI "); /* root bus */ + smp_write_bus(mc, 1, "PCI "); /* agp? */ + smp_write_bus(mc, 2, "PCI "); /* pcie x16 */ + smp_write_bus(mc, 3, "PCI "); /* pcie x1 */ + smp_write_bus(mc, 4, "PCI "); /* pcie x1 */ + smp_write_bus(mc, 5, "PCI "); /* pcie x1 */ + smp_write_bus(mc, 6, "PCI "); /* azalia audio */ + smp_write_bus(mc, 7, "PCI "); /* pci */ + smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, VT8237R_APIC_ID, 0x3, IO_APIC_ADDR); + smp_write_ioapic(mc, K8T890_APIC_ID, 0x3, K8T890_APIC_BASE); + + mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); + + /* agp? bridge */ + smp_write_intsrc_pci(mc, 0, (0x1 << 2) | 0, VT8237R_APIC_ID, 0x10); + smp_write_intsrc_pci(mc, 0, (0x1 << 2) | 1, VT8237R_APIC_ID, 0x11); + smp_write_intsrc_pci(mc, 0, (0x1 << 2) | 2, VT8237R_APIC_ID, 0x12); + smp_write_intsrc_pci(mc, 0, (0x1 << 2) | 3, VT8237R_APIC_ID, 0x13); + + /* peg bridge */ + smp_write_intsrc_pci(mc, 0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3); + smp_write_intsrc_pci(mc, 0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3); + smp_write_intsrc_pci(mc, 0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3); + smp_write_intsrc_pci(mc, 0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3); + + /* pex bridge */ + smp_write_intsrc_pci(mc, 0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7); + smp_write_intsrc_pci(mc, 0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb); + smp_write_intsrc_pci(mc, 0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf); + smp_write_intsrc_pci(mc, 0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13); + + /* SATA / IDE */ + smp_write_intsrc_pci(mc, 0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x15); + + /* USB */ + smp_write_intsrc_pci(mc, 0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x14); + smp_write_intsrc_pci(mc, 0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x16); + smp_write_intsrc_pci(mc, 0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15); + smp_write_intsrc_pci(mc, 0, (0x10 << 2) | 3, VT8237R_APIC_ID, 0x17); + + /* PCIE graphics */ + smp_write_intsrc_pci(mc, 2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0); + smp_write_intsrc_pci(mc, 2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1); + smp_write_intsrc_pci(mc, 2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2); + smp_write_intsrc_pci(mc, 2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3); + + /* onboard PCIE atl1 ethernet */ + smp_write_intsrc_pci(mc, 3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4); + smp_write_intsrc_pci(mc, 3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5); + smp_write_intsrc_pci(mc, 3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6); + smp_write_intsrc_pci(mc, 3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7); + + /* PCIE slot */ + smp_write_intsrc_pci(mc, 4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8); + smp_write_intsrc_pci(mc, 4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9); + smp_write_intsrc_pci(mc, 4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa); + smp_write_intsrc_pci(mc, 4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb); + + /* onboard marvell mv6121 sata */ + smp_write_intsrc_pci(mc, 5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc); + smp_write_intsrc_pci(mc, 5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd); + smp_write_intsrc_pci(mc, 5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe); + smp_write_intsrc_pci(mc, 5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf); + + /* azalia HDCA */ + smp_write_intsrc_pci(mc, 6, (0x01 << 2) | 0, VT8237R_APIC_ID, 0x11); + + /* pci slot 1 */ + smp_write_intsrc_pci(mc, 7, (6 << 2) | 0, VT8237R_APIC_ID, 0x10); + smp_write_intsrc_pci(mc, 7, (6 << 2) | 1, VT8237R_APIC_ID, 0x11); + smp_write_intsrc_pci(mc, 7, (6 << 2) | 2, VT8237R_APIC_ID, 0x12); + smp_write_intsrc_pci(mc, 7, (6 << 2) | 3, VT8237R_APIC_ID, 0x13); + + /* pci slot 2 */ + smp_write_intsrc_pci(mc, 7, (7 << 2) | 0, VT8237R_APIC_ID, 0x11); + smp_write_intsrc_pci(mc, 7, (7 << 2) | 1, VT8237R_APIC_ID, 0x12); + smp_write_intsrc_pci(mc, 7, (7 << 2) | 2, VT8237R_APIC_ID, 0x13); + smp_write_intsrc_pci(mc, 7, (7 << 2) | 3, VT8237R_APIC_ID, 0x10); + + /* pci slot 3 */ + smp_write_intsrc_pci(mc, 7, (8 << 2) | 0, VT8237R_APIC_ID, 0x12); + smp_write_intsrc_pci(mc, 7, (8 << 2) | 1, VT8237R_APIC_ID, 0x13); + smp_write_intsrc_pci(mc, 7, (8 << 2) | 2, VT8237R_APIC_ID, 0x10); + smp_write_intsrc_pci(mc, 7, (8 << 2) | 3, VT8237R_APIC_ID, 0x11); + + /* pci slot 4 */ + smp_write_intsrc_pci(mc, 7, (9 << 2) | 0, VT8237R_APIC_ID, 0x13); + smp_write_intsrc_pci(mc, 7, (9 << 2) | 1, VT8237R_APIC_ID, 0x10); + smp_write_intsrc_pci(mc, 7, (9 << 2) | 2, VT8237R_APIC_ID, 0x11); + smp_write_intsrc_pci(mc, 7, (9 << 2) | 3, VT8237R_APIC_ID, 0x12); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums. */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), + mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +}

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[PATCH] Dynamically generate PNP0C02 mainboard resources in SSDT
by Tobias Diedrich 10 Nov '10

10 Nov '10

Dynamically generate PNP0C02 mainboard resources in SSDT While adding the area between TOM1 and 4GB to \SB.PCI0._CRS seems to be the easiest way to get both Linux and Windows happy, it is not quite correct because reserved areas like APIC, MMCONF etc. ranges need to be excluded. This is a proof of concept patch for the M2V board that dynamically creates a ResourceTemplate() containing these in the SSDT and adds a corresponding PNP0C02 device to the DSDT. All resources that have IORESOURCE_RESERVE and (IORESOURCE_MEM or IORESOURCE_IO) set are added. Here applied on top of the "Ranges unavailable for PCI BARs should be marked as reserved in the E820 memory map, in case the OS wants to change the BARs" patch, which adds the IORESOURCE_RESERVE flag to via k8t890/vt8237 apic/mmconf/bios resources. coreboot log excerpt: |ACPI: * SSDT |processor_brand=AMD Athlon(tm) 64 Processor 3200+ |Pstates Algorithm ... |Pstate_freq[0] = 2000MHz Pstate_vid[0] = 8 Pstate_volt[0] = 1350mv Pstate_power[0] = 62000mw |Pstate_freq[1] = 1800MHz Pstate_vid[1] = 10 Pstate_volt[1] = 1300mv Pstate_power[1] = 51743mw |Pstate_freq[2] = 1000MHz Pstate_vid[2] = 18 Pstate_volt[2] = 1100mv Pstate_power[2] = 20581mw |m2v_write_mainboard_resources() |Adding M2V reserved resources |acpigen_add_mainboard_rsvd_mem32: base=fec00000 size=00000100 |acpigen_add_mainboard_rsvd_mem32: base=ffc00000 size=00400000 |acpigen_add_mainboard_rsvd_mem32: base=fecc0000 size=00000100 |acpigen_add_mainboard_rsvd_mem32: base=c0000000 size=10000000 |acpigen_add_mainboard_rsvd_io: base=0a20 size=0008 |ACPI: added table 7/32 Length now 64 Linux dmesg excerpt: |ACPI: ACPI bus type pnp unregistered |system 00:04: [io 0x0a20-0x0a27] has been reserved |system 00:04: [mem 0xfec00000-0xfec000ff] could not be reserved |system 00:04: [mem 0xffc00000-0xffffffff] has been reserved |system 00:04: [mem 0xfecc0000-0xfecc00ff] could not be reserved |system 00:04: [mem 0xc0000000-0xcfffffff] has been reserved |pci 0000:00:03.0: BAR 9: assigned [mem 0xd0500000-0xd06fffff 64bit pref] Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- Index: src/mainboard/asus/m2v/acpi_tables.c =================================================================== --- src/mainboard/asus/m2v/acpi_tables.c.orig 2010-11-10 02:39:36.000000000 +0100 +++ src/mainboard/asus/m2v/acpi_tables.c 2010-11-10 02:39:41.000000000 +0100 @@ -25,6 +25,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/smp/mpspec.h> #include <arch/ioapic.h> #include <device/device.h> @@ -84,10 +85,30 @@ return current; } +struct lb_memory; + +extern int add_mainboard_resources(struct lb_memory *mem); + +static void m2v_write_mainboard_resources(void) +{ + int lens; + const char pscope[] = "\\_SB.PCI0"; + + printk(BIOS_INFO, "m2v_write_mainboard_resources()\n"); + + add_mainboard_resources(NULL); + + lens = acpigen_write_scope(pscope); + lens += acpigen_write_name("RSVD"); + lens += acpigen_write_mainboard_resources(); + acpigen_patch_len(lens - 1); +} + unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) { k8acpi_write_vars(); amd_model_fxx_generate_powernow(0, 0, 0); + m2v_write_mainboard_resources(); return (unsigned long) (acpigen_get_current()); } Index: src/mainboard/asus/m2v/dsdt.asl =================================================================== --- src/mainboard/asus/m2v/dsdt.asl.orig 2010-11-10 02:39:36.000000000 +0100 +++ src/mainboard/asus/m2v/dsdt.asl 2010-11-10 02:39:41.000000000 +0100 @@ -399,6 +399,16 @@ } } + External(RSVD) /* CRS with reserved mainboard resources */ + Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + + Method(_CRS) { + Return (RSVD) + } + } + External(TOM1) /* top of memory below 4GB */ Method(_CRS, 0) { Index: src/arch/i386/boot/acpigen.c =================================================================== --- src/arch/i386/boot/acpigen.c.orig 2010-11-10 02:39:36.000000000 +0100 +++ src/arch/i386/boot/acpigen.c 2010-11-10 02:39:41.000000000 +0100 @@ -28,6 +28,7 @@ #include <string.h> #include <arch/acpigen.h> #include <console/console.h> +#include <device/device.h> static char *gencurrent; @@ -372,3 +373,97 @@ acpigen_patch_len(len - 1); return len + lenh; } + +int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size) +{ + acpigen_emit_byte(0x86); + acpigen_emit_byte(0x09); + acpigen_emit_byte(0x00); + acpigen_emit_byte(readwrite ? 0x01 : 0x00); + acpigen_emit_byte(base & 0xff); + acpigen_emit_byte((base >> 8) & 0xff); + acpigen_emit_byte((base >> 16) & 0xff); + acpigen_emit_byte((base >> 24) & 0xff); + acpigen_emit_byte(size & 0xff); + acpigen_emit_byte((size >> 8) & 0xff); + acpigen_emit_byte((size >> 16) & 0xff); + acpigen_emit_byte((size >> 24) & 0xff); + return 12; +} + +int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len) +{ + acpigen_emit_byte(0x47); + acpigen_emit_byte(0x01); + acpigen_emit_byte(min & 0xff); + acpigen_emit_byte((min >> 8) & 0xff); + acpigen_emit_byte(max & 0xff); + acpigen_emit_byte((max >> 8) & 0xff); + acpigen_emit_byte(align & 0xff); + acpigen_emit_byte(len & 0xff); + return 8; +} + +int acpigen_write_resourcetemplate_header(void) +{ + int len; + len = acpigen_emit_byte(0x11); + len += acpigen_write_len_f(); + len += acpigen_emit_byte(0x0b); /* word */ + len_stack[ltop++] = acpigen_get_current(); + len += acpigen_emit_byte(0x00); + len += acpigen_emit_byte(0x00); + return len; +} + +int acpigen_write_resourcetemplate_footer(int len) +{ + len += acpigen_emit_byte(0x79); + len += acpigen_emit_byte(0x00); + acpigen_patch_len(len-4); + acpigen_patch_len(len-1); + return len; +} + +static void acpigen_add_mainboard_rsvd_mem32(void *gp, struct device *dev, + struct resource *res) +{ + printk(BIOS_INFO, "acpigen_add_mainboard_rsvd_mem32: base=%08x size=%08x\n", (int)res->base, (int)res->size); + acpigen_write_mem32fixed(0, res->base, res->size); +} + +static void acpigen_add_mainboard_rsvd_io(void *gp, struct device *dev, + struct resource *res) +{ + printk(BIOS_INFO, "acpigen_add_mainboard_rsvd_io: base=%04x size=%04x\n", (int)res->base, (int)res->size); + if (res->size > 255) { + printk(BIOS_ERR, "acpigen_add_mainboard_rsvd_io: size %d > 255!\n", (int)res->size); + } + acpigen_write_io16(res->base, res->base, 0, res->size); +} + +int acpigen_write_mainboard_resources(void) +{ + int len; + char *start; + char *end; + len = acpigen_write_resourcetemplate_header(); + start = acpigen_get_current(); + + /* Add reserved memory ranges */ + search_global_resources( + IORESOURCE_MEM | IORESOURCE_RESERVE, + IORESOURCE_MEM | IORESOURCE_RESERVE, + acpigen_add_mainboard_rsvd_mem32, 0); + + /* Add reserved io ranges */ + search_global_resources( + IORESOURCE_IO | IORESOURCE_RESERVE, + IORESOURCE_IO | IORESOURCE_RESERVE, + acpigen_add_mainboard_rsvd_io, 0); + + end = acpigen_get_current(); + len += end-start; + len += acpigen_write_resourcetemplate_footer(len); + return len; +} Index: src/arch/i386/include/arch/acpigen.h =================================================================== --- src/arch/i386/include/arch/acpigen.h.orig 2010-11-10 02:39:36.000000000 +0100 +++ src/arch/i386/include/arch/acpigen.h 2010-11-10 02:39:41.000000000 +0100 @@ -46,5 +46,10 @@ typedef enum { SW_ALL=0xfc, SW_ANY=0xfd, HW_ALL=0xfe } PSD_coord; int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len); +int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size); +int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len); +int acpigen_write_resourcetemplate_header(void); +int acpigen_write_resourcetemplate_footer(int len); +int acpigen_write_mainboard_resources(void); #endif Index: src/mainboard/asus/m2v/mainboard.c =================================================================== --- src/mainboard/asus/m2v/mainboard.c.orig 2010-11-10 02:39:36.000000000 +0100 +++ src/mainboard/asus/m2v/mainboard.c 2010-11-10 02:39:41.000000000 +0100 @@ -17,9 +17,39 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#include <console/console.h> #include <device/device.h> +#include <device/pci_ids.h> +#include <boot/tables.h> #include "chip.h" +#define IT8712F_GPIO_BASE 0x0a20 + +int add_mainboard_resources(struct lb_memory *mem) +{ + struct device *dev; + struct resource *res; + + printk(BIOS_INFO, "Adding M2V reserved resources\n"); + + dev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237A_LPC, 0); + if (!dev) { + printk(BIOS_ERR, "LPC not found!\n"); + return 0; + } + + res = new_resource(dev, 42); + res->base = IT8712F_GPIO_BASE; + res->size = 8; + res->limit = 0xffff; + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + return 0; +} + + struct chip_operations mainboard_ops = { CHIP_NAME("ASUS M2V") }; Index: src/mainboard/asus/m2v/Kconfig =================================================================== --- src/mainboard/asus/m2v/Kconfig.orig 2010-11-10 02:39:41.000000000 +0100 +++ src/mainboard/asus/m2v/Kconfig 2010-11-10 02:39:41.000000000 +0100 @@ -21,6 +21,7 @@ select PIRQ_ROUTE select HAVE_ACPI_TABLES select HAVE_MP_TABLE + select HAVE_MAINBOARD_RESOURCES config MAINBOARD_DIR string

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coreboot November 2010