coreboot November 2010

coreboot@coreboot.org

48 participants
285 discussions

[commit] r6054 - in trunk/src: . lib
by repository service 09 Nov '10

09 Nov '10

Author: uwe Date: Wed Nov 10 01:14:32 2010 New Revision: 6054 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6054 Log: Debugging facility improvements. - Hook up malloc() debug code via CONFIG_DEBUG_MALLOC. Only show it in menuconfig if at least DEBUG or SPEW are selected as loglevel, as this code does additional printk(BIOS_DEBUG, ...) calls which would otherwise not be visible anyway. - Similarly, make DEBUG_CAR and REALMODE_DEBUG only visible if thr DEBUG or SPEW loglevel is selected. - Get rid of a custom "debug" macro, use printk() as usual. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/Kconfig trunk/src/lib/cbmem.c trunk/src/lib/malloc.c Modified: trunk/src/Kconfig ============================================================================== --- trunk/src/Kconfig Wed Nov 10 01:08:42 2010 (r6053) +++ trunk/src/Kconfig Wed Nov 10 01:14:32 2010 (r6054) @@ -502,10 +502,13 @@ config HAVE_DEBUG_CAR def_bool n +# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional +# printk(BIOS_DEBUG, ...) calls. config DEBUG_CAR bool "Output verbose Cache-as-RAM debug messages" default n - depends on HAVE_DEBUG_CAR + depends on HAVE_DEBUG_CAR && \ + (DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8) help This option enables additional CAR related debug messages. @@ -553,10 +556,26 @@ If unsure, say N. +# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional +# printk(BIOS_DEBUG, ...) calls. +config DEBUG_MALLOC + bool "Output verbose malloc debug messages" + default n + depends on DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8 + help + This option enables additional malloc related debug messages. + + Note: This option will increase the size of the coreboot image. + + If unsure, say N. + +# Only visible if debug level is DEBUG (7) or SPEW (8) as it does additional +# printk(BIOS_DEBUG, ...) calls. config REALMODE_DEBUG bool "Enable debug messages for option ROM execution" default n - depends on PCI_OPTION_ROM_RUN_REALMODE + depends on PCI_OPTION_ROM_RUN_REALMODE && \ + (DEFAULT_CONSOLE_LOGLEVEL_7 || DEFAULT_CONSOLE_LOGLEVEL_8) help This option enables additional x86emu related debug messages. Modified: trunk/src/lib/cbmem.c ============================================================================== --- trunk/src/lib/cbmem.c Wed Nov 10 01:08:42 2010 (r6053) +++ trunk/src/lib/cbmem.c Wed Nov 10 01:14:32 2010 (r6054) @@ -22,12 +22,6 @@ #include <cbmem.h> #include <console/console.h> -#if 1 -#define debug(x...) printk(BIOS_DEBUG, x) -#else -#define debug(x...) -#endif - // The CBMEM TOC reserves 512 bytes to keep // the other entries somewhat aligned. // Increase if MAX_CBMEM_ENTRIES exceeds 21 @@ -68,10 +62,11 @@ bss_cbmem_toc = cbmem_toc; #endif - debug("Initializing CBMEM area to 0x%llx (%lld bytes)\n", baseaddr, size); + printk(BIOS_DEBUG, "Initializing CBMEM area to 0x%llx (%lld bytes)\n", + baseaddr, size); if (size < (64 * 1024)) { - debug("Increase CBMEM size!!\n"); + printk(BIOS_DEBUG, "Increase CBMEM size!\n"); for (;;) ; } @@ -90,7 +85,9 @@ struct cbmem_entry *cbmem_toc; cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr; - debug("Re-Initializing CBMEM area to 0x%lx\n", (unsigned long)baseaddr); + printk(BIOS_DEBUG, "Re-Initializing CBMEM area to 0x%lx\n", + (unsigned long)baseaddr); + #ifndef __PRE_RAM__ bss_cbmem_toc = cbmem_toc; #endif @@ -135,7 +132,7 @@ return NULL; } - debug("Adding CBMEM entry as no. %d\n", i); + printk(BIOS_DEBUG, "Adding CBMEM entry as no. %d\n", i); cbmem_toc[i] = (struct cbmem_entry) { .magic = CBMEM_MAGIC, Modified: trunk/src/lib/malloc.c ============================================================================== --- trunk/src/lib/malloc.c Wed Nov 10 01:08:42 2010 (r6053) +++ trunk/src/lib/malloc.c Wed Nov 10 01:14:32 2010 (r6054) @@ -1,11 +1,12 @@ #include <stdlib.h> #include <console/console.h> -#if 0 -#define MALLOCDBG(x) -#else +#if CONFIG_DEBUG_MALLOC #define MALLOCDBG(x...) printk(BIOS_SPEW, x) +#else +#define MALLOCDBG(x) #endif + extern unsigned char _heap, _eheap; static void *free_mem_ptr = &_heap; /* Start of heap */ static void *free_mem_end_ptr = &_eheap; /* End of heap */

1 0

[commit] r6053 - trunk/src/superio/ite/it8661f
by repository service 09 Nov '10

09 Nov '10

Author: uwe Date: Wed Nov 10 01:08:42 2010 New Revision: 6053 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6053 Log: ITE IT8661F changes to match the common code structure. - it8661f_enable_serial() is now in the usual format, using pnp_* functions. - Factor out pnp_enter_ext_func_mode()/pnp_exit_ext_func_mode(). - Factor out it8661f_set_clkin() to set the CLKIN to 24/48MHz. - Factor out it8661f_enable_logical_devices(), might not be needed though. We leave it here until it's confirmed on hardware that it's not needed. - Move some #defines to it8661f.h. - Drop no longer used it8661f_sio_write(). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/superio/ite/it8661f/it8661f.h trunk/src/superio/ite/it8661f/it8661f_early_serial.c trunk/src/superio/ite/it8661f/superio.c Modified: trunk/src/superio/ite/it8661f/it8661f.h ============================================================================== --- trunk/src/superio/ite/it8661f/it8661f.h Tue Nov 9 23:31:11 2010 (r6052) +++ trunk/src/superio/ite/it8661f/it8661f.h Wed Nov 10 01:08:42 2010 (r6053) @@ -23,6 +23,7 @@ /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8661_2.asp */ +/* Logical device numbers (LDNs). */ #define IT8661F_FDC 0x00 /* Floppy */ #define IT8661F_SP1 0x01 /* Com1 */ #define IT8661F_SP2 0x02 /* Com2 */ @@ -30,4 +31,25 @@ #define IT8661F_IR 0x04 /* IR */ #define IT8661F_GPIO 0x05 /* GPIO & Alternate Function Configuration */ +/* Register and bit definitions. */ +#define IT8661F_REG_CC 0x02 /* Configure Control (write-only). */ +#define IT8661F_REG_LDE 0x23 /* PnP Logical Device Enable. */ +#define IT8661F_REG_SWSUSP 0x24 /* Software Suspend + Clock Select. */ + +#define IT8661F_ISA_PNP_PORT 0x0279 /* Write-only. */ + +#define IT8661F_CLKIN_24_MHZ 0 +#define IT8661F_CLKIN_48_MHZ 1 + +/* + * Special values used for entering MB PnP mode. The first four bytes of + * each line determine the address port, the last four are data. + */ +static const u8 init_values[] = { + 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe, + 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61, + 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1, + 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, +}; + #endif Modified: trunk/src/superio/ite/it8661f/it8661f_early_serial.c ============================================================================== --- trunk/src/superio/ite/it8661f/it8661f_early_serial.c Tue Nov 9 23:31:11 2010 (r6052) +++ trunk/src/superio/ite/it8661f/it8661f_early_serial.c Wed Nov 10 01:08:42 2010 (r6053) @@ -21,74 +21,59 @@ #include <arch/romcc_io.h> #include "it8661f.h" -/* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ -#define SIO_BASE 0x3f0 -#define SIO_INDEX SIO_BASE -#define SIO_DATA (SIO_BASE + 1) - -/* Global configuration registers. */ -#define IT8661F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ -#define IT8661F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */ -#define IT8661F_CONFIG_REG_LDE 0x23 /* PnP Logical Device Enable. */ -#define IT8661F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend + Clock Select. */ +/* Perform MB PnP setup to put the SIO chip at 0x3f0. */ +/* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ +/* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */ +/* Base address 0x370: 0x86 0x80 0xaa 0x55. */ +static void pnp_enter_ext_func_mode(device_t dev) +{ + int i; + u16 port = dev >> 8; + + /* TODO: Don't hardcode Super I/O config port to 0x3f0. */ + outb(0x86, IT8661F_ISA_PNP_PORT); + outb(0x80, IT8661F_ISA_PNP_PORT); + outb(0x55, IT8661F_ISA_PNP_PORT); + outb(0x55, IT8661F_ISA_PNP_PORT); + + /* Sequentially write the 32 special values. */ + for (i = 0; i < 32; i++) + outb(init_values[i], port); +} -#define IT8661F_CONFIGURATION_PORT 0x0279 /* Write-only. */ +static void pnp_exit_ext_func_mode(device_t dev) +{ + pnp_write_config(dev, IT8661F_REG_CC, (1 << 1)); +} /* - * Special values used for entering MB PnP mode. The first four bytes of - * each line determine the address port, the last four are data. + * The logical devices will only be involved in the ISA PnP sequence if their + * respective enable bits in IT8661F_REG_LDE are set. + * + * TODO: Find out if we actually need this (we use MB PnP mode). + * + * Bits: FDC (0), Com1 (1), Com2 (2), PP (3), IR (4). Bits 5-7 are reserved. */ -static const u8 init_values[] = { - 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe, - 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61, - 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1, - 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, -}; +static void it8661f_enable_logical_devices(device_t dev) +{ + pnp_enter_ext_func_mode(dev); + pnp_write_config(dev, IT8661F_REG_LDE, 0x1f); + pnp_exit_ext_func_mode(dev); +} -static void it8661f_sio_write(u8 ldn, u8 index, u8 value) +static void it8661f_set_clkin(device_t dev, u8 clkin) { - outb(IT8661F_CONFIG_REG_LDN, SIO_BASE); - outb(ldn, SIO_DATA); - outb(index, SIO_BASE); - outb(value, SIO_DATA); + pnp_enter_ext_func_mode(dev); + pnp_write_config(dev, IT8661F_REG_SWSUSP, (clkin << 1)); + pnp_exit_ext_func_mode(dev); } -/* Enable the serial port(s). */ static void it8661f_enable_serial(device_t dev, u16 iobase) { - int i; - - /* (1) Enter the configuration state (MB PnP mode). */ - - /* Perform MB PnP setup to put the SIO chip at 0x3f0. */ - /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ - /* Base address 0x3bd: 0x86 0x80 0x55 0xaa. */ - /* Base address 0x370: 0x86 0x80 0xaa 0x55. */ - outb(0x86, IT8661F_CONFIGURATION_PORT); - outb(0x80, IT8661F_CONFIGURATION_PORT); - outb(0x55, IT8661F_CONFIGURATION_PORT); - outb(0x55, IT8661F_CONFIGURATION_PORT); - - /* Sequentially write the 32 special values. */ - for (i = 0; i < 32; i++) - outb(init_values[i], SIO_BASE); - - /* (2) Modify the data of configuration registers. */ - - /* - * Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2), - * PP (3), IR (4). Bits 5-7 are reserved. - */ - it8661f_sio_write(0x00, IT8661F_CONFIG_REG_LDE, 0x1f); - - /* Enable serial port(s). */ - it8661f_sio_write(IT8661F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8661f_sio_write(IT8661F_SP2, 0x30, 0x1); /* Serial port 2 */ - - /* Select 24MHz CLKIN (clear bit 1) and clear software suspend mode - (clear bit 0). */ - it8661f_sio_write(0x00, IT8661F_CONFIG_REG_SWSUSP, 0x00); - - /* (3) Exit the configuration state (MB PnP mode). */ - it8661f_sio_write(0x00, IT8661F_CONFIG_REG_CC, 0x02); + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_ext_func_mode(dev); } Modified: trunk/src/superio/ite/it8661f/superio.c ============================================================================== --- trunk/src/superio/ite/it8661f/superio.c Tue Nov 9 23:31:11 2010 (r6052) +++ trunk/src/superio/ite/it8661f/superio.c Wed Nov 10 01:08:42 2010 (r6053) @@ -25,10 +25,12 @@ #include "chip.h" #include "it8661f.h" +/* TODO: Add pnp_enter_ext_func_mode() etc. and wrap functions. */ + static void init(device_t dev) { struct superio_ite_it8661f_config *conf = dev->chip_info; - struct resource *res0, *res1; + struct resource *res0; if (!dev->enabled) return;

1 0

[PATCH]mirror fix about superio makefile
by Qing Pei Wang 09 Nov '10

09 Nov '10

see the patch Signed-off-by: Wang Qing Pei <wangqingpei(a)gmail.com> Best wishes Wang Qing Pei Phone: 86+18930528086

2 1

[commit] r6052 - trunk/src/cpu/amd/mtrr
by repository service 09 Nov '10

09 Nov '10

Author: ruik Date: Tue Nov 9 23:31:11 2010 New Revision: 6052 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6052 Log: This fixes a FIXME in src/cpu/amd/mtrr/amd_mtrr.c and shuts up the Linux kernel, which was previously complaining that the MTRR setup is wrong, if the cpu supports more than CONFIG_CPU_ADDR_BITS bits of address space. Shamelessly copied from Linux arch/x86/kernel/cpu/mtrr/main.c Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Scott Duplichan <scott(a)notabs.org> Modified: trunk/src/cpu/amd/mtrr/amd_mtrr.c Modified: trunk/src/cpu/amd/mtrr/amd_mtrr.c ============================================================================== --- trunk/src/cpu/amd/mtrr/amd_mtrr.c Tue Nov 9 23:18:28 2010 (r6051) +++ trunk/src/cpu/amd/mtrr/amd_mtrr.c Tue Nov 9 23:31:11 2010 (r6052) @@ -1,5 +1,6 @@ #include <console/console.h> #include <device/device.h> +#include <arch/cpu.h> #include <cpu/x86/mtrr.h> #include <cpu/amd/mtrr.h> #include <cpu/x86/cache.h> @@ -175,11 +176,13 @@ enable_cache(); - /* FIXME we should probably query the cpu for this - * but so far this is all any recent AMD cpu has supported. - */ address_bits = CONFIG_CPU_ADDR_BITS; //K8 could be 40, and GH could be 48 + /* AMD specific cpuid function to query number of address bits */ + if (cpuid_eax(0x80000000) >= 0x80000008) { + address_bits = cpuid_eax(0x80000008) & 0xff; + } + /* Now that I have mapped what is memory and what is not * Setup the mtrrs so we can cache the memory. */

1 0

[commit] r6051 - trunk/src/mainboard/asus/m2v
by repository service 09 Nov '10

09 Nov '10

Author: ruik Date: Tue Nov 9 23:18:28 2010 New Revision: 6051 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6051 Log: Add acpi tables and dsdt. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Added: trunk/src/mainboard/asus/m2v/acpi_tables.c trunk/src/mainboard/asus/m2v/dsdt.asl Modified: trunk/src/mainboard/asus/m2v/Kconfig Modified: trunk/src/mainboard/asus/m2v/Kconfig ============================================================================== --- trunk/src/mainboard/asus/m2v/Kconfig Tue Nov 9 23:11:00 2010 (r6050) +++ trunk/src/mainboard/asus/m2v/Kconfig Tue Nov 9 23:18:28 2010 (r6051) @@ -18,6 +18,7 @@ select RAMINIT_SYSINFO select TINY_BOOTBLOCK select HAVE_PIRQ_TABLE + select HAVE_ACPI_TABLES config MAINBOARD_DIR string Added: trunk/src/mainboard/asus/m2v/acpi_tables.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/m2v/acpi_tables.c Tue Nov 9 23:18:28 2010 (r6051) @@ -0,0 +1,196 @@ +/* + * This file is part of the coreboot project. + * + * Written by Stefan Reinauer <stepan(a)openbios.org>. + * ACPI FADT, FACS, and DSDT table support added by + * + * Copyright (C) 2004 Stefan Reinauer <stepan(a)openbios.org> + * Copyright (C) 2005 Nick Barker <nick.barker9(a)btinternet.com> + * Copyright (C) 2007, 2008 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <string.h> +#include <arch/acpi.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" +#include "northbridge/amd/amdk8/amdk8_acpi.h" +#include <cpu/amd/model_fxx_powernow.h> + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + device_t dev; + struct resource *res; + + dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CF_5, 0); + if (!dev) + return current; + + res = find_resource(dev, K8T890_MMCONFIG_MBAR); + if (res) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) + current, res->base, 0x0, 0x0, 0xff); + } + return current; +} + +unsigned long acpi_fill_madt(unsigned long current) +{ + unsigned int gsi_base = 0x18; + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapics(current); + + /* Write SB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + VT8237R_APIC_ID, IO_APIC_ADDR, 0); + + /* Write NB IOAPIC. */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, + K8T890_APIC_ID, K8T890_APIC_BASE, gsi_base); + + /* IRQ9 ACPI active low. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW); + + /* IRQ0 -> APIC IRQ2. */ + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0x0); + + /* Create all subtables for processors. */ + current = acpi_create_madt_lapic_nmis(current, + MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, 1); + + return current; +} + +unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) +{ + k8acpi_write_vars(); + amd_model_fxx_generate_powernow(0, 0, 0); + return (unsigned long) (acpigen_get_current()); +} + +unsigned long write_acpi_tables(unsigned long start) +{ + unsigned long current; + acpi_rsdp_t *rsdp; + acpi_srat_t *srat; + acpi_rsdt_t *rsdt; + acpi_mcfg_t *mcfg; + acpi_hpet_t *hpet; + acpi_madt_t *madt; + acpi_fadt_t *fadt; + acpi_facs_t *facs; + acpi_slit_t *slit; + acpi_header_t *ssdt; + acpi_header_t *dsdt; + + /* Align ACPI tables to 16 byte. */ + start = (start + 0x0f) & -0x10; + current = start; + + printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start); + + /* We need at least an RSDP and an RSDT table. */ + rsdp = (acpi_rsdp_t *) current; + current += sizeof(acpi_rsdp_t); + rsdt = (acpi_rsdt_t *) current; + current += sizeof(acpi_rsdt_t); + + /* Clear all table memory. */ + memset((void *) start, 0, current - start); + + acpi_write_rsdp(rsdp, rsdt, NULL); + acpi_write_rsdt(rsdt); + + /* We explicitly add these tables later on: */ + printk(BIOS_DEBUG, "ACPI: * FACS\n"); + + /* we should align FACS to 64B as per ACPI specs */ + + current = ALIGN(current, 64); + facs = (acpi_facs_t *) current; + current += sizeof(acpi_facs_t); + acpi_create_facs(facs); + + dsdt = (acpi_header_t *) current; + memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); + current += dsdt->length; + memcpy(dsdt, &AmlCode, dsdt->length); + dsdt->checksum = 0; /* Don't trust iasl to get this right. */ + dsdt->checksum = acpi_checksum((u8*)dsdt, dsdt->length); + printk(BIOS_DEBUG, "ACPI: * DSDT @ %p Length %x\n", dsdt, + dsdt->length); + printk(BIOS_DEBUG, "ACPI: * FADT\n"); + + fadt = (acpi_fadt_t *) current; + current += sizeof(acpi_fadt_t); + + acpi_create_fadt(fadt, facs, dsdt); + acpi_add_table(rsdp, fadt); + + printk(BIOS_DEBUG, "ACPI: * HPET\n"); + hpet = (acpi_hpet_t *) current; + current += sizeof(acpi_hpet_t); + acpi_create_hpet(hpet); + acpi_add_table(rsdp, hpet); + + /* If we want to use HPET timers Linux wants an MADT. */ + printk(BIOS_DEBUG, "ACPI: * MADT\n"); + madt = (acpi_madt_t *) current; + acpi_create_madt(madt); + current += madt->header.length; + acpi_add_table(rsdp, madt); + + printk(BIOS_DEBUG, "ACPI: * MCFG\n"); + mcfg = (acpi_mcfg_t *) current; + acpi_create_mcfg(mcfg); + current += mcfg->header.length; + acpi_add_table(rsdp, mcfg); + + printk(BIOS_DEBUG, "ACPI: * SRAT\n"); + srat = (acpi_srat_t *) current; + acpi_create_srat(srat); + current += srat->header.length; + acpi_add_table(rsdp, srat); + + /* SLIT */ + printk(BIOS_DEBUG, "ACPI: * SLIT\n"); + slit = (acpi_slit_t *) current; + acpi_create_slit(slit); + current+=slit->header.length; + acpi_add_table(rsdp,slit); + + /* SSDT */ + printk(BIOS_DEBUG, "ACPI: * SSDT\n"); + ssdt = (acpi_header_t *)current; + + acpi_create_ssdt_generator(ssdt, "DYNADATA"); + current += ssdt->length; + acpi_add_table(rsdp, ssdt); + + printk(BIOS_INFO, "ACPI: done.\n"); + + return current; +} Added: trunk/src/mainboard/asus/m2v/dsdt.asl ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/m2v/dsdt.asl Tue Nov 9 23:18:28 2010 (r6051) @@ -0,0 +1,534 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2004 Nick Barker <Nick.Barker9(a)btinternet.com> + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* + * ISA portions taken from QEMU acpi-dsdt.dsl. + */ + +#define LNKA INTA +#define LNKB INTB +#define LNKC INTC +#define LNKD INTD + +/* + * For simplicity map LNK[E-H] to LNK[A-D]. + * This also means we are 82C596 compatible. + * Needs 0:11.0 0x46[4] set to 0. + */ +#define LNKE INTA +#define LNKF INTB +#define LNKG INTC +#define LNKH INTD + +DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) +{ + Name(APIC, 0) // 0=>8259, 1=>IOAPIC + + /* The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local Apic/IOAPIC configuration. + */ + + Method(_PIC, 1) + { + // Remember the OS' IRQ routing choice. + Store(Arg0, APIC) + } + + /* _PR CPU0 is dynamically supplied by SSDT */ + + /* For now only define 2 power states: + * - S0 which is fully on + * - S5 which is soft off + * Any others would involve declaring the wake up methods. + * + * Package contents: + * ofs len desc + * 0 1 Value for PM1a_CNT.SLP_TYP register to enter this system state. + * 1 1 Value for PM1b_CNT.SLP_TYP register to enter this system state. To enter any + * given state, OSPM must write the PM1a_CNT.SLP_TYP register before the + * PM1b_CNT.SLP_TYP register. + * 2 2 Reserved + */ + Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 }) + Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 }) + + /* Root of the bus hierarchy */ + Scope (\_SB) + { + /* Top PCI device */ + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_ADR, 0x00180000) + Name (_BBN, 0x00) + + Name (APRT, Package() { + /* AGP? */ + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x13 }, + /* PCIe graphics bridge */ + Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1B }, + Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1B }, + /* PCIe bridge */ + Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1F }, + Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x23 }, + Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x27 }, + Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x2B }, + /* SATA */ + Package (0x04) { 0x000FFFFF, 0x01, 0x00, 0x15 }, + /* IDE */ + Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x15 }, + /* USB */ + Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x14 }, + Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x16 }, + Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x15 }, + Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x17 }, + /* PCI bridge */ + Package (0x04) { 0x0013FFFF, 0x00, 0x00, 0x14 }, + Package (0x04) { 0x0013FFFF, 0x01, 0x00, 0x14 }, + Package (0x04) { 0x0013FFFF, 0x02, 0x00, 0x14 }, + Package (0x04) { 0x0013FFFF, 0x03, 0x00, 0x14 }, + }) + Name (PPRT, Package() { + /* ?? */ + Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x0001FFFF, 0x03, LNKD, 0x00 }, + /* PCIe graphics bridge */ + Package (0x04) { 0x0002FFFF, 0x00, LNKH, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x01, LNKH, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x02, LNKH, 0x00 }, + Package (0x04) { 0x0002FFFF, 0x03, LNKH, 0x00 }, + /* PCIe bridge */ + Package (0x04) { 0x0003FFFF, 0x00, LNKH, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x01, LNKH, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x02, LNKH, 0x00 }, + Package (0x04) { 0x0003FFFF, 0x03, LNKH, 0x00 }, + /* SATA */ + Package (0x04) { 0x000FFFFF, 0x01, LNKB, 0x00 }, + /* USB */ + Package (0x04) { 0x0010FFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x0010FFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0x0010FFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x0010FFFF, 0x03, LNKD, 0x00 }, + /* PCI bridge */ + Package (0x04) { 0x0013FFFF, 0x00, LNKD, 0x00 }, + Package (0x04) { 0x0013FFFF, 0x01, LNKD, 0x00 }, + Package (0x04) { 0x0013FFFF, 0x02, LNKD, 0x00 }, + Package (0x04) { 0x0013FFFF, 0x03, LNKD, 0x00 }, + }) + + /* PCI Routing Table */ + Method (_PRT, 0, NotSerialized) + { + If (APIC) + { + Return (APRT) + } + Return (PPRT) + } + + Device (PEGG) + { + Name (_ADR, 0x00020000) + Name (APRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x18 }, /* PCIE IRQ24-IRQ27 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x19 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1A }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1B }, + }) + Name (PPRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 }, + }) + Method (_PRT, 0, NotSerialized) + { + If (APIC) + { + Return (APRT) + } + Return (PPRT) + } + } + + Device (PEX0) + { + Name (_ADR, 0x00030000) + Name (APRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1C }, /* PCIE IRQ28-IRQ31 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x1D }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x1E }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x1F }, + }) + Name (PPRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 }, + }) + Method (_PRT, 0, NotSerialized) + { + If (APIC) + { + Return (APRT) + } + Return (PPRT) + } + } + + Device (PEX1) + { + Name (_ADR, 0x00030001) + Name (APRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x20 }, /* PCIE IRQ32-IRQ35 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x21 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x22 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x23 }, + }) + Name (PPRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 }, + }) + Method (_PRT, 0, NotSerialized) + { + If (APIC) + { + Return (APRT) + } + Return (PPRT) + } + } + + Device (PEX2) + { + Name (_ADR, 0x00030002) + Name (APRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x24 }, /* PCIE IRQ36-IRQ39 */ + Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x25 }, + Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x26 }, + Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x27 }, + }) + Name (PPRT, Package () { + Package (0x04) { 0x0000FFFF, 0x00, LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x01, LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x02, LNKH, 0x00 }, + Package (0x04) { 0x0000FFFF, 0x03, LNKH, 0x00 }, + }) + Method (_PRT, 0, NotSerialized) + { + If (APIC) + { + Return (APRT) + } + Return (PPRT) + } + } + + Device (PCI6) + { + Name (_ADR, 0x00130000) + Name (APRT, Package () { + Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x11 }, /* IRQ17 */ + }) + Name (PPRT, Package () { + Package (0x04) { 0x0001FFFF, 0x00, LNKB, 0x00 }, + }) + Method (_PRT, 0, NotSerialized) + { + If (APIC) + { + Return (APRT) + } + Return (PPRT) + } + } + + Device (PCI7) + { + Name (_ADR, 0x00130001) + Name (APRT, Package () { + /* PCI slot 1 */ + Package (0x04) { 0x0006FFFF, 0x00, 0x00, 0x10 }, + Package (0x04) { 0x0006FFFF, 0x01, 0x00, 0x11 }, + Package (0x04) { 0x0006FFFF, 0x02, 0x00, 0x12 }, + Package (0x04) { 0x0006FFFF, 0x03, 0x00, 0x13 }, + + /* PCI slot 2 */ + Package (0x04) { 0x0007FFFF, 0x00, 0x00, 0x11 }, + Package (0x04) { 0x0007FFFF, 0x01, 0x00, 0x12 }, + Package (0x04) { 0x0007FFFF, 0x02, 0x00, 0x13 }, + Package (0x04) { 0x0007FFFF, 0x03, 0x00, 0x10 }, + + /* PCI slot 3 */ + Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x12 }, + Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x13 }, + Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x10 }, + Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x11 }, + + /* PCI slot 4 */ + Package (0x04) { 0x0009FFFF, 0x00, 0x00, 0x13 }, + Package (0x04) { 0x0009FFFF, 0x01, 0x00, 0x10 }, + Package (0x04) { 0x0009FFFF, 0x02, 0x00, 0x11 }, + Package (0x04) { 0x0009FFFF, 0x03, 0x00, 0x12 }, + }) + Name (PPRT, Package () { + /* PCI slot 1 */ + Package (0x04) { 0x0006FFFF, 0x00, LNKA, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x01, LNKB, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x02, LNKC, 0x00 }, + Package (0x04) { 0x0006FFFF, 0x03, LNKD, 0x00 }, + + /* PCI slot 2 */ + Package (0x04) { 0x0007FFFF, 0x00, LNKB, 0x00 }, + Package (0x04) { 0x0007FFFF, 0x01, LNKC, 0x00 }, + Package (0x04) { 0x0007FFFF, 0x02, LNKD, 0x00 }, + Package (0x04) { 0x0007FFFF, 0x03, LNKA, 0x00 }, + + /* PCI slot 3 */ + Package (0x04) { 0x0008FFFF, 0x00, LNKC, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x01, LNKD, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x02, LNKA, 0x00 }, + Package (0x04) { 0x0008FFFF, 0x03, LNKB, 0x00 }, + + /* PCI slot 4 */ + Package (0x04) { 0x0009FFFF, 0x00, LNKD, 0x00 }, + Package (0x04) { 0x0009FFFF, 0x01, LNKA, 0x00 }, + Package (0x04) { 0x0009FFFF, 0x02, LNKB, 0x00 }, + Package (0x04) { 0x0009FFFF, 0x03, LNKC, 0x00 }, + }) + + Method (_PRT, 0, NotSerialized) + { + If (APIC) + { + Return (APRT) + } + Return (PPRT) + } + } + + Device (SBRG) { /* southbridge */ + Name (_ADR, 0x00110000) + + /* PS/2 keyboard (seems to be important for WinXP install) */ + Device (KBD) + { + Name (_HID, EisaId ("PNP0303")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) + IO (Decode16, 0x0064, 0x0064, 0x01, 0x01) + IRQNoFlags () {1} + }) + Return (TMP) + } + } + + /* PS/2 mouse */ + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IRQNoFlags () {12} + }) + Return (TMP) + } + } + + /* Parallel port */ + Device (LPT0) + { + Name (_HID, EisaId ("PNP0401")) + Method (_STA, 0, NotSerialized) + { + Return (0x0f) + } + Method (_CRS, 0, NotSerialized) + { + Name (TMP, ResourceTemplate () { + IO (Decode16, 0x0378, 0x0378, 0x01, 0x08) + IO (Decode16, 0x0778, 0x0778, 0x01, 0x08) + IRQNoFlags () {7} + DMA (Compatibility, NotBusMaster, Transfer8) {3} + }) + Return (TMP) + } + } + } + + External(TOM1) /* top of memory below 4GB */ + + Method(_CRS, 0) { + Name(TMP, ResourceTemplate() { + WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, + ) + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + }) + CreateDWordField(TMP, MMIO._BAS, MM1B) + CreateDWordField(TMP, MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) + + Return(TMP) + } + } + + OperationRegion (PCI0.SBRG.SBR1, PCI_Config, 0x55, 0x03) + Field (PCI0.SBRG.SBR1, ByteAcc, NoLock, Preserve) + { + /* + * Offset 0x55: + * 3-0: reserved + * 7-4: PCI INTA# routing + * Offset 0x56: + * 3-0: PCI INTB# routing + * 7-4: PCI INTC# routing + * Offset 0x57: + * 3-0: reserved + * 7-4: PCI INTD# routing + * + * Valid values for routing link: + * 0: disabled + * 2,8,13: reserved + * 1,3-7,9-12,14,15: corresponding irq + */ + , 4, + PINA, 4, + PINB, 4, + PINC, 4, + , 4, + PIND, 4, + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 6, 7, 10, 11, 12} + }) + + /* adapted from ma78gm/dsdt.asl */ +#define PCI_INTX_DEV(intx, pinx, uid) \ + Device(intx) { \ + Name(_HID, EISAID("PNP0C0F")) \ + Name(_UID, uid) \ + \ + Method(_STA, 0) { \ + if (pinx) { \ + Return(0x0B) \ + } \ + Return(0x09) \ + } \ + \ + Method(_DIS ,0) { \ + Store(0, pinx) \ + } \ + \ + Method(_PRS ,0) { \ + Return(IRQP) \ + } \ + \ + Method(_CRS ,0) { \ + CreateWordField(IRQB, 1, IRQN) \ + ShiftLeft(1, pinx, IRQN) \ + Return(IRQB) \ + } \ + \ + Method(_SRS, 1) { \ + CreateWordField(ARG0, 1, IRQM) \ + \ + /* Use lowest available IRQ */ \ + FindSetRightBit(IRQM, Local0) \ + if (Local0) { \ + Decrement(Local0) \ + } \ + Store(Local0, pinx) \ + } \ + } \ + +PCI_INTX_DEV(INTA, PINA, 1) +PCI_INTX_DEV(INTB, PINB, 2) +PCI_INTX_DEV(INTC, PINC, 3) +PCI_INTX_DEV(INTD, PIND, 4) + } +}

1 0

[commit] r6050 - trunk/src/mainboard/asus/m2v
by repository service 09 Nov '10

09 Nov '10

Author: ruik Date: Tue Nov 9 23:11:00 2010 New Revision: 6050 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6050 Log: Add pirq table for ASUS M2V. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Added: trunk/src/mainboard/asus/m2v/irq_tables.c Modified: trunk/src/mainboard/asus/m2v/Kconfig Modified: trunk/src/mainboard/asus/m2v/Kconfig ============================================================================== --- trunk/src/mainboard/asus/m2v/Kconfig Mon Nov 8 21:55:24 2010 (r6049) +++ trunk/src/mainboard/asus/m2v/Kconfig Tue Nov 9 23:11:00 2010 (r6050) @@ -17,6 +17,7 @@ select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select TINY_BOOTBLOCK + select HAVE_PIRQ_TABLE config MAINBOARD_DIR string @@ -74,4 +75,8 @@ hex default 0x1043 +config IRQ_SLOT_COUNT + int + default 14 + endif # BOARD_ASUS_M2V Added: trunk/src/mainboard/asus/m2v/irq_tables.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/m2v/irq_tables.c Tue Nov 9 23:11:00 2010 (r6050) @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + * + * IRQ Routing Table + * + * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM + */ +#include <string.h> +#include <stdint.h> +#include <arch/pirq_routing.h> +#include <device/pci_ids.h> + +/* Free irqs are 3, 5, 10 and 11 */ +#define IRQBM ((1<<3)|(1<<5)|(1<<10)|(1<<11)) + +#define LNKA 1 +#define LNKB 2 +#define LNKC 3 +#define LNKD 4 + +/* + * For simplicity map LNK[E-H] to LNK[A-D]. + * This also means we are 82C596 compatible. + * Needs 0:11.0 0x46[4] set to 0. + */ +#define LNKE 1 +#define LNKF 2 +#define LNKG 3 +#define LNKH 4 + +const struct irq_routing_table intel_irq_routing_table = { + PIRQ_SIGNATURE, /* u32 signature */ + PIRQ_VERSION, /* u16 version */ + 32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */ + 0, /* Where the interrupt router lies (bus) */ + (0x11<<3)|0, /* Where the interrupt router lies (dev) */ + 0, /* IRQs devoted exclusively to PCI usage */ + PCI_VENDOR_ID_VIA, /* Compatible Vendor (VIA) */ + PCI_DEVICE_ID_VIA_82C596, /* Compatible Device (82C596) */ + 0, /* Miniport data */ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ + 0x5f, /* u8 checksum, this has to be set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */ + { + /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ + /* peg bridge */ + {0x00, (0x02 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0}, + /* pcie bridge */ + {0x00, (0x03 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0}, + /* sata/ide */ + {0x00, (0x0f << 3) | 0x0, {{0x00, 0x0000}, {LNKB, IRQBM}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + /* usb */ + {0x00, (0x10 << 3) | 0x0, {{LNKA, IRQBM}, {LNKB, IRQBM}, {LNKC, IRQBM}, {LNKD, IRQBM}}, 0x0, 0x0}, + /* agp bus? */ + {0x01, (0x00 << 3) | 0x0, {{LNKA, IRQBM}, {LNKB, IRQBM}, {LNKC, IRQBM}, {LNKD, IRQBM}}, 0x0, 0x0}, + /* pcie graphics */ + {0x02, (0x00 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x6, 0x0}, + /* onboard pcie atl1 ethernet */ + {0x03, (0x00 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0}, + /* pcie slot */ + {0x04, (0x00 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x5, 0x0}, + /* onboard marvell mv6121 sata */ + {0x05, (0x00 << 3) | 0x0, {{LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}, {LNKH, IRQBM}}, 0x0, 0x0}, + /* Azalia HDAC */ + {0x06, (0x01 << 3) | 0x0, {{LNKB, IRQBM}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0}, + /* PCI slots */ + {0x07, (0x06 << 3) | 0x0, {{LNKA, IRQBM}, {LNKB, IRQBM}, {LNKC, IRQBM}, {LNKD, IRQBM}}, 0x1, 0x0}, + {0x07, (0x07 << 3) | 0x0, {{LNKB, IRQBM}, {LNKC, IRQBM}, {LNKD, IRQBM}, {LNKA, IRQBM}}, 0x2, 0x0}, + {0x07, (0x08 << 3) | 0x0, {{LNKC, IRQBM}, {LNKD, IRQBM}, {LNKA, IRQBM}, {LNKB, IRQBM}}, 0x3, 0x0}, + {0x07, (0x09 << 3) | 0x0, {{LNKD, IRQBM}, {LNKA, IRQBM}, {LNKB, IRQBM}, {LNKC, IRQBM}}, 0x4, 0x0}, + } +}; + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + return copy_pirq_routing_table(addr); +}

1 0

[PATCH]adjust some code/comment of sb700 sata init
by Qing Pei Wang 09 Nov '10

09 Nov '10

the inline comment of sata_init function seems not placed correctly. rearrange it. Signed-off-by: Wang Qing Pei <wangqingpei(a)gmail.com> Best wishes Wang Qing Pei Phone: 86+18930528086

2 1

[PATCH]disable dev3 under ma78gm-us2h
by Qing Pei Wang 09 Nov '10

09 Nov '10

disable bus 0 dev 3 pci bridge for ma78gm-us2h does not have this slot. Signed-off-by: Wang Qing Pei <wangqingpei(a)gmail.com> Best wishes Wang Qing Pei Phone: 86+18930528086

2 1

questions on coreboot bootlog w/ EP80579(Truxton platform)
by Xavier Carcelle 09 Nov '10

09 Nov '10

Hi there, I am currently testing coreboot for the Intel EP80579 w/ the Truxton platform w/ DDR2 (not ECC) on the DIMM0 slot of the platform. I am having the following bootlog but don't understand what is the output meaning ? Thanks, Xavier. "coreboot-4.0-r5689 coreboot-4.0-r5689 50AI 00 01 51AI 00 01 52AI 00 01 53AI 0080 08 08 0e 0a 00 40 00 05 3d 50 00 82 08 00 00 AI 100c 08 38 01 02 00 03 3d 50 50 60 3c 1e 3c 2d 01 AI 2025 37 10 220 01 55AI 00 01 56AI 00 01 57AI 00ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff AI 10ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff AI 20ff ff ff ff 00 00 MHz DDR Sc cd` - 25c cd` - 0000000000000201` - c cd` - DR ffffffffDRB = 00000000 TOM = 0000 TOLM = 0000 cl = 00 trc = 7e trfc = 00 tras = 00 trtp = 40 twtr = 00 drt0 = ffffffea drt1 = fc700000 magic = 009a62b1 mrs = 69020000 0000T @Q000000000000000000000000000000000010T @Q000000000000000000000000000000000020T @Q000000000000000000000000000000000030T @0 ``c` CS01 q00000010DDR R 00T @QR 01T @Q0000T @Q001000000000000000000000000000000010T @Q000000000000000000000000000000000020T @Q0000000000000000000000000000000000 0000T @Q001000000000000000000000000000000010T @Q000000000000000000000000000000000020T @Q000000000000000000000000000000000030T @S 00:00.0000: 86 80 20 50 06 00 10 00 01 00 00 06 00 00 80 00 10: 00 00 00 00 00 00 00 90 00 00 00 00 00 00 00 00 20: 00 00 00 00"

2 2

MCP55 Mac Address copying/change
by Harald Gutmann 08 Nov '10

08 Nov '10

Hello! Yesterday I tried coreboot again, and it worked fine so far. But I faced a nasty problem, like the last time I tried it with the MAC address on MCP55. This is nothing serious as you can change it by editing the romcache.inc from the southbridge, but it's nasty. I was thinking about fixing this in a decent way. I'd love to see a KConfig value to enter in the configure process to get this done, or even to copy the mac address of the board. As of now the MAC is stored in the romcache.inc file of the southbridge, and as far as I guess, this value is read in the mcp55_nic.c and used. There is as of now in the bugtracker a script to apply the new mac after compiling the image, but I think this is not a really good solution. If my guess is right, readout from romcache.inc and usage in mcp55_nic.c it should be possible to solve this via KConfig, and not read the value from the romcache.inc, but store it a config value and take this value. Possibly with a fallback on the romcache.inc value. My questions on this suggestion are: Would there be any good reason not to do it that way? Is my guess right? (Until now I didn't look that careful into the code of mcp55_nic.c.) If my guess is right, and there is no problem to do as suggested, I'd prepare a patch for it. Any comments are welcome. Kind regards, Harald

6 7

← Newer
1
...
17
18
19
20
21
22
23
...
29
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

2012

2011

2010

2009

2008

2007

2006

2005

2004

2003

2002

coreboot November 2010