coreboot November 2010

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[commit] r6049 - in trunk/src/superio: fintek/f71805f fintek/f71859 fintek/f71863fg fintek/f71889 intel/i3100 ite/it8661f ite/it8671f ite/it8673f ite/it8705f ite/it8712f ite/it8716f ite/it8718f nsc...
by repository service 08 Nov '10

08 Nov '10

Author: uwe Date: Mon Nov 8 21:55:24 2010 New Revision: 6049 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6049 Log: Add #include guards to all Super I/O header files (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/superio/fintek/f71805f/chip.h trunk/src/superio/fintek/f71805f/f71805f.h trunk/src/superio/fintek/f71859/chip.h trunk/src/superio/fintek/f71859/f71859.h trunk/src/superio/fintek/f71863fg/chip.h trunk/src/superio/fintek/f71863fg/f71863fg.h trunk/src/superio/fintek/f71889/chip.h trunk/src/superio/fintek/f71889/f71889.h trunk/src/superio/intel/i3100/i3100.h trunk/src/superio/ite/it8661f/it8661f.h trunk/src/superio/ite/it8671f/it8671f.h trunk/src/superio/ite/it8673f/it8673f.h trunk/src/superio/ite/it8705f/it8705f.h trunk/src/superio/ite/it8712f/it8712f.h trunk/src/superio/ite/it8716f/it8716f.h trunk/src/superio/ite/it8718f/it8718f.h trunk/src/superio/nsc/pc8374/chip.h trunk/src/superio/nsc/pc8374/pc8374.h trunk/src/superio/nsc/pc87309/chip.h trunk/src/superio/nsc/pc87309/pc87309.h trunk/src/superio/nsc/pc87351/chip.h trunk/src/superio/nsc/pc87351/pc87351.h trunk/src/superio/nsc/pc87360/chip.h trunk/src/superio/nsc/pc87360/pc87360.h trunk/src/superio/nsc/pc87366/chip.h trunk/src/superio/nsc/pc87366/pc87366.h trunk/src/superio/nsc/pc87417/chip.h trunk/src/superio/nsc/pc87417/pc87417.h trunk/src/superio/nsc/pc87427/chip.h trunk/src/superio/nsc/pc87427/pc87427.h trunk/src/superio/nsc/pc97307/chip.h trunk/src/superio/nsc/pc97307/pc97307.h trunk/src/superio/nsc/pc97317/chip.h trunk/src/superio/nsc/pc97317/pc97317.h trunk/src/superio/renesas/m3885x/chip.h trunk/src/superio/serverengines/pilot/pilot.h trunk/src/superio/smsc/fdc37m60x/chip.h trunk/src/superio/smsc/fdc37m60x/fdc37m60x.h trunk/src/superio/smsc/fdc37n972/chip.h trunk/src/superio/smsc/fdc37n972/fdc37n972.h trunk/src/superio/smsc/lpc47b272/chip.h trunk/src/superio/smsc/lpc47b272/lpc47b272.h trunk/src/superio/smsc/lpc47b397/chip.h trunk/src/superio/smsc/lpc47b397/lpc47b397.h trunk/src/superio/smsc/lpc47m10x/chip.h trunk/src/superio/smsc/lpc47m10x/lpc47m10x.h trunk/src/superio/smsc/lpc47m15x/chip.h trunk/src/superio/smsc/lpc47m15x/lpc47m15x.h trunk/src/superio/smsc/lpc47n217/chip.h trunk/src/superio/smsc/lpc47n217/lpc47n217.h trunk/src/superio/smsc/lpc47n227/chip.h trunk/src/superio/smsc/lpc47n227/lpc47n227.h trunk/src/superio/smsc/sio10n268/chip.h trunk/src/superio/smsc/sio10n268/sio10n268.h trunk/src/superio/smsc/smscsuperio/Makefile.inc trunk/src/superio/smsc/smscsuperio/chip.h trunk/src/superio/via/vt1211/vt1211.h trunk/src/superio/winbond/w83627dhg/chip.h trunk/src/superio/winbond/w83627dhg/w83627dhg.h trunk/src/superio/winbond/w83627ehg/chip.h trunk/src/superio/winbond/w83627ehg/w83627ehg.h trunk/src/superio/winbond/w83627hf/chip.h trunk/src/superio/winbond/w83627hf/w83627hf.h trunk/src/superio/winbond/w83627thf/chip.h trunk/src/superio/winbond/w83627thf/w83627thf.h trunk/src/superio/winbond/w83627thg/chip.h trunk/src/superio/winbond/w83627thg/w83627thg.h trunk/src/superio/winbond/w83627uhg/chip.h trunk/src/superio/winbond/w83627uhg/w83627uhg.h trunk/src/superio/winbond/w83697hf/chip.h trunk/src/superio/winbond/w83697hf/w83697hf.h trunk/src/superio/winbond/w83977f/chip.h trunk/src/superio/winbond/w83977f/w83977f.h trunk/src/superio/winbond/w83977tf/chip.h trunk/src/superio/winbond/w83977tf/w83977tf.h Modified: trunk/src/superio/fintek/f71805f/chip.h ============================================================================== --- trunk/src/superio/fintek/f71805f/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/fintek/f71805f/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_FINTEK_F71805F_CHIP_H +#define SUPERIO_FINTEK_F71805F_CHIP_H + #include <device/device.h> #include <uart8250.h> @@ -28,3 +31,5 @@ struct superio_fintek_f71805f_config { struct uart8250 com1, com2; }; + +#endif Modified: trunk/src/superio/fintek/f71805f/f71805f.h ============================================================================== --- trunk/src/superio/fintek/f71805f/f71805f.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/fintek/f71805f/f71805f.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_FINTEK_F71805F_F71805F_H +#define SUPERIO_FINTEK_F71805F_F71805F_H + /* * Datasheet: * - Name: F71805F/FG Super H/W Monitor + LPC IO @@ -34,3 +37,5 @@ #define F71805F_HWM 0x04 /* Hardware monitor */ #define F71805F_GPIO 0x06 /* General Purpose I/O (GPIO) */ #define F71805F_PME 0x0a /* Power Management Events (PME) */ + +#endif Modified: trunk/src/superio/fintek/f71859/chip.h ============================================================================== --- trunk/src/superio/fintek/f71859/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/fintek/f71859/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_FINTEK_F71859_CHIP_H +#define SUPERIO_FINTEK_F71859_CHIP_H + #include <device/device.h> #include <uart8250.h> @@ -26,3 +29,5 @@ struct superio_fintek_f71859_config { struct uart8250 com1, com2; }; + +#endif Modified: trunk/src/superio/fintek/f71859/f71859.h ============================================================================== --- trunk/src/superio/fintek/f71859/f71859.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/fintek/f71859/f71859.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,7 +18,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Logical Device Numbers (LDN). */ +#ifndef SUPERIO_FINTEK_F71859_F71859_H +#define SUPERIO_FINTEK_F71859_F71859_H +/* Logical Device Numbers (LDN). */ #define F71859_SP1 0x03 /* UART1 */ +#endif Modified: trunk/src/superio/fintek/f71863fg/chip.h ============================================================================== --- trunk/src/superio/fintek/f71863fg/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/fintek/f71863fg/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_FINTEK_F71863FG_CHIP_H +#define SUPERIO_FINTEK_F71863FG_CHIP_H + #include <pc80/keyboard.h> #include <device/device.h> #include <uart8250.h> @@ -28,3 +31,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/fintek/f71863fg/f71863fg.h ============================================================================== --- trunk/src/superio/fintek/f71863fg/f71863fg.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/fintek/f71863fg/f71863fg.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_FINTEK_F71863FG_F71863FG_H +#define SUPERIO_FINTEK_F71863FG_F71863FG_H + /* Logical Device Numbers (LDN). */ #define F71863FG_FDC 0x00 /* Floppy */ #define F71863FG_SP1 0x01 /* UART1 */ @@ -29,3 +32,5 @@ #define F71863FG_VID 0x07 /* VID */ #define F71863FG_SPI 0x08 /* SPI */ #define F71863FG_PME 0x0a /* Power Management Events (PME) and ACPI */ + +#endif Modified: trunk/src/superio/fintek/f71889/chip.h ============================================================================== --- trunk/src/superio/fintek/f71889/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/fintek/f71889/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_FINTEK_F71889_CHIP_H +#define SUPERIO_FINTEK_F71889_CHIP_H + #include <pc80/keyboard.h> #include <device/device.h> #include <uart8250.h> @@ -28,3 +31,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/fintek/f71889/f71889.h ============================================================================== --- trunk/src/superio/fintek/f71889/f71889.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/fintek/f71889/f71889.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_FINTEK_F71889_F71889_H +#define SUPERIO_FINTEK_F71889_F71889_H + /* Logical Device Numbers (LDN). */ #define F71889_FDC 0x00 /* Floppy */ #define F71889_SP1 0x01 /* UART1 */ @@ -30,3 +33,5 @@ #define F71889_SPI 0x08 /* SPI */ #define F71889_PME 0x0a /* Power Management Events (PME) and ACPI */ #define F71889_VREF 0x0b /* Vref */ + +#endif Modified: trunk/src/superio/intel/i3100/i3100.h ============================================================================== --- trunk/src/superio/intel/i3100/i3100.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/intel/i3100/i3100.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_INTEL_I3100_I3100_H +#define SUPERIO_INTEL_I3100_I3100_H + /* * Datasheet: * - Name: Intel 3100 Chipset @@ -27,9 +30,6 @@ * - Order number: 313458-007US */ -#ifndef SUPERIO_INTEL_I3100_I3100_H -#define SUPERIO_INTEL_I3100_I3100_H - /* * The SIW ("Serial I/O and Watchdog Timer") integrated into the i3100 is * very similar to a Super I/O, both in functionality and config mechanism. Modified: trunk/src/superio/ite/it8661f/it8661f.h ============================================================================== --- trunk/src/superio/ite/it8661f/it8661f.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/ite/it8661f/it8661f.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_ITE_IT8661F_IT8661F_H +#define SUPERIO_ITE_IT8661F_IT8661F_H + /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8661_2.asp */ #define IT8661F_FDC 0x00 /* Floppy */ @@ -26,3 +29,5 @@ #define IT8661F_PP 0x03 /* Parallel port */ #define IT8661F_IR 0x04 /* IR */ #define IT8661F_GPIO 0x05 /* GPIO & Alternate Function Configuration */ + +#endif Modified: trunk/src/superio/ite/it8671f/it8671f.h ============================================================================== --- trunk/src/superio/ite/it8671f/it8671f.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/ite/it8671f/it8671f.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_ITE_IT8671F_IT8671F_H +#define SUPERIO_ITE_IT8671F_IT8671F_H + /* Datasheet: Not available online, got it from ITE per request. */ #define IT8671F_FDC 0x00 /* Floppy */ @@ -26,3 +29,5 @@ #define IT8671F_PP 0x03 /* Parallel port */ #define IT8671F_KBCK 0x05 /* PS/2 keyboard */ #define IT8671F_KBCM 0x06 /* PS/2 mouse */ + +#endif Modified: trunk/src/superio/ite/it8673f/it8673f.h ============================================================================== --- trunk/src/superio/ite/it8673f/it8673f.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/ite/it8673f/it8673f.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_ITE_IT8673F_IT8673F_H +#define SUPERIO_ITE_IT8673F_IT8673F_H + /* Datasheet: http://www.datasheet4u.com/html/I/T/8/IT8673F_ITE.pdf.html */ #define IT8673F_FDC 0x00 /* Floppy */ @@ -27,3 +30,5 @@ #define IT8673F_FAN 0x04 /* Fan controller */ #define IT8673F_KBCK 0x05 /* PS/2 keyboard */ #define IT8673F_KBCM 0x06 /* PS/2 mouse */ + +#endif Modified: trunk/src/superio/ite/it8705f/it8705f.h ============================================================================== --- trunk/src/superio/ite/it8705f/it8705f.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/ite/it8705f/it8705f.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_ITE_IT8705F_IT8705F_H +#define SUPERIO_ITE_IT8705F_IT8705F_H + /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8705_2.asp */ /* Note: This should also work on an IT8705AF, they're almost the same. */ @@ -31,3 +34,5 @@ #define IT8705F_GAME 0x06 /* GAME port */ #define IT8705F_IR 0x07 /* Consumer IR */ #define IT8705F_MIDI 0x08 /* MIDI port */ + +#endif Modified: trunk/src/superio/ite/it8712f/it8712f.h ============================================================================== --- trunk/src/superio/ite/it8712f/it8712f.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/ite/it8712f/it8712f.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_ITE_IT8712F_IT8712F_H +#define SUPERIO_ITE_IT8712F_IT8712F_H + /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8712_2.asp */ #define IT8712F_FDC 0x00 /* Floppy */ @@ -38,3 +41,5 @@ void it8712f_24mhz_clkin(void); void it8712f_enable_3vsbsw(void); #endif + +#endif Modified: trunk/src/superio/ite/it8716f/it8716f.h ============================================================================== --- trunk/src/superio/ite/it8716f/it8716f.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/ite/it8716f/it8716f.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,11 +18,12 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */ - #ifndef SUPERIO_ITE_IT8716F_IT8716F_H #define SUPERIO_ITE_IT8716F_IT8716F_H +/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */ + +/* Logical device numbers (LDNs). */ #define IT8716F_FDC 0x00 /* Floppy */ #define IT8716F_SP1 0x01 /* Com1 */ #define IT8716F_SP2 0x02 /* Com2 */ Modified: trunk/src/superio/ite/it8718f/it8718f.h ============================================================================== --- trunk/src/superio/ite/it8718f/it8718f.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/ite/it8718f/it8718f.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_ITE_IT8718F_IT8718F_H +#define SUPERIO_ITE_IT8718F_IT8718F_H + /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8718_2.asp */ #define IT8718F_FDC 0x00 /* Floppy */ @@ -36,3 +39,4 @@ void it8718f_enable_serial(device_t dev, u16 iobase); #endif +#endif Modified: trunk/src/superio/nsc/pc8374/chip.h ============================================================================== --- trunk/src/superio/nsc/pc8374/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/nsc/pc8374/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_NSC_PC8374_CHIP_H +#define SUPERIO_NSC_PC8374_CHIP_H + struct chip_operations; extern struct chip_operations superio_nsc_pc8374_ops; @@ -29,3 +32,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/nsc/pc8374/pc8374.h ============================================================================== --- trunk/src/superio/nsc/pc8374/pc8374.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/nsc/pc8374/pc8374.h Mon Nov 8 21:55:24 2010 (r6049) @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_NSC_PC8374_PC8374_H +#define SUPERIO_NSC_PC8374_PC8374_H + #define PC8374_FDC 0x00 /* Floppy */ #define PC8374_PP 0x01 /* Parallel port */ #define PC8374_SP2 0x02 /* Com2 */ @@ -27,4 +30,6 @@ #define PC8374_KBCM 0x05 /* Mouse */ #define PC8374_KBCK 0x06 /* Keyboard */ #define PC8374_GPIO 0x07 -#define PC8374_HM 0x08 +#define PC8374_HM 0x08 + +#endif Modified: trunk/src/superio/nsc/pc87309/chip.h ============================================================================== --- trunk/src/superio/nsc/pc87309/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/nsc/pc87309/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_NSC_PC87309_CHIP_H +#define SUPERIO_NSC_PC87309_CHIP_H + #include <pc80/keyboard.h> #include <uart8250.h> @@ -27,3 +30,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/nsc/pc87309/pc87309.h ============================================================================== --- trunk/src/superio/nsc/pc87309/pc87309.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/nsc/pc87309/pc87309.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,8 +18,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_NSC_PC87309_PC87309_H +#define SUPERIO_NSC_PC87309_PC87309_H + /* Datasheet: PC87309 SuperI/O Plug and Play Compatible Chip. */ -/* Status: Pre-RAM serial output is tested and works. The rest is untested. */ #define PC87309_FDC 0x00 /* Floppy */ #define PC87309_PP 0x01 /* Parallel port */ @@ -28,3 +30,5 @@ #define PC87309_PM 0x04 /* Power management */ #define PC87309_KBCM 0x05 /* Mouse */ #define PC87309_KBCK 0x06 /* Keyboard */ + +#endif Modified: trunk/src/superio/nsc/pc87351/chip.h ============================================================================== --- trunk/src/superio/nsc/pc87351/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/nsc/pc87351/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_NSC_PC87351_CHIP_H +#define SUPERIO_NSC_PC87351_CHIP_H + struct chip_operations; extern struct chip_operations superio_nsc_pc87351_ops; @@ -29,3 +32,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/nsc/pc87351/pc87351.h ============================================================================== --- trunk/src/superio/nsc/pc87351/pc87351.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/nsc/pc87351/pc87351.h Mon Nov 8 21:55:24 2010 (r6049) @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_NSC_PC87351_PC87351_H +#define SUPERIO_NSC_PC87351_PC87351_H + #define PC87351_FDC 0x00 /* Floppy */ #define PC87351_PP 0x01 /* Parallel port */ #define PC87351_SP2 0x02 /* Com2 */ @@ -28,3 +31,5 @@ #define PC87351_KBCK 0x06 /* Keyboard */ #define PC87351_GPIO 0x07 /* General purpose IO */ #define PC87351_FSD 0x08 /* Fan speed device */ + +#endif Modified: trunk/src/superio/nsc/pc87360/chip.h ============================================================================== --- trunk/src/superio/nsc/pc87360/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/nsc/pc87360/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_NSC_PC87360_CHIP_H +#define SUPERIO_NSC_PC87360_CHIP_H + struct chip_operations; extern struct chip_operations superio_nsc_pc87360_ops; @@ -29,3 +32,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/nsc/pc87360/pc87360.h ============================================================================== --- trunk/src/superio/nsc/pc87360/pc87360.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/nsc/pc87360/pc87360.h Mon Nov 8 21:55:24 2010 (r6049) @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_NSC_PC87360_PC87360_H +#define SUPERIO_NSC_PC87360_PC87360_H + #define PC87360_FDC 0x00 /* Floppy */ #define PC87360_PP 0x01 /* Parallel port */ #define PC87360_SP2 0x02 /* Com2 */ @@ -30,3 +33,5 @@ #define PC87360_ACB 0x08 #define PC87360_FSCM 0x09 #define PC87360_WDT 0x0A + +#endif Modified: trunk/src/superio/nsc/pc87366/chip.h ============================================================================== --- trunk/src/superio/nsc/pc87366/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/nsc/pc87366/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_NSC_PC87366_CHIP_H +#define SUPERIO_NSC_PC87366_CHIP_H + extern struct chip_operations superio_nsc_pc87366_ops; #include <pc80/keyboard.h> @@ -28,3 +31,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/nsc/pc87366/pc87366.h ============================================================================== --- trunk/src/superio/nsc/pc87366/pc87366.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/nsc/pc87366/pc87366.h Mon Nov 8 21:55:24 2010 (r6049) @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_NSC_PC87366_PC87366_H +#define SUPERIO_NSC_PC87366_PC87366_H + #define PC87366_FDC 0x00 /* Floppy */ #define PC87366_PP 0x01 /* Parallel port */ #define PC87366_SP2 0x02 /* Com2 */ @@ -31,6 +34,8 @@ #define PC87366_FSCM 0x09 #define PC87366_WDT 0x0A #define PC87366_GMP 0x0b -#define PC87366_MIDI 0x0C +#define PC87366_MIDI 0x0C #define PC87366_VLM 0x0D #define PC87366_TMS 0x0E + +#endif Modified: trunk/src/superio/nsc/pc87417/chip.h ============================================================================== --- trunk/src/superio/nsc/pc87417/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/nsc/pc87417/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -20,6 +20,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_NSC_PC87417_CHIP_H +#define SUPERIO_NSC_PC87417_CHIP_H + extern struct chip_operations superio_nsc_pc87417_ops; #include <pc80/keyboard.h> @@ -29,3 +32,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/nsc/pc87417/pc87417.h ============================================================================== --- trunk/src/superio/nsc/pc87417/pc87417.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/nsc/pc87417/pc87417.h Mon Nov 8 21:55:24 2010 (r6049) @@ -20,6 +20,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_NSC_PC87417_PC87417_H +#define SUPERIO_NSC_PC87417_PC87417_H + #define PC87417_FDC 0x00 /* Floppy */ #define PC87417_PP 0x01 /* Parallel Port */ #define PC87417_SP2 0x02 /* Com2 */ @@ -116,3 +119,4 @@ void pc87417_enable_dev(device_t dev); #endif +#endif Modified: trunk/src/superio/nsc/pc87427/chip.h ============================================================================== --- trunk/src/superio/nsc/pc87427/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/nsc/pc87427/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_NSC_PC87427_CHIP_H +#define SUPERIO_NSC_PC87427_CHIP_H + extern struct chip_operations superio_nsc_pc87427_ops; #include <pc80/keyboard.h> @@ -28,3 +31,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/nsc/pc87427/pc87427.h ============================================================================== --- trunk/src/superio/nsc/pc87427/pc87427.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/nsc/pc87427/pc87427.h Mon Nov 8 21:55:24 2010 (r6049) @@ -1,3 +1,6 @@ +#ifndef SUPERIO_NSC_PC87427_PC87427_H +#define SUPERIO_NSC_PC87427_PC87427_H + #define PC87427_FDC 0x00 /* Floppy */ #define PC87427_SP2 0x02 /* Com2 */ #define PC87427_SP1 0x03 /* Com1 */ @@ -91,4 +94,4 @@ #define PC87427_XSCNF 0x15 #define PC87427_XWBCNF 0x16 - +#endif Modified: trunk/src/superio/nsc/pc97307/chip.h ============================================================================== --- trunk/src/superio/nsc/pc97307/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/nsc/pc97307/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_NSC_PC97307 -#define _SUPERIO_NSC_PC97307 +#ifndef SUPERIO_NSC_PC97307_CHIP_H +#define SUPERIO_NSC_PC97307_CHIP_H #ifndef PNP_INDEX_REG #define PNP_INDEX_REG 0x15C @@ -37,4 +37,4 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; -#endif /* _SUPERIO_NSC_PC97307 */ +#endif Modified: trunk/src/superio/nsc/pc97307/pc97307.h ============================================================================== --- trunk/src/superio/nsc/pc97307/pc97307.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/nsc/pc97307/pc97307.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_NSC_PC97307_PC97307_H +#define SUPERIO_NSC_PC97307_PC97307_H + #define PC97307_KBCK 0x00 /* Keyboard */ #define PC97307_KBCM 0x01 /* Mouse */ #define PC97307_RTC 0x02 /* Real-Time Clock */ @@ -28,3 +31,4 @@ #define PC97307_GPIO 0x07 #define PC97307_PM 0x08 /* Power Management */ +#endif Modified: trunk/src/superio/nsc/pc97317/chip.h ============================================================================== --- trunk/src/superio/nsc/pc97317/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/nsc/pc97317/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_NSC_PC97317 -#define _SUPERIO_NSC_PC97317 +#ifndef SUPERIO_NSC_PC97317_CHIP_H +#define SUPERIO_NSC_PC97317_CHIP_H #ifndef PNP_INDEX_REG #define PNP_INDEX_REG 0x15C @@ -38,4 +38,4 @@ struct pc_keyboard keyboard; }; -#endif /* _SUPERIO_NSC_PC97317 */ +#endif Modified: trunk/src/superio/nsc/pc97317/pc97317.h ============================================================================== --- trunk/src/superio/nsc/pc97317/pc97317.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/nsc/pc97317/pc97317.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_NSC_PC97317_PC97317_H +#define SUPERIO_NSC_PC97317_PC97317_H + #define PC97317_KBCK 0x00 /* Keyboard */ #define PC97317_KBCM 0x01 /* Mouse */ #define PC97317_RTC 0x02 /* Real-Time Clock */ @@ -27,3 +30,5 @@ #define PC97317_SP1 0x06 /* Com1 */ #define PC97317_GPIO 0x07 #define PC97317_PM 0x08 /* Power Management */ + +#endif Modified: trunk/src/superio/renesas/m3885x/chip.h ============================================================================== --- trunk/src/superio/renesas/m3885x/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/renesas/m3885x/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_RENESAS_M3885X_CHIP_H +#define SUPERIO_RENESAS_M3885X_CHIP_H + #include <device/device.h> #include <pc80/keyboard.h> @@ -26,3 +29,4 @@ struct pc_keyboard keyboard; }; +#endif Modified: trunk/src/superio/serverengines/pilot/pilot.h ============================================================================== --- trunk/src/superio/serverengines/pilot/pilot.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/serverengines/pilot/pilot.h Mon Nov 8 21:55:24 2010 (r6049) @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_SERVERENGINES_PILOT_PILOT_H +#define SUPERIO_SERVERENGINES_PILOT_PILOT_H + /* PILOT Super I/O is only based on LPC observation done on factory system. */ #define PILOT_LD1 0x01 /* Logical device 1 */ @@ -26,3 +29,5 @@ #define PILOT_LD4 0x04 /* Logical device 4 */ #define PILOT_LD5 0x05 /* Logical device 5 */ #define PILOT_LD7 0x07 /* Logical device 7 */ + +#endif Modified: trunk/src/superio/smsc/fdc37m60x/chip.h ============================================================================== --- trunk/src/superio/smsc/fdc37m60x/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/smsc/fdc37m60x/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_SMSC_FDC37M60X -#define _SUPERIO_SMSC_FDC37M60X +#ifndef SUPERIO_SMSC_FDC37M60X_CHIP_H +#define SUPERIO_SMSC_FDC37M60X_CHIP_H #include <device/device.h> #include <pc80/keyboard.h> @@ -32,4 +32,4 @@ struct pc_keyboard keyboard; }; -#endif /* _SUPERIO_SMSC_FDC37M60X */ +#endif Modified: trunk/src/superio/smsc/fdc37m60x/fdc37m60x.h ============================================================================== --- trunk/src/superio/smsc/fdc37m60x/fdc37m60x.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/smsc/fdc37m60x/fdc37m60x.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_SMSC_FDC37M60X_FDC37M60X_H +#define SUPERIO_SMSC_FDC37M60X_FDC37M60X_H + /* * Datasheet: * - Name: FDC37M60x Enhanced Super I/O Controller with Infrared Support. @@ -36,3 +39,5 @@ #define FDC37M60X_SP2 0x05 /* Com2 */ #define FDC37M60X_KBCK 0x07 /* Keyboard */ #define FDC37M60X_AUX 0x08 /* Auxiliary I/O */ + +#endif Modified: trunk/src/superio/smsc/fdc37n972/chip.h ============================================================================== --- trunk/src/superio/smsc/fdc37n972/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/smsc/fdc37n972/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_SMSC_FDC37N972 -#define _SUPERIO_SMSC_FDC37N972 +#ifndef SUPERIO_SMSC_FDC37N972_CHIP_H +#define SUPERIO_SMSC_FDC37N972_CHIP_H #include <device/device.h> #include <pc80/keyboard.h> @@ -31,5 +31,5 @@ struct pc_keyboard keyboard; }; -#endif /* _SUPERIO_SMSC_FDC37N972 */ +#endif Modified: trunk/src/superio/smsc/fdc37n972/fdc37n972.h ============================================================================== --- trunk/src/superio/smsc/fdc37n972/fdc37n972.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/smsc/fdc37n972/fdc37n972.h Mon Nov 8 21:55:24 2010 (r6049) @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_SMSC_FDC37N972_FDC37N972_H +#define SUPERIO_SMSC_FDC37N972_FDC37N972_H + #define FDC37N972_FDC 0x00 /* Floppy */ #define FDC37N972_PP 0x03 /* Parallel port */ #define FDC37N972_SP1 0x04 /* Serial port 1 */ @@ -26,3 +29,4 @@ #define FDC37N972_EC 0x08 /* Environmental Controller */ #define FDC37N972_MBX 0x09 /* Mailbox register */ +#endif Modified: trunk/src/superio/smsc/lpc47b272/chip.h ============================================================================== --- trunk/src/superio/smsc/lpc47b272/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/smsc/lpc47b272/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_SMSC_LPC47B272_CHIP_H +#define SUPERIO_SMSC_LPC47B272_CHIP_H + struct chip_operations; extern struct chip_operations superio_smsc_lpc47b272_ops; @@ -28,3 +31,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/smsc/lpc47b272/lpc47b272.h ============================================================================== --- trunk/src/superio/smsc/lpc47b272/lpc47b272.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/smsc/lpc47b272/lpc47b272.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_SMSC_LPC47B272_LPC47B272_H +#define SUPERIO_SMSC_LPC47B272_LPC47B272_H + #define LPC47B272_FDC 0 /* Floppy */ #define LPC47B272_PP 3 /* Parallel Port */ #define LPC47B272_SP1 4 /* Com1 */ @@ -26,3 +29,5 @@ #define LPC47B272_RT 10 /* Runtime reg*/ #define LPC47B272_MAX_CONFIG_REGISTER 0x5F + +#endif Modified: trunk/src/superio/smsc/lpc47b397/chip.h ============================================================================== --- trunk/src/superio/smsc/lpc47b397/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/smsc/lpc47b397/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -20,6 +20,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_SMSC_LPC47B397_CHIP_H +#define SUPERIO_SMSC_LPC47B397_CHIP_H + struct chip_operations; extern struct chip_operations superio_smsc_lpc47b397_ops; @@ -30,3 +33,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/smsc/lpc47b397/lpc47b397.h ============================================================================== --- trunk/src/superio/smsc/lpc47b397/lpc47b397.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/smsc/lpc47b397/lpc47b397.h Mon Nov 8 21:55:24 2010 (r6049) @@ -20,6 +20,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_SMSC_LPC47B397_LPC47B397_H +#define SUPERIO_SMSC_LPC47B397_LPC47B397_H + #define LPC47B397_FDC 0 /* Floppy */ #define LPC47B397_PP 3 /* Parallel Port */ #define LPC47B397_SP1 4 /* Com1 */ @@ -27,3 +30,5 @@ #define LPC47B397_KBC 7 /* Keyboard & Mouse */ #define LPC47B397_HWM 8 /* HW Monitor */ #define LPC47B397_RT 10 /* Runtime reg*/ + +#endif Modified: trunk/src/superio/smsc/lpc47m10x/chip.h ============================================================================== --- trunk/src/superio/smsc/lpc47m10x/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/smsc/lpc47m10x/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -22,6 +22,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_SMSC_LPC47M10X_CHIP_H +#define SUPERIO_SMSC_LPC47M10X_CHIP_H + struct chip_operations; extern struct chip_operations superio_smsc_lpc47m10x_ops; @@ -32,3 +35,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/smsc/lpc47m10x/lpc47m10x.h ============================================================================== --- trunk/src/superio/smsc/lpc47m10x/lpc47m10x.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/smsc/lpc47m10x/lpc47m10x.h Mon Nov 8 21:55:24 2010 (r6049) @@ -20,6 +20,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_SMSC_LPC47M10X_LPC47M10X_H +#define SUPERIO_SMSC_LPC47M10X_LPC47M10X_H + #define LPC47M10X2_FDC 0 /* Floppy */ #define LPC47M10X2_PP 3 /* Parallel Port */ #define LPC47M10X2_SP1 4 /* Com1 */ @@ -30,3 +33,5 @@ #define LPC47M10X2_MPU 10 /* MPE -- who knows -- reg*/ #define LPC47M10X2_MAX_CONFIG_REGISTER 0x5F + +#endif Modified: trunk/src/superio/smsc/lpc47m15x/chip.h ============================================================================== --- trunk/src/superio/smsc/lpc47m15x/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/smsc/lpc47m15x/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_SMSC_LPC47M15X_CHIP_H +#define SUPERIO_SMSC_LPC47M15X_CHIP_H + struct chip_operations; extern struct chip_operations superio_smsc_lpc47m15x_ops; @@ -27,3 +30,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/smsc/lpc47m15x/lpc47m15x.h ============================================================================== --- trunk/src/superio/smsc/lpc47m15x/lpc47m15x.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/smsc/lpc47m15x/lpc47m15x.h Mon Nov 8 21:55:24 2010 (r6049) @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_SMSC_LPC47M15X_LPC47M15X_H +#define SUPERIO_SMSC_LPC47M15X_LPC47M15X_H + #define LPC47M15X_FDC 0 /* Floppy */ #define LPC47M15X_PP 3 /* Parallel Port */ #define LPC47M15X_SP1 4 /* Com1 */ @@ -27,3 +30,5 @@ #define LPC47M15X_MPU 11 /* MPE -- who knows -- reg*/ #define LPC47M15X2_MAX_CONFIG_REGISTER 0x5F + +#endif Modified: trunk/src/superio/smsc/lpc47n217/chip.h ============================================================================== --- trunk/src/superio/smsc/lpc47n217/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/smsc/lpc47n217/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_SMSC_LPC47N217_CHIP_H +#define SUPERIO_SMSC_LPC47N217_CHIP_H + struct chip_operations; extern struct chip_operations superio_smsc_lpc47n217_ops; @@ -26,3 +29,5 @@ struct superio_smsc_lpc47n217_config { struct uart8250 com1, com2; }; + +#endif Modified: trunk/src/superio/smsc/lpc47n217/lpc47n217.h ============================================================================== --- trunk/src/superio/smsc/lpc47n217/lpc47n217.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/smsc/lpc47n217/lpc47n217.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,12 +18,17 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* These are arbitrary, but must match declarations in the mainboard config file. - * Values chosen to match SMSC 47B37x. - */ +#ifndef SUPERIO_SMSC_LPC47N217_LPC47N217_H +#define SUPERIO_SMSC_LPC47N217_LPC47N217_H +/* + * These are arbitrary, but must match declarations in the mainboard + * devicetree.cb file. Values chosen to match SMSC LPC47B37x. + */ #define LPC47N217_PP 3 /* Parallel Port */ #define LPC47N217_SP1 4 /* Com1 */ #define LPC47N217_SP2 5 /* Com2 */ #define LPC47N217_MAX_CONFIG_REGISTER 0x39 + +#endif Modified: trunk/src/superio/smsc/lpc47n227/chip.h ============================================================================== --- trunk/src/superio/smsc/lpc47n227/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/smsc/lpc47n227/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_SMSC_LPC47N227_CHIP_H +#define SUPERIO_SMSC_LPC47N227_CHIP_H + #include <device/device.h> #include <pc80/keyboard.h> #include <uart8250.h> @@ -27,3 +30,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/smsc/lpc47n227/lpc47n227.h ============================================================================== --- trunk/src/superio/smsc/lpc47n227/lpc47n227.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/smsc/lpc47n227/lpc47n227.h Mon Nov 8 21:55:24 2010 (r6049) @@ -17,6 +17,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_SMSC_LPC47N227_LPC47N227_H +#define SUPERIO_SMSC_LPC47N227_LPC47N227_H + /* * Since the LPC47N227 does not have logical devices but a flat configuration * space, these are arbitrary, but must match declarations in the mainboard @@ -28,3 +31,5 @@ #define LPC47N227_KBDC 5 /* Keyboard */ #define LPC47N227_MAX_CONFIG_REGISTER 0x39 + +#endif Modified: trunk/src/superio/smsc/sio10n268/chip.h ============================================================================== --- trunk/src/superio/smsc/sio10n268/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/smsc/sio10n268/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -17,8 +17,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_SMSC_SIO10N268 -#define _SUPERIO_SMSC_SIO10N268 +#ifndef SUPERIO_SMSC_SIO10N268_CHIP_H +#define SUPERIO_SMSC_SIO10N268_CHIP_H #include <device/device.h> #include <pc80/keyboard.h> @@ -31,5 +31,4 @@ struct pc_keyboard keyboard; }; -#endif /* _SUPERIO_SMSC_SIO10N268 */ - +#endif Modified: trunk/src/superio/smsc/sio10n268/sio10n268.h ============================================================================== --- trunk/src/superio/smsc/sio10n268/sio10n268.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/smsc/sio10n268/sio10n268.h Mon Nov 8 21:55:24 2010 (r6049) @@ -17,9 +17,13 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -// XXX the SIO10N268 has no logical devices. +#ifndef SUPERIO_SMSC_SIO10N268_SIO10N268_H +#define SUPERIO_SMSC_SIO10N268_SIO10N268_H + +/* Note: The SIO10N268 has no logical devices. */ #define SIO10N268_FDC 0x00 /* Floppy */ #define SIO10N268_PP 0x03 /* Parallel port */ #define SIO10N268_KBDC 0x05 /* Keyboard */ +#endif Modified: trunk/src/superio/smsc/smscsuperio/Makefile.inc ============================================================================== --- trunk/src/superio/smsc/smscsuperio/Makefile.inc Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/smsc/smscsuperio/Makefile.inc Mon Nov 8 21:55:24 2010 (r6049) @@ -18,5 +18,4 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_SMSC_SMSCSUPERIO) += superio.c Modified: trunk/src/superio/smsc/smscsuperio/chip.h ============================================================================== --- trunk/src/superio/smsc/smscsuperio/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/smsc/smscsuperio/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_SMSC_SMSCSUPERIO_CHIP_H +#define SUPERIO_SMSC_SMSCSUPERIO_CHIP_H + #include <device/device.h> #include <pc80/keyboard.h> #include <uart8250.h> @@ -28,3 +31,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/via/vt1211/vt1211.h ============================================================================== --- trunk/src/superio/via/vt1211/vt1211.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/via/vt1211/vt1211.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_VIA_VT1211_VT1211_H +#define SUPERIO_VIA_VT1211_VT1211_H + /* Logical device numbers (LDNs). */ #define VT1211_FDC 0x00 /* Floppy */ #define VT1211_PP 0x01 /* Parallel port */ @@ -31,3 +34,5 @@ #define VT1211_HWM 0x0b /* Hardware monitor (HM) */ #define VT1211_FIR 0x0c /* Very fast IR (VFIR/FIR) */ #define VT1211_ROM 0x0d /* Flash ROM */ + +#endif Modified: trunk/src/superio/winbond/w83627dhg/chip.h ============================================================================== --- trunk/src/superio/winbond/w83627dhg/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/winbond/w83627dhg/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_WINBOND_W83627DHG_CHIP_H +#define SUPERIO_WINBOND_W83627DHG_CHIP_H + #include <pc80/keyboard.h> #include <uart8250.h> @@ -27,3 +30,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/winbond/w83627dhg/w83627dhg.h ============================================================================== --- trunk/src/superio/winbond/w83627dhg/w83627dhg.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/winbond/w83627dhg/w83627dhg.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_WINBOND_W83627DHG_W83627DHG_H +#define SUPERIO_WINBOND_W83627DHG_W83627DHG_H + #define W83627DHG_FDC 0 /* Floppy */ #define W83627DHG_PP 1 /* Parallel port */ #define W83627DHG_SP1 2 /* Com1 */ @@ -30,3 +33,5 @@ #define W83627DHG_ACPI 10 /* ACPI */ #define W83627DHG_HWM 11 /* Hardware monitor */ #define W83627DHG_PECI_SST 12 /* PECI, SST */ + +#endif Modified: trunk/src/superio/winbond/w83627ehg/chip.h ============================================================================== --- trunk/src/superio/winbond/w83627ehg/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/winbond/w83627ehg/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -19,6 +19,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_WINBOND_W83627EHG_CHIP_H +#define SUPERIO_WINBOND_W83627EHG_CHIP_H + #include <pc80/keyboard.h> #include <uart8250.h> @@ -28,3 +31,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/winbond/w83627ehg/w83627ehg.h ============================================================================== --- trunk/src/superio/winbond/w83627ehg/w83627ehg.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/winbond/w83627ehg/w83627ehg.h Mon Nov 8 21:55:24 2010 (r6049) @@ -19,8 +19,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __SUPERIO_WINBOND_W83627EHG_W83627EHG_H -#define __SUPERIO_WINBOND_W83627EHG_W83627EHG_H +#ifndef SUPERIO_WINBOND_W83627EHG_W83627EHG_H +#define SUPERIO_WINBOND_W83627EHG_W83627EHG_H #define W83627EHG_FDC 0 /* Floppy */ #define W83627EHG_PP 1 /* Parallel Port */ Modified: trunk/src/superio/winbond/w83627hf/chip.h ============================================================================== --- trunk/src/superio/winbond/w83627hf/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/winbond/w83627hf/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -20,6 +20,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_WINBOND_W83627HF_CHIP_H +#define SUPERIO_WINBOND_W83627HF_CHIP_H + #include <pc80/keyboard.h> #include <uart8250.h> @@ -29,3 +32,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/winbond/w83627hf/w83627hf.h ============================================================================== --- trunk/src/superio/winbond/w83627hf/w83627hf.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/winbond/w83627hf/w83627hf.h Mon Nov 8 21:55:24 2010 (r6049) @@ -20,8 +20,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef __SUPERIO_WINBOND_W83627HF_W83627HF_H -#define __SUPERIO_WINBOND_W83627HF_W83627HF_H +#ifndef SUPERIO_WINBOND_W83627HF_W83627HF_H +#define SUPERIO_WINBOND_W83627HF_W83627HF_H #define W83627HF_FDC 0 /* Floppy */ #define W83627HF_PP 1 /* Parallel Port */ Modified: trunk/src/superio/winbond/w83627thf/chip.h ============================================================================== --- trunk/src/superio/winbond/w83627thf/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/winbond/w83627thf/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -20,6 +20,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_WINBOND_W83627THF_CHIP_H +#define SUPERIO_WINBOND_W83627THF_CHIP_H + #include <pc80/keyboard.h> #include <uart8250.h> @@ -29,3 +32,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/winbond/w83627thf/w83627thf.h ============================================================================== --- trunk/src/superio/winbond/w83627thf/w83627thf.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/winbond/w83627thf/w83627thf.h Mon Nov 8 21:55:24 2010 (r6049) @@ -20,6 +20,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_WINBOND_W83627THF_W83627THF_H +#define SUPERIO_WINBOND_W83627THF_W83627THF_H + #define W83627THF_FDC 0 /* Floppy */ #define W83627THF_PP 1 /* Parallel Port */ #define W83627THF_SP1 2 /* Com1 */ @@ -31,3 +34,5 @@ #define W83627THF_GPIO3 9 #define W83627THF_ACPI 10 #define W83627THF_HWM 11 /* Hardware Monitor */ + +#endif Modified: trunk/src/superio/winbond/w83627thg/chip.h ============================================================================== --- trunk/src/superio/winbond/w83627thg/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/winbond/w83627thg/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -20,6 +20,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_WINBOND_W83627THG_CHIP_H +#define SUPERIO_WINBOND_W83627THG_CHIP_H + #include <pc80/keyboard.h> #include <uart8250.h> @@ -29,3 +32,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/winbond/w83627thg/w83627thg.h ============================================================================== --- trunk/src/superio/winbond/w83627thg/w83627thg.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/winbond/w83627thg/w83627thg.h Mon Nov 8 21:55:24 2010 (r6049) @@ -20,6 +20,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_WINBOND_W83627THG_W83627THG_H +#define SUPERIO_WINBOND_W83627THG_W83627THG_H + #define W83627THG_FDC 0 /* Floppy */ #define W83627THG_PP 1 /* Parallel Port */ #define W83627THG_SP1 2 /* Com1 */ @@ -30,3 +33,5 @@ #define W83627THG_GPIO3 9 #define W83627THG_ACPI 10 #define W83627THG_HWM 11 /* Hardware Monitor */ + +#endif Modified: trunk/src/superio/winbond/w83627uhg/chip.h ============================================================================== --- trunk/src/superio/winbond/w83627uhg/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/winbond/w83627uhg/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 $ */ +#ifndef SUPERIO_WINBOND_W83627UHG_CHIP_H +#define SUPERIO_WINBOND_W83627UHG_CHIP_H + #include <pc80/keyboard.h> #include <uart8250.h> @@ -27,3 +30,5 @@ struct uart8250 com1, com2, com3, com4, com5, com6; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/winbond/w83627uhg/w83627uhg.h ============================================================================== --- trunk/src/superio/winbond/w83627uhg/w83627uhg.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/winbond/w83627uhg/w83627uhg.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 $ */ +#ifndef SUPERIO_WINBOND_W83627UHG_W83627UHG_H +#define SUPERIO_WINBOND_W83627UHG_W83627UHG_H + #define W83627UHG_FDC 0 /* Floppy */ #define W83627UHG_PP 1 /* Parallel port */ #define W83627UHG_SP1 2 /* Com1 */ @@ -33,3 +36,5 @@ #define W83627UHG_SP4 13 /* Com4 */ #define W83627UHG_SP5 14 /* Com5 */ #define W83627UHG_SP6 15 /* Com6 */ + +#endif Modified: trunk/src/superio/winbond/w83697hf/chip.h ============================================================================== --- trunk/src/superio/winbond/w83697hf/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/winbond/w83697hf/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_WINBOND_W83697HF_CHIP_H +#define SUPERIO_WINBOND_W83697HF_CHIP_H + #include <uart8250.h> extern struct chip_operations superio_winbond_w83697hf_ops; @@ -25,3 +28,5 @@ struct superio_winbond_w83697hf_config { struct uart8250 com1, com2; }; + +#endif Modified: trunk/src/superio/winbond/w83697hf/w83697hf.h ============================================================================== --- trunk/src/superio/winbond/w83697hf/w83697hf.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/winbond/w83697hf/w83697hf.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_WINBOND_W83697HF_W83697HF_H +#define SUPERIO_WINBOND_W83697HF_W83697HF_H + #define W83697HF_FDC 0 /* Floppy */ #define W83697HF_PP 1 /* Parallel Port */ #define W83697HF_SP1 2 /* Com1 */ @@ -28,3 +31,5 @@ #define W83697HF_GPIO234 9 /* GPIO 2, 3, 4 */ #define W83697HF_ACPI 10 /* ACPI */ #define W83697HF_HWM 11 /* Hardware Monitor */ + +#endif Modified: trunk/src/superio/winbond/w83977f/chip.h ============================================================================== --- trunk/src/superio/winbond/w83977f/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/winbond/w83977f/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_WINBOND_W83977F_CHIP_H +#define SUPERIO_WINBOND_W83977F_CHIP_H + #include <pc80/keyboard.h> #include <uart8250.h> @@ -27,3 +30,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/winbond/w83977f/w83977f.h ============================================================================== --- trunk/src/superio/winbond/w83977f/w83977f.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/winbond/w83977f/w83977f.h Mon Nov 8 21:55:24 2010 (r6049) @@ -18,6 +18,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_WINBOND_W83977F_W83977F_H +#define SUPERIO_WINBOND_W83977F_W83977F_H + #define W83977F_FDC 0 /* Floppy */ #define W83977F_PP 1 /* Parallel Port */ #define W83977F_SP1 2 /* Com1 */ @@ -27,3 +30,5 @@ #define W83977F_IR 6 /* Infrared Port */ #define W83977F_GPIO1 7 /* General Purpose I/O 1 */ #define W83977F_GPIO2 8 /* General Purpose I/O 2 */ + +#endif Modified: trunk/src/superio/winbond/w83977tf/chip.h ============================================================================== --- trunk/src/superio/winbond/w83977tf/chip.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/winbond/w83977tf/chip.h Mon Nov 8 21:55:24 2010 (r6049) @@ -20,6 +20,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_WINBOND_W83977TF_CHIP_H +#define SUPERIO_WINBOND_W83977TF_CHIP_H + #include <pc80/keyboard.h> #include <uart8250.h> @@ -29,3 +32,5 @@ struct uart8250 com1, com2; struct pc_keyboard keyboard; }; + +#endif Modified: trunk/src/superio/winbond/w83977tf/w83977tf.h ============================================================================== --- trunk/src/superio/winbond/w83977tf/w83977tf.h Mon Nov 8 18:41:43 2010 (r6048) +++ trunk/src/superio/winbond/w83977tf/w83977tf.h Mon Nov 8 21:55:24 2010 (r6049) @@ -20,6 +20,9 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ +#ifndef SUPERIO_WINBOND_W83977TF_W83977TF_H +#define SUPERIO_WINBOND_W83977TF_W83977TF_H + #define W83977TF_FDC 0 /* Floppy */ #define W83977TF_PP 1 /* Parallel Port */ #define W83977TF_SP1 2 /* Com1 */ @@ -30,3 +33,5 @@ #define W83977TF_GPIO2 8 #define W83977TF_GPIO3 9 #define W83977TF_ACPI 10 + +#endif

1 0

[PATCH] don't print too early on mcp55-based boards
by Ward Vandewege 08 Nov '10

08 Nov '10

See attached. Perhaps we should also print a post code if the SMBus controller can't be found - suggestions for a value? Thanks, Ward. -- Ward Vandewege <ward(a)fsf.org> Free Software Foundation - Senior Systems Administrator

4 6

[commit] r6048 - trunk/src/southbridge/nvidia/mcp55
by repository service 08 Nov '10

08 Nov '10

Author: ward Date: Mon Nov 8 18:41:43 2010 New Revision: 6048 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6048 Log: We can't print this early. This patch fixes a hang on supermicro/h8dme supermicro/h8dmr supermicro/h8dmr_fam10 and possibly on other mcp55-based boards. Signed-off-by: Ward Vandewege <ward(a)gnu.org> Acked-by: Peter Stuge <peter(a)stuge.se> Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c ============================================================================== --- trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c Mon Nov 8 16:16:30 2010 (r6047) +++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c Mon Nov 8 18:41:43 2010 (r6048) @@ -32,11 +32,8 @@ device_t dev; dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0); - if (dev == PCI_DEV_INVALID) { - printk(BIOS_WARNING, "SMBUS controller not found\n"); - } else { - printk(BIOS_DEBUG, "SMBus controller enabled\n"); - } + if (dev == PCI_DEV_INVALID) + die("SMBus controller not found\n"); /* set smbus iobase */ pci_write_config32(dev, 0x20, SMBUS0_IO_BASE | 1);

1 0

coreboot on dell mini 9
by HacKurx 08 Nov '10

08 Nov '10

Hello, Is it possible to install coreboot on dell mini9? I enclose my command to see. Thank you for your help and sorry for my English. --------------------------------- [hackurx@Admin ~]$ su root Mot de passe : [root@Admin hackurx]# cd Dell-mini9/ [root@Admin Dell-mini9]# lspci -nnvvvxxxx > lscpi.log [root@Admin Dell-mini9]# lspnp -vv > lspnp.log Commande non trouvée [root@Admin Dell-mini9]# lsusb -vvv > lsusb.log [root@Admin Dell-mini9]# superiotool -deV > superiotool.log [root@Admin Dell-mini9]# inteltool -a > inteltool.log [root@Admin Dell-mini9]# ectool > ectool.log [root@Admin Dell-mini9]# msrtool > msrtool.log msrtool 5566 Detected system linux: Linux with /dev/cpu/*/msr Unable to detect a known target; can not decode any MSRs! (Use -t to force) Please send a report or patch to coreboot(a)coreboot.org. Thanks for your help! [root@Admin Dell-mini9]# msrtool -t > msrtool.log msrtool: option requires an argument -- 't' msrtool 5566 Detected system linux: Linux with /dev/cpu/*/msr Unable to detect a known target; can not decode any MSRs! (Use -t to force) Please send a report or patch to coreboot(a)coreboot.org. Thanks for your help! [root@Admin Dell-mini9]# msrtool --t > msrtool.log msrtool: invalid option -- '-' msrtool: option requires an argument -- 't' msrtool 5566 Detected system linux: Linux with /dev/cpu/*/msr Unable to detect a known target; can not decode any MSRs! (Use -t to force) Please send a report or patch to coreboot(a)coreboot.org. Thanks for your help! [root@Admin Dell-mini9]# msrtool t > msrtool.log msrtool 5566 Detected system linux: Linux with /dev/cpu/*/msr Unable to detect a known target; can not decode any MSRs! (Use -t to force) Please send a report or patch to coreboot(a)coreboot.org. Thanks for your help! [root@Admin Dell-mini9]# msrtool -t > msrtool.log msrtool: option requires an argument -- 't' msrtool 5566 Detected system linux: Linux with /dev/cpu/*/msr Unable to detect a known target; can not decode any MSRs! (Use -t to force) Please send a report or patch to coreboot(a)coreboot.org. Thanks for your help! [root@Admin Dell-mini9]# dmidecode > dmidecode.log [root@Admin Dell-mini9]# biosdecode > biosdecode.log [root@Admin Dell-mini9]# nvramtool -x > nvramtool.log [root@Admin Dell-mini9]# dmesg > dmesg.log [root@Admin Dell-mini9]# flashrom -V -p internal:laptop=force_I_want_a_brick > flashrom_info.log ======================================================================== WARNING! You seem to be running flashrom on a laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Proceeding anyway because user specified laptop=force_I_want_a_brick [root@Admin Dell-mini9]# flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin > flashrom_read.log ======================================================================== WARNING! You seem to be running flashrom on a laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. ======================================================================== Proceeding anyway because user specified laptop=force_I_want_a_brick [root@Admin Dell-mini9]# ----------------------------------------

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[commit] r6047 - in trunk/src/superio/ite: it8661f it8671f it8673f it8705f it8712f it8716f it8718f
by repository service 08 Nov '10

08 Nov '10

Author: uwe Date: Mon Nov 8 16:16:30 2010 New Revision: 6047 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6047 Log: Random ITE Super I/O fixes. - Drop some of the less useful / outdated / duplicated comments. - Simplify and streamline some code to look like the other Super I/Os. - Use u8/16/etc. everywhere. - ITE IT8718F: Add missing GPIO LDN. - Add missing braces around SIO_DATA #defines, potential bug even. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/superio/ite/it8661f/Makefile.inc trunk/src/superio/ite/it8661f/chip.h trunk/src/superio/ite/it8661f/it8661f.h trunk/src/superio/ite/it8661f/it8661f_early_serial.c trunk/src/superio/ite/it8661f/superio.c trunk/src/superio/ite/it8671f/Makefile.inc trunk/src/superio/ite/it8671f/chip.h trunk/src/superio/ite/it8671f/it8671f.h trunk/src/superio/ite/it8671f/it8671f_early_serial.c trunk/src/superio/ite/it8671f/superio.c trunk/src/superio/ite/it8673f/Makefile.inc trunk/src/superio/ite/it8673f/chip.h trunk/src/superio/ite/it8673f/it8673f.h trunk/src/superio/ite/it8673f/it8673f_early_serial.c trunk/src/superio/ite/it8673f/superio.c trunk/src/superio/ite/it8705f/Makefile.inc trunk/src/superio/ite/it8705f/chip.h trunk/src/superio/ite/it8705f/it8705f.h trunk/src/superio/ite/it8705f/it8705f_early_serial.c trunk/src/superio/ite/it8705f/superio.c trunk/src/superio/ite/it8712f/Makefile.inc trunk/src/superio/ite/it8712f/chip.h trunk/src/superio/ite/it8712f/it8712f.h trunk/src/superio/ite/it8712f/it8712f_early_serial.c trunk/src/superio/ite/it8712f/superio.c trunk/src/superio/ite/it8716f/Makefile.inc trunk/src/superio/ite/it8716f/chip.h trunk/src/superio/ite/it8716f/it8716f.h trunk/src/superio/ite/it8716f/it8716f_early_init.c trunk/src/superio/ite/it8716f/it8716f_early_serial.c trunk/src/superio/ite/it8716f/superio.c trunk/src/superio/ite/it8718f/Makefile.inc trunk/src/superio/ite/it8718f/chip.h trunk/src/superio/ite/it8718f/it8718f.h trunk/src/superio/ite/it8718f/it8718f_early_serial.c trunk/src/superio/ite/it8718f/superio.c Modified: trunk/src/superio/ite/it8661f/Makefile.inc ============================================================================== --- trunk/src/superio/ite/it8661f/Makefile.inc Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8661f/Makefile.inc Mon Nov 8 16:16:30 2010 (r6047) @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_ITE_IT8661F) += superio.c + Modified: trunk/src/superio/ite/it8661f/chip.h ============================================================================== --- trunk/src/superio/ite/it8661f/chip.h Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8661f/chip.h Mon Nov 8 16:16:30 2010 (r6047) @@ -18,10 +18,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_ITE_IT8661F -#define _SUPERIO_ITE_IT8661F +#ifndef SUPERIO_ITE_IT8661F_CHIP_H +#define SUPERIO_ITE_IT8661F_CHIP_H -/* This chip doesn't seem to have keyboard and mouse support. */ +/* This chip doesn't have keyboard and mouse support. */ #include <device/device.h> #include <uart8250.h> @@ -32,4 +32,4 @@ struct uart8250 com1, com2; }; -#endif /* _SUPERIO_ITE_IT8661F */ +#endif Modified: trunk/src/superio/ite/it8661f/it8661f.h ============================================================================== --- trunk/src/superio/ite/it8661f/it8661f.h Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8661f/it8661f.h Mon Nov 8 16:16:30 2010 (r6047) @@ -19,9 +19,6 @@ */ /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8661_2.asp */ -/* Status: Untested on real hardware, but it compiles. */ - -/* This chip doesn't seem to have keyboard and mouse support. */ #define IT8661F_FDC 0x00 /* Floppy */ #define IT8661F_SP1 0x01 /* Com1 */ Modified: trunk/src/superio/ite/it8661f/it8661f_early_serial.c ============================================================================== --- trunk/src/superio/ite/it8661f/it8661f_early_serial.c Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8661f/it8661f_early_serial.c Mon Nov 8 16:16:30 2010 (r6047) @@ -24,7 +24,7 @@ /* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ #define SIO_BASE 0x3f0 #define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 +#define SIO_DATA (SIO_BASE + 1) /* Global configuration registers. */ #define IT8661F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ @@ -34,18 +34,18 @@ #define IT8661F_CONFIGURATION_PORT 0x0279 /* Write-only. */ -/* Special values used for entering MB PnP mode. The first four bytes of - each line determine the address port, the last four are data. */ -static const uint8_t init_values[] = { +/* + * Special values used for entering MB PnP mode. The first four bytes of + * each line determine the address port, the last four are data. + */ +static const u8 init_values[] = { 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe, 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61, 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1, 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, }; -/* The content of IT8661F_CONFIG_REG_LDN (index 0x07) must be set to the - LDN the register belongs to, before you can access the register. */ -static void it8661f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) +static void it8661f_sio_write(u8 ldn, u8 index, u8 value) { outb(IT8661F_CONFIG_REG_LDN, SIO_BASE); outb(ldn, SIO_DATA); @@ -53,10 +53,10 @@ outb(value, SIO_DATA); } -/* Enable the peripheral devices on the IT8661F Super I/O chip. */ -static void it8661f_enable_serial(device_t dev, unsigned iobase) +/* Enable the serial port(s). */ +static void it8661f_enable_serial(device_t dev, u16 iobase) { - uint8_t i; + int i; /* (1) Enter the configuration state (MB PnP mode). */ @@ -70,19 +70,20 @@ outb(0x55, IT8661F_CONFIGURATION_PORT); /* Sequentially write the 32 special values. */ - for (i = 0; i < 32; i++) { + for (i = 0; i < 32; i++) outb(init_values[i], SIO_BASE); - } /* (2) Modify the data of configuration registers. */ - /* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2), - PP (3), IR (4). Bits 5-7 are reserved. */ + /* + * Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2), + * PP (3), IR (4). Bits 5-7 are reserved. + */ it8661f_sio_write(0x00, IT8661F_CONFIG_REG_LDE, 0x1f); /* Enable serial port(s). */ - it8661f_sio_write(IT8661F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8661f_sio_write(IT8661F_SP2, 0x30, 0x1); /* Serial port 2 */ + it8661f_sio_write(IT8661F_SP1, 0x30, 0x1); /* Serial port 1 */ + it8661f_sio_write(IT8661F_SP2, 0x30, 0x1); /* Serial port 2 */ /* Select 24MHz CLKIN (clear bit 1) and clear software suspend mode (clear bit 0). */ Modified: trunk/src/superio/ite/it8661f/superio.c ============================================================================== --- trunk/src/superio/ite/it8661f/superio.c Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8661f/superio.c Mon Nov 8 16:16:30 2010 (r6047) @@ -18,8 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This chip doesn't seem to have keyboard and mouse support. */ - #include <device/device.h> #include <device/pnp.h> #include <uart8250.h> @@ -29,14 +27,11 @@ static void init(device_t dev) { - struct superio_ite_it8661f_config *conf; + struct superio_ite_it8661f_config *conf = dev->chip_info; struct resource *res0, *res1; - if (!dev->enabled) { + if (!dev->enabled) return; - } - - conf = dev->chip_info; switch (dev->path.pnp.device) { case IT8661F_FDC: /* TODO. */ Modified: trunk/src/superio/ite/it8671f/Makefile.inc ============================================================================== --- trunk/src/superio/ite/it8671f/Makefile.inc Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8671f/Makefile.inc Mon Nov 8 16:16:30 2010 (r6047) @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_ITE_IT8671F) += superio.c + Modified: trunk/src/superio/ite/it8671f/chip.h ============================================================================== --- trunk/src/superio/ite/it8671f/chip.h Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8671f/chip.h Mon Nov 8 16:16:30 2010 (r6047) @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_ITE_IT8671F -#define _SUPERIO_ITE_IT8671F +#ifndef SUPERIO_ITE_IT8671F_CHIP_H +#define SUPERIO_ITE_IT8671F_CHIP_H #include <device/device.h> #include <pc80/keyboard.h> @@ -32,4 +32,4 @@ struct pc_keyboard keyboard; }; -#endif /* _SUPERIO_ITE_IT8671F */ +#endif Modified: trunk/src/superio/ite/it8671f/it8671f.h ============================================================================== --- trunk/src/superio/ite/it8671f/it8671f.h Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8671f/it8671f.h Mon Nov 8 16:16:30 2010 (r6047) @@ -19,11 +19,10 @@ */ /* Datasheet: Not available online, got it from ITE per request. */ -/* Status: Com1 is tested and works. */ #define IT8671F_FDC 0x00 /* Floppy */ #define IT8671F_SP1 0x01 /* Com1 */ #define IT8671F_SP2 0x02 /* Com2 */ #define IT8671F_PP 0x03 /* Parallel port */ -#define IT8671F_KBCK 0x05 /* Keyboard */ -#define IT8671F_KBCM 0x06 /* Mouse */ +#define IT8671F_KBCK 0x05 /* PS/2 keyboard */ +#define IT8671F_KBCM 0x06 /* PS/2 mouse */ Modified: trunk/src/superio/ite/it8671f/it8671f_early_serial.c ============================================================================== --- trunk/src/superio/ite/it8671f/it8671f_early_serial.c Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8671f/it8671f_early_serial.c Mon Nov 8 16:16:30 2010 (r6047) @@ -38,18 +38,14 @@ * Special values used for entering MB PnP mode. The first four bytes of * each line determine the address port, the last four are data. */ -static const uint8_t init_values[] = { +static const u8 init_values[] = { 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe, 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61, 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1, 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, }; -/* - * The content of IT8671F_CONFIG_REG_LDN (index 0x07) must be set to the - * LDN the register belongs to, before you can access the register. - */ -static void it8671f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) +static void it8671f_sio_write(u8 ldn, u8 index, u8 value) { outb(IT8671F_CONFIG_REG_LDN, SIO_BASE); outb(ldn, SIO_DATA); @@ -60,7 +56,7 @@ /* Enter the configuration state (MB PnP mode). */ static void it8671f_enter_conf(void) { - uint8_t i; + int i; /* Perform MB PnP setup to put the SIO chip at 0x3f0. */ /* Base address 0x3f0: 0x86 0x80 0x55 0x55. */ @@ -90,13 +86,15 @@ it8671f_exit_conf(); } -/* Enable the serial ports on the IT8671F Super I/O chip. */ -static void it8671f_enable_serial(device_t dev, unsigned iobase) +/* Enable the serial port(s). */ +static void it8671f_enable_serial(device_t dev, u16 iobase) { it8671f_enter_conf(); - /* Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2), - PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). */ + /* + * Allow all devices to be enabled. Bits: FDC (0), Com1 (1), Com2 (2), + * PP (3), Reserved (4), KBCK (5), KBCM (6), Reserved (7). + */ it8671f_sio_write(0x00, IT8671F_CONFIG_REG_LDE, 0x6f); /* Enable serial port(s). */ Modified: trunk/src/superio/ite/it8671f/superio.c ============================================================================== --- trunk/src/superio/ite/it8671f/superio.c Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8671f/superio.c Mon Nov 8 16:16:30 2010 (r6047) @@ -28,14 +28,11 @@ static void init(device_t dev) { - struct superio_ite_it8671f_config *conf; + struct superio_ite_it8671f_config *conf = dev->chip_info; struct resource *res0, *res1; - if (!dev->enabled) { + if (!dev->enabled) return; - } - - conf = dev->chip_info; switch (dev->path.pnp.device) { case IT8671F_FDC: /* TODO. */ Modified: trunk/src/superio/ite/it8673f/Makefile.inc ============================================================================== --- trunk/src/superio/ite/it8673f/Makefile.inc Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8673f/Makefile.inc Mon Nov 8 16:16:30 2010 (r6047) @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_ITE_IT8673F) += superio.c + Modified: trunk/src/superio/ite/it8673f/chip.h ============================================================================== --- trunk/src/superio/ite/it8673f/chip.h Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8673f/chip.h Mon Nov 8 16:16:30 2010 (r6047) @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_ITE_IT8673F -#define _SUPERIO_ITE_IT8673F +#ifndef SUPERIO_ITE_IT8673F_CHIP_H +#define SUPERIO_ITE_IT8673F_CHIP_H #include <device/device.h> #include <pc80/keyboard.h> @@ -32,4 +32,4 @@ struct pc_keyboard keyboard; }; -#endif /* _SUPERIO_ITE_IT8673F */ +#endif Modified: trunk/src/superio/ite/it8673f/it8673f.h ============================================================================== --- trunk/src/superio/ite/it8673f/it8673f.h Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8673f/it8673f.h Mon Nov 8 16:16:30 2010 (r6047) @@ -19,12 +19,11 @@ */ /* Datasheet: http://www.datasheet4u.com/html/I/T/8/IT8673F_ITE.pdf.html */ -/* Status: Untested on real hardware, but it compiles. */ #define IT8673F_FDC 0x00 /* Floppy */ #define IT8673F_SP1 0x01 /* Com1 */ #define IT8673F_SP2 0x02 /* Com2 */ #define IT8673F_PP 0x03 /* Parallel port */ #define IT8673F_FAN 0x04 /* Fan controller */ -#define IT8673F_KBCK 0x05 /* Keyboard */ -#define IT8673F_KBCM 0x06 /* Mouse */ +#define IT8673F_KBCK 0x05 /* PS/2 keyboard */ +#define IT8673F_KBCM 0x06 /* PS/2 mouse */ Modified: trunk/src/superio/ite/it8673f/it8673f_early_serial.c ============================================================================== --- trunk/src/superio/ite/it8673f/it8673f_early_serial.c Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8673f/it8673f_early_serial.c Mon Nov 8 16:16:30 2010 (r6047) @@ -24,7 +24,7 @@ /* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ #define SIO_BASE 0x3f0 #define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 +#define SIO_DATA (SIO_BASE + 1) /* Global configuration registers. */ #define IT8673F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ @@ -34,18 +34,18 @@ #define IT8673F_CONFIGURATION_PORT 0x0279 /* Write-only. */ -/* Special values used for entering MB PnP mode. The first four bytes of - each line determine the address port, the last four are data. */ -static const uint8_t init_values[] = { +/* + * Special values used for entering MB PnP mode. The first four bytes of + * each line determine the address port, the last four are data. + */ +static const u8 init_values[] = { 0x6a, 0xb5, 0xda, 0xed, /**/ 0xf6, 0xfb, 0x7d, 0xbe, 0xdf, 0x6f, 0x37, 0x1b, /**/ 0x0d, 0x86, 0xc3, 0x61, 0xb0, 0x58, 0x2c, 0x16, /**/ 0x8b, 0x45, 0xa2, 0xd1, 0xe8, 0x74, 0x3a, 0x9d, /**/ 0xce, 0xe7, 0x73, 0x39, }; -/* The content of IT8673F_CONFIG_REG_LDN (index 0x07) must be set to the - LDN the register belongs to, before you can access the register. */ -static void it8673f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) +static void it8673f_sio_write(u8 ldn, u8 index, u8 value) { outb(IT8673F_CONFIG_REG_LDN, SIO_BASE); outb(ldn, SIO_DATA); @@ -53,10 +53,10 @@ outb(value, SIO_DATA); } -/* Enable the peripheral devices on the IT8673F Super I/O chip. */ -static void it8673f_enable_serial(device_t dev, unsigned iobase) +/* Enable the serial port(s). */ +static void it8673f_enable_serial(device_t dev, u16 iobase) { - uint8_t i; + int i; /* (1) Enter the configuration state (MB PnP mode). */ @@ -70,15 +70,14 @@ outb(0x55, IT8673F_CONFIGURATION_PORT); /* Sequentially write the 32 special values. */ - for (i = 0; i < 32; i++) { + for (i = 0; i < 32; i++) outb(init_values[i], SIO_BASE); - } /* (2) Modify the data of configuration registers. */ /* Enable all devices. */ - it8673f_sio_write(IT8673F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8673f_sio_write(IT8673F_SP2, 0x30, 0x1); /* Serial port 2 */ + it8673f_sio_write(IT8673F_SP1, 0x30, 0x1); /* Serial port 1 */ + it8673f_sio_write(IT8673F_SP2, 0x30, 0x1); /* Serial port 2 */ /* Select 24MHz CLKIN (clear bit 0). */ it8673f_sio_write(0x00, IT8673F_CONFIG_REG_CLOCKSEL, 0x00); Modified: trunk/src/superio/ite/it8673f/superio.c ============================================================================== --- trunk/src/superio/ite/it8673f/superio.c Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8673f/superio.c Mon Nov 8 16:16:30 2010 (r6047) @@ -28,14 +28,11 @@ static void init(device_t dev) { - struct superio_ite_it8673f_config *conf; + struct superio_ite_it8673f_config *conf = dev->chip_info; struct resource *res0, *res1; - if (!dev->enabled) { + if (!dev->enabled) return; - } - - conf = dev->chip_info; switch (dev->path.pnp.device) { case IT8673F_FDC: /* TODO. */ Modified: trunk/src/superio/ite/it8705f/Makefile.inc ============================================================================== --- trunk/src/superio/ite/it8705f/Makefile.inc Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8705f/Makefile.inc Mon Nov 8 16:16:30 2010 (r6047) @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_ITE_IT8705F) += superio.c + Modified: trunk/src/superio/ite/it8705f/chip.h ============================================================================== --- trunk/src/superio/ite/it8705f/chip.h Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8705f/chip.h Mon Nov 8 16:16:30 2010 (r6047) @@ -18,10 +18,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_ITE_IT8705F -#define _SUPERIO_ITE_IT8705F +#ifndef SUPERIO_ITE_IT8705F_CHIP_H +#define SUPERIO_ITE_IT8705F_CHIP_H -/* This chip doesn't seem to have keyboard and mouse support. */ +/* This chip doesn't have keyboard and mouse support. */ #include <device/device.h> #include <uart8250.h> @@ -32,4 +32,4 @@ struct uart8250 com1, com2; }; -#endif /* _SUPERIO_ITE_IT8705F */ +#endif Modified: trunk/src/superio/ite/it8705f/it8705f.h ============================================================================== --- trunk/src/superio/ite/it8705f/it8705f.h Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8705f/it8705f.h Mon Nov 8 16:16:30 2010 (r6047) @@ -19,10 +19,8 @@ */ /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8705_2.asp */ -/* Status: Untested on real hardware, but it compiles. */ -/* Note: This should also work on an IT8705AF, they're almost the same. */ -/* This chip doesn't seem to have keyboard and mouse support. */ +/* Note: This should also work on an IT8705AF, they're almost the same. */ #define IT8705F_FDC 0x00 /* Floppy */ #define IT8705F_SP1 0x01 /* Com1 */ Modified: trunk/src/superio/ite/it8705f/it8705f_early_serial.c ============================================================================== --- trunk/src/superio/ite/it8705f/it8705f_early_serial.c Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8705f/it8705f_early_serial.c Mon Nov 8 16:16:30 2010 (r6047) @@ -24,7 +24,7 @@ /* The base address is 0x2e or 0x4e, depending on config bytes. */ #define SIO_BASE 0x2e #define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 +#define SIO_DATA (SIO_BASE + 1) /* Global configuration registers. */ #define IT8705F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ @@ -37,9 +37,7 @@ #define IT8705F_CONFIGURATION_PORT 0x2e /* Write-only. */ -/* The content of IT8705F_CONFIG_REG_LDN (index 0x07) must be set to the - LDN the register belongs to, before you can access the register. */ -static void it8705f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) +static void it8705f_sio_write(u8 ldn, u8 index, u8 value) { outb(IT8705F_CONFIG_REG_LDN, SIO_BASE); outb(ldn, SIO_DATA); @@ -47,8 +45,8 @@ outb(value, SIO_DATA); } -/* Enable the peripheral devices on the IT8705F Super I/O chip. */ -static void it8705f_enable_serial(device_t dev, unsigned iobase) +/* Enable the serial port(s). */ +static void it8705f_enable_serial(device_t dev, u16 iobase) { /* (1) Enter the configuration state (MB PnP mode). */ @@ -62,14 +60,16 @@ /* (2) Modify the data of configuration registers. */ - /* Select the chip to configure (if there's more than one). - Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - If this register is not written, both chips are configured. */ + /* + * Select the chip to configure (if there's more than one). + * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. + * If this register is not written, both chips are configured. + */ /* it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CONFIGSEL, 0x00); */ /* Enable serial port(s). */ - it8705f_sio_write(IT8705F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8705f_sio_write(IT8705F_SP2, 0x30, 0x1); /* Serial port 2 */ + it8705f_sio_write(IT8705F_SP1, 0x30, 0x1); /* Serial port 1 */ + it8705f_sio_write(IT8705F_SP2, 0x30, 0x1); /* Serial port 2 */ /* Select 24MHz CLKIN (set bit 0). */ it8705f_sio_write(0x00, IT8705F_CONFIG_REG_CLOCKSEL, 0x01); Modified: trunk/src/superio/ite/it8705f/superio.c ============================================================================== --- trunk/src/superio/ite/it8705f/superio.c Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8705f/superio.c Mon Nov 8 16:16:30 2010 (r6047) @@ -18,8 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* This chip doesn't seem to have keyboard and mouse support. */ - #include <device/device.h> #include <device/pnp.h> #include <uart8250.h> @@ -29,14 +27,11 @@ static void init(device_t dev) { - struct superio_ite_it8705f_config *conf; + struct superio_ite_it8705f_config *conf = dev->chip_info; struct resource *res0, *res1; - if (!dev->enabled) { + if (!dev->enabled) return; - } - - conf = dev->chip_info; switch (dev->path.pnp.device) { case IT8705F_FDC: /* TODO. */ Modified: trunk/src/superio/ite/it8712f/Makefile.inc ============================================================================== --- trunk/src/superio/ite/it8712f/Makefile.inc Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8712f/Makefile.inc Mon Nov 8 16:16:30 2010 (r6047) @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_ITE_IT8712F) += superio.c + Modified: trunk/src/superio/ite/it8712f/chip.h ============================================================================== --- trunk/src/superio/ite/it8712f/chip.h Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8712f/chip.h Mon Nov 8 16:16:30 2010 (r6047) @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_ITE_IT8712F -#define _SUPERIO_ITE_IT8712F +#ifndef SUPERIO_ITE_IT8712F_CHIP_H +#define SUPERIO_ITE_IT8712F_CHIP_H #include <device/device.h> #include <pc80/keyboard.h> @@ -32,4 +32,4 @@ struct pc_keyboard keyboard; }; -#endif /* _SUPERIO_ITE_IT8712F */ +#endif Modified: trunk/src/superio/ite/it8712f/it8712f.h ============================================================================== --- trunk/src/superio/ite/it8712f/it8712f.h Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8712f/it8712f.h Mon Nov 8 16:16:30 2010 (r6047) @@ -19,7 +19,6 @@ */ /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8712_2.asp */ -/* Status: Com1 is tested and works. */ #define IT8712F_FDC 0x00 /* Floppy */ #define IT8712F_SP1 0x01 /* Com1 */ @@ -35,7 +34,7 @@ #ifndef __ROMCC__ void it8712f_kill_watchdog(void); -void it8712f_enable_serial(device_t dev, unsigned iobase); +void it8712f_enable_serial(device_t dev, u16 iobase); void it8712f_24mhz_clkin(void); void it8712f_enable_3vsbsw(void); #endif Modified: trunk/src/superio/ite/it8712f/it8712f_early_serial.c ============================================================================== --- trunk/src/superio/ite/it8712f/it8712f_early_serial.c Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8712f/it8712f_early_serial.c Mon Nov 8 16:16:30 2010 (r6047) @@ -24,7 +24,7 @@ /* The base address is 0x2e or 0x4e, depending on config bytes. */ #define SIO_BASE 0x2e #define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 +#define SIO_DATA (SIO_BASE + 1) /* Global configuration registers. */ #define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ @@ -35,11 +35,7 @@ #define IT8712F_CONFIG_REG_MFC 0x2a /* Multi-function control */ #define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */ -#define IT8712F_CONFIGURATION_PORT 0x2e /* Write-only. */ - -/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the - LDN the register belongs to, before you can access the register. */ -static void it8712f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) +static void it8712f_sio_write(u8 ldn, u8 index, u8 value) { outb(IT8712F_CONFIG_REG_LDN, SIO_BASE); outb(ldn, SIO_DATA); @@ -49,75 +45,69 @@ static void it8712f_enter_conf(void) { - /* Enter the configuration state (MB PnP mode). */ + u16 port = 0x2e; /* TODO: Don't hardcode! */ - /* Perform MB PnP setup to put the SIO chip at 0x2e. */ - /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ - /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ - outb(0x87, IT8712F_CONFIGURATION_PORT); - outb(0x01, IT8712F_CONFIGURATION_PORT); - outb(0x55, IT8712F_CONFIGURATION_PORT); - outb(0x55, IT8712F_CONFIGURATION_PORT); + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); } static void it8712f_exit_conf(void) { - /* Exit the configuration state (MB PnP mode). */ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02); } +/* Select 24MHz CLKIN (48MHz is the default). */ void it8712f_24mhz_clkin(void) { it8712f_enter_conf(); - - /* Select 24MHz CLKIN (48MHZ default)*/ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1); - it8712f_exit_conf(); } +/* + * We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2! + * + * LDN 7, reg 0x2a - needed for S3, or memory power will be cut off. + * + * Enable 3VSBSW#. (For System Suspend-to-RAM) + * 0: 3VSBSW# will be always inactive. + * 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#. + */ void it8712f_enable_3vsbsw(void) { - - /* We need to set enable 3VSBSW#, this was documented only in IT8712F_V0.9.2! - LDN 7, reg 0x2a - needed for S3, or memory power will be cut off. - Enable 3VSBSW#. (For System Suspend-to-RAM) - 0: 3VSBSW# will be always inactive. - 1: 3VSBSW# enabled. It will be (NOT SUSB#) NAND SUSC#. - */ - it8712f_enter_conf(); - it8712f_sio_write(0x07, IT8712F_CONFIG_REG_MFC, 0x80); + it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_MFC, 0x80); it8712f_exit_conf(); } void it8712f_kill_watchdog(void) { it8712f_enter_conf(); - - /* Kill the Watchdog */ - it8712f_sio_write(0x07, IT8712F_CONFIG_REG_WATCHDOG, 0x00); - + it8712f_sio_write(IT8712F_GPIO, IT8712F_CONFIG_REG_WATCHDOG, 0x00); it8712f_exit_conf(); } -/* Enable the peripheral devices on the IT8712F Super I/O chip. */ -void it8712f_enable_serial(device_t dev, unsigned iobase) +/* Enable the serial port(s). */ +void it8712f_enable_serial(device_t dev, u16 iobase) { - /* (1) Enter the configuration state (MB PnP mode). */ it8712f_enter_conf(); /* (2) Modify the data of configuration registers. */ - /* Select the chip to configure (if there's more than one). - Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - If this register is not written, both chips are configured. */ + /* + * Select the chip to configure (if there's more than one). + * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. + * If this register is not written, both chips are configured. + */ + /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */ /* Enable serial port(s). */ - it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */ + it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */ + it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */ /* Clear software suspend mode (clear bit 0). TODO: Needed? */ /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */ Modified: trunk/src/superio/ite/it8712f/superio.c ============================================================================== --- trunk/src/superio/ite/it8712f/superio.c Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8712f/superio.c Mon Nov 8 16:16:30 2010 (r6047) @@ -28,19 +28,14 @@ #include "chip.h" #include "it8712f.h" -/* Base address 0x2e: 0x87 0x01 0x55 0x55. */ -/* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ static void pnp_enter_ext_func_mode(device_t dev) { - outb(0x87, dev->path.pnp.port); - outb(0x01, dev->path.pnp.port); - outb(0x55, dev->path.pnp.port); - - if (dev->path.pnp.port == 0x4e) { - outb(0xaa, dev->path.pnp.port); - } else { - outb(0x55, dev->path.pnp.port); - } + u16 port = dev->path.pnp.port; + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); } static void pnp_exit_ext_func_mode(device_t dev) @@ -50,14 +45,11 @@ static void it8712f_init(device_t dev) { - struct superio_ite_it8712f_config *conf; + struct superio_ite_it8712f_config *conf = dev->chip_info; struct resource *res0, *res1; - if (!dev->enabled) { + if (!dev->enabled) return; - } - - conf = dev->chip_info; switch (dev->path.pnp.device) { case IT8712F_FDC: /* TODO. */ Modified: trunk/src/superio/ite/it8716f/Makefile.inc ============================================================================== --- trunk/src/superio/ite/it8716f/Makefile.inc Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8716f/Makefile.inc Mon Nov 8 16:16:30 2010 (r6047) @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_ITE_IT8716F) += superio.c + Modified: trunk/src/superio/ite/it8716f/chip.h ============================================================================== --- trunk/src/superio/ite/it8716f/chip.h Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8716f/chip.h Mon Nov 8 16:16:30 2010 (r6047) @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_ITE_IT8716F -#define _SUPERIO_ITE_IT8716F +#ifndef SUPERIO_ITE_IT8716F_CHIP_H +#define SUPERIO_ITE_IT8716F_CHIP_H #include <device/device.h> #include <pc80/keyboard.h> @@ -32,4 +32,4 @@ struct pc_keyboard keyboard; }; -#endif /* _SUPERIO_ITE_IT8716F */ +#endif Modified: trunk/src/superio/ite/it8716f/it8716f.h ============================================================================== --- trunk/src/superio/ite/it8716f/it8716f.h Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8716f/it8716f.h Mon Nov 8 16:16:30 2010 (r6047) @@ -19,7 +19,6 @@ */ /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8716_2.asp */ -/* Status: Untested on real hardware, but it compiles. */ #ifndef SUPERIO_ITE_IT8716F_IT8716F_H #define SUPERIO_ITE_IT8716F_IT8716F_H @@ -29,22 +28,22 @@ #define IT8716F_SP2 0x02 /* Com2 */ #define IT8716F_PP 0x03 /* Parallel port */ #define IT8716F_EC 0x04 /* Environment controller */ -#define IT8716F_KBCK 0x05 /* Keyboard */ -#define IT8716F_KBCM 0x06 /* Mouse */ +#define IT8716F_KBCK 0x05 /* PS/2 keyboard */ +#define IT8716F_KBCM 0x06 /* PS/2 mouse */ #define IT8716F_GPIO 0x07 /* GPIO */ #define IT8716F_MIDI 0x08 /* MIDI port */ #define IT8716F_GAME 0x09 /* GAME port */ #define IT8716F_IR 0x0a /* Consumer IR */ #if defined(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) && CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL -/* provided by mainboard, called by it8716f superio.c */ -void init_ec(uint16_t base); +/* Provided by mainboard, called by IT8716F superio.c. */ +void init_ec(u16 base); #endif #if defined(__PRE_RAM__) && !defined(__ROMCC__) void it8716f_disable_dev(device_t dev); -void it8716f_enable_dev(device_t dev, unsigned iobase); -void it8716f_enable_serial(device_t dev, unsigned iobase); +void it8716f_enable_dev(device_t dev, u16 iobase); +void it8716f_enable_serial(device_t dev, u16 iobase); #endif #endif Modified: trunk/src/superio/ite/it8716f/it8716f_early_init.c ============================================================================== --- trunk/src/superio/ite/it8716f/it8716f_early_init.c Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8716f/it8716f_early_init.c Mon Nov 8 16:16:30 2010 (r6047) @@ -28,7 +28,7 @@ pnp_set_enable(dev, 0); } -void it8716f_enable_dev(device_t dev, unsigned iobase) +void it8716f_enable_dev(device_t dev, u16 iobase) { pnp_set_logical_device(dev); pnp_set_enable(dev, 0); Modified: trunk/src/superio/ite/it8716f/it8716f_early_serial.c ============================================================================== --- trunk/src/superio/ite/it8716f/it8716f_early_serial.c Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8716f/it8716f_early_serial.c Mon Nov 8 16:16:30 2010 (r6047) @@ -27,7 +27,7 @@ /* The base address is 0x2e or 0x4e, depending on config bytes. */ #define SIO_BASE 0x2e #define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 +#define SIO_DATA (SIO_BASE + 1) /* Global configuration registers. */ #define IT8716F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ @@ -36,30 +36,22 @@ #define IT8716F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8716F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ -#define IT8716F_CONFIGURATION_PORT 0x2e /* Write-only. */ - -/* Perform MB PnP setup to put the SIO chip at 0x2e. */ -/* Base address 0x2e: 0x87 0x01 0x55 0x55. */ -/* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ -static inline void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(device_t dev) { - unsigned port = dev >> 8; + u16 port = dev >> 8; + outb(0x87, port); outb(0x01, port); outb(0x55, port); - if (port == 0x4e) { - outb(0xaa, port); - } else { - outb(0x55, port); - } + outb((port == 0x4e) ? 0xaa : 0x55, port); } static void pnp_exit_ext_func_mode(device_t dev) { - pnp_write_config(dev, 0x02, 0x02); + pnp_write_config(dev, IT8716F_CONFIG_REG_CC, 0x02); } -void it8716f_enable_serial(device_t dev, unsigned iobase) +void it8716f_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); Modified: trunk/src/superio/ite/it8716f/superio.c ============================================================================== --- trunk/src/superio/ite/it8716f/superio.c Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8716f/superio.c Mon Nov 8 16:16:30 2010 (r6047) @@ -31,19 +31,14 @@ #include "chip.h" #include "it8716f.h" -/* Base address 0x2e: 0x87 0x01 0x55 0x55. */ -/* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ static void pnp_enter_ext_func_mode(device_t dev) { - outb(0x87, dev->path.pnp.port); - outb(0x01, dev->path.pnp.port); - outb(0x55, dev->path.pnp.port); - - if (dev->path.pnp.port == 0x4e) { - outb(0xaa, dev->path.pnp.port); - } else { - outb(0x55, dev->path.pnp.port); - } + u16 port = dev->path.pnp.port; + + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); } static void pnp_exit_ext_func_mode(device_t dev) @@ -52,45 +47,41 @@ } #if !defined(CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL) || !CONFIG_SUPERIO_ITE_IT8716F_OVERRIDE_FANCTL -static void pnp_write_index(uint16_t port_base, uint8_t reg, uint8_t value) +static void pnp_write_index(u16 port_base, u8 reg, u8 value) { outb(reg, port_base); outb(value, port_base + 1); } -static uint8_t pnp_read_index(uint16_t port_base, uint8_t reg) +static u8 pnp_read_index(u16 port_base, u8 reg) { outb(reg, port_base); return inb(port_base + 1); } -static void init_ec(uint16_t base) +static void init_ec(u16 base) { - uint8_t value; + u8 value; - /* Read out current value of FAN_CTL control register (0x14). */ + /* Read out current value of FAN_CTL (0x14). */ value = pnp_read_index(base, 0x14); printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, read value = 0x%02x\n", - base + 0x14, value); + base + 0x14, value); - /* Set FAN_CTL control register (0x14) polarity to high, and - activate fans 1, 2 and 3. */ + /* Set FAN_CTL (0x14) polarity to high, activate fans 1, 2 and 3. */ pnp_write_index(base, 0x14, value | 0x87); printk(BIOS_DEBUG, "FAN_CTL: reg = 0x%04x, writing value = 0x%02x\n", - base + 0x14, value | 0x87); + base + 0x14, value | 0x87); } #endif static void it8716f_init(device_t dev) { - struct superio_ite_it8716f_config *conf; + struct superio_ite_it8716f_config *conf = dev->chip_info; struct resource *res0, *res1; - if (!dev->enabled) { + if (!dev->enabled) return; - } - - conf = dev->chip_info; /* TODO: FDC, PP, KBCM, MIDI, GAME, IR. */ switch (dev->path.pnp.device) { @@ -163,8 +154,7 @@ static void enable_dev(struct device *dev) { - pnp_enable_devices(dev, &ops, - ARRAY_SIZE(pnp_dev_info), pnp_dev_info); + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_ite_it8716f_ops = { Modified: trunk/src/superio/ite/it8718f/Makefile.inc ============================================================================== --- trunk/src/superio/ite/it8718f/Makefile.inc Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8718f/Makefile.inc Mon Nov 8 16:16:30 2010 (r6047) @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_ITE_IT8718F) += superio.c + Modified: trunk/src/superio/ite/it8718f/chip.h ============================================================================== --- trunk/src/superio/ite/it8718f/chip.h Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8718f/chip.h Mon Nov 8 16:16:30 2010 (r6047) @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_ITE_IT8718F -#define _SUPERIO_ITE_IT8718F +#ifndef SUPERIO_ITE_IT8718F_CHIP_H +#define SUPERIO_ITE_IT8718F_CHIP_H #include <device/device.h> #include <pc80/keyboard.h> @@ -32,4 +32,4 @@ struct pc_keyboard keyboard; }; -#endif /* _SUPERIO_ITE_IT8718F */ +#endif Modified: trunk/src/superio/ite/it8718f/it8718f.h ============================================================================== --- trunk/src/superio/ite/it8718f/it8718f.h Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8718f/it8718f.h Mon Nov 8 16:16:30 2010 (r6047) @@ -19,20 +19,20 @@ */ /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8718_2.asp */ -/* Status: Untested on real hardware, but it compiles. */ #define IT8718F_FDC 0x00 /* Floppy */ #define IT8718F_SP1 0x01 /* Com1 */ #define IT8718F_SP2 0x02 /* Com2 */ #define IT8718F_PP 0x03 /* Parallel port */ #define IT8718F_EC 0x04 /* Environment controller */ -#define IT8718F_KBCK 0x05 /* Keyboard */ -#define IT8718F_KBCM 0x06 /* Mouse */ +#define IT8718F_KBCK 0x05 /* PS/2 keyboard */ +#define IT8718F_KBCM 0x06 /* PS/2 mouse */ +#define IT8718F_GPIO 0x07 /* GPIO */ #define IT8718F_IR 0x0a /* Consumer IR */ #if defined(__PRE_RAM__) && !defined(__ROMCC__) void it8718f_24mhz_clkin(void); void it8718f_disable_reboot(void); -void it8718f_enable_serial(device_t dev, unsigned iobase); +void it8718f_enable_serial(device_t dev, u16 iobase); #endif Modified: trunk/src/superio/ite/it8718f/it8718f_early_serial.c ============================================================================== --- trunk/src/superio/ite/it8718f/it8718f_early_serial.c Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8718f/it8718f_early_serial.c Mon Nov 8 16:16:30 2010 (r6047) @@ -24,7 +24,7 @@ /* The base address is 0x2e or 0x4e, depending on config bytes. */ #define SIO_BASE 0x2e #define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 +#define SIO_DATA (SIO_BASE + 1) /* Global configuration registers. */ #define IT8718F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ @@ -33,11 +33,7 @@ #define IT8718F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */ #define IT8718F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */ -#define IT8718F_CONFIGURATION_PORT 0x2e /* Write-only. */ - -/* The content of IT8718F_CONFIG_REG_LDN (index 0x07) must be set to the - LDN the register belongs to, before you can access the register. */ -static void it8718f_sio_write(uint8_t ldn, uint8_t index, uint8_t value) +static void it8718f_sio_write(u8 ldn, u8 index, u8 value) { outb(IT8718F_CONFIG_REG_LDN, SIO_BASE); outb(ldn, SIO_DATA); @@ -47,63 +43,58 @@ static void it8718f_enter_conf(void) { - /* Enter the configuration state (MB PnP mode). */ + u16 port = 0x2e; /* TODO: Don't hardcode! */ - /* Perform MB PnP setup to put the SIO chip at 0x2e. */ - /* Base address 0x2e: 0x87 0x01 0x55 0x55. */ - /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */ - outb(0x87, IT8718F_CONFIGURATION_PORT); - outb(0x01, IT8718F_CONFIGURATION_PORT); - outb(0x55, IT8718F_CONFIGURATION_PORT); - outb(0x55, IT8718F_CONFIGURATION_PORT); + outb(0x87, port); + outb(0x01, port); + outb(0x55, port); + outb((port == 0x4e) ? 0xaa : 0x55, port); } static void it8718f_exit_conf(void) { - /* Exit the configuration state (MB PnP mode). */ it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CC, 0x02); } +/* Select 24MHz CLKIN (48MHz default). */ void it8718f_24mhz_clkin(void) { it8718f_enter_conf(); - - /* Select 24MHz CLKIN (48MHZ default)*/ it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CLOCKSEL, 0x1); - it8718f_exit_conf(); } -/* GIGABYTE uses a special SuperIO register to protect its Dual BIOS +/* + * GIGABYTE uses a special Super I/O register to protect its Dual BIOS * mechanism. It lives in the GPIO LDN. However, register 0xEF is not - * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for - * now. + * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for now. */ void it8718f_disable_reboot(void) { it8718f_enter_conf(); - - it8718f_sio_write(0x07, 0xEF, 0x7E); - + it8718f_sio_write(IT8718F_GPIO, 0xEF, 0x7E); it8718f_exit_conf(); } -/* Enable the peripheral devices on the IT8718F Super I/O chip. */ -void it8718f_enable_serial(device_t dev, unsigned iobase) +/* Enable the serial port(s). */ +void it8718f_enable_serial(device_t dev, u16 iobase) { /* (1) Enter the configuration state (MB PnP mode). */ it8718f_enter_conf(); /* (2) Modify the data of configuration registers. */ - /* Select the chip to configure (if there's more than one). - Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. - If this register is not written, both chips are configured. */ + /* + * Select the chip to configure (if there's more than one). + * Set bit 7 to select JP3=1, clear bit 7 to select JP3=0. + * If this register is not written, both chips are configured. + */ + /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_CONFIGSEL, 0x00); */ /* Enable serial port(s). */ - it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */ - it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */ + it8718f_sio_write(IT8718F_SP1, 0x30, 0x1); /* Serial port 1 */ + it8718f_sio_write(IT8718F_SP2, 0x30, 0x1); /* Serial port 2 */ /* Clear software suspend mode (clear bit 0). TODO: Needed? */ /* it8718f_sio_write(0x00, IT8718F_CONFIG_REG_SWSUSP, 0x00); */ Modified: trunk/src/superio/ite/it8718f/superio.c ============================================================================== --- trunk/src/superio/ite/it8718f/superio.c Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8718f/superio.c Mon Nov 8 16:16:30 2010 (r6047) @@ -28,14 +28,11 @@ static void init(device_t dev) { - struct superio_ite_it8718f_config *conf; + struct superio_ite_it8718f_config *conf = dev->chip_info; struct resource *res0, *res1; - if (!dev->enabled) { + if (!dev->enabled) return; - } - - conf = dev->chip_info; switch (dev->path.pnp.device) { case IT8718F_FDC: /* TODO. */

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Trac reminder: list of new ticket(s)
by coreboot tracker 08 Nov '10

08 Nov '10

1 0

build service results for r6045
by repository service 08 Nov '10

08 Nov '10

Dear coreboot readers! This is the automatic build system of coreboot. The developer "ruik" checked in revision 6045 to the coreboot repository. This caused the following changes: Change Log: Should be part of 6044. I forgot to add the directory :/ This adds the m2v directory and necessary files to src/mainboards/asus and adjusts the Kconfig. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Build Log: Configuration of a-trend:atc-6220 has been fixed Configuration of a-trend:atc-6240 has been fixed Configuration of abit:be6-ii_v2_0 has been fixed Configuration of advantech:pcm-5820 has been fixed Configuration of amd:db800 has been fixed Configuration of amd:dbm690t has been fixed Configuration of amd:mahogany has been fixed Configuration of amd:mahogany_fam10 has been fixed Configuration of amd:norwich has been fixed Configuration of amd:pistachio has been fixed Configuration of amd:rumba has been fixed Configuration of amd:serengeti_cheetah has been fixed Configuration of amd:serengeti_cheetah_fam10 has been fixed Configuration of amd:tilapia_fam10 has been fixed Configuration of arima:hdama has been fixed Configuration of artecgroup:dbe61 has been fixed Configuration of asi:mb_5blgp has been fixed Configuration of asi:mb_5blmp has been fixed Configuration of asrock:939a785gmh has been fixed Configuration of asus:a8n_e has been fixed Configuration of asus:a8v-e_se has been fixed Configuration of asus:m2v-mx_se has been fixed Configuration of asus:m4a785-m has been fixed Configuration of asus:mew-am has been fixed Configuration of asus:mew-vm has been fixed Configuration of asus:p2b has been fixed Configuration of asus:p2b-d has been fixed Configuration of asus:p2b-ds has been fixed Configuration of asus:p2b-f has been fixed Configuration of asus:p2b-ls has been fixed Configuration of asus:p3b-f has been fixed Configuration of axus:tc320 has been fixed Configuration of azza:pt-6ibd has been fixed Configuration of bcom:winnet100 has been fixed Configuration of bcom:winnetp680 has been fixed Configuration of biostar:m6tba has been fixed Configuration of broadcom:blast has been fixed Configuration of compaq:deskpro_en_sff_p600 has been fixed Configuration of dell:s1850 has been fixed Configuration of digitallogic:adl855pc has been fixed Configuration of digitallogic:msm586seg has been fixed Configuration of digitallogic:msm800sev has been fixed Configuration of eaglelion:5bcm has been fixed Configuration of ecs:p6iwp-fe has been fixed Configuration of emulation:qemu-x86 has been fixed Configuration of getac:p470 has been fixed Configuration of gigabyte:ga-6bxc has been fixed Configuration of gigabyte:ga-6bxe has been fixed Configuration of gigabyte:ga_2761gxdk has been fixed Configuration of gigabyte:m57sli has been fixed Configuration of gigabyte:ma785gmt has been fixed Configuration of gigabyte:ma78gm has been fixed Configuration of hp:dl145_g1 has been fixed Configuration of hp:dl145_g3 has been fixed Configuration of hp:dl165_g6_fam10 has been fixed Configuration of hp:e_vectra_p2706t has been fixed Configuration of ibase:mb899 has been fixed Configuration of ibm:e325 has been fixed Configuration of ibm:e326 has been fixed Configuration of iei:juki-511p has been fixed Configuration of iei:kino-780am2-fam10 has been fixed Configuration of iei:nova4899r has been fixed Configuration of iei:pcisa-lx-800-r10 has been fixed Configuration of intel:d810e2cb has been fixed Configuration of intel:d945gclf has been fixed Configuration of intel:eagleheights has been fixed Configuration of intel:jarrell has been fixed Configuration of intel:mtarvon has been fixed Configuration of intel:truxton has been fixed Configuration of intel:xe7501devkit has been fixed Configuration of iwill:dk8_htx has been fixed Configuration of iwill:dk8s2 has been fixed Configuration of iwill:dk8x has been fixed Configuration of jetway:j7f24 has been fixed Configuration of jetway:pa78vm5 has been fixed Configuration of kontron:986lcd-m has been fixed Configuration of kontron:kt690 has been fixed Configuration of lanner:em8510 has been fixed Configuration of lippert:frontrunner has been fixed Configuration of lippert:hurricane-lx has been fixed Configuration of lippert:literunner-lx has been fixed Configuration of lippert:roadrunner-lx has been fixed Configuration of lippert:spacerunner-lx has been fixed Configuration of mitac:6513wu has been fixed Configuration of msi:ms6119 has been fixed Configuration of msi:ms6147 has been fixed Configuration of msi:ms6156 has been fixed Configuration of msi:ms6178 has been fixed Configuration of msi:ms7135 has been fixed Configuration of msi:ms7260 has been fixed Configuration of msi:ms9185 has been fixed Configuration of msi:ms9282 has been fixed Configuration of msi:ms9652_fam10 has been fixed Configuration of nec:powermate2000 has been fixed Configuration of newisys:khepri has been fixed Configuration of nokia:ip530 has been fixed Configuration of nvidia:l1_2pvv has been fixed Configuration of pcengines:alix1c has been fixed Configuration of pcengines:alix2d has been fixed Configuration of rca:rm4100 has been fixed Configuration of roda:rk886ex has been fixed Configuration of soyo:sy-6ba-plus-iii has been fixed Configuration of sunw:ultra40 has been fixed Configuration of supermicro:h8dme has been fixed Configuration of supermicro:h8dmr has been fixed Configuration of supermicro:h8dmr_fam10 has been fixed Configuration of supermicro:h8qme_fam10 has been fixed Configuration of supermicro:x6dai_g has been fixed Configuration of supermicro:x6dhe_g has been fixed Configuration of supermicro:x6dhe_g2 has been fixed Configuration of supermicro:x6dhr_ig has been fixed Configuration of supermicro:x6dhr_ig2 has been fixed Configuration of technexion:tim5690 has been fixed Configuration of technexion:tim8690 has been fixed Configuration of technologic:ts5300 has been fixed Configuration of televideo:tc7020 has been fixed Configuration of thomson:ip1000 has been fixed Configuration of traverse:geos has been fixed Configuration of tyan:s1846 has been fixed Configuration of tyan:s2735 has been fixed Configuration of tyan:s2850 has been fixed Configuration of tyan:s2875 has been fixed Configuration of tyan:s2880 has been fixed Configuration of tyan:s2881 has been fixed Configuration of tyan:s2882 has been fixed Configuration of tyan:s2885 has been fixed Configuration of tyan:s2891 has been fixed Configuration of tyan:s2892 has been fixed Configuration of tyan:s2895 has been fixed Configuration of tyan:s2912 has been fixed Configuration of tyan:s2912_fam10 has been fixed Configuration of tyan:s4880 has been fixed Configuration of tyan:s4882 has been fixed Configuration of via:epia has been fixed Configuration of via:epia-cn has been fixed Configuration of via:epia-m has been fixed Configuration of via:epia-m700 has been fixed Configuration of via:epia-n has been fixed Configuration of via:pc2500e has been fixed Configuration of via:vt8454c has been fixed Configuration of winent:pl6064 has been fixed Configuration of wyse:s50 has been fixed If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system

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build service results for r6044
by repository service 08 Nov '10

08 Nov '10

1 0

[commit] r6046 - in trunk/src/mainboard: amd/dbm690t amd/mahogany amd/mahogany_fam10 amd/pistachio amd/tilapia_fam10 asrock/939a785gmh asus/m4a785-m gigabyte/ma785gmt gigabyte/ma78gm iei/kino-780am...
by repository service 07 Nov '10

07 Nov '10

Author: sduplichan Date: Sun Nov 7 21:11:39 2010 New Revision: 6046 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6046 Log: DSDT.asl should not report the AMD SB600/SB700 RTC as Intel PIIX4 compatible. The extended cmos is accessed differently for AMD and Intel RTCs. Not sure what if any OS cares about this distinction, but non-Intel compatible seems like a safer way to report the AMD RTC. Tested with Win7 on Mahogany_fam10 and kino-780am2-fam10. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Acked-by: Marc Jones <marcj303(a)gmail.com> Modified: trunk/src/mainboard/amd/dbm690t/dsdt.asl trunk/src/mainboard/amd/mahogany/dsdt.asl trunk/src/mainboard/amd/mahogany_fam10/dsdt.asl trunk/src/mainboard/amd/pistachio/dsdt.asl trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl trunk/src/mainboard/asrock/939a785gmh/dsdt.asl trunk/src/mainboard/asus/m4a785-m/dsdt.asl trunk/src/mainboard/gigabyte/ma785gmt/dsdt.asl trunk/src/mainboard/gigabyte/ma78gm/dsdt.asl trunk/src/mainboard/iei/kino-780am2-fam10/dsdt.asl trunk/src/mainboard/jetway/pa78vm5/dsdt.asl trunk/src/mainboard/kontron/kt690/dsdt.asl trunk/src/mainboard/technexion/tim5690/dsdt.asl trunk/src/mainboard/technexion/tim8690/dsdt.asl Modified: trunk/src/mainboard/amd/dbm690t/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/dbm690t/dsdt.asl Sun Nov 7 21:08:45 2010 (r6045) +++ trunk/src/mainboard/amd/dbm690t/dsdt.asl Sun Nov 7 21:11:39 2010 (r6046) @@ -1308,7 +1308,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Modified: trunk/src/mainboard/amd/mahogany/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/mahogany/dsdt.asl Sun Nov 7 21:08:45 2010 (r6045) +++ trunk/src/mainboard/amd/mahogany/dsdt.asl Sun Nov 7 21:11:39 2010 (r6046) @@ -1324,7 +1324,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Modified: trunk/src/mainboard/amd/mahogany_fam10/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/mahogany_fam10/dsdt.asl Sun Nov 7 21:08:45 2010 (r6045) +++ trunk/src/mainboard/amd/mahogany_fam10/dsdt.asl Sun Nov 7 21:11:39 2010 (r6046) @@ -1366,7 +1366,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Modified: trunk/src/mainboard/amd/pistachio/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/pistachio/dsdt.asl Sun Nov 7 21:08:45 2010 (r6045) +++ trunk/src/mainboard/amd/pistachio/dsdt.asl Sun Nov 7 21:11:39 2010 (r6046) @@ -1307,7 +1307,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Modified: trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl ============================================================================== --- trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl Sun Nov 7 21:08:45 2010 (r6045) +++ trunk/src/mainboard/amd/tilapia_fam10/dsdt.asl Sun Nov 7 21:11:39 2010 (r6046) @@ -1366,7 +1366,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Modified: trunk/src/mainboard/asrock/939a785gmh/dsdt.asl ============================================================================== --- trunk/src/mainboard/asrock/939a785gmh/dsdt.asl Sun Nov 7 21:08:45 2010 (r6045) +++ trunk/src/mainboard/asrock/939a785gmh/dsdt.asl Sun Nov 7 21:11:39 2010 (r6046) @@ -1282,7 +1282,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Modified: trunk/src/mainboard/asus/m4a785-m/dsdt.asl ============================================================================== --- trunk/src/mainboard/asus/m4a785-m/dsdt.asl Sun Nov 7 21:08:45 2010 (r6045) +++ trunk/src/mainboard/asus/m4a785-m/dsdt.asl Sun Nov 7 21:11:39 2010 (r6046) @@ -1366,7 +1366,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Modified: trunk/src/mainboard/gigabyte/ma785gmt/dsdt.asl ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/dsdt.asl Sun Nov 7 21:08:45 2010 (r6045) +++ trunk/src/mainboard/gigabyte/ma785gmt/dsdt.asl Sun Nov 7 21:11:39 2010 (r6046) @@ -1366,7 +1366,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Modified: trunk/src/mainboard/gigabyte/ma78gm/dsdt.asl ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/dsdt.asl Sun Nov 7 21:08:45 2010 (r6045) +++ trunk/src/mainboard/gigabyte/ma78gm/dsdt.asl Sun Nov 7 21:11:39 2010 (r6046) @@ -1366,7 +1366,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Modified: trunk/src/mainboard/iei/kino-780am2-fam10/dsdt.asl ============================================================================== --- trunk/src/mainboard/iei/kino-780am2-fam10/dsdt.asl Sun Nov 7 21:08:45 2010 (r6045) +++ trunk/src/mainboard/iei/kino-780am2-fam10/dsdt.asl Sun Nov 7 21:11:39 2010 (r6046) @@ -1366,7 +1366,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Modified: trunk/src/mainboard/jetway/pa78vm5/dsdt.asl ============================================================================== --- trunk/src/mainboard/jetway/pa78vm5/dsdt.asl Sun Nov 7 21:08:45 2010 (r6045) +++ trunk/src/mainboard/jetway/pa78vm5/dsdt.asl Sun Nov 7 21:11:39 2010 (r6046) @@ -1366,7 +1366,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Modified: trunk/src/mainboard/kontron/kt690/dsdt.asl ============================================================================== --- trunk/src/mainboard/kontron/kt690/dsdt.asl Sun Nov 7 21:08:45 2010 (r6045) +++ trunk/src/mainboard/kontron/kt690/dsdt.asl Sun Nov 7 21:11:39 2010 (r6046) @@ -1308,7 +1308,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Modified: trunk/src/mainboard/technexion/tim5690/dsdt.asl ============================================================================== --- trunk/src/mainboard/technexion/tim5690/dsdt.asl Sun Nov 7 21:08:45 2010 (r6045) +++ trunk/src/mainboard/technexion/tim5690/dsdt.asl Sun Nov 7 21:11:39 2010 (r6046) @@ -1308,7 +1308,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Modified: trunk/src/mainboard/technexion/tim8690/dsdt.asl ============================================================================== --- trunk/src/mainboard/technexion/tim8690/dsdt.asl Sun Nov 7 21:08:45 2010 (r6045) +++ trunk/src/mainboard/technexion/tim8690/dsdt.asl Sun Nov 7 21:11:39 2010 (r6046) @@ -1308,7 +1308,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2)

1 0

[commit] r6045 - trunk/src/mainboard/asus/m2v
by repository service 07 Nov '10

07 Nov '10

Author: ruik Date: Sun Nov 7 21:08:45 2010 New Revision: 6045 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6045 Log: Should be part of 6044. I forgot to add the directory :/ This adds the m2v directory and necessary files to src/mainboards/asus and adjusts the Kconfig. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Added: trunk/src/mainboard/asus/m2v/ trunk/src/mainboard/asus/m2v/Kconfig trunk/src/mainboard/asus/m2v/chip.h trunk/src/mainboard/asus/m2v/cmos.layout trunk/src/mainboard/asus/m2v/devicetree.cb trunk/src/mainboard/asus/m2v/mainboard.c trunk/src/mainboard/asus/m2v/romstage.c Added: trunk/src/mainboard/asus/m2v/Kconfig ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/m2v/Kconfig Sun Nov 7 21:08:45 2010 (r6045) @@ -0,0 +1,77 @@ +if BOARD_ASUS_M2V + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select ARCH_X86 + select CPU_AMD_SOCKET_AM2 + select DIMM_DDR2 + select QRANK_DIMM_SUPPORT + select HAVE_OPTION_TABLE + select K8_HT_FREQ_1G_SUPPORT + select NORTHBRIDGE_AMD_AMDK8 + select NORTHBRIDGE_AMD_AMDK8_ROOT_COMPLEX + select SOUTHBRIDGE_VIA_VT8237R + select SOUTHBRIDGE_VIA_K8T890 + select SUPERIO_ITE_IT8712F + select CACHE_AS_RAM + select BOARD_ROMSIZE_KB_512 + select RAMINIT_SYSINFO + select TINY_BOOTBLOCK + +config MAINBOARD_DIR + string + default asus/m2v + +config DCACHE_RAM_BASE + hex + default 0xcc000 + +config DCACHE_RAM_SIZE + hex + default 0x4000 + +config DCACHE_RAM_GLOBAL_VAR_SIZE + hex + default 0x1000 + +config APIC_ID_OFFSET + hex + default 0x10 + +config SB_HT_CHAIN_ON_BUS0 + int + default 1 + +config MAINBOARD_PART_NUMBER + string + default "M2V" + +config HW_MEM_HOLE_SIZEK + hex + default 0 + +config MAX_CPUS + int + default 2 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config HEAP_SIZE + hex + default 0x40000 + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x20 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1043 + +endif # BOARD_ASUS_M2V Added: trunk/src/mainboard/asus/m2v/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/m2v/chip.h Sun Nov 7 21:08:45 2010 (r6045) @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +extern struct chip_operations mainboard_ops; + +struct mainboard_config {}; Added: trunk/src/mainboard/asus/m2v/cmos.layout ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/m2v/cmos.layout Sun Nov 7 21:08:45 2010 (r6045) @@ -0,0 +1,98 @@ +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 DDR400 +8 1 DDR333 +8 2 DDR266 +8 3 DDR200 +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 + + Added: trunk/src/mainboard/asus/m2v/devicetree.cb ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/m2v/devicetree.cb Sun Nov 7 21:08:45 2010 (r6045) @@ -0,0 +1,74 @@ +chip northbridge/amd/amdk8/root_complex # Root complex + device lapic_cluster 0 on # APIC cluster + chip cpu/amd/socket_AM2 # CPU + device lapic 0 on end # APIC + end + end + device pci_domain 0 on # PCI domain + chip northbridge/amd/amdk8 # mc0 + device pci 18.0 on # Northbridge + # Devices on link 0, link 0 == LDT 0 + chip southbridge/via/vt8237r # Southbridge + register "ide0_enable" = "1" # Enable IDE channel 0 + register "ide1_enable" = "1" # Enable IDE channel 1 + register "ide0_80pin_cable" = "1" # 80pin cable on IDE channel 0 + register "ide1_80pin_cable" = "1" # 80pin cable on IDE channel 1 + register "fn_ctrl_lo" = "0xc0" # Enable SB functions + register "fn_ctrl_hi" = "0x0d" # Enable SB functions + device pci 0.0 on end # HT + device pci f.1 on end # IDE + device pci 11.0 on # LPC + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip superio/ite/it8712f # Super I/O + device pnp 2e.0 on # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off end # Com2 (N/A on this board) + device pnp 2e.3 on # Lpt1 + io 0x60 = 0x378 + irq 0x70 = 7 + drq 0x74 = 3 + end + device pnp 2e.4 on # Environment controller + io 0x60 = 0xd00 + io 0x62 = 0xc00 + irq 0x70 = 0x00 + end + device pnp 2e.5 off end # PS/2 keyboard + device pnp 2e.6 off end # PS/2 mouse + device pnp 2e.7 off end # GPIO config + device pnp 2e.8 off end # Midi port + device pnp 2e.9 off end # Game port + device pnp 2e.a off end # IR + end + end + device pci 12.0 off end # VIA LAN (off, other chip used) + device pci 13.0 on end # br + device pci 13.1 on end # br2, need to have it here to discover it + end + chip southbridge/via/k8t890 # "Southbridge" K8T890 + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end +end Added: trunk/src/mainboard/asus/m2v/mainboard.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/m2v/mainboard.c Sun Nov 7 21:08:45 2010 (r6045) @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <device/device.h> +#include "chip.h" + +struct chip_operations mainboard_ops = { + CHIP_NAME("ASUS M2V") +}; Added: trunk/src/mainboard/asus/m2v/romstage.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/mainboard/asus/m2v/romstage.c Sun Nov 7 21:08:45 2010 (r6045) @@ -0,0 +1,299 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2006 AMD + * (Written by Yinghai Lu <yinghailu(a)amd.com> for AMD) + * Copyright (C) 2006 MSI + * (Written by Bingxun Shi <bingxunshi(a)gmail.com> for MSI) + * Copyright (C) 2008 Rudolf Marek <r.marek(a)assembler.cz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +unsigned int get_sbdn(unsigned bus); + +/* Used by init_cpus and fidvid */ +#define SET_FIDVID 1 + +/* If we want to wait for core1 done before DQS training, set it to 0. */ +#define SET_FIDVID_CORE0_ONLY 1 + +#if CONFIG_K8_REV_F_SUPPORT == 1 +#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0 +#endif + +#include <stdint.h> +#include <string.h> +#include <device/pci_def.h> +#include <arch/io.h> +#include <device/pnp_def.h> +#include <arch/romcc_io.h> +#include <cpu/amd/mtrr.h> +#include <cpu/x86/lapic.h> +#include <pc80/mc146818rtc.h> +#include <console/console.h> +#include <cpu/amd/model_fxx_rev.h> +#include "northbridge/amd/amdk8/raminit.h" +#include "cpu/amd/model_fxx/apic_timer.c" +#include "lib/delay.c" +#include "northbridge/amd/amdk8/reset_test.c" +#include "northbridge/amd/amdk8/debug.c" +#include "superio/ite/it8712f/it8712f_early_serial.c" +#include "southbridge/via/vt8237r/vt8237r_early_smbus.c" +#include "cpu/x86/mtrr/earlymtrr.c" +#include "cpu/x86/bist.h" +#include "northbridge/amd/amdk8/setup_resource_map.c" + +#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) +#define WATCHDOG_DEV PNP_DEV(0x2e, IT8712F_GPIO) + +#define IT8712F_GPIO_BASE 0x0a20 + +static void memreset(int controllers, const struct mem_controller *ctrl) +{ +} + +static inline int spd_read_byte(unsigned device, unsigned address) +{ + return smbus_read_byte(device, address); +} + +static void activate_spd_rom(const struct mem_controller *ctrl) +{ +} + +// defines S3_NVRAM_EARLY: +#include "southbridge/via/k8t890/k8t890_early_car.c" + +#include "northbridge/amd/amdk8/amdk8.h" +#include "northbridge/amd/amdk8/incoherent_ht.c" +#include "northbridge/amd/amdk8/coherent_ht.c" +#include "northbridge/amd/amdk8/raminit_f.c" +#include "lib/generic_sdram.c" + +#include "cpu/amd/dualcore/dualcore.c" + +#include "cpu/amd/car/post_cache_as_ram.c" +#include "cpu/amd/model_fxx/init_cpus.c" +#include "cpu/amd/model_fxx/fidvid.c" +#include "northbridge/amd/amdk8/resourcemap.c" + +void soft_reset(void) +{ + uint8_t tmp; + + set_bios_reset(); + print_debug("soft reset\n"); + + /* PCI reset */ + tmp = pci_read_config8(PCI_DEV(0, 0x11, 0), 0x4f); + tmp |= 0x01; + /* FIXME from S3 set bit1 to disable USB reset VT8237A/S */ + pci_write_config8(PCI_DEV(0, 0x11, 0), 0x4f, tmp); + + while (1) { + /* daisy daisy ... */ + hlt(); + } +} + +unsigned int get_sbdn(unsigned bus) +{ + device_t dev; + + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), bus); + return (dev >> 15) & 0x1f; +} + +struct gpio_init_val { + u8 addr; + u8 val; +}; + +static const struct gpio_init_val gpio_init_data[] = { + /* multi-function pin selection */ + { 0x25, 0x00 }, + { 0x28, 0x00 }, /* gp46 is infrared receive input */ + { 0x29, 0x40 }, /* reserved value?!? */ + { 0x2a, 0x00 }, + { 0x2c, 0x1d }, /* pin91 is VIN7 instead of PCIRSTIN# */ + /* gpio i/o port base */ + { 0x62, IT8712F_GPIO_BASE >> 8 }, + { 0x63, IT8712F_GPIO_BASE & 0xff }, + /* 0xb8 - 0xbc: gpio pull-up enable */ + { 0xb8, 0x00 }, + /* 0xc0 - 0xc4: gpio alternate function select */ + { 0xc0, 0x00 }, + { 0xc3, 0x00 }, + { 0xc4, 0xc0 }, + /* 0xc8 - 0xcc: gpio output enable */ + { 0xc8, 0x00 }, + { 0xcb, 0x00 }, + { 0xcc, 0xc0 }, + /* end of list */ + { 0, 0 }, +}; + +static void m2v_it8712f_gpio_init(void) +{ + const struct gpio_init_val *giv; + + printk(BIOS_SPEW, "it8712f gpio init...\n"); + + /* + * it8712f gpio config + * + * Most importantly this switches pin 91 from + * PCIRSTIN# to VIN7. + * Note that only PCIRST3# and PCIRST5# are affected + * by PCIRSTIN#, the PCIRST1#, PCIRST2#, PCIRST4# are always + * direct buffers of #LRESET (low pin count bus reset). + * If this is not done All PCIRST are in reset state and the + * pcie slots don't initialize. + * + * pci reset handling: + * pin 91: VIN7 (alternate PCIRSTIN#) + * pin 48: PCIRST5# / gpio port 5 bit 0 + * pin 84: PCIRST4# / gpio port 1 bit 0 + * pin 31: PCIRST1# / gpio port 1 bit 4 + * pin 33: PCIRST2# / gpio port 1 bit 2 + * pin 34: PCIRST3# / gpio port 1 bit 1 + * + * PCIRST[0-5]# are connected as follows: + * pcirst1# -> pci bus + * pcirst2# -> ide bus + * pcirst3# -> pcie devices + * pcirst4# -> pcie graphics + * pcirst5# -> maybe n/c (untested) + * + * For software control of PCIRST[1-5]#: + * 0x2a=0x17 (deselect pcirst# hardwiring, enable 0x25 control) + * 0x25=0x17 (select gpio function) + * 0xc0=0x17, 0xc8=0x17 gpio port 1 select & output enable + * 0xc4=0xc1, 0xcc=0xc1 gpio port 5 select & output enable + */ + it8712f_enter_conf(); + giv = gpio_init_data; + while (giv->addr) { + printk(BIOS_SPEW, "it8712f gpio: %02x=%02x\n", + giv->addr, giv->val); + it8712f_sio_write(IT8712F_GPIO, giv->addr, giv->val); + giv++; + } + it8712f_exit_conf(); +} + +static void m2v_bus_init(void) +{ + device_t dev; + + printk(BIOS_SPEW, "m2v_bus_init\n"); + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CF_0), 0); + pci_write_config8(dev, K8T890_MULTIPLE_FN_EN, 0x01); + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CF_5), 0); + /* + * bit | meaning + * 6 | 0: hide scratch register function 0:0.6 (we don't use it) + * 5 | 1: enable pcie bridge 0:2.0 + * 4 | 0: hide pcie bridge 0:3.3 (not connected) + * 3 | 1: enable pcie bridge 0:3.2 + * 2 | 1: enable pcie bridge 0:3.1 + * 1 | 1: enable pcie bridge 0:3.0 + */ + pci_write_config8(dev, 0xf0, 0x2e); +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + static const uint16_t spd_addr[] = { + // Node 0 + (0xa << 3) | 0, (0xa << 3) | 2, 0, 0, + (0xa << 3) | 1, (0xa << 3) | 3, 0, 0, + // Node 1 + (0xa << 3) | 4, (0xa << 3) | 6, 0, 0, + (0xa << 3) | 5, (0xa << 3) | 7, 0, 0, + }; + unsigned bsp_apicid = 0; + int needs_reset = 0; + struct sys_info *sysinfo = + (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); + + it8712f_24mhz_clkin(); + it8712f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + it8712f_kill_watchdog(); + uart_init(); + console_init(); + enable_rom_decode(); + m2v_bus_init(); + m2v_it8712f_gpio_init(); + + printk(BIOS_INFO, "now booting... \n"); + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + /* Halt if there was a built in self test failure. */ + report_bist_failure(bist); + setup_default_resource_map(); + setup_coherent_ht_domain(); + wait_all_core0_started(); + + printk(BIOS_INFO, "now booting... All core 0 started\n"); + +#if CONFIG_LOGICAL_CPUS==1 + /* It is said that we should start core1 after all core0 launched. */ + start_other_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + init_timer(); + ht_setup_chains_x(sysinfo); /* Init sblnk and sbbusn, nodes, sbdn. */ + + needs_reset = optimize_link_coherent_ht(); + print_debug_hex8(needs_reset); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + print_debug_hex8(needs_reset); + needs_reset |= k8t890_early_setup_ht(); + print_debug_hex8(needs_reset); + + if (needs_reset) { + printk(BIOS_DEBUG, "ht reset -\n"); + soft_reset(); + printk(BIOS_DEBUG, "FAILED!\n"); + } + + /* the HT settings needs to be OK, because link freq chnage may cause HT disconnect */ + /* allow LDT STOP asserts */ + vt8237_sb_enable_fid_vid(); + + enable_fid_change(); + print_debug("after enable_fid_change\n"); + + init_fidvid_bsp(bsp_apicid); + + /* Stop the APs so we can start them later in init. */ + allow_all_aps_stop(bsp_apicid); + + /* It's the time to set ctrl now. */ + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + enable_smbus(); + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + post_cache_as_ram(); +} +

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coreboot November 2010