coreboot November 2010

coreboot@coreboot.org

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285 discussions

[commit] r6035 - in trunk/src: include/device mainboard/asus/p2b southbridge/via/vt8237r
by repository service 07 Nov '10

07 Nov '10

Author: ruik Date: Sun Nov 7 19:20:32 2010 New Revision: 6035 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6035 Log: This adds the VT8237A LPC device id and the pci_driver struct in vt8237r_lpc.c Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Added: trunk/src/mainboard/asus/p2b/acpi_tables.c trunk/src/mainboard/asus/p2b/dsdt.asl trunk/src/mainboard/asus/p2b/romstage.c.orig Modified: trunk/src/include/device/pci_ids.h trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c Modified: trunk/src/include/device/pci_ids.h ============================================================================== --- trunk/src/include/device/pci_ids.h Sun Nov 7 18:49:05 2010 (r6034) +++ trunk/src/include/device/pci_ids.h Sun Nov 7 19:20:32 2010 (r6035) @@ -1226,6 +1226,7 @@ #define PCI_DEVICE_ID_VIA_K8T890CE_BR 0xb188 #define PCI_DEVICE_ID_VIA_VT6420_SATA 0x3149 #define PCI_DEVICE_ID_VIA_VT8237R_LPC 0x3227 +#define PCI_DEVICE_ID_VIA_VT8237A_LPC 0x3337 #define PCI_DEVICE_ID_VIA_VT8237S_LPC 0x3372 #define PCI_DEVICE_ID_VIA_VT8237_SATA 0x5372 #define PCI_DEVICE_ID_VIA_VT8237_VLINK 0x287e Added: trunk/src/mainboard/asus/p2b/acpi_tables.c ============================================================================== Added: trunk/src/mainboard/asus/p2b/dsdt.asl ============================================================================== Added: trunk/src/mainboard/asus/p2b/romstage.c.orig ============================================================================== Modified: trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c Sun Nov 7 18:49:05 2010 (r6034) +++ trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c Sun Nov 7 19:20:32 2010 (r6035) @@ -543,6 +543,12 @@ .device = PCI_DEVICE_ID_VIA_VT8237R_LPC, }; +static const struct pci_driver lpc_driver_a __pci_driver = { + .ops = &vt8237r_lpc_ops_r, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237A_LPC, +}; + static const struct pci_driver lpc_driver_s __pci_driver = { .ops = &vt8237r_lpc_ops_s, .vendor = PCI_VENDOR_ID_VIA,

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[commit] r6034 - in trunk/src/mainboard: arima/hdama ibm/e325 ibm/e326 tyan/s2882
by repository service 07 Nov '10

07 Nov '10

Author: oxygene Date: Sun Nov 7 18:49:05 2010 New Revision: 6034 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6034 Log: FIRST_CPU, SECOND_CPU, TOTAL_CPUS are only used in one other place, and that defines these symbols itself (and identical, too). Drop them. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/src/mainboard/arima/hdama/romstage.c trunk/src/mainboard/ibm/e325/romstage.c trunk/src/mainboard/ibm/e326/romstage.c trunk/src/mainboard/tyan/s2882/romstage.c Modified: trunk/src/mainboard/arima/hdama/romstage.c ============================================================================== --- trunk/src/mainboard/arima/hdama/romstage.c Sun Nov 7 18:47:01 2010 (r6033) +++ trunk/src/mainboard/arima/hdama/romstage.c Sun Nov 7 18:49:05 2010 (r6034) @@ -78,12 +78,6 @@ #endif #include "cpu/amd/dualcore/dualcore.c" -#define FIRST_CPU 1 -#define SECOND_CPU 1 -#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) - - - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/ibm/e325/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e325/romstage.c Sun Nov 7 18:47:01 2010 (r6033) +++ trunk/src/mainboard/ibm/e325/romstage.c Sun Nov 7 18:49:05 2010 (r6034) @@ -75,12 +75,6 @@ #endif #include "cpu/amd/dualcore/dualcore.c" -#define FIRST_CPU 1 -#define SECOND_CPU 1 -#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) - - - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/ibm/e326/romstage.c ============================================================================== --- trunk/src/mainboard/ibm/e326/romstage.c Sun Nov 7 18:47:01 2010 (r6033) +++ trunk/src/mainboard/ibm/e326/romstage.c Sun Nov 7 18:49:05 2010 (r6034) @@ -75,12 +75,6 @@ #endif #include "cpu/amd/dualcore/dualcore.c" -#define FIRST_CPU 1 -#define SECOND_CPU 1 -#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) - - - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" Modified: trunk/src/mainboard/tyan/s2882/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2882/romstage.c Sun Nov 7 18:47:01 2010 (r6033) +++ trunk/src/mainboard/tyan/s2882/romstage.c Sun Nov 7 18:49:05 2010 (r6034) @@ -73,12 +73,6 @@ #endif #include "cpu/amd/dualcore/dualcore.c" -#define FIRST_CPU 1 -#define SECOND_CPU 1 -#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU) - - - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c"

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[commit] r6033 - in trunk/src/mainboard/gigabyte: . ma785gmt ma78gm
by repository service 07 Nov '10

07 Nov '10

Author: uwe Date: Sun Nov 7 18:47:01 2010 New Revision: 6033 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6033 Log: Fix a few incorrect GIGABYTE board names (trivial). Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/gigabyte/Kconfig trunk/src/mainboard/gigabyte/ma785gmt/Kconfig trunk/src/mainboard/gigabyte/ma78gm/Kconfig Modified: trunk/src/mainboard/gigabyte/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/Kconfig Sun Nov 7 17:49:31 2010 (r6032) +++ trunk/src/mainboard/gigabyte/Kconfig Sun Nov 7 18:47:01 2010 (r6033) @@ -30,9 +30,9 @@ config BOARD_GIGABYTE_M57SLI bool "GA-M57SLI-S4" config BOARD_GIGABYTE_GA785GMT - bool "MA785GMT" + bool "GA-MA785GMT-UD2H" config BOARD_GIGABYTE_MA78GM - bool "MA78GM-US2H" + bool "GA-MA78GM-US2H" endchoice Modified: trunk/src/mainboard/gigabyte/ma785gmt/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ma785gmt/Kconfig Sun Nov 7 17:49:31 2010 (r6032) +++ trunk/src/mainboard/gigabyte/ma785gmt/Kconfig Sun Nov 7 18:47:01 2010 (r6033) @@ -40,7 +40,7 @@ config MAINBOARD_PART_NUMBER string - default "Gigabyte GA785GMT" + default "GA-MA785GMT-UD2H" config MAX_CPUS int Modified: trunk/src/mainboard/gigabyte/ma78gm/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ma78gm/Kconfig Sun Nov 7 17:49:31 2010 (r6032) +++ trunk/src/mainboard/gigabyte/ma78gm/Kconfig Sun Nov 7 18:47:01 2010 (r6033) @@ -40,7 +40,7 @@ config MAINBOARD_PART_NUMBER string - default "GIGABYTE MA78GM" + default "GA-MA78GM-US2H" config MAX_CPUS int

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Buying a new mainboard. Which vendors support coreboot?
by Niklas Cholmkvist 07 Nov '10

07 Nov '10

Hi, I would like a mainboard from a vendor that supports coreboot, but also has an Intel GMA(3D acceleration) on the same mainboard.(Intel GMA because of my percieved 'good 3D FLOSS drivers'...though irrelevant to coreboot) I've read that AMD is very supportive of coreboot. Do you think it's possible that there is an AMD mainboard with an Intel GMA(3D acceleration) on it? --

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[commit] r6032 - in trunk/src/mainboard/ecs: . p6iwp-fe
by repository service 07 Nov '10

07 Nov '10

Author: uwe Date: Sun Nov 7 17:49:31 2010 New Revision: 6032 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6032 Log: ECS P6IWP-Fe: Fix typo, add missing license header. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/mainboard/ecs/Kconfig trunk/src/mainboard/ecs/p6iwp-fe/devicetree.cb Modified: trunk/src/mainboard/ecs/Kconfig ============================================================================== --- trunk/src/mainboard/ecs/Kconfig Sun Nov 7 09:15:13 2010 (r6031) +++ trunk/src/mainboard/ecs/Kconfig Sun Nov 7 17:49:31 2010 (r6032) @@ -23,7 +23,7 @@ prompt "Mainboard model" config BOARD_ECS_P6IWP_FE - bool "P6IWP-FE" + bool "P6IWP-Fe" endchoice Modified: trunk/src/mainboard/ecs/p6iwp-fe/devicetree.cb ============================================================================== --- trunk/src/mainboard/ecs/p6iwp-fe/devicetree.cb Sun Nov 7 09:15:13 2010 (r6031) +++ trunk/src/mainboard/ecs/p6iwp-fe/devicetree.cb Sun Nov 7 17:49:31 2010 (r6032) @@ -1,3 +1,23 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Anders Jenbo <anders(a)jenbo.dk> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + chip northbridge/intel/i82810 # Northbridge device lapic_cluster 0 on # APIC cluster chip cpu/intel/socket_PGA370 # CPU

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interesting request for serial console over enet
by ron minnich 07 Nov '10

07 Nov '10

someone I know from a Big telecom company just pushed an interesting idea on me. If coreboot+seabios would provide a bios service for serial console over enet, it would improve their life a lot. They could stop building cyclades boxes into their racks, and stop worrying about which mainboards had serial ports. I know that coreboot can now do console over enet; would be neat if seabios could provide a path for payloads to use it. Note they don't want vga over enet or IPMI. Just a very simple "until we're booted" console over enet that looks like serial port. Sort of a bios-level version of this: http://man.cat-v.org/plan_9/8/cec Just thought I'd mention it ... ron

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[commit] r6031 - trunk/src/mainboard/intel/eagleheights
by repository service 07 Nov '10

07 Nov '10

Author: oxygene Date: Sun Nov 7 09:15:13 2010 New Revision: 6031 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6031 Log: Remove unused defines (UART_*) All other uses of these symbols have their own (identical) definitions. abuild-tested and trivial Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/src/mainboard/intel/eagleheights/romstage.c Modified: trunk/src/mainboard/intel/eagleheights/romstage.c ============================================================================== --- trunk/src/mainboard/intel/eagleheights/romstage.c Sun Nov 7 00:36:49 2010 (r6030) +++ trunk/src/mainboard/intel/eagleheights/romstage.c Sun Nov 7 09:15:13 2010 (r6031) @@ -40,24 +40,6 @@ #include "superio/intel/i3100/i3100_early_serial.c" #include "superio/smsc/smscsuperio/smscsuperio_early_serial.c" -/* Data */ -#define UART_RBR 0x00 -#define UART_TBR 0x00 - -/* Control */ -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/* Status */ -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 - #define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0) #define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)

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[PATCH]Move SET_FIDVID* to Kconfig
by Patrick Georgi 07 Nov '10

07 Nov '10

Hi, I moved the SET_FIDVID family of configuration options to Kconfig, adapting its use (CONFIG_ prefix), and tried to minimize the board specific settings. They get some defaults in src/cpu/amd/model_*xx/Kconfig, which are derived from the various #ifndef ... #define ... #endif blocks I removed in the cpu specific code. All "#define SET_FIDVID 0" in romstage.c files weren't necessary due to these defaults, as well as all "#define SET_FIDVID 1" in Fam10 boards, so these were stripped. Some "select SET_FIDVID" could probably still be removed. SET_FIDVID_CORE_RANGE was always 0, so I just chose that in the CPU config, instead of per-board. SET_FIDVID_CORE0_ONLY was always 1, so again, I moved this to the CPU. Any change in SET_FIDVID* configuration values as a result of this patch is a bug in this patch. Regards, Patrick Move SET_FIDVID family of configuration options to Kconfig. Reduce their per-board use and rely on per-cpu values instead. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>

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[commit] r6030 - in trunk/src/superio: renesas/m3885x serverengines/pilot via/vt1211
by repository service 06 Nov '10

06 Nov '10

Author: uwe Date: Sun Nov 7 00:36:49 2010 New Revision: 6030 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6030 Log: Various Super I/O fixes and corrections. - VIA VT1211: - Add missing LDNs and respective code to handle them. - Add some TODOs for other stuff that needs fixing. - Use VT1211_SP1 instead of hardcoding the LDN number (2). - Fixup pnp_dev_info[] as per datasheet, but some TODOs remain. - Various coding style fixes and changes to u8/u16/etc. - Serverengines Pilot: Various coding style fixes and changes to u8/u16/etc. Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/superio/renesas/m3885x/superio.c trunk/src/superio/serverengines/pilot/pilot.h trunk/src/superio/serverengines/pilot/pilot_early_init.c trunk/src/superio/serverengines/pilot/pilot_early_serial.c trunk/src/superio/via/vt1211/Makefile.inc trunk/src/superio/via/vt1211/chip.h trunk/src/superio/via/vt1211/vt1211.c trunk/src/superio/via/vt1211/vt1211.h Modified: trunk/src/superio/renesas/m3885x/superio.c ============================================================================== --- trunk/src/superio/renesas/m3885x/superio.c Sat Nov 6 01:57:19 2010 (r6029) +++ trunk/src/superio/renesas/m3885x/superio.c Sun Nov 7 00:36:49 2010 (r6030) @@ -44,15 +44,14 @@ m3885_configure_multikey(); } - static void m3885x_read_resources(device_t dev) { - // nothing, but this function avoids an error on serial console. + /* Nothing, but this function avoids an error on serial console. */ } static void m3885x_enable_resources(device_t dev) { - // nothing, but this function avoids an error on serial console. + /* Nothing, but this function avoids an error on serial console. */ } static struct device_operations ops = { @@ -74,5 +73,3 @@ CHIP_NAME("Renesas M3885x Super I/O") .enable_dev = enable_dev, }; - - Modified: trunk/src/superio/serverengines/pilot/pilot.h ============================================================================== --- trunk/src/superio/serverengines/pilot/pilot.h Sat Nov 6 01:57:19 2010 (r6029) +++ trunk/src/superio/serverengines/pilot/pilot.h Sun Nov 7 00:36:49 2010 (r6030) @@ -21,8 +21,8 @@ /* PILOT Super I/O is only based on LPC observation done on factory system. */ -#define PILOT_SP1 0x02 /* Com1 */ #define PILOT_LD1 0x01 /* Logical device 1 */ +#define PILOT_SP1 0x02 /* Com1 */ #define PILOT_LD4 0x04 /* Logical device 4 */ #define PILOT_LD5 0x05 /* Logical device 5 */ #define PILOT_LD7 0x07 /* Logical device 7 */ Modified: trunk/src/superio/serverengines/pilot/pilot_early_init.c ============================================================================== --- trunk/src/superio/serverengines/pilot/pilot_early_init.c Sat Nov 6 01:57:19 2010 (r6029) +++ trunk/src/superio/serverengines/pilot/pilot_early_init.c Sun Nov 7 00:36:49 2010 (r6030) @@ -29,7 +29,7 @@ */ static void pilot_early_init(device_t dev) { - unsigned port = dev >> 8; + u16 port = dev >> 8; print_debug("Using port: "); print_debug_hex16(port); @@ -55,6 +55,7 @@ pnp_set_enable(PNP_DEV(port, 0x3), 0); pnp_exit_ext_func_mode(dev); */ + pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x4)); pnp_exit_ext_func_mode(dev); @@ -95,6 +96,7 @@ pnp_enter_ext_func_mode(dev); pnp_set_enable(PNP_DEV(port, 0x7), 0); pnp_exit_ext_func_mode(dev); + /* pnp_enter_ext_func_mode(dev); pnp_set_logical_device(PNP_DEV(port, 0x8)); Modified: trunk/src/superio/serverengines/pilot/pilot_early_serial.c ============================================================================== --- trunk/src/superio/serverengines/pilot/pilot_early_serial.c Sat Nov 6 01:57:19 2010 (r6029) +++ trunk/src/superio/serverengines/pilot/pilot_early_serial.c Sun Nov 7 00:36:49 2010 (r6030) @@ -25,20 +25,20 @@ #include "pilot.h" /* Pilot uses 0x5A/0xA5 pattern to actiavte deactivate config access. */ -static inline void pnp_enter_ext_func_mode(device_t dev) +static void pnp_enter_ext_func_mode(device_t dev) { - unsigned port = dev >> 8; + u16 port = dev >> 8; outb(0x5A, port); } static void pnp_exit_ext_func_mode(device_t dev) { - unsigned port = dev >> 8; + u16 port = dev >> 8; outb(0xA5, port); } /* Serial config is a fairly standard procedure. */ -static void pilot_enable_serial(device_t dev, unsigned iobase) +static void pilot_enable_serial(device_t dev, u16 iobase) { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); @@ -51,7 +51,7 @@ { pnp_enter_ext_func_mode(dev); pnp_set_logical_device(dev); - pnp_set_iobase(dev, PNP_IDX_IO0, 0x00); + pnp_set_iobase(dev, PNP_IDX_IO0, 0x0000); pnp_set_enable(dev, 0); pnp_exit_ext_func_mode(dev); } Modified: trunk/src/superio/via/vt1211/Makefile.inc ============================================================================== --- trunk/src/superio/via/vt1211/Makefile.inc Sat Nov 6 01:57:19 2010 (r6029) +++ trunk/src/superio/via/vt1211/Makefile.inc Sun Nov 7 00:36:49 2010 (r6030) @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_VIA_VT1211) += vt1211.c + Modified: trunk/src/superio/via/vt1211/chip.h ============================================================================== --- trunk/src/superio/via/vt1211/chip.h Sat Nov 6 01:57:19 2010 (r6029) +++ trunk/src/superio/via/vt1211/chip.h Sun Nov 7 00:36:49 2010 (r6030) @@ -18,8 +18,8 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_VIA_VT1211 -#define _SUPERIO_VIA_VT1211 +#ifndef SUPERIO_VIA_VT1211_CHIP_H +#define SUPERIO_VIA_VT1211_CHIP_H #include <uart8250.h> @@ -29,4 +29,4 @@ struct uart8250 com1, com2; }; -#endif /* _SUPERIO_VIA_VT1211 */ +#endif Modified: trunk/src/superio/via/vt1211/vt1211.c ============================================================================== --- trunk/src/superio/via/vt1211/vt1211.c Sat Nov 6 01:57:19 2010 (r6029) +++ trunk/src/superio/via/vt1211/vt1211.c Sun Nov 7 00:36:49 2010 (r6030) @@ -19,33 +19,30 @@ * MA 02110-1301 USA */ - /* vt1211 routines and defines*/ - #include <arch/io.h> #include <console/console.h> #include <device/device.h> #include <device/pnp.h> #include <uart8250.h> #include <stdlib.h> - #include "vt1211.h" #include "chip.h" -static unsigned char vt1211hwmonitorinits[]={ - 0x10,0x3, 0x11,0x10, 0x12,0xd, 0x13,0x7f, +static u8 hwm_io_regs[] = { + 0x10,0x03, 0x11,0x10, 0x12,0x0d, 0x13,0x7f, 0x14,0x21, 0x15,0x81, 0x16,0xbd, 0x17,0x8a, - 0x18,0x0, 0x19,0x0, 0x1a,0x0, 0x1b,0x0, - 0x1d,0xff, 0x1e,0x0, 0x1f,0x73, 0x20,0x67, + 0x18,0x00, 0x19,0x00, 0x1a,0x00, 0x1b,0x00, + 0x1d,0xff, 0x1e,0x00, 0x1f,0x73, 0x20,0x67, 0x21,0xc1, 0x22,0xca, 0x23,0x74, 0x24,0xc2, - 0x25,0xc7, 0x26,0xc9, 0x27,0x7f, 0x29,0x0, - 0x2a,0x0, 0x2b,0xff, 0x2c,0x0, 0x2d,0xff, - 0x2e,0x0, 0x2f,0xff, 0x30,0x0, 0x31,0xff, - 0x32,0x0, 0x33,0xff, 0x34,0x0, 0x39,0xff, - 0x3a,0x0, 0x3b,0xff, 0x3c,0xff, 0x3d,0xff, - 0x3e,0x0, 0x3f,0xb0, 0x43,0xff, 0x44,0xff, - 0x46,0xff, 0x47,0x50, 0x4a,0x3, 0x4b,0xc0, - 0x4c,0x0, 0x4d,0x0, 0x4e,0xf, 0x5d,0x77, - 0x5c,0x0, 0x5f,0x33, 0x40,0x1 + 0x25,0xc7, 0x26,0xc9, 0x27,0x7f, 0x29,0x00, + 0x2a,0x00, 0x2b,0xff, 0x2c,0x00, 0x2d,0xff, + 0x2e,0x00, 0x2f,0xff, 0x30,0x00, 0x31,0xff, + 0x32,0x00, 0x33,0xff, 0x34,0x00, 0x39,0xff, + 0x3a,0x00, 0x3b,0xff, 0x3c,0xff, 0x3d,0xff, + 0x3e,0x00, 0x3f,0xb0, 0x43,0xff, 0x44,0xff, + 0x46,0xff, 0x47,0x50, 0x4a,0x03, 0x4b,0xc0, + 0x4c,0x00, 0x4d,0x00, 0x4e,0x0f, 0x5d,0x77, + 0x5c,0x00, 0x5f,0x33, 0x40,0x01, }; static void pnp_enter_ext_func_mode(device_t dev) @@ -59,32 +56,39 @@ outb(0xaa, dev->path.pnp.port); } -static void vt1211_set_iobase(device_t dev, unsigned index, unsigned iobase) +static void vt1211_set_iobase(device_t dev, u8 index, u16 iobase) { switch (dev->path.pnp.device) { - case VT1211_FDC: - case VT1211_PP: - case VT1211_SP1: - case VT1211_SP2: - pnp_write_config(dev, index + 0, (iobase >> 2) & 0xff); - break; - case VT1211_HWM: - default: - pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff); - pnp_write_config(dev, index + 1, iobase & 0xff); - break; + case VT1211_FDC: + case VT1211_PP: + case VT1211_SP1: + case VT1211_SP2: + pnp_write_config(dev, index + 0, (iobase >> 2) & 0xff); + break; + case VT1211_ROM: + /* TODO: Error. VT1211_ROM doesn't have an I/O base. */ + break; + case VT1211_MIDI: + case VT1211_GAME: + case VT1211_GPIO: + case VT1211_WDG: + case VT1211_WUC: + case VT1211_HWM: + case VT1211_FIR: + default: + pnp_write_config(dev, index + 0, (iobase >> 8) & 0xff); + pnp_write_config(dev, index + 1, iobase & 0xff); + break; } } -static void init_hwm(unsigned long base) +/* Initialize VT1211 hardware monitor registers, which are at 0xECXX. */ +static void init_hwm(u16 base) { int i; - /* initialize vt1211 hardware monitor registers, which are at 0xECXX */ - for(i = 0; i < sizeof(vt1211hwmonitorinits); i += 2) { - outb(vt1211hwmonitorinits[i + 1], - base + vt1211hwmonitorinits[i]); - } + for (i = 0; i < sizeof(hwm_io_regs); i += 2) + outb(hwm_io_regs[i + 1], base + hwm_io_regs[i]); } static void vt1211_init(struct device *dev) @@ -92,14 +96,10 @@ struct superio_via_vt1211_config *conf = dev->chip_info; struct resource *res0; - if (!dev->enabled) { + if (!dev->enabled) return; - } switch (dev->path.pnp.device) { - case VT1211_FDC: - case VT1211_PP: - break; case VT1211_SP1: res0 = find_resource(dev, PNP_IDX_IO0); init_uart8250(res0->base, &conf->com1); @@ -112,14 +112,25 @@ res0 = find_resource(dev, PNP_IDX_IO0); init_hwm(res0->base); break; + case VT1211_FDC: + case VT1211_PP: + case VT1211_MIDI: + case VT1211_GAME: + case VT1211_GPIO: + case VT1211_WDG: + case VT1211_WUC: + case VT1211_FIR: + case VT1211_ROM: + /* TODO: Any init needed for these LDNs? */ + break; default: - printk(BIOS_INFO, "vt1211 asked to initialise unknown device!\n"); + printk(BIOS_INFO, "VT1211: Cannot init unknown device!\n"); } } static void vt1211_pnp_enable_resources(device_t dev) { - printk(BIOS_DEBUG, "%s - enabling\n",dev_path(dev)); + printk(BIOS_DEBUG, "%s - enabling\n", dev_path(dev)); pnp_enter_ext_func_mode(dev); pnp_enable_resources(dev); pnp_exit_ext_func_mode(dev); @@ -130,41 +141,39 @@ struct resource *res; #if CONFIG_CONSOLE_SERIAL8250 == 1 - if( dev->path.pnp.device == 2 ){ - for(res = dev->resource_list; res; res = res->next){ + /* TODO: Do the same for SP2? */ + if (dev->path.pnp.device == VT1211_SP1) { + for (res = dev->resource_list; res; res = res->next) { res->flags |= IORESOURCE_STORED; report_resource_stored(dev, res, ""); } return; } #endif + pnp_enter_ext_func_mode(dev); - /* Select the device */ + pnp_set_logical_device(dev); /* Paranoia says I should disable the device here... */ - for(res = dev->resource_list; res; res = res->next){ + for (res = dev->resource_list; res; res = res->next) { if (!(res->flags & IORESOURCE_ASSIGNED)) { - printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010Lx not assigned\n", - dev_path(dev), res->index, - resource_type(res), - res->size); + printk(BIOS_ERR, "ERROR: %s %02lx %s size: 0x%010Lx " + "not assigned\n", dev_path(dev), res->index, + resource_type(res), res->size); continue; } - /* Now store the resource */ + /* Now store the resource. */ if (res->flags & IORESOURCE_IO) { vt1211_set_iobase(dev, res->index, res->base); - } - else if (res->flags & IORESOURCE_DRQ) { + } else if (res->flags & IORESOURCE_DRQ) { pnp_set_drq(dev, res->index, res->base); - } - else if (res->flags & IORESOURCE_IRQ) { + } else if (res->flags & IORESOURCE_IRQ) { pnp_set_irq(dev, res->index, res->base); - } - else { - printk(BIOS_ERR, "ERROR: %s %02lx unknown resource type\n", - dev_path(dev), res->index); + } else { + printk(BIOS_ERR, "ERROR: %s %02lx unknown resource " + "type\n", dev_path(dev), res->index); return; } res->flags |= IORESOURCE_STORED; @@ -177,12 +186,13 @@ static void vt1211_pnp_enable(device_t dev) { - if (!dev->enabled) { - pnp_enter_ext_func_mode(dev); - pnp_set_logical_device(dev); - pnp_set_enable(dev, 0); - pnp_exit_ext_func_mode(dev); - } + if (dev->enabled) + return; + + pnp_enter_ext_func_mode(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_exit_ext_func_mode(dev); } struct device_operations ops = { @@ -193,21 +203,25 @@ .init = vt1211_init, }; +/* TODO: Check if 0x07f8 is correct for FDC/PP/SP1/SP2, the rest is correct. */ static struct pnp_info pnp_dev_info[] = { - { &ops, VT1211_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, VT1211_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, - { &ops, VT1211_SP1, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0}, }, - { &ops, VT1211_SP2, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0}, }, - { &ops, VT1211_HWM, PNP_IO0 , { 0xff00, 0 }, }, + { &ops, VT1211_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, }, + { &ops, VT1211_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0 }, }, + { &ops, VT1211_SP1, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 }, }, + { &ops, VT1211_SP2, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0 }, }, + { &ops, VT1211_MIDI, PNP_IO0 | PNP_IRQ0, { 0xfffc, 0 }, }, + { &ops, VT1211_GAME, PNP_IO0, { 0xfff8, 0 }, }, + { &ops, VT1211_GPIO, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, + { &ops, VT1211_WDG, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, + { &ops, VT1211_WUC, PNP_IO0 | PNP_IRQ0, { 0xfff0, 0 }, }, + { &ops, VT1211_HWM, PNP_IO0 | PNP_IRQ0, { 0xff00, 0 }, }, + { &ops, VT1211_FIR, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0xff00, 0 }, }, + { &ops, VT1211_ROM, }, }; static void enable_dev(struct device *dev) { - printk(BIOS_DEBUG, "vt1211 enabling PNP devices.\n"); - pnp_enable_devices(dev, - &ops, - ARRAY_SIZE(pnp_dev_info), - pnp_dev_info); + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); } struct chip_operations superio_via_vt1211_ops = { Modified: trunk/src/superio/via/vt1211/vt1211.h ============================================================================== --- trunk/src/superio/via/vt1211/vt1211.h Sat Nov 6 01:57:19 2010 (r6029) +++ trunk/src/superio/via/vt1211/vt1211.h Sun Nov 7 00:36:49 2010 (r6030) @@ -18,17 +18,16 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -/* vt1211 PNP devices */ - -#define VT1211_FDC 0 /* Floppy */ -#define VT1211_PP 1 /* Parallel Port */ -#define VT1211_SP1 2 /* COM1 */ -#define VT1211_SP2 3 /* COM2 */ -#define VT1211_MIDI 6 /* MIDI */ -#define VT1211_GAME 7 /* Game port */ -#define VT1211_GPIO 8 /* GPIO pins */ -#define VT1211_WATCHDOG 9 /* Watchdog timer */ -#define VT1211_WAKEUP 10 /* Wakeup control */ -#define VT1211_HWM 11 /* Hardware monitor */ -#define VT1211_FIR 12 /* Irda */ -#define VT1211_ROM 13 /* ROM control */ +/* Logical device numbers (LDNs). */ +#define VT1211_FDC 0x00 /* Floppy */ +#define VT1211_PP 0x01 /* Parallel port */ +#define VT1211_SP1 0x02 /* COM1 */ +#define VT1211_SP2 0x03 /* COM2 */ +#define VT1211_MIDI 0x06 /* MIDI */ +#define VT1211_GAME 0x07 /* Game port (GMP) */ +#define VT1211_GPIO 0x08 /* GPIO */ +#define VT1211_WDG 0x09 /* Watchdog timer (WDG) */ +#define VT1211_WUC 0x0a /* Wake-up control (WUC) */ +#define VT1211_HWM 0x0b /* Hardware monitor (HM) */ +#define VT1211_FIR 0x0c /* Very fast IR (VFIR/FIR) */ +#define VT1211_ROM 0x0d /* Flash ROM */

2 1

[PATCH/RFC]Move SYSTEM_TYPE to Kconfig
by Patrick Georgi 06 Nov '10

06 Nov '10

Hi, we currently have a config variable SYSTEM_TYPE in AMD based boards' romstage.c, which defines if the board is "server", "desktop" or "mobile". Among other things, the AMD code expects "server" to do ECC. I broke that out to Kconfig, but extended the categories to the ACPI set (which the OS can use for tuning the power management profile accordingly). Now, it's declared in Kconfig with ACPI categories (which provides a couple more values, like "SOHO Server" and "Performance Server"), and based on these, the AMD value is chosen. The Kconfig selection is also used to set the preferred PM profile in ACPI (on the modified boards only for now). The upside of this approach is that we only set the board type once, and have it trickle down to whoever cares for it - so consistency is implicitely ensured through the build system. We also won't have to worry about this field should we ever get to the point that the fadt is handled by unified code instead of per-board code (and I hope we'll get there eventually). The downside is that some things can't be modelled quite right (eg. one AMD board was marked "server" for the AMD code, but "workstation" for ACPI - I made that a "SOHO Server" instead in this patch). If this patch is accepted, I'd build another patch that adapts those boards which provide an FADT (which contains the PM profile field) to this new config option. All others are of "unspecified" type by default if they're ever made ACPI aware. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de>

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coreboot November 2010