coreboot November 2010

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285 discussions

Gigabyte M57SLI - some troubles with recent coreboot version
by Harald Gutmann 04 Nov '10

04 Nov '10

Hello readers, after some while I tried to use coreboot again on my well supported Gigabyte M57SLI and I was really happy, that the first built image booted the machine. Last time I tried this, I stumbled across an error with the RAM, and had no time to investigate this further. With the recent version of coreboot (r6013) I get some errors which I'd like to fix. I don't know if some changes to coreboot happened in the meanwhile or, if the kernel got changed so that this errors appear. My kernel version running is from debian sid with the version number 2.6.32-27 for AMD64. The problems I get are the following: [ 0.000000] mtrr: your BIOS has set up an incorrect mask, fixing it up. [ 0.000000] Modules linked in: [ 0.000000] Pid: 0, comm: swapper Not tainted 2.6.32-5-amd64 #1 [ 0.000000] Call Trace: [ 0.000000] [<ffffffff8102189f>] ? generic_get_mtrr+0xbf/0xf9 [ 0.000000] [<ffffffff8102189f>] ? generic_get_mtrr+0xbf/0xf9 [ 0.000000] [<ffffffff8104dd8c>] ? warn_slowpath_common+0x77/0xa3 [ 0.000000] [<ffffffff8104de14>] ? warn_slowpath_fmt+0x51/0x59 [ 0.000000] [<ffffffff810219ab>] ? mtrr_wrmsr+0x1c/0x49 [ 0.000000] [<ffffffff81021bb0>] ? get_fixed_ranges+0x71/0x98 [ 0.000000] [<ffffffff810219ab>] ? mtrr_wrmsr+0x1c/0x49 [ 0.000000] [<ffffffff81021a6f>] ? prepare_set+0x97/0x9d [ 0.000000] [<ffffffff81021ac8>] ? post_set+0x53/0x60 [ 0.000000] [<ffffffff814fb0d6>] ? get_mtrr_state+0x2eb/0x2f6 [ 0.000000] [<ffffffff8102189f>] ? generic_get_mtrr+0xbf/0xf9 [ 0.000000] [<ffffffff812f96e3>] ? printk+0x4e/0x5b [ 0.000000] [<ffffffff814fbcad>] ? mtrr_trim_uncached_memory+0x91/0x311 [ 0.000000] [<ffffffff814fac46>] ? mtrr_bp_init+0x1b1/0x1d4 [ 0.000000] [<ffffffff8123a7b7>] ? dmi_name_in_serial+0x1d/0x28 [ 0.000000] [<ffffffff81504f2b>] ? early_gart_iommu_check+0x9b/0x287 [ 0.000000] [<ffffffff814f7141>] ? setup_arch+0x43f/0x9cb [ 0.000000] [<ffffffff811f6a9f>] ? extract_entropy+0x6a/0x125 [ 0.000000] [<ffffffff814f3140>] ? early_idt_handler+0x0/0x71 [ 0.000000] [<ffffffff814f39d0>] ? start_kernel+0xdb/0x3e8 [ 0.000000] [<ffffffff814f33b7>] ? x86_64_start_kernel+0xf9/0x106 [ 0.000000] ---[ end trace a7919e7f17c0a725 ]--- [ 0.000000] initial memory mapped : 0 - 20000000 [ 0.000000] init_memory_mapping: 0000000000000000-000000007ffef000 [ 0.000000] 0000000000 - 007fe00000 page 2M [ 0.000000] 007fe00000 - 007ffef000 page 4k [ 0.000000] kernel direct mapping tables up to 7ffef000 @ 8000-c000 [ 0.000000] RAMDISK: 37753000 - 37fefe82 According to /proc/mtrr it looks like something failed on the MTRR setup: reg00: base=0x000000000 ( 0MB), size= 2048MB, count=1: write-back I don't really know how this table looked like the last time I had coreboot running without troubles (it was around my last commit about rev. 4362), but it definitely had no MTRR error and the table contained more lines with different values. Rudolf Marek told me yesterday on the IRC that there are some MTRR problems with different boards, but not the same type of problem. The second one, which is delaying the boot process form the kernel is something regarding the USB controller on the board. Here are the messages from the dmesg, but right now I didn't look that up in detail until now: [ 1.038117] hub 2-0:1.0: USB hub found [ 1.396015] usb 1-10: new high speed USB device using ehci_hcd and address 4 [ 11.528167] usb 1-10: device descriptor read/all, error -110 [ 11.640020] usb 1-10: new high speed USB device using ehci_hcd and address 5 [ 21.772039] usb 1-10: device descriptor read/all, error -110 [ 21.884014] usb 1-10: new high speed USB device using ehci_hcd and address 6 [ 26.904039] usb 1-10: device descriptor read/8, error -110 Oh, I just saw that this could be related to a new USB device which doesn't give a proper name via USB identification. - Need to try booting without device or booting on the proprietary bios. On the last point I'm not really sure if I should call it problem, or if this is just warnings/errors from kernel changes:[ 5.400416] k8temp 0000:00:18.3: Temperature readouts might be wrong - check erratum #141 [ 5.670067] EDAC MC: Ver: 2.1.0 Oct 30 2010 [ 5.671976] EDAC amd64_edac: Ver: 3.2.0 Oct 30 2010 [ 5.672079] EDAC amd64: This node reports that Memory ECC is currently disabled, set F3x44[22] (0000:00:18.3). [ 5.672087] EDAC amd64: ECC disabled in the BIOS or no ECC capability, module will not load. [ 5.672088] Either enable ECC checking or force module loading by setting 'ecc_enable_override'. [ 5.672089] (Note that use of the override may cause unknown side effects.) [ 5.672113] amd64_edac: probe of 0000:00:18.2 failed with error -22 About the temperature readouts I'm not sure if this is only a warning, because I know that there was some discussion about this erratum from AMD on the list. Does anyone know something about this one? The ECC check might also only be a warning, as the mainboard (afaik) does not support ECC ram. Hints on that one? For everyone who read until here, thank you for your time reading the mail. Kind regards, Harald Gutmann

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[commit] r6018 - in trunk/src: mainboard/via/epia southbridge/via/vt8231
by repository service 04 Nov '10

04 Nov '10

Author: myles Date: Thu Nov 4 19:33:42 2010 New Revision: 6018 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6018 Log: Add a rom_enable() function to via/vt8231 and call it from via/epia/romstage.c Signed-off-by: Uwe Hermann <uwe(a)hermann-uwe.de> Signed-off-by: Myles Watson <mylesgw(a)gmail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/src/southbridge/via/vt8231/vt8231_enable_rom.c Modified: trunk/src/mainboard/via/epia/romstage.c trunk/src/southbridge/via/vt8231/vt8231_lpc.c Modified: trunk/src/mainboard/via/epia/romstage.c ============================================================================== --- trunk/src/mainboard/via/epia/romstage.c Wed Nov 3 22:46:41 2010 (r6017) +++ trunk/src/mainboard/via/epia/romstage.c Thu Nov 4 19:33:42 2010 (r6018) @@ -15,6 +15,7 @@ #include "lib/debug.c" #include "southbridge/via/vt8231/vt8231_early_smbus.c" #include "southbridge/via/vt8231/vt8231_early_serial.c" +#include "southbridge/via/vt8231/vt8231_enable_rom.c" static inline int spd_read_byte(unsigned device, unsigned address) { @@ -86,6 +87,7 @@ /* Halt if there was a built in self test failure */ report_bist_failure(bist); + vt8231_enable_rom(); enable_mainboard_devices(); enable_smbus(); enable_shadow_ram(); Added: trunk/src/southbridge/via/vt8231/vt8231_enable_rom.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/southbridge/via/vt8231/vt8231_enable_rom.c Thu Nov 4 19:33:42 2010 (r6018) @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Uwe Hermann <uwe(a)hermann-uwe.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <arch/romcc_io.h> +#include <device/pci_ids.h> + +static void vt8231_enable_rom(void) +{ + device_t dev; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_8231), 0); + + /* + * ROM decode control register (0x43): + * + * Bit Decode range + * ----------------- + * 7 0xFFFE0000-0xFFFEFFFF + * 6 0xFFF80000-0xFFFDFFFF + * 5 0xFFF00000-0xFFF7FFFF + * 4 0x000E0000-0x000EFFFF + * 3 0x000D8000-0x000DFFFF + * 2 0x000D0000-0x000D7FFF + * 1 0x000C8000-0x000CFFFF + * 0 0x000C0000-0x000C7FFF + */ + pci_write_config8(dev, 0x43, (1 << 7) | (1 << 6) | (1 << 5)); +} Modified: trunk/src/southbridge/via/vt8231/vt8231_lpc.c ============================================================================== --- trunk/src/southbridge/via/vt8231/vt8231_lpc.c Wed Nov 3 22:46:41 2010 (r6017) +++ trunk/src/southbridge/via/vt8231/vt8231_lpc.c Thu Nov 4 19:33:42 2010 (r6018) @@ -61,9 +61,6 @@ enables |= 0x80; pci_write_config8(dev, 0x6C, enables); - // Map 4MB of FLASH into the address space - pci_write_config8(dev, 0x41, 0x7f); - // Set bit 6 of 0x40, because Award does it (IO recovery time) // IMPORTANT FIX - EISA 0x4d0 decoding must be on so that PCI // interrupts can be properly marked as level triggered.

1 0

EPIA halting after vt8601 init
by QCUIAG QCUIAG 04 Nov '10

04 Nov '10

Hello, please advise on EPIA 800 board hanging after northbridge initialisation. I checked against chipset datasheet and working AWARD dump - the northbridge SDRAM configuration registers are correctly set. There are no errors in memory test, I can induce errors in memory test for example with wrongly configured paging registers. I have tested with five different memory modules (single/double sided, differing speeds, latencys). I did found an old thread (by Al Hooton) with similar problem, that was resolved with correct CAS latency setting, does not help in this case. Outcome does not differ with/without payload(s) and the hardware passes all tests with AWARD I can throw at it. Is this rom structure reasonable (missing fallback/romstage?): CBFSPRINT coreboot.rom coreboot.rom: 256 kB, bootblocksize 65536, romsize 262144, offset 0x0 Alignment: 64 bytes Name Offset Type Size fallback/coreboot_ram 0x0 stage 47306 fallback/payload 0xb940 payload 17021 pci1023,8500.rom 0xfc00 optionrom 49152 (empty) 0x1bc40 null 82808 What I get out from console with SPEW: coreboot-4.0-r6016M Wed Nov 3 21:17:24 EET 2010 starting... 87 is the comm register SMBus controller enabled vt8601 init starting 00000000 is the north 1106 0601 0120d4 is the computed timing NOP PRECHARGE DUMMY READS CBR MRS NORMAL set ref. rate enable multi-page open Slot 00 is SDRAM 20000000 bytes 000e is the MA type Slot 01 is empty Slot 02 is empty Slot 03 is empty vt8601 done <northbridge dump> 00:06 11 01 06 06 00 90 22 05 00 00 06 00 00 00 00 10:08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30:00 00 00 00 a0 00 00 00 00 00 00 00 00 00 00 00 40:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 50:ac 08 80 00 00 00 40 40 e0 00 40 40 40 40 40 40 60:3f 00 00 31 e6 95 95 00 52 3c 86 0d 08 7f 00 00 70:00 00 00 00 00 00 00 00 01 f0 00 00 00 00 00 00 80:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0:02 00 20 00 03 02 00 07 00 00 00 00 08 02 00 00 b0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0:00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0:00 00 00 00 00 00 01 01 00 00 00 00 00 00 00 00 <memory tests> Testing DRAM : 00000000-000a0000 DRAM fill: 00000000-000a0000 000a0000 DRAM filled DRAM verify: 00000000-000a0000 000a0000 DRAM range verified. Done. Testing DRAM : 00100000-01000000 DRAM fill: 00100000-01000000 01000000 DRAM filled DRAM verify: 00100000-01000000 01000000 DRAM range verified. Done. Loading stage image. Check CBFS header at <hangs here> With lower loglevel: coreboot-4.0-r6016M Wed Nov 3 21:30:53 EET 2010 starting... vt8601 init starting Slot 00 is SDRAM 20000000 bytes Slot 01 is empty Slot 02 is empty Slot 03 is empty vt8601 done Stage: loading fallback/coreboot_ram @ 0x <hangs here> Regards, Toomas Pruuden

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Re: [coreboot] [superiotool] Fix VID / SPI registers for F71889
by Neo The User 04 Nov '10

04 Nov '10

Sorry, I forgot to sign-off. Signed-off-by: Alec Ari <neotheuser(a)ymail.com> --- On Thu, 11/4/10, Neo The User <neotheuser(a)ymail.com> wrote: > From: Neo The User <neotheuser(a)ymail.com> > Subject: [superiotool] Fix VID / SPI registers for F71889 > To: coreboot(a)coreboot.org > Date: Thursday, November 4, 2010, 3:17 PM > Hi, The SPI should be on 0x8, not > 0x7, as that is the VID. I double checked the datasheet and > came across this while working on the coreboot port for my > board. This is a follow-up for the initial F71889 support > for superiotool. > > >

1 0

[superiotool] Fix VID / SPI registers for F71889
by Neo The User 04 Nov '10

04 Nov '10

Hi, The SPI should be on 0x8, not 0x7, as that is the VID. I double checked the datasheet and came across this while working on the coreboot port for my board. This is a follow-up for the initial F71889 support for superiotool.

1 0

[PATCH] ACPI: XP doesn't like qwords...
by Tobias Diedrich 04 Nov '10

04 Nov '10

Since XP only implements parts of ACPI 2.0, it chokes on the TOM2 qword in the SSDT, which is present if a board uses k8acpi_write_vars. With the acpigen_write_name_qword("TOM2"... in place I get a Stop A5 (0x11, 0x8, <virtual address of SSDT>, <somevalue>) bluescreen on boot. This patch replaces the qword with a dword, which contains (TOM2 >> 20), giving us 1MB granularity and a limit of almost 4Exabyte of memory. I added corresponding ShiftLeft calls in the commented out dsdt sections that would use TOM2 if they were not commented out. This problem was introduced with http://tracker.coreboot.org/trac/coreboot/changeset/3953 Note that all corresponding DSDTs currently only ever check TOM2 against 0. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- Index: src/northbridge/amd/amdk8/amdk8_acpi.c =================================================================== --- src/northbridge/amd/amdk8/amdk8_acpi.c.orig 2010-11-03 23:19:03.000000000 +0100 +++ src/northbridge/amd/amdk8/amdk8_acpi.c 2010-11-03 23:19:37.000000000 +0100 @@ -270,7 +270,15 @@ msr = rdmsr(TOP_MEM); lens += acpigen_write_name_dword("TOM1", msr.lo); msr = rdmsr(TOP_MEM2); - lens += acpigen_write_name_qword("TOM2", (((uint64_t) msr.hi) << 32) | msr.lo); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); lens += k8acpi_write_HT(); //minus opcode Index: src/mainboard/gigabyte/ma78gm/dsdt.asl =================================================================== --- src/mainboard/gigabyte/ma78gm/dsdt.asl.orig 2010-11-03 23:19:03.000000000 +0100 +++ src/mainboard/gigabyte/ma78gm/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Index: src/mainboard/asrock/939a785gmh/dsdt.asl =================================================================== --- src/mainboard/asrock/939a785gmh/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/asrock/939a785gmh/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1122,7 +1122,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1530,7 +1530,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Index: src/mainboard/kontron/kt690/dsdt.asl =================================================================== --- src/mainboard/kontron/kt690/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/kontron/kt690/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1129,7 +1129,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1557,7 +1557,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Index: src/mainboard/gigabyte/ma785gmt/dsdt.asl =================================================================== --- src/mainboard/gigabyte/ma785gmt/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/gigabyte/ma785gmt/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Index: src/mainboard/amd/mahogany/dsdt.asl =================================================================== --- src/mainboard/amd/mahogany/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/amd/mahogany/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1126,7 +1126,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1572,7 +1572,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Index: src/mainboard/amd/pistachio/dsdt.asl =================================================================== --- src/mainboard/amd/pistachio/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/amd/pistachio/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1128,7 +1128,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1480,7 +1480,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Index: src/mainboard/amd/dbm690t/dsdt.asl =================================================================== --- src/mainboard/amd/dbm690t/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/amd/dbm690t/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1129,7 +1129,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1557,7 +1557,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Index: src/mainboard/amd/mahogany_fam10/dsdt.asl =================================================================== --- src/mainboard/amd/mahogany_fam10/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/amd/mahogany_fam10/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Index: src/mainboard/amd/tilapia_fam10/dsdt.asl =================================================================== --- src/mainboard/amd/tilapia_fam10/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/amd/tilapia_fam10/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Index: src/mainboard/iei/kino-780am2-fam10/dsdt.asl =================================================================== --- src/mainboard/iei/kino-780am2-fam10/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/iei/kino-780am2-fam10/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Index: src/mainboard/jetway/pa78vm5/dsdt.asl =================================================================== --- src/mainboard/jetway/pa78vm5/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/jetway/pa78vm5/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Index: src/mainboard/technexion/tim8690/dsdt.asl =================================================================== --- src/mainboard/technexion/tim8690/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/technexion/tim8690/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1129,7 +1129,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1557,7 +1557,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Index: src/mainboard/technexion/tim5690/dsdt.asl =================================================================== --- src/mainboard/technexion/tim5690/dsdt.asl.orig 2010-11-03 23:19:29.000000000 +0100 +++ src/mainboard/technexion/tim5690/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1129,7 +1129,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1557,7 +1557,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */ Index: src/mainboard/asus/m4a785-m/dsdt.asl =================================================================== --- src/mainboard/asus/m4a785-m/dsdt.asl.orig 2010-11-03 23:19:29.000000000 +0100 +++ src/mainboard/asus/m4a785-m/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */

2 2

[PATCH] Geode GX2 print(k)
by Nils 03 Nov '10

03 Nov '10

Remove banner wrapper function and unify print(k). Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> The banner part was requested by Uwe. This is Abuild and boot tested. Thanks, Nils.

2 1

Re: [coreboot] F71889 Super I/O patch
by Neo The User 03 Nov '10

03 Nov '10

Signed-off-by: Alec Ari <neotheuser(a)ymail.com> --- On Wed, 11/3/10, Neo The User <neotheuser(a)ymail.com> wrote: > From: Neo The User <neotheuser(a)ymail.com> > Subject: F71889 Super I/O patch > To: coreboot(a)coreboot.org > Date: Wednesday, November 3, 2010, 5:55 PM > Hello, I looked over the F71889 > Fintek datasheet, and its very similar to the F71863FG I > noticed. I used sed to replace some of the names around and > such. I haven't tested it, nor will I, since I have little > to no experience with flashing devices, and have no back-up > (can't recover) and I do have a stub (that most likely wont > work) for the MSI MS785GT-E63 board, and it compiled fine > and all, using the F71889 code, I mainly just changed the > romstage.c file around to make it fit, while still basing > the code off the other 785 boards. If anybody wants to test > the F71889 patch, feel free. > > Also I wasn't sure to keep the same name in the other > Fintek chips or not, so I changed the name to mine, and the > year. I apologize if that was incorrect, and will be more > than willing to keep the original GNU header. > > Some indentation was changed when using svn diff to > generate the patch. > > -Alec Ari <neotheuser(a)ymail.com> > > >

2 1

[commit] r6017 - in trunk/src/superio/fintek: . f71889
by repository service 03 Nov '10

03 Nov '10

Author: uwe Date: Wed Nov 3 22:46:41 2010 New Revision: 6017 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6017 Log: Add Fintek F71889 Super I/O support. Untested, but should work mostly (even though some TODOs remain). Signed-off-by: Alec Ari <neotheuser(a)ymail.com> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Added: trunk/src/superio/fintek/f71889/ trunk/src/superio/fintek/f71889/Makefile.inc trunk/src/superio/fintek/f71889/chip.h trunk/src/superio/fintek/f71889/f71889.h trunk/src/superio/fintek/f71889/f71889_early_serial.c trunk/src/superio/fintek/f71889/superio.c Modified: trunk/src/superio/fintek/Kconfig trunk/src/superio/fintek/Makefile.inc Modified: trunk/src/superio/fintek/Kconfig ============================================================================== --- trunk/src/superio/fintek/Kconfig Wed Nov 3 14:24:29 2010 (r6016) +++ trunk/src/superio/fintek/Kconfig Wed Nov 3 22:46:41 2010 (r6017) @@ -4,3 +4,5 @@ bool config SUPERIO_FINTEK_F71859 bool +config SUPERIO_FINTEK_F71889 + bool Modified: trunk/src/superio/fintek/Makefile.inc ============================================================================== --- trunk/src/superio/fintek/Makefile.inc Wed Nov 3 14:24:29 2010 (r6016) +++ trunk/src/superio/fintek/Makefile.inc Wed Nov 3 22:46:41 2010 (r6017) @@ -1,3 +1,4 @@ subdirs-y += f71805f subdirs-y += f71863fg subdirs-y += f71859 +subdirs-y += f71889 Added: trunk/src/superio/fintek/f71889/Makefile.inc ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/fintek/f71889/Makefile.inc Wed Nov 3 22:46:41 2010 (r6017) @@ -0,0 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Alec Ari <neotheuser(a)ymail.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ramstage-$(CONFIG_SUPERIO_FINTEK_F71889) += superio.c + Added: trunk/src/superio/fintek/f71889/chip.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/fintek/f71889/chip.h Wed Nov 3 22:46:41 2010 (r6017) @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Alec Ari <neotheuser(a)ymail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <pc80/keyboard.h> +#include <device/device.h> +#include <uart8250.h> + +extern struct chip_operations superio_fintek_f71889_ops; + +struct superio_fintek_f71889_config { + struct uart8250 com1, com2; + struct pc_keyboard keyboard; +}; Added: trunk/src/superio/fintek/f71889/f71889.h ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/fintek/f71889/f71889.h Wed Nov 3 22:46:41 2010 (r6017) @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Alec Ari <neotheuser(a)ymail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/* Logical Device Numbers (LDN). */ +#define F71889_FDC 0x00 /* Floppy */ +#define F71889_SP1 0x01 /* UART1 */ +#define F71889_SP2 0x02 /* UART2 */ +#define F71889_PP 0x03 /* Parallel port */ +#define F71889_HWM 0x04 /* Hardware monitor */ +#define F71889_KBC 0x05 /* Keyboard and mouse */ +#define F71889_GPIO 0x06 /* General Purpose I/O (GPIO) */ +#define F71889_VID 0x07 /* VID */ +#define F71889_SPI 0x08 /* SPI */ +#define F71889_PME 0x0a /* Power Management Events (PME) and ACPI */ +#define F71889_VREF 0x0b /* Vref */ Added: trunk/src/superio/fintek/f71889/f71889_early_serial.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/fintek/f71889/f71889_early_serial.c Wed Nov 3 22:46:41 2010 (r6017) @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Alec Ari <neotheuser(a)ymail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <stdint.h> +#include <arch/romcc_io.h> +#include "f71889.h" + +static void pnp_enter_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0x87, port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + u16 port = dev >> 8; + outb(0xaa, port); +} + +static void f71889_enable_serial(device_t dev, u16 iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_enable(dev, 0); + pnp_set_iobase(dev, PNP_IDX_IO0, iobase); + pnp_set_enable(dev, 1); + pnp_exit_conf_state(dev); +} Added: trunk/src/superio/fintek/f71889/superio.c ============================================================================== --- /dev/null 00:00:00 1970 (empty, because file is newly added) +++ trunk/src/superio/fintek/f71889/superio.c Wed Nov 3 22:46:41 2010 (r6017) @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Alec Ari <neotheuser(a)ymail.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <console/console.h> +#include <stdlib.h> +#include <uart8250.h> +#include "chip.h" +#include "f71889.h" + +static void pnp_enter_conf_state(device_t dev) +{ + outb(0x87, dev->path.pnp.port); +} + +static void pnp_exit_conf_state(device_t dev) +{ + outb(0xaa, dev->path.pnp.port); +} + +static void f71889_init(device_t dev) +{ + struct superio_fintek_f71889_config *conf = dev->chip_info; + struct resource *res0, *res1; + + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + /* TODO: Might potentially need code for HWM or FDC etc. */ + case F71889_SP1: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com1); + break; + case F71889_SP2: + res0 = find_resource(dev, PNP_IDX_IO0); + init_uart8250(res0->base, &conf->com2); + break; + case F71889_KBC: + res0 = find_resource(dev, PNP_IDX_IO0); + res1 = find_resource(dev, PNP_IDX_IO1); + pc_keyboard_init(&conf->keyboard); + break; + } +} + +static void f71889_pnp_set_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_resources(dev); + pnp_exit_conf_state(dev); +} + +static void f71889_pnp_enable_resources(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_enable_resources(dev); + pnp_exit_conf_state(dev); +} + +static void f71889_pnp_enable(device_t dev) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + (dev->enabled) ? pnp_set_enable(dev, 1) : pnp_set_enable(dev, 0); + pnp_exit_conf_state(dev); +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = f71889_pnp_set_resources, + .enable_resources = f71889_pnp_enable_resources, + .enable = f71889_pnp_enable, + .init = f71889_init, +}; + +static struct pnp_info pnp_dev_info[] = { + /* TODO: Some of the 0x7f8 etc. values may not be correct. */ + { &ops, F71889_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, F71889_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F71889_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, }, + { &ops, F71889_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, }, + { &ops, F71889_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0}, }, + { &ops, F71889_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, { 0x7ff, 0 }, { 0x7ff, 0x4}, }, + { &ops, F71889_GPIO, }, + { &ops, F71889_VID, PNP_IO0 | PNP_IRQ0, { 0x07f8, 0}, }, + { &ops, F71889_SPI, }, + { &ops, F71889_PME, }, + { &ops, F71889_VREF, }, +}; + +static void enable_dev(device_t dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f71889_ops = { + CHIP_NAME("Fintek F71889 Super I/O") + .enable_dev = enable_dev +};

1 0

[PATCH] via k8t890/vt8237: mark mmconf, apic and bios resources as reserved
by Tobias Diedrich 03 Nov '10

03 Nov '10

Ranges unavailable for PCI BARs should be marked as reserved in the E820 memory map, in case the OS wants to change the BARs. This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF resource flags to do this. I also added a new resource for the mapped bios rom area just below 4GB. I'm not sure if the choice for the index parameter of new_resource() is correct though. Note that the bios rom decode is enabled in src/southbridge/via/vt8237r/vt8237r_early_smbus.c for the whole 4MB area (even though the comment says 1MB). Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- Index: coreboot-svn-m2v-splitpatches/src/southbridge/via/k8t890/k8t890_traf_ctrl.c =================================================================== --- coreboot-svn-m2v-splitpatches.orig/src/southbridge/via/k8t890/k8t890_traf_ctrl.c 2010-11-03 21:38:32.000000000 +0100 +++ coreboot-svn-m2v-splitpatches/src/southbridge/via/k8t890/k8t890_traf_ctrl.c 2010-11-03 21:45:21.000000000 +0100 @@ -58,7 +58,7 @@ res->limit = res->base + res->size - 1; res->align = 8; res->gran = 8; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_STORED | IORESOURCE_ASSIGNED; /* Add an MMCONFIG resource. */ @@ -67,7 +67,7 @@ res->align = log2(res->size); res->gran = log2(res->size); res->limit = 0xffffffff; /* 4G */ - res->flags = IORESOURCE_MEM; + res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE; } static void traf_ctrl_enable_generic(struct device *dev) Index: coreboot-svn-m2v-splitpatches/src/southbridge/via/vt8237r/vt8237r_lpc.c =================================================================== --- coreboot-svn-m2v-splitpatches.orig/src/southbridge/via/vt8237r/vt8237r_lpc.c 2010-11-03 21:50:45.000000000 +0100 +++ coreboot-svn-m2v-splitpatches/src/southbridge/via/vt8237r/vt8237r_lpc.c 2010-11-03 21:58:52.000000000 +0100 @@ -566,7 +566,15 @@ res->limit = 0xffffffffUL; res->align = 8; res->gran = 8; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Fixed flashrom resource */ + res = new_resource(dev, 4); + res->base = 0xffc00000UL; + res->size = 0x00400000UL; /* 4MB */ + res->limit = 0xffffffffUL; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_STORED | IORESOURCE_ASSIGNED; res = new_resource(dev, 1);

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coreboot November 2010