coreboot November 2010

coreboot@coreboot.org

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285 discussions

[PATCH] Remove unused code from Geode GX2
by Nils 03 Nov '10

03 Nov '10

This patch removes some unused code from gx2/raminit.c . Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> This is Abuild and boot tested. Thanks, Nils.

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[PATCH] Geode GX2 comment cleanup 2
by Nils 03 Nov '10

03 Nov '10

This patch cleans up some more comments and white space in model_gx2/cpureginit.c . Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> This is Abuild and boot tested. Thanks, Nils.

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[PATCH] Geode GX2 comment cleanup 1
by Nils 03 Nov '10

03 Nov '10

This patch cleans up some comments and white space in gx2/northbridgeinit.c and gx2/raminit.c. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> This is Abuild and boot tested. Thanks, Nils.

2 2

[PATCH 0/7] ASUS M2V support (v2)
by Tobias Diedrich 03 Nov '10

03 Nov '10

An update to this patch series: I found the gpio that was keeping the pcie slots in reset. Azalia HDAC is also working now. Remaining problems: - While my ati pcie graphics card works in the peg slot, a network card (x1 link) doesn't, but with the asus bios both work. - ACPI still giving stop 0xa5 (next debugging target) -- Tobias PGP: http://8ef7ddba.uguu.de

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F71889 Super I/O patch
by Neo The User 03 Nov '10

03 Nov '10

Hello, I looked over the F71889 Fintek datasheet, and its very similar to the F71863FG I noticed. I used sed to replace some of the names around and such. I haven't tested it, nor will I, since I have little to no experience with flashing devices, and have no back-up (can't recover) and I do have a stub (that most likely wont work) for the MSI MS785GT-E63 board, and it compiled fine and all, using the F71889 code, I mainly just changed the romstage.c file around to make it fit, while still basing the code off the other 785 boards. If anybody wants to test the F71889 patch, feel free. Also I wasn't sure to keep the same name in the other Fintek chips or not, so I changed the name to mine, and the year. I apologize if that was incorrect, and will be more than willing to keep the original GNU header. Some indentation was changed when using svn diff to generate the patch. -Alec Ari <neotheuser(a)ymail.com>

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[commit] r6016 - trunk/src/northbridge/amd/gx2
by repository service 03 Nov '10

03 Nov '10

Author: uwe Date: Wed Nov 3 14:24:29 2010 New Revision: 6016 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6016 Log: Remove some unused code from gx2/raminit.c. This is Abuild and boot tested. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/northbridge/amd/gx2/raminit.c Modified: trunk/src/northbridge/amd/gx2/raminit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/raminit.c Wed Nov 3 14:21:41 2010 (r6015) +++ trunk/src/northbridge/amd/gx2/raminit.c Wed Nov 3 14:24:29 2010 (r6016) @@ -460,12 +460,6 @@ msr.lo &= ~0xC0; msr.lo |= 0x0; /* set refresh to 4SDRAM clocks */ wrmsr(msrnum, msr); - - /* Memory Interleave: Set HOI here otherwise default is LOI */ - /* msrnum = MC_CF8F_DATA; - msr = rdmsr(msrnum); - msr.hi |= CF8F_UPPER_HOI_LOI_SET; - wrmsr(msrnum, msr); */ } static void sdram_set_spd_registers(const struct mem_controller *ctrl)

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[commit] r6015 - trunk/src/cpu/amd/model_gx2
by repository service 03 Nov '10

03 Nov '10

Author: uwe Date: Wed Nov 3 14:21:41 2010 New Revision: 6015 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6015 Log: Clean up some more comments and white space in model_gx2/cpureginit.c. This is Abuild and boot tested. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/cpu/amd/model_gx2/cpureginit.c Modified: trunk/src/cpu/amd/model_gx2/cpureginit.c ============================================================================== --- trunk/src/cpu/amd/model_gx2/cpureginit.c Wed Nov 3 14:19:50 2010 (r6014) +++ trunk/src/cpu/amd/model_gx2/cpureginit.c Wed Nov 3 14:21:41 2010 (r6015) @@ -1,134 +1,120 @@ -/* ***************************************************************************/ -/* * cpuRegInit*/ -/* ***************************************************************************/ +/* cpuRegInit */ void cpuRegInit (void) { int msrnum; msr_t msr; - /* Turn on BTM for early debug based on setup. */ - /*if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) {*/ - /* - * The following is only for diagnostics mode; do not use for OLPC - */ + /* Turn on BTM for early debug based on setup. */ + /* if (getnvram( TOKEN_BTM_DIAG_MODE) & 3) { */ + /* The following is only for diagnostics mode; do not use for OLPC */ if (0) { - /* Set Diagnostic Mode */ + /* Set Diagnostic Mode */ msrnum = CPU_GLD_MSR_DIAG; msr.hi = 0; msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET; wrmsr(msrnum, msr); - /* Set up GLCP to grab BTM data.*/ - msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR*/ + /* Set up GLCP to grab BTM data. */ + msrnum = 0x04C00000C; /* GLCP_DBGOUT MSR */ msr.hi = 0x0; - msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out,*/ - wrmsr(msrnum, msr); /* exchange it to anything else to prevent this*/ + msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO toshift out, */ + wrmsr(msrnum, msr); /* exchange it to anything else to prevent this */ - /* ;Turn off debug clock*/ + /* Turn off debug clock */ msrnum = 0x04C000016; /* DBG_CLK_CTL*/ msr.lo = 0x00; /* No clock*/ msr.hi = 0x00; wrmsr(msrnum, msr); - /* ;Set debug clock to CPU*/ - msrnum = 0x04C000016; /* DBG_CLK_CTL*/ - msr.lo = 0x01; /* CPU CLOCK*/ + /* Set debug clock to CPU */ + msrnum = 0x04C000016; /* DBG_CLK_CTL */ + msr.lo = 0x01; /* CPU CLOCK */ msr.hi = 0x00; wrmsr(msrnum, msr); - /* ;Set fifo ctl to BTM bits wide*/ - msrnum = 0x04C00005E; /* FIFO_CTL*/ - msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit)*/ - wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0)*/ - /* Bit [19] sets it up in slow data mode.*/ - - /* ;enable fifo loading - BTM sizing will constrain*/ - /* ; only valid BTM packets to load - this action should always be on*/ - - msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo*/ - msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger*/ - msr.hi = 0x000000000; /* */ - wrmsr(msrnum, msr); - - /* ;start storing diag data in the fifo*/ - msrnum = 0x04C00005F; /* DIAG CTL*/ - msr.lo = 0x080000000; /* enable actions*/ + /* Set fifo ctl to BTM bits wide */ + msrnum = 0x04C00005E; /* FIFO_CTL */ + msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit) */ + wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0) */ + /* Bit [19] sets it up in slow data mode. */ + + /* enable fifo loading - BTM sizing will constrain */ + /* only valid BTM packets to load - this action should always be on */ + msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo */ + msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger */ msr.hi = 0x000000000; wrmsr(msrnum, msr); - /* Set up delay on data lines, so that the hold time*/ - /* is 1 ns.*/ - msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS*/ + /* start storing diag data in the fifo */ + msrnum = 0x04C00005F; /* DIAG CTL */ + msr.lo = 0x080000000; /* enable actions */ + msr.hi = 0x000000000; + wrmsr(msrnum, msr); + + /* Set up delay on data lines, so that the hold time */ + /* is 1 ns. */ + msrnum = 0x04C00000D ; /* GLCP IO DELAY CONTROLS */ msr.lo = 0x082b5ad68; - msr.hi = 0x080ad6b57; /* RGB delay = 0x07*/ + msr.hi = 0x080ad6b57; /* RGB delay = 0x07 */ wrmsr(msrnum, msr); - /* Set up DF to output diag information on DF pins.*/ + /* Set up DF to output diag information on DF pins. */ msrnum = DF_GLD_MSR_MASTER_CONF; msr.lo = 0x0220; msr.hi = 0; wrmsr(msrnum, msr); - msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR*/ + msrnum = 0x04C00000C ; /* GLCP_DBGOUT MSR */ msr.hi = 0x0; - msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out,*/ + msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out, */ wrmsr(msrnum, msr); /* end of code for BTM */ } - /* Enable Suspend on Halt*/ + /* Enable Suspend on Halt */ msrnum = CPU_XC_CONFIG; msr = rdmsr(msrnum); msr.lo |= XC_CONFIG_SUSP_ON_HLT; wrmsr(msrnum, msr); - /* ENable SUSP and allow TSC to run in Suspend */ - /* to keep speed detection happy*/ + /* ENable SUSP and allow TSC to run in Suspend */ + /* to keep speed detection happy */ msrnum = CPU_BC_CONF_0; msr = rdmsr(msrnum); msr.lo |= TSC_SUSP_SET | SUSP_EN_SET; wrmsr(msrnum, msr); - /* Setup throttling to proper mode if it is ever enabled.*/ + /* Setup throttling to proper mode if it is ever enabled. */ msrnum = 0x04C00001E; msr.hi = 0x000000000; msr.lo = 0x00000603C; wrmsr(msrnum, msr); - -/* Only do this if we are building for 5535*/ -/* */ -/* FooGlue Setup*/ -/* */ +/* Only do this if we are building for 5535 */ +/* FooGlue Setup */ #if 1 - /* Enable CIS mode B in FooGlue*/ + /* Enable CIS mode B in FooGlue */ msrnum = MSR_FG + 0x10; msr = rdmsr(msrnum); msr.lo &= ~3; - msr.lo |= 2; /* ModeB*/ + msr.lo |= 2; /* ModeB */ wrmsr(msrnum, msr); #endif -/* */ -/* Disable DOT PLL. Graphics init will enable it if needed.*/ -/* */ +/* Disable DOT PLL. Graphics init will enable it if needed. */ msrnum = GLCP_DOTPLL; msr = rdmsr(msrnum); msr.lo |= DOTPPL_LOWER_PD_SET; wrmsr(msrnum, msr); -/* */ -/* Enable RSDC*/ -/* */ +/* Enable RSDC */ msrnum = 0x1301 ; msr = rdmsr(msrnum); msr.lo |= 0x08; wrmsr(msrnum, msr); -/* */ -/* Enable BTB*/ -/* */ - /* I hate to put this check here but it doesn't really work in cpubug.asm*/ +/* Enable BTB */ + /* I hate to put this check here but it doesn't really work in cpubug.asm */ msrnum = MSR_GLCP+0x17; msr = rdmsr(msrnum); if (msr.lo >= CPU_REV_2_1){ @@ -138,10 +124,8 @@ wrmsr(msrnum, msr); } -/* */ -/* FPU impercise exceptions bit*/ -/* */ - /*if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) {*/ +/* FPU impercise exceptions bit */ + /* if (getnvram( TOKEN_FPU_IE_ENABLE) != TVALUE_DISABLE) { */ { msrnum = CPU_FPU_MSR_MODE; msr = rdmsr(msrnum); @@ -150,16 +134,13 @@ } #if 0 - /* */ - /* Cache Overides*/ - /* */ + /* Cache Overides */ /* This code disables the data cache. Don't execute this * unless you're testing something. */ - /* Allow NVRam to override DM Setup*/ - /*if (getnvram( TOKEN_CACHE_DM_MODE) != 1) {*/ + /* Allow NVRam to override DM Setup */ + /* if (getnvram( TOKEN_CACHE_DM_MODE) != 1) { */ { - msrnum = CPU_DM_CONFIG0; msr = rdmsr(msrnum); msr.lo |= DM_CONFIG0_LOWER_DCDIS_SET; @@ -168,8 +149,8 @@ /* This code disables the instruction cache. Don't execute * this unless you're testing something. */ - /* Allow NVRam to override IM Setup*/ - /*if (getnvram( TOKEN_CACHE_IM_MODE) ==1) {*/ + /* Allow NVRam to override IM Setup */ + /* if (getnvram( TOKEN_CACHE_IM_MODE) ==1) { */ { msrnum = CPU_IM_CONFIG; msr = rdmsr(msrnum);

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[commit] r6014 - trunk/src/northbridge/amd/gx2
by repository service 03 Nov '10

03 Nov '10

Author: uwe Date: Wed Nov 3 14:19:50 2010 New Revision: 6014 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6014 Log: Clean up some comments and white space in gx2/northbridgeinit.c and gx2/raminit.c. This is Abuild and boot tested. Signed-off-by: Nils Jacobs <njacobs8(a)hetnet.nl> Acked-by: Uwe Hermann <uwe(a)hermann-uwe.de> Modified: trunk/src/northbridge/amd/gx2/northbridgeinit.c trunk/src/northbridge/amd/gx2/raminit.c Modified: trunk/src/northbridge/amd/gx2/northbridgeinit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/northbridgeinit.c Tue Nov 2 22:24:29 2010 (r6013) +++ trunk/src/northbridge/amd/gx2/northbridgeinit.c Wed Nov 3 14:19:50 2010 (r6014) @@ -22,26 +22,25 @@ }; struct gliutable gliu0table[] = { - {.desc_name=MSR_GLIU0_BASE1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC*/ - {.desc_name=MSR_GLIU0_BASE2, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc*/ - {.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo*/ - {.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/ - {.desc_name=MSR_GLIU0_DMM, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/ - {.desc_name=MSR_GLIU0_SMM, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly.*/ + {.desc_name=MSR_GLIU0_BASE1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ + {.desc_name=MSR_GLIU0_BASE2, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */ + {.desc_name=MSR_GLIU0_SHADOW, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */ + {.desc_name=MSR_GLIU0_SYSMEM, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=MSR_GLIU0_DMM, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=MSR_GLIU0_SMM, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */ {.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU}, {.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0}, }; - struct gliutable gliu1table[] = { - {.desc_name=MSR_GLIU1_BASE1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC*/ - {.desc_name=MSR_GLIU1_BASE2,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0}, /* 80000-9ffff to Mc*/ - {.desc_name=MSR_GLIU1_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode)*/ - {.desc_name=MSR_GLIU1_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly.*/ - {.desc_name=MSR_GLIU1_DMM,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly.*/ - {.desc_name=MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly.*/ + {.desc_name=MSR_GLIU1_BASE1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */ + {.desc_name=MSR_GLIU1_BASE2,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0}, /* 80000-9ffff to Mc */ + {.desc_name=MSR_GLIU1_SHADOW,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */ + {.desc_name=MSR_GLIU1_SYSMEM,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=MSR_GLIU1_DMM,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ + {.desc_name=MSR_GLIU1_SMM,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */ {.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0}, - {.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0*/ + {.desc_name=MSR_GLIU1_FPU_TRAP,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */ {.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0}, }; @@ -54,18 +53,18 @@ struct msrinit ClockGatingDefault [] = { {GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}}, - /* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142*/ + /* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142 */ {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, {GLIU1_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}}, - {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163*/ + {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163 */ {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}}, {DF_GLD_MSR_PM, {.hi=0x00,.lo=0x0155}}, {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, {GLPCI_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, - {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* Always on*/ + {FG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* Always on */ {0xffffffff, {0xffffffff, 0xffffffff}}, }; - /* All On*/ + /* All On */ struct msrinit ClockGatingAllOn[] = { {GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, {MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0FFFFFFFF}}, @@ -79,7 +78,7 @@ {0xffffffff, {0xffffffff, 0xffffffff}}, }; - /* Performance*/ + /* Performance */ struct msrinit ClockGatingPerformance[] = { {VG_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}}, /* lotus #77.163*/ {GP_GLD_MSR_PM, {.hi=0x00,.lo=0x0001}}, @@ -87,19 +86,18 @@ {GLCP_GLD_MSR_PM, {.hi=0x00,.lo=0x0015}}, {0xffffffff, {0xffffffff, 0xffffffff}}, }; -/* */ -/* SET GeodeLink PRIORITY*/ -/* */ + + /* SET GeodeLink PRIORITY */ struct msrinit GeodeLinkPriorityTable [] = { - {CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, /* CPU Priority.*/ - {DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority.*/ - {VG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0720}}, /* VG Primary and Secondary Priority.*/ - {GP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0010}}, /* Graphics Priority.*/ - {GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0027}}, /* GLPCI Priority + PID*/ - {GLCP_GLD_MSR_CONF, {.hi=0x00,.lo=0x0001}}, /* GLCP Priority + PID*/ - {VIP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0622}}, /* VIP PID*/ - {AES_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0013}}, /* AES PID*/ - {0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END*/ + {CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, /* CPU Priority. */ + {DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority. */ + {VG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0720}}, /* VG Primary and Secondary Priority. */ + {GP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0010}}, /* Graphics Priority. */ + {GLPCI_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0027}}, /* GLPCI Priority + PID */ + {GLCP_GLD_MSR_CONF, {.hi=0x00,.lo=0x0001}}, /* GLCP Priority + PID */ + {VIP_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0622}}, /* VIP PID */ + {AES_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0013}}, /* AES PID */ + {0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END */ }; /* do we have dmi or not? assume NO per AMD */ @@ -111,7 +109,7 @@ msr.lo = gl->lo; msr.hi = gl->hi; - wrmsr(gl->desc_name, msr); // MSR - see table above + wrmsr(gl->desc_name, msr); /* MSR - see table above */ printk(BIOS_DEBUG, "%s: write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); /* they do this, so we do this */ msr = rdmsr(gl->desc_name); @@ -131,10 +129,9 @@ } /* NOTE: transcribed from assembly code. There is the usual redundant assembly nonsense in here. - * CLEAN ME UP - */ -/* yes, this duplicates later code, but it seems that is how they want it done. - */ + * CLEAN ME UP + */ +/* yes, this duplicates later code, but it seems that is how they want it done. */ static void SysmemInit(struct gliutable *gl) { @@ -161,12 +158,12 @@ sizebytes &= 0xfff00000; sizebytes |= 0x100; msr.lo = sizebytes; - wrmsr(gl->desc_name, msr); // MSR - see table above + wrmsr(gl->desc_name, msr); /* MSR - see table above */ msr = rdmsr(gl->desc_name); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); - } + static void DMMGL0Init(struct gliutable *gl) { msr_t msr; @@ -189,11 +186,11 @@ msr.lo = DMM_OFFSET << 8; msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff; - wrmsr(gl->desc_name, msr); // MSR - See table above + wrmsr(gl->desc_name, msr); /* MSR - See table above */ msr = rdmsr(gl->desc_name); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); - } + static void DMMGL1Init(struct gliutable *gl) { msr_t msr; @@ -212,10 +209,11 @@ printk(BIOS_ERR, "%s: warning, using DMM_SIZE even though AMD used SMM_SIZE\n", __func__); msr.lo |= ((~(DMM_SIZE*1024)+1)>>12)&0xfffff; - wrmsr(gl->desc_name, msr); // MSR - See table above + wrmsr(gl->desc_name, msr); /* MSR - See table above */ msr = rdmsr(gl->desc_name); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } + static void SMMGL0Init(struct gliutable *gl) { msr_t msr; @@ -239,10 +237,11 @@ msr.lo = SMM_OFFSET << 8; msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff; - wrmsr(gl->desc_name, msr); // MSR - See table above + wrmsr(gl->desc_name, msr); /* MSR - See table above */ msr = rdmsr(gl->desc_name); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } + static void SMMGL1Init(struct gliutable *gl) { msr_t msr; @@ -255,7 +254,7 @@ msr.lo = SMM_OFFSET << 8; msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff; - wrmsr(gl->desc_name, msr); // MSR - See table above + wrmsr(gl->desc_name, msr); /* MSR - See table above */ msr = rdmsr(gl->desc_name); printk(BIOS_DEBUG, "%s: AFTER write msr 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo); } @@ -268,69 +267,58 @@ default: /* For Unknown types: Write then read MSR */ writeglmsr(gl); - case SC_SHADOW: /* Check for a Shadow entry*/ + case SC_SHADOW: /* Check for a Shadow entry */ ShadowInit(gl); break; - case R_SYSMEM: /* check for a SYSMEM entry*/ + case R_SYSMEM: /* check for a SYSMEM entry */ SysmemInit(gl); break; - case BMO_DMM: /* check for a DMM entry*/ + case BMO_DMM: /* check for a DMM entry */ DMMGL0Init(gl); break; - case BM_DMM : /* check for a DMM entry*/ + case BM_DMM : /* check for a DMM entry */ DMMGL1Init(gl); break; - case BMO_SMM : /* check for a SMM entry*/ + case BMO_SMM : /* check for a SMM entry */ SMMGL0Init(gl); break; - case BM_SMM : /* check for a SMM entry*/ + case BM_SMM : /* check for a SMM entry */ SMMGL1Init(gl); break; } gl++; } - } - /* ***************************************************************************/ - /* **/ - /* * GLPCIInit*/ - /* **/ - /* * Set up GLPCI settings for reads/write into memory*/ - /* * R0: 0-640KB,*/ - /* * R1: 1MB - Top of System Memory*/ - /* * R2: SMM Memory*/ - /* * R3: Framebuffer? - not set up yet*/ - /* * R4: ??*/ - /* **/ - /* * Entry:*/ - /* * Exit:*/ - /* * Modified:*/ - /* **/ - /* ***************************************************************************/ + +/* + * Set up GLPCI settings for reads/write into memory. + * + * R0: 0-640KB, + * R1: 1MB - Top of System Memory + * R2: SMM Memory + * R3: Framebuffer? - not set up yet + * R4: ?? + */ static void GLPCIInit(void){ struct gliutable *gl = 0; int i; msr_t msr; int msrnum; - /* */ - /* R0 - GLPCI settings for Conventional Memory space.*/ - /* */ - msr.hi = (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT /* 640*/; - msr.lo = 0 /* 0*/; + /* R0 - GLPCI settings for Conventional Memory space. */ + msr.hi = (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; /* 640 */ + msr.lo = 0; /* 0 */ msr.lo |= GLPCI_RC_LOWER_EN_SET+ GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET; msrnum = GLPCI_RC0; wrmsr(msrnum, msr); - /* */ - /* R1 - GLPCI settings for SysMem space.*/ - /* */ - /* Get systop from GLIU0 SYSTOP Descriptor*/ + /* R1 - GLPCI settings for SysMem space. */ + /* Get systop from GLIU0 SYSTOP Descriptor */ for(i = 0; gliu0table[i].desc_name != GL_END; i++) { if (gliu0table[i].desc_type == R_SYSMEM) { gl = &gliu0table[i]; @@ -345,8 +333,8 @@ * translates to a base of 0x00100000 and top of 0xffbf0000 * base of 1M and top of around 256M */ - /* we have to create a page-aligned (4KB page) address for base and top */ - /* So we need a high page aligned addresss (pah) and low page aligned address (pal) + /* we have to create a page-aligned (4KB page) address for base and top + * So we need a high page aligned addresss (pah) and low page aligned address (pal) * pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12 */ printk(BIOS_DEBUG, "GLPCI r1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi); @@ -363,9 +351,7 @@ wrmsr(msrnum, msr); } - /* */ - /* R2 - GLPCI settings for SMM space.*/ - /* */ + /* R2 - GLPCI settings for SMM space. */ msr.hi = ((SMM_OFFSET+(SMM_SIZE*1024-1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT; msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET; @@ -373,9 +359,9 @@ wrmsr(msrnum, msr); /* this is done elsewhere already, but it does no harm to do it more than once */ - /* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility.*/ - msr.lo = 0x021212121 /* cache disabled and write serialized*/; - msr.hi = 0x021212121 /* cache disabled and write serialized*/; + /* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility. */ + msr.lo = 0x021212121; /* cache disabled and write serialized */ + msr.hi = 0x021212121; /* cache disabled and write serialized */ msrnum = CPU_RCONF_A0_BF; wrmsr(msrnum, msr); @@ -386,7 +372,7 @@ msrnum = CPU_RCONF_E0_FF; wrmsr(msrnum, msr); - /* Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup.*/ + /* Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup. */ msrnum = GLPCI_A0_BF; msr.hi = 0x35353535; msr.lo = 0x35353535; @@ -402,29 +388,26 @@ msr.lo = 0x35353535; wrmsr(msrnum, msr); - /* Set WSREQ*/ + /* Set WSREQ */ msrnum = CPU_DM_CONFIG0; msr = rdmsr(msrnum); msr.hi &= ~ (7 << DM_CONFIG0_UPPER_WSREQ_SHIFT); - msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT ; /* reduce to 1 for safe mode.*/ + msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT ; /* reduce to 1 for safe mode. */ wrmsr(msrnum, msr); /* we are ignoring the 5530 case for now, and perhaps forever. */ - /* */ - /* 5535 NB Init*/ - /* */ + /* 5535 NB Init */ msrnum = GLPCI_ARB; msr = rdmsr(msrnum); msr.hi |= GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET; msr.lo |= GLPCI_ARB_LOWER_IIE_SET; wrmsr(msrnum, msr); - msrnum = GLPCI_CTRL; msr = rdmsr(msrnum); - msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; /* (Out will be disabled in CPUBUG649 for < 2.0 parts .)*/ + msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; /* (Out will be disabled in CPUBUG649 for < 2.0 parts .) */ msr.lo |= GLPCI_CTRL_LOWER_LDE_SET; msr.lo &= ~ (0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT); @@ -449,37 +432,23 @@ msr.hi |= 0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT; wrmsr(msrnum, msr); - - /* Set GLPCI Latency Timer.*/ + /* Set GLPCI Latency Timer. */ msrnum = GLPCI_CTRL; msr = rdmsr(msrnum); - msr.hi |= 0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; /* Change once 1.x is gone.*/ + msr.hi |= 0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; /* Change once 1.x is gone. */ wrmsr(msrnum, msr); - /* GLPCI_SPARE*/ + /* GLPCI_SPARE */ msrnum = GLPCI_SPARE; msr = rdmsr(msrnum); msr.lo &= ~ 0x7; msr.lo |= GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET | GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET | GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET; wrmsr(msrnum, msr); - } - - - /* ***************************************************************************/ - /* **/ - /* * ClockGatingInit*/ - /* **/ - /* * Enable Clock Gating.*/ - /* **/ - /* * Entry:*/ - /* * Exit:*/ - /* * Modified:*/ - /* **/ - /* ***************************************************************************/ -static void -ClockGatingInit (void){ +/* Enable Clock Gating. */ +static void ClockGatingInit (void) +{ msr_t msr; struct msrinit *gating = ClockGatingDefault; int i; @@ -511,14 +480,13 @@ msr.lo |= gating->msr.lo; printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to 0x%08x:0x%08x\n", __func__, gating->msrnum, msr.hi, msr.lo); - wrmsr(gating->msrnum, msr); // MSR - See the table above + wrmsr(gating->msrnum, msr); /* MSR - See the table above */ gating +=1; } - } -static void -GeodeLinkPriority(void){ +static void GeodeLinkPriority(void) +{ msr_t msr; struct msrinit *prio = GeodeLinkPriorityTable; int i; @@ -531,17 +499,16 @@ msr.lo |= prio->msr.lo; printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to 0x%08x:0x%08x\n", __func__, prio->msrnum, msr.hi, msr.lo); - wrmsr(prio->msrnum, msr); // MSR - See the table above + wrmsr(prio->msrnum, msr); /* MSR - See the table above */ prio +=1; } } - - /* - * Get the GLIU0 shadow register settings - * If the setShadow function is used then all shadow descriptors - * will stay sync'ed. + * Get the GLIU0 shadow register settings. + * + * If the setShadow function is used then all shadow descriptors + * will stay sync'ed. */ static uint64_t getShadow(void) { @@ -550,83 +517,81 @@ return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo; } - /* - * Set the cache RConf registers for the memory hole. - * Keeps all cache shadow descriptors sync'ed. - * This is part of the PCI lockup solution - * Entry: EDX:EAX is the shadow settings + * Set the cache RConf registers for the memory hole. + * + * Keeps all cache shadow descriptors sync'ed. + * This is part of the PCI lockup solution. + * + * Entry: EDX:EAX is the shadow settings. */ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo) { - // ok this is whacky bit translation time. + /* ok this is whacky bit translation time. */ int bit; uint8_t shadowByte; msr_t msr; shadowByte = (uint8_t) (shadowLo >> 16); - // load up D000 settings in edx. + /* load up D000 settings in edx. */ for (bit = 8; (bit > 4); bit--) { msr.hi <<= 8; - msr.hi |= 1; // cache disable PCI/Shadow memory + msr.hi |= 1; /* cache disable PCI/Shadow memory */ if (shadowByte && (1 << bit)) - msr.hi |= 0x20; // write serialize PCI memory + msr.hi |= 0x20; /* write serialize PCI memory */ } - // load up C000 settings in eax. + /* load up C000 settings in eax. */ for ( ; bit; bit--) { msr.lo <<= 8; - msr.lo |= 1; // cache disable PCI/Shadow memory + msr.lo |= 1; /* cache disable PCI/Shadow memory */ if (shadowByte && (1 << bit)) - msr.lo |= 0x20; // write serialize PCI memory + msr.lo |= 0x20; /* write serialize PCI memory */ } wrmsr(CPU_RCONF_C0_DF, msr); shadowByte = (uint8_t) (shadowLo >> 24); - // load up F000 settings in edx. + /* load up F000 settings in edx. */ for (bit = 8; (bit > 4); bit--) { msr.hi <<= 8; - msr.hi |= 1; // cache disable PCI/Shadow memory + msr.hi |= 1; /* cache disable PCI/Shadow memory */ if (shadowByte && (1 << bit)) - msr.hi |= 0x20; // write serialize PCI memory + msr.hi |= 0x20; /* write serialize PCI memory */ } - // load up E000 settings in eax. + /* load up E000 settings in eax. */ for ( ; bit; bit--) { msr.lo <<= 8; - msr.lo |= 1; // cache disable PCI/Shadow memory + msr.lo |= 1; /* cache disable PCI/Shadow memory */ if (shadowByte && (1 << bit)) - msr.lo |= 0x20; // write serialize PCI memory + msr.lo |= 0x20; /* write serialize PCI memory */ } wrmsr(CPU_RCONF_E0_FF, msr); } - /* - * Set the GLPCI registers for the memory hole. - * Keeps all cache shadow descriptors sync'ed. - * Entry: EDX:EAX is the shadow settings + * Set the GLPCI registers for the memory hole. + * Keeps all cache shadow descriptors sync'ed. + * Entry: EDX:EAX is the shadow settings */ static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo) { msr_t msr; -// Set the Enable Register. - + /* Set the Enable Register. */ msr = rdmsr(GLPCI_REN); msr.lo &= 0xFFFF00FF; msr.lo |= ( (shadowLo & 0xFFFF0000) >> 8); wrmsr(GLPCI_REN, msr); } - /* - * Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW. - * Keeps all shadow descriptors sync'ed. - * Entry: EDX:EAX is the shadow settings + * Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW. + * Keeps all shadow descriptors sync'ed. + * Entry: EDX:EAX is the shadow settings */ static void setShadow(uint64_t shadowSettings) { @@ -647,50 +612,34 @@ msr = rdmsr(pTable->desc_name); msr.lo = (uint32_t) shadowSettings; - msr.hi &= 0xFFFF0000; // maintain PDID in upper EDX + msr.hi &= 0xFFFF0000; /* maintain PDID in upper EDX */ msr.hi |= ((uint32_t) (shadowSettings >> 32)) & 0x0000FFFF; - wrmsr(pTable->desc_name, msr); // MSR - See the table above + wrmsr(pTable->desc_name, msr); /* MSR - See the table above */ } } } } -/************************************************************************** - * - * shadowRom - * - * Set up a stack for ease of further testing - * - * Entry: - * Exit: - * Destroys: - * - **************************************************************************/ -static void -shadowRom(void) +/* Set up a stack for ease of further testing. */ +static void shadowRom(void) { uint64_t shadowSettings = getShadow(); - shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; // Disable read & writes - shadowSettings |= (uint64_t) 0x0000FFFFFFFF0000ULL; // Enable reads for C0000-FFFFF + shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; /* Disable read & writes */ + shadowSettings |= (uint64_t) 0x0000FFFFFFFF0000ULL; /* Enable reads for C0000-FFFFF */ setShadow(shadowSettings); } - - -/*************************************************************************** - * - * RCONFInit - * Set up RCONF_DEFAULT and any other RCONF registers needed - * - * DEVRC_RCONF_DEFAULT: - * ROMRC(63:56) = 04h ; write protect ROMBASE - * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area - * DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst. - * SYSTOP(27:8) = top of system memory - * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough +/* + * Set up RCONF_DEFAULT and any other RCONF registers needed. * - ***************************************************************************/ + * DEVRC_RCONF_DEFAULT: + * ROMRC(63:56) = 04h ; write protect ROMBASE + * ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of rom chipselect area + * DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst. + * SYSTOP(27:8) = top of system memory + * SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough + */ #define SYSMEM_RCONF_WRITETHROUGH 8 #define DEVRC_RCONF_DEFAULT 0x21 #define ROMBASE_RCONF_DEFAULT 0xFFFC0000 @@ -712,11 +661,11 @@ } } if (gl == 0) { - post_code(0xCE); /* POST_RCONFInitError */ + post_code(0xCE); /* POST_RCONFInitError */ while (1); } -// sysdescfound: +/* sysdescfound: */ /* found the descriptor... get its contents */ msr = rdmsr(gl->desc_name); @@ -725,26 +674,26 @@ */ msr.lo = (msr.lo & 0xFFFFFF00) | (msr.hi & 0xFF); msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF; - msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT; // 8 + msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT; /* 8 */ - // Set Default SYSMEM region properties - msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH; // 8 (or ~8) + /* Set Default SYSMEM region properties */ + msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH; /* 8 (or ~8) */ - // Set PCI space cache properties - msr.hi = (DEVRC_RCONF_DEFAULT >> 4); // only need the bottom bits and lets clean the rest of edx + /* Set PCI space cache properties */ + msr.hi = (DEVRC_RCONF_DEFAULT >> 4); /* only need the bottom bits and lets clean the rest of edx */ msr.lo |= (DEVRC_RCONF_DEFAULT << 28); - // Set the ROMBASE. This is usually FFFC0000h + /* Set the ROMBASE. This is usually FFFC0000h */ msr.hi |= (ROMBASE_RCONF_DEFAULT >> 12) << RCONF_DEFAULT_UPPER_ROMBASE_SHIFT; - // Set ROMBASE cache properties. + /* Set ROMBASE cache properties. */ msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24)); - // now program RCONF_DEFAULT + /* now program RCONF_DEFAULT */ wrmsr(CPU_RCONF_DEFAULT, msr); - // RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties. - // Set to match system memory cache properties. + /* RCONF_BYPASS: Cache tablewalk properties and SMM/DMM header access properties. */ + /* Set to match system memory cache properties. */ msr = rdmsr(CPU_RCONF_DEFAULT); SysMemCacheProp = (uint8_t) (msr.lo & 0xFF); msr = rdmsr(CPU_RCONF_BYPASS); @@ -752,21 +701,8 @@ wrmsr(CPU_RCONF_BYPASS, msr); } - -/* ***************************************************************************/ -/* **/ -/* * northBridgeInit*/ -/* **/ -/* * Core Logic initialization: Host bridge*/ -/* **/ -/* * Entry:*/ -/* * Exit:*/ -/* * Modified:*/ -/* **/ -/* ***************************************************************************/ - -void -northbridgeinit(void) +/* Core Logic initialization: Host bridge. */ +void northbridgeinit(void) { msr_t msr; int i; @@ -779,22 +715,23 @@ shadowRom(); - // GeodeROM ensures that the BIOS waits the required 1 second before - // allowing anything to access PCI + /* GeodeROM ensures that the BIOS waits the required 1 second before */ + /* allowing anything to access PCI */ // PCIDelay(); RCONFInit(); - // The cacheInit function in GeodeROM tests cache and, among other things, - // makes sure all INVD instructions are treated as WBINVD. We do this - // because we've found some programs which require this behavior. - // That subset of cacheInit() is implemented here: + /* The cacheInit function in GeodeROM tests cache and, among other things, + * makes sure all INVD instructions are treated as WBINVD. We do this + * because we've found some programs which require this behavior. + * That subset of cacheInit() is implemented here: + */ msr = rdmsr(CPU_DM_CONFIG0); msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET; wrmsr(CPU_DM_CONFIG0, msr); - /* Now that the descriptor to memory is set up.*/ - /* The memory controller needs one read to synch its lines before it can be used.*/ + /* Now that the descriptor to memory is set up. */ + /* The memory controller needs one read to synch its lines before it can be used. */ i = *(int *) 0; GLPCIInit(); Modified: trunk/src/northbridge/amd/gx2/raminit.c ============================================================================== --- trunk/src/northbridge/amd/gx2/raminit.c Tue Nov 2 22:24:29 2010 (r6013) +++ trunk/src/northbridge/amd/gx2/raminit.c Wed Nov 3 14:19:50 2010 (r6014) @@ -80,12 +80,13 @@ dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT; banner("SPDNUMROWS"); - /*; Field: DIMM size - *; EEPROM byte usage: (3) Number of Row Addresses - *; (4) Number of Column Addresses - *; (5) Number of DIMM Banks - *; (31) Module Bank Density - *; Size = Module Density * Module Banks + /* Field: DIMM size + * EEPROM byte usage: + * (3) Number of Row Addresses + * (4) Number of Column Addresses + * (5) Number of DIMM Banks + * (31) Module Bank Density + * Size = Module Density * Module Banks */ if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0) || (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) { @@ -100,7 +101,7 @@ dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */ dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */ - /* Module Density * Module Banks */ + /* Module Density * Module Banks */ dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */ banner("BEFORT CTZ"); dimm_size = __builtin_ctz(dimm_size); @@ -113,27 +114,32 @@ dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT; banner("PAGESIZE"); -/*; Field: PAGE size -*; EEPROM byte usage: (4) Number of Column Addresses -*; PageSize = 2^# Column Addresses * Data width in bytes (should be 8bytes for a normal DIMM) -* -*; But this really works by magic. -*; If ma[11:0] is the memory address pins, and pa[13:0] is the physical column address -*; that MC generates, here is how the MC assigns the pa onto the ma pins: -* -*;ma 11 10 09 08 07 06 05 04 03 02 01 00 -*;-------------------------------------------------------------------------------------------------------------------------------------- -*;pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size) -*;pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size) -*;pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size) -*;pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size) -*;pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size) -*; *AP=autoprecharge bit -* -*; Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes), -*; so lower 3 address bits are dont_cares.So from the table above, -*; it's easier to see what the old code is doing: if for example,#col_addr_bits=7(06h), -*; it adds 3 to get 10, then does 2^10=1K. Get it?*/ +/* + * Field: PAGE size + * EEPROM byte usage: (4) Number of Column Addresses + * PageSize = 2^# Column Addresses * Data width in bytes + * (should be 8bytes for a normal DIMM) + * + * But this really works by magic. + * If ma[11:0] is the memory address pins, and pa[13:0] is the physical column + * address that MC generates, here is how the MC assigns the pa onto the + * ma pins: + * + * ma 11 10 09 08 07 06 05 04 03 02 01 00 + * --------------------------------------- + * pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size) + * pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size) + * pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size) + * pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size) + * pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size) + * + * (AP = autoprecharge bit) + * + * Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes), + * so lower 3 address bits are dont_cares. So from the table above, + * it's easier to see what the old code is doing: if for example, + * #col_addr_bits=7(06h), it adds 3 to get 10, then does 2^10=1K. + */ spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF]; banner("MAXCOLADDR"); @@ -269,26 +275,25 @@ static void setCAS(void) { -/*;***************************************************************************** -;* -;* setCAS -;* EEPROM byte usage: (18) SDRAM device attributes - CAS latency -;* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5 -;* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1 -;* -;* The CAS setting is based on the information provided in each DIMMs SPD. -;* The speed at which a DIMM can run is described relative to the slowest -;* CAS the DIMM supports. Each speed for the relative CAS settings is -;* checked that it is within the GeodeLink speed. If it isn't within the GeodeLink -;* speed, the CAS setting is removed from the list of good settings for -;* the DIMM. This is done for both DIMMs and the lists are compared to -;* find the lowest common CAS latency setting. If there are no CAS settings -;* in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt. -;* -;* Entry: -;* Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information. -;* Destroys: We really use everything ! -;*****************************************************************************/ +/* + * setCAS + * EEPROM byte usage: (18) SDRAM device attributes - CAS latency + * EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5 + * EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1 + * + * The CAS setting is based on the information provided in each DIMMs SPD. + * The speed at which a DIMM can run is described relative to the slowest + * CAS the DIMM supports. Each speed for the relative CAS settings is + * checked that it is within the GeodeLink speed. If it isn't within the GeodeLink + * speed, the CAS setting is removed from the list of good settings for + * the DIMM. This is done for both DIMMs and the lists are compared to + * find the lowest common CAS latency setting. If there are no CAS settings + * in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt. + * + * Entry: + * Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information. + * Destroys: We really use everything ! + */ uint16_t glspeed; uint8_t spd_byte, casmap0, casmap1; msr_t msr; @@ -298,7 +303,7 @@ casmap0 = getcasmap(DIMM0, glspeed); casmap1 = getcasmap(DIMM1, glspeed); - /********************* CAS_LAT MAP COMPARE ***************************/ + /* CAS_LAT MAP COMPARE */ if (casmap0 == 0) { spd_byte = CASDDR[__builtin_ctz(casmap1)]; } else if (casmap1 == 0) { @@ -468,7 +473,7 @@ uint8_t spd_byte; banner("sdram_set_spd_register"); - post_code(POST_MEM_SETUP); // post_70h + post_code(POST_MEM_SETUP); /* post_70h */ spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES); banner("Check DIMM 0"); @@ -486,23 +491,23 @@ hcf(); } - post_code(POST_MEM_SETUP2); // post_72h + post_code(POST_MEM_SETUP2); /* post_72h */ banner("Check DDR MAX"); /* Check that the memory is not overclocked. */ checkDDRMax(); /* Size the DIMMS */ - post_code(POST_MEM_SETUP3); // post_73h + post_code(POST_MEM_SETUP3); /* post_73h */ banner("AUTOSIZE DIMM 0"); auto_size_dimm(DIMM0); - post_code(POST_MEM_SETUP4); // post_74h + post_code(POST_MEM_SETUP4); /* post_74h */ banner("AUTOSIZE DIMM 1"); auto_size_dimm(DIMM1); /* Set CAS latency */ banner("set cas latency"); - post_code(POST_MEM_SETUP5); // post_75h + post_code(POST_MEM_SETUP5); /* post_75h */ setCAS(); /* Set all the other latencies here (tRAS, tRP....) */ @@ -563,7 +568,7 @@ //print_debug("sdram_enable step 6\n"); /* 7. Reset DLL, Bit 27 is undocumented in GX datasheet, - * it is documented in LX datasheet */ + * it is documented in LX datasheet */ /* load Mode Register by set and clear PROG_DRAM */ msr = rdmsr(MC_CF07_DATA); msr.lo |= ((0x01 << 27) | 0x01);

1 0

Compaq Presario CQ50-115NR Notebook PC
by Monte Cabet 03 Nov '10

03 Nov '10

Product info page: http://h10025.www1.hp.com/ewfrf/wc/document?cc=us&lc=en&docname=c01486798&p… lspci -tvnn: $ lspci -tvnn -[0000:00]-+-00.0 nVidia Corporation MCP78S [GeForce 8200] Memory Controller [10de:0754] +-01.0 nVidia Corporation Device [10de:075e] +-01.1 nVidia Corporation MCP78S [GeForce 8200] SMBus [10de:0752] +-01.3 nVidia Corporation MCP78S [GeForce 8200] Co-Processor [10de:0753] +-01.4 nVidia Corporation MCP78S [GeForce 8200] Memory Controller [10de:0568] +-02.0 nVidia Corporation MCP78S [GeForce 8200] OHCI USB 1.1 Controller [10de:077b] +-02.1 nVidia Corporation MCP78S [GeForce 8200] EHCI USB 2.0 Controller [10de:077c] +-04.0 nVidia Corporation MCP78S [GeForce 8200] OHCI USB 1.1 Controller [10de:077d] +-04.1 nVidia Corporation MCP78S [GeForce 8200] EHCI USB 2.0 Controller [10de:077e] +-06.0 nVidia Corporation MCP78S [GeForce 8200] IDE [10de:0759] +-07.0 nVidia Corporation MCP72XE/MCP72P/MCP78U/MCP78S High Definition Audio [10de:0774] +-08.0-[0000:01]-- +-09.0 nVidia Corporation MCP78S [GeForce 8200] SATA Controller (non-AHCI mode) [10de:0ad0] +-0a.0 nVidia Corporation MCP77 Ethernet [10de:0760] +-0b.0-[0000:02]----00.0 nVidia Corporation C77 [GeForce 8200M G] [10de:0845] +-14.0-[0000:07]----00.0 Atheros Communications Inc. AR5001 Wireless Network Adapter [168c:001c] +-18.0 Advanced Micro Devices [AMD] Mobile K10 [Turion X2, Athlon X2, Sempron] HyperTransport Configuration [1022:1300] +-18.1 Advanced Micro Devices [AMD] Family 11h [Turion X2, Athlon X2, Sempron] Address Map [1022:1301] +-18.2 Advanced Micro Devices [AMD] Mobile K10 [Turion X2, Athlon X2, Sempron] DRAM Controller [1022:1302] +-18.3 Advanced Micro Devices [AMD] Mobile K10 [Turion X2, Athlon X2, Sempron] Miscellaneous Control [1022:1303] \-18.4 Advanced Micro Devices [AMD] Mobile K10 [Turion X2, Athlon X2, Sempron] Link Control [1022:1304] superiotool -dV: superiotool r3844 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0xffff, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0xffff, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0xffff, id=0xffff Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x0000, id=0x11fc Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0xfc11, rev=0x0 Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0xfc11, rev=0x0 Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0xfc11, rev=0x0 Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0xfc11, rev=0x0 Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0xffff, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: sid=0xfc, srid=0xa2 Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xfc, rev=0x11 Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0x00, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x4e... Failed. Returned data: id/oldid=0xfc/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x89) at 0x4e... Failed. Returned data: id/oldid=0xfc/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x86,0x86) at 0x4e... Failed. Returned data: id/oldid=0xfc/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id/oldid=0xfc/0x00, rev=0x11 Probing for Winbond Super I/O (init=0x88) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x3f0... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x370... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x87,0x87) at 0x250... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff No Super I/O found flashrom -V: flashrom v0.9.1-r946 No coreboot table found. DMI string system-manufacturer: "Hewlett-Packard" DMI string system-product-name: "Compaq Presario CQ50 Notebook PC" DMI string system-version: "F.07" DMI string baseboard-manufacturer: "Wistron" DMI string baseboard-product-name: "360A" DMI string baseboard-version: "08.36" DMI string chassis-type: "Notebook" Laptop detected via DMI ======================================================================== WARNING! You seem to be running flashrom on a laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. ======================================================================== This chipset supports the following protocols: Non-SPI. WARNING: No chipset found. Flash detection will most likely fail. Calibrating delay loop... 487M loops per second, 100 myus = 196 us. OK. Probing for AMD Am29F010A/B, 128 KB: probe_jedec_common: id1 0xf6, id2 0x0d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F016D, 2048 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29F080B, 1024 KB: probe_jedec_common: id1 0x61, id2 0x87, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMD Am29LV081B, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x61, id2 0x87, id1 is normal flash content, id2 is normal flash content Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: probe_jedec_common: id1 0x3c, id2 0x40, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C010A, 128 KB: probe_jedec_common: id1 0xf6, id2 0x0d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C020, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT29C040A, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: probe_jedec_common: id1 0x3c, id2 0x40, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F002(N), 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A25L40PT, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for AMIC A25L40PU, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A29040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for AMIC A49LF040A, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EMST F49B002UA, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Eon EN25B05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B05T, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B10T, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B20T, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B40T, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B80T, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B16T, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B32T, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25B64T, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25D16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F05, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN25F32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Eon EN29F010, 128 KB: probe_jedec_common: id1 0xf6, id2 0x0d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EON EN29F002(A)(N)B, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for EON EN29F002(A)(N)T, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004BC, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F004TC, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Fujitsu MBM29F400BC, 512 KB: probe_m29f400bt: id1 0x4e, id2 0x50 Probing for Fujitsu MBM29F400TC, 512 KB: probe_m29f400bt: id1 0x4e, id2 0x50 Probing for Intel 28F001BX-B, 128 KB: probe_jedec_common: id1 0xf6, id2 0x0d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F001BX-T, 128 KB: probe_jedec_common: id1 0xf6, id2 0x0d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Intel 28F004S5, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for Intel 82802AB, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for Intel 82802AC, 1024 KB: probe_82802ab: id1 0x61, id2 0x87 Probing for Macronix MX25L512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1005, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L2005, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L4005, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L8005, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1605, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L1635D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3205, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L3235D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L6405, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX25L12805, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix MX29F001B, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf6, id2 0x0d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F001T, 128 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xf6, id2 0x0d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Macronix MX29LV040, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Numonyx M25PE10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Numonyx M25PE16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV020, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm25LV512, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC Pm29F002T, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm29F002B, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm39LV010, 128 KB: probe_jedec_common: id1 0xf6, id2 0x0d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL002, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for PMC Pm49FL004, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Sanyo LF25FW203A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Sharp LHF00L04, 1024 KB: probe_82802ab: id1 0x61, id2 0x87 Probing for Spansion S25FL008A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Spansion S25FL016A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF016B, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF032B, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF040B.REMS, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST25VF080B, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST SST28SF040A, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for SST SST29EE010, 128 KB: probe_jedec_common: id1 0xf6, id2 0x0d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29LE010, 128 KB: probe_jedec_common: id1 0xf6, id2 0x0d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29EE020A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST29LE020, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF512, 64 KB: probe_jedec_common: id1 0x3c, id2 0x40, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF010A, 128 KB: probe_jedec_common: id1 0xf6, id2 0x0d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF020A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39SF040, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF512, 64 KB: probe_jedec_common: id1 0x3c, id2 0x40, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF010, 128 KB: probe_jedec_common: id1 0xf6, id2 0x0d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF020, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF040, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST39VF080, 1024 KB: probe_jedec_common: id1 0x61, id2 0x87, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF002A/B, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF003A/B, 384 KB: probe_jedec_common: id1 0x07, id2 0xbf, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004A/B, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF004C, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for SST SST49LF008A, 1024 KB: probe_jedec_common: id1 0x61, id2 0x87, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF008C, 1024 KB: probe_82802ab: id1 0x61, id2 0x87 Probing for SST SST49LF016C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for SST SST49LF020, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF020A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF040B, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF080A, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x61, id2 0x87, id1 is normal flash content, id2 is normal flash content Probing for SST SST49LF160C, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M25P05-A, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P05.RES, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10-A, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P10.RES, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P40-old, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M25P128, 16384 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST M29F002B, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F002T/NT, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F040B, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29F400BT, 512 KB: probe_m29f400bt: id1 0x4e, id2 0x50 Probing for ST M29W010B, 128 KB: probe_jedec_common: id1 0xf6, id2 0x0d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W040B, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M29W512B, 64 KB: probe_jedec_common: id1 0x3c, id2 0x40, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for ST M50FLW040A, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for ST M50FLW040B, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for ST M50FLW080A, 1024 KB: probe_82802ab: id1 0x61, id2 0x87 Probing for ST M50FLW080B, 1024 KB: probe_82802ab: id1 0x61, id2 0x87 Probing for ST M50FW002, 256 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW016, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for ST M50FW040, 512 KB: probe_82802ab: id1 0x4e, id2 0x41 Probing for ST M50FW080, 1024 KB: probe_82802ab: id1 0x61, id2 0x87 Probing for ST M50LPW116, 2048 KB: probe_82802ab: id1 0xff, id2 0xff Probing for SyncMOS S29C31004T, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C51001T, 128 KB: probe_jedec_common: id1 0xf6, id2 0x0d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C51002T, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for SyncMOS S29C51004T, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RB, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for TI TMS29F002RT, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W25x10, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x20, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x40, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x80, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x16, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x32, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W25x64, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Winbond W29C011, 128 KB: probe_jedec_common: id1 0xf6, id2 0x0d, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C020C, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29C040P, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W29EE011, 128 KB: Probing disabled for Winbond W29EE011 because the probing sequence puts the AMIC A49LF040A in a funky state. Use 'flashrom -c W29EE011' if you have a board with this chip. Probing for Winbond W39V040A, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040B, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040C, 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V040FA, 512 KB: probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080A, 1024 KB: probe_jedec_common: id1 0x61, id2 0x87, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49F002U, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002A, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W49V002FA, 256 KB: probe_jedec_common: id1 0xff, id2 0xff, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA, 1024 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x61, id2 0x87, id1 is normal flash content, id2 is normal flash content Probing for Winbond W39V080FA (dual mode), 512 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec_common: id1 0x4e, id2 0x41, id1 parity violation, id1 is normal flash content, id2 is normal flash content Probing for Atmel unknown Atmel SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for EON unknown EON SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Macronix unknown Macronix SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for PMC unknown PMC SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for SST unknown SST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for ST unknown ST SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Sanyo unknown Sanyo SPI chip, 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (RDID), 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Generic unknown SPI chip (REMS), 0 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. No EEPROM/flash device found. If you know which flash chip you have, and if this version of flashrom supports a similar flash chip, you can try to force read your chip. Run: flashrom -f -r -c similar_supported_flash_chip filename Note: flashrom can never write when the flash chip isn't found automatically. I posted all the info the FAQ said to post when asking of the mailing list; it does seem abit overkill, but I don't know what I'm looking at/for. I didn't see my laptop on the "Laptops" section of "Supported Motherboards". I did notice the top of flashrom that it said that since I want to flash my laptop's BIOS, I should use the factory tool (I cheated and used Win Vista as the OS when I'm really running Ubuntu 10.10; http://h10025.www1.hp.com/ewfrf/wc/softwareDownloadIndex?softwareitem=ob-76…). If there is any other information you require, please let me know as I'll do my best to provide it. The question is if I can flash my BIOS and replace it with coreboot? Or is coreboot not mature enough to handle laptops and my mileage may vary?

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[PATCH] Fix AMD HD 3200 uma graphics problems in Win7
by Scott Duplichan 02 Nov '10

02 Nov '10

This patch solves crashes and BSODs that occur when booting Win7 with AMD RS780 uma graphics. Tested with frame buffer sizes 64m through 1GB by running dxdiag and Windows media player at 1600x1200 true color. Additional changes needed to boot Win7 on Mahogany_fam10 will follow. -- Leave graphics debug bar enabled because the ATI driver uses it. -- Disable the family 10h processor mmconf while the RS780 mmconf is in use. -- Make strap programming more closely follow the reference BIOS. -- Disable PCIe bar 3 after using it. -- UMA size is no longer hardcoded. -- Disable write combining for all steppings to eliminate stability problem. -- Correct task file data. -- Improve the accuracy of the Atom table that passes information to the driver. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Index: src/southbridge/amd/rs780/rs780.c =================================================================== --- src/southbridge/amd/rs780/rs780.c (revision 6011) +++ src/southbridge/amd/rs780/rs780.c (working copy) @@ -133,11 +133,6 @@ temp32 = pci_read_config32(nb_dev, 0x4c); printk(BIOS_DEBUG, "NB_PCI_REG4C = %x.\n", temp32); - /* disable GFX debug. */ - temp8 = pci_read_config8(nb_dev, 0x8d); - temp8 &= ~(1<<1); - pci_write_config8(nb_dev, 0x8d, temp8); - /* set temporary NB TOM to 0x40000000. */ rs780_set_tom(nb_dev); @@ -194,15 +189,27 @@ static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev) { /* NB_InitGFXStraps */ - u32 MMIOBase, apc04, apc18, apc24; + u32 MMIOBase, apc04, apc18, apc24, romstrap2; + msr_t pcie_mmio_save; volatile u32 * strap; + // disable processor pcie mmio, if enabled + if (is_family10h()) { + msr_t temp; + pcie_mmio_save = temp = rdmsr (0xc0010058); + temp.lo &= ~1; + wrmsr (0xc0010058, temp); + } + /* Get PCIe configuration space. */ MMIOBase = pci_read_config32(nb_dev, 0x1c) & 0xfffffff0; /* Temporarily disable PCIe configuration space. */ + set_htiu_enable_bits(nb_dev, 0x32, 1<<28, 0); + // 1E: NB_BIF_SPARE set_nbmisc_enable_bits(nb_dev, 0x1e, 0xffffffff, 1<<1 | 1<<4 | 1<<6 | 1<<7); + /* Set a temporary Bus number. */ apc18 = pci_read_config32(dev, 0x18); pci_write_config32(dev, 0x18, 0x010100); @@ -214,18 +221,27 @@ pci_write_config8(dev, 0x04, 0x02); /* Program Straps. */ - strap = (volatile u32 *)(MMIOBase + 0x15020); + romstrap2 = 1 << 26; // enables audio function #if (CONFIG_GFXUMA == 1) - *strap = 1<<7; /* the format of BIF_MEM_AP_SIZE. 001->256MB? */ -#else - *strap = 0; /* 128M SP memory, 000 -> 128MB */ + extern uint64_t uma_memory_size; + // bits 7-9: aperture size + // 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g + if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7; + if (uma_memory_size == 0x04000000) romstrap2 |= 2 << 7; + if (uma_memory_size == 0x08000000) romstrap2 |= 0 << 7; + if (uma_memory_size == 0x10000000) romstrap2 |= 1 << 7; + if (uma_memory_size == 0x20000000) romstrap2 |= 4 << 7; + if (uma_memory_size == 0x40000000) romstrap2 |= 5 << 7; + if (uma_memory_size == 0x80000000) romstrap2 |= 6 << 7; #endif + strap = (volatile u32 *)(MMIOBase + 0x15020); + *strap = romstrap2; strap = (volatile u32 *)(MMIOBase + 0x15000); *strap = 0x2c006300; strap = (volatile u32 *)(MMIOBase + 0x15010); *strap = 0x03015330; - //strap = (volatile u32 *)(MMIOBase + 0x15020); - //*strap |= 0x00000040; /* Disable HDA device. */ + strap = (volatile u32 *)(MMIOBase + 0x15020); + *strap = romstrap2 | 0x00000040; strap = (volatile u32 *)(MMIOBase + 0x15030); *strap = 0x00001002; strap = (volatile u32 *)(MMIOBase + 0x15040); @@ -240,8 +256,9 @@ /* BIF switches into normal functional mode. */ set_nbmisc_enable_bits(nb_dev, 0x1e, 1<<4 | 1<<5, 1<<5); - /* NB Revision is A12. */ - set_nbmisc_enable_bits(nb_dev, 0x1e, 1<<9, 1<<9); + /* NB Revision is A12 or newer */ + if (get_nb_rev(nb_dev) >= REV_RS780_A12) + set_nbmisc_enable_bits(nb_dev, 0x1e, 1<<9, 1<<9); /* Restore APC04, APC18, APC24. */ pci_write_config32(dev, 0x04, apc04); @@ -250,6 +267,11 @@ /* Enable PCIe configuration space. */ set_htiu_enable_bits(nb_dev, 0x32, 0, 1<<28); + + // restore processor pcie mmio + if (is_family10h()) + wrmsr (0xc0010058, pcie_mmio_save); + printk(BIOS_INFO, "GC is accessible from now on.\n"); } @@ -332,18 +354,16 @@ (dev->enabled ? 1 : 0) << 6); if (dev->enabled) rs780_gpp_sb_init(nb_dev, dev, dev_ind); - disable_pcie_bar3(nb_dev); break; case 9: /* bus 0, dev 9,10, GPP */ case 10: printk(BIOS_INFO, "Bus-0, Dev-9, 10, Fun-0. enable=%d\n", dev->enabled); - enable_pcie_bar3(nb_dev); /* PCIEMiscInit */ set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << (7 + dev_ind), (dev->enabled ? 0 : 1) << (7 + dev_ind)); if (dev->enabled) rs780_gpp_sb_init(nb_dev, dev, dev_ind); - /* Dont call disable_pcie_bar3(nb_dev) here, otherwise the screen will crash. */ + if (dev_ind == 10) disable_pcie_bar3(nb_dev); break; default: printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev)); Index: src/southbridge/amd/rs780/rs780.h =================================================================== --- src/southbridge/amd/rs780/rs780.h (revision 6011) +++ src/southbridge/amd/rs780/rs780.h (working copy) @@ -208,4 +208,9 @@ void config_gpp_core(device_t nb_dev, device_t sb_dev); void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port); u8 PcieTrainPort(device_t nb_dev, device_t dev, u32 port); +u32 extractbit(u32 data, int bit_number); +u32 extractbits(u32 source, int lsb, int msb); +int cpuidFamily(void); +int is_family0Fh(void); +int is_family10h(void); #endif /* RS780_H */ Index: src/southbridge/amd/rs780/rs780_cmn.c =================================================================== --- src/southbridge/amd/rs780/rs780_cmn.c (revision 6011) +++ src/southbridge/amd/rs780/rs780_cmn.c (working copy) @@ -29,6 +29,7 @@ #include <cpu/amd/mtrr.h> #include <boot/coreboot_tables.h> #include <delay.h> +#include <cpu/cpu.h> #include "rs780.h" static u32 nb_read_index(device_t dev, u32 index_reg, u32 index) @@ -223,7 +224,7 @@ pci_write_config32(k8_f1, 0xbc, 0); pci_write_config32(k8_f1, 0xb0, 0); pci_write_config32(k8_f1, 0xb4, 0); - } + } } void PcieReleasePortTraining(device_t nb_dev, device_t dev, u32 port) @@ -361,3 +362,42 @@ pci_write_config32(nb_dev, 0x90, uma_memory_base); //nbmc_write_index(nb_dev, 0x1e, uma_memory_base); } + +// extract single bit +u32 extractbit(u32 data, int bit_number) +{ + return (data >> bit_number) & 1; +} + +// extract bit field +u32 extractbits(u32 source, int lsb, int msb) +{ + int field_width = msb - lsb + 1; + u32 mask = 0xFFFFFFFF >> (32 - field_width); + return (source >> lsb) & mask; +} + +// return AMD cpuid family +int cpuidFamily(void) +{ + u32 baseFamily, extendedFamily, fms; + + fms = cpuid_eax (1); + baseFamily = extractbits (fms, 8, 11); + extendedFamily = extractbits (fms, 20, 27); + return baseFamily + extendedFamily; +} + + +// return non-zero for AMD family 0Fh processor found +int is_family0Fh(void) +{ + return cpuidFamily() == 0x0F; +} + + +// return non-zero for AMD family 10h processor found +int is_family10h(void) +{ + return cpuidFamily() == 0x10; +} Index: src/southbridge/amd/rs780/rs780_early_setup.c =================================================================== --- src/southbridge/amd/rs780/rs780_early_setup.c (revision 6011) +++ src/southbridge/amd/rs780/rs780_early_setup.c (working copy) @@ -485,7 +485,7 @@ /*Reg8Ch[10:9] = 0x3 Enables Gfx Debug BAR, * force this BAR as mem type in rs780_gfx.c */ - set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x03); + set_nbcfg_enable_bits_8(nb_dev, 0x8D, (u8)(~0xFF), 0x06); } static void rs780_por_mc_index_init(device_t nb_dev) Index: src/southbridge/amd/rs780/rs780_gfx.c =================================================================== --- src/southbridge/amd/rs780/rs780_gfx.c (revision 6011) +++ src/southbridge/amd/rs780/rs780_gfx.c (working copy) @@ -39,6 +39,8 @@ void set_pcie_reset(void); void set_pcie_dereset(void); +extern uint64_t uma_memory_base, uma_memory_size; + /* Trust the original resource allocation. Don't do it again. */ #undef DONT_TRUST_RESOURCE_ALLOCATION //#define DONT_TRUST_RESOURCE_ALLOCATION @@ -304,11 +306,15 @@ volatile u32 * pointer; int i; u16 command; - u32 value, sblk; + u32 value; u16 deviceid, vendorid; device_t nb_dev = dev_find_slot(0, 0); device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2)); device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0)); + static u8 ht_freq_lookup [] = {2, 0, 4, 0, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 0, 0, 28, 30, 32}; + static u8 ht_width_lookup [] = {8, 16, 0, 0, 2, 4, 0, 0}; + static u16 memclk_lookup_fam0F [] = {100, 0, 133, 0, 0, 166, 0, 200}; + static u16 memclk_lookup_fam10 [] = {200, 266, 333, 400, 533, 667, 800, 800}; /* We definetely will use this in future. Just leave it here. */ /*struct southbridge_amd_rs780_config *cfg = @@ -339,6 +345,8 @@ *(GpuF0MMReg + 0x2180/4) = ((value&0xff00)>>8)|((value&0xff000000)>>8); *(GpuF0MMReg + 0x2c04/4) = ((value&0xff00)<<8); *(GpuF0MMReg + 0x5428/4) = ((value&0xffff0000)+0x10000)-((value&0xffff)<<16); + *(GpuF0MMReg + 0xF774/4) = 0xffffffff; + *(GpuF0MMReg + 0xF770/4) = 0x00000001; *(GpuF0MMReg + 0x2000/4) = 0x00000011; *(GpuF0MMReg + 0x200c/4) = 0x00000020; *(GpuF0MMReg + 0x2010/4) = 0x10204810; @@ -352,21 +360,26 @@ *(GpuF0MMReg + 0x7de4/4) |= (1<<3) | (1<<4); /* Force allow LDT_STOP Cool'n'Quiet workaround. */ *(GpuF0MMReg + 0x655c/4) |= 1<<4; + + // disable write combining, needed for stability + *(GpuF0MMReg + 0x2000/4) = 0x00000010; + *(GpuF0MMReg + 0x2408/4) = 1 << 9; + *(GpuF0MMReg + 0x2000/4) = 0x00000011; + /* GFX_InitFBAccess finished. */ +#if (CONFIG_GFXUMA == 1) /* for UMA mode. */ /* GFX_StartMC. */ -#if (CONFIG_GFXUMA == 1) /* for UMA mode. */ - /* MC_INIT_COMPLETE. */ - set_nbmc_enable_bits(nb_dev, 0x2, 0, 1<<31); - /* MC_STARTUP, MC_POWERED_UP and MC_VMODE.*/ - set_nbmc_enable_bits(nb_dev, 0x1, 1<<18, 1|1<<2); - - set_nbmc_enable_bits(nb_dev, 0xb1, 0, 1<<6); - set_nbmc_enable_bits(nb_dev, 0xc3, 0, 1); - nbmc_write_index(nb_dev, 0x07, 0x18); - nbmc_write_index(nb_dev, 0x06, 0x00000102); - nbmc_write_index(nb_dev, 0x09, 0x40000008); - set_nbmc_enable_bits(nb_dev, 0x6, 0, 1<<31); + set_nbmc_enable_bits(nb_dev, 0x02, 0x00000000, 0x80000000); + set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000001); + set_nbmc_enable_bits(nb_dev, 0x01, 0x00000000, 0x00000004); + set_nbmc_enable_bits(nb_dev, 0x01, 0x00040000, 0x00000000); + set_nbmc_enable_bits(nb_dev, 0xB1, 0xFFFF0000, 0x00000040); + set_nbmc_enable_bits(nb_dev, 0xC3, 0x00000000, 0x00000001); + set_nbmc_enable_bits(nb_dev, 0x07, 0xFFFFFFFF, 0x00000018); + set_nbmc_enable_bits(nb_dev, 0x06, 0xFFFFFFFF, 0x00000102); + set_nbmc_enable_bits(nb_dev, 0x09, 0xFFFFFFFF, 0x40000008); + set_nbmc_enable_bits(nb_dev, 0x06, 0x00000000, 0x80000000); /* GFX_StartMC finished. */ #else /* for SP mode. */ @@ -418,77 +431,110 @@ vgainfo.sHeader.ucTableContentRevision = 2; #if (CONFIG_GFXUMA == 0) /* SP mode. */ + // Side port support is incomplete, do not use it + // These parameters must match the motherboard vgainfo.ulBootUpSidePortClock = 667*100; - vgainfo.ucMemoryType = 3; + vgainfo.ucMemoryType = 3; // 3=ddr3 sp mem, 2=ddr2 sp mem vgainfo.ulMinSidePortClock = 333*100; #endif - vgainfo.ulBootUpEngineClock = 500 * 100; /* set boot up GFX engine clock. */ - vgainfo.ulReserved1[0] = 0; vgainfo.ulReserved1[1] = 0; - value = pci_read_config32(k8_f2, 0x94); - printk(BIOS_DEBUG, "MEMCLK = %x\n", value&0x7); - vgainfo.ulBootUpUMAClock = 333 * 100; /* set boot up UMA memory clock. */ - vgainfo.ulBootUpSidePortClock = 0; /* disable SP. */ - vgainfo.ulMinSidePortClock = 0; /* disable SP. */ - for(i=0; i<6; i++) - vgainfo.ulReserved2[i] = 0; - vgainfo.ulSystemConfig = 0; - //vgainfo.ulSystemConfig |= 1<<1 | 1<<3 | 1<<4 | 1<<5 | 1<<6 | 1<<7 | 1; - vgainfo.ulBootUpReqDisplayVector = 0; //? - vgainfo.ulOtherDisplayMisc = 0; //? - vgainfo.ulDDISlot1Config = 0x000c0011; //0; //VGA - //vgainfo.ulDDISlot1Config = 0x000c00FF; //0; //HDMI - vgainfo.ulDDISlot2Config = 0x00130022; //0; //? - vgainfo.ucMemoryType = 2; - /* UMA Channel Number: 1 or 2. */ - vgainfo.ucUMAChannelNumber = 2; - vgainfo.ucDockingPinBit = 0; //? - vgainfo.ucDockingPinPolarity = 0; //? - vgainfo.ulDockingPinCFGInfo = 0; //? - vgainfo.ulCPUCapInfo = 3; /* K8. */ + vgainfo.ulBootUpEngineClock = 500 * 100; // setup option on reference BIOS, 500 is default - /* page 5-19 on BDG. */ - vgainfo.usNumberOfCyclesInPeriod = 0x8019; - vgainfo.usMaxNBVoltage = 0x1a; - vgainfo.usMinNBVoltage = 0; - vgainfo.usBootUpNBVoltage = 0x1a; + // find the DDR memory frequency + if (is_family10h()) { + value = pci_read_config32(k8_f2, 0x94); // read channel 0 DRAM Configuration High Register + if (extractbit(value, 14)) // if channel 0 disabled, channel 1 must have memory + value = pci_read_config32(k8_f2, 0x194);// read channel 1 DRAM Configuration High Register + vgainfo.ulBootUpUMAClock = memclk_lookup_fam10 [extractbits (value, 0, 2)] * 100; + } + if (is_family0Fh()) { + value = pci_read_config32(k8_f2, 0x94); + vgainfo.ulBootUpUMAClock = memclk_lookup_fam0F [extractbits (value, 20, 22)] * 100; + } - /* Get SBLink value (HyperTransport I/O Hub Link ID). */ - value = pci_read_config32(k8_f0, 0x64); - sblk = (value >> 8) & 0x3; - printk(BIOS_DEBUG, "SBLINK = %d.\n", sblk); + /* UMA Channel Number: 1 or 2. */ + vgainfo.ucUMAChannelNumber = 1; + if (is_family0Fh()) { + value = pci_read_config32(k8_f2, 0x90); + if (extractbit(value, 11)) // 128-bit mode + vgainfo.ucUMAChannelNumber = 2; + } + if (is_family10h()) { + u32 dch0 = pci_read_config32(k8_f2, 0x94); + u32 dch1 = pci_read_config32(k8_f2, 0x194); + if (extractbit(dch0, 14) == 0 && extractbit(dch1, 14) == 0) { // both channels enabled + value = pci_read_config32(k8_f2, 0x110); + if (extractbit(value, 4)) // ganged mode + vgainfo.ucUMAChannelNumber = 2; + } + } + + // processor type + if (is_family0Fh()) + vgainfo.ulCPUCapInfo = 3; + if (is_family10h()) + vgainfo.ulCPUCapInfo = 2; /* HT speed */ - value = pci_read_config32(nb_dev, 0xd0); - printk(BIOS_DEBUG, "NB HT speed = %x.\n", value); - value = pci_read_config32(k8_f0, 0x88 + (sblk * 0x20)); - printk(BIOS_DEBUG, "CPU HT speed = %x.\n", value); - vgainfo.ulHTLinkFreq = 100 * 100; /* set HT speed. */ + value = pci_read_config8(nb_dev, 0xd1); + value = ht_freq_lookup [value] * 100; // HT link frequency in MHz + vgainfo.ulHTLinkFreq = value * 100; // HT frequency in units of 100 MHz + vgainfo.ulHighVoltageHTLinkFreq = vgainfo.ulHTLinkFreq; + vgainfo.ulLowVoltageHTLinkFreq = vgainfo.ulHTLinkFreq; + if (value <= 1800) + vgainfo.ulLowVoltageHTLinkFreq = vgainfo.ulHTLinkFreq; + else { + int sblink, cpuLnkFreqCap, nbLnkFreqCap; + value = pci_read_config32(k8_f0, 0x64); + sblink = extractbits(value, 8, 10); + cpuLnkFreqCap = pci_read_config16(k8_f0, 0x8a + sblink * 0x20); + nbLnkFreqCap = pci_read_config16(nb_dev, 0xd2); + if (cpuLnkFreqCap & nbLnkFreqCap & (1 << 10)) // if both 1800 MHz capable + vgainfo.ulLowVoltageHTLinkFreq = 1800*100; + } + /* HT width. */ - value = pci_read_config32(nb_dev, 0xc8); - printk(BIOS_DEBUG, "HT width = %x.\n", value); - vgainfo.usMinHTLinkWidth = 16; - vgainfo.usMaxHTLinkWidth = 16; - vgainfo.usUMASyncStartDelay = 322; - vgainfo.usUMADataReturnTime = 86; - vgainfo.usLinkStatusZeroTime = 0x00c8; //0; //? - vgainfo.usReserved = 0; - vgainfo.ulHighVoltageHTLinkFreq = 100 * 100; - vgainfo.ulLowVoltageHTLinkFreq = 100 * 100; - vgainfo.usMaxUpStreamHTLinkWidth = 16; - vgainfo.usMaxDownStreamHTLinkWidth = 16; - vgainfo.usMinUpStreamHTLinkWidth = 16; - vgainfo.usMinDownStreamHTLinkWidth = 16; - for(i=0; i<97; i++) - vgainfo.ulReserved3[i] = 0; + value = pci_read_config8(nb_dev, 0xcb); + vgainfo.usMinDownStreamHTLinkWidth = + vgainfo.usMaxDownStreamHTLinkWidth = + vgainfo.usMinUpStreamHTLinkWidth = + vgainfo.usMaxUpStreamHTLinkWidth = + vgainfo.usMinHTLinkWidth = + vgainfo.usMaxHTLinkWidth = ht_width_lookup [extractbits(value, 0, 2)]; + if (is_family0Fh()) { + vgainfo.usUMASyncStartDelay = 322; + vgainfo.usUMADataReturnTime = 286; + } + + if (is_family10h()) { + static u16 t0mult_lookup [] = {10, 50, 200, 2000}; + int t0time, t0scale; + value = pci_read_config32(k8_f0, 0x16c); + t0time = extractbits(value, 0, 3); + t0scale = extractbits(value, 4, 5); + vgainfo.usLinkStatusZeroTime = t0mult_lookup [t0scale] * t0time; + vgainfo.usUMASyncStartDelay = 100; + if (vgainfo.ulHTLinkFreq < 1000 * 100) { // less than 1000 MHz + vgainfo.usUMADataReturnTime = 300; + vgainfo.usLinkStatusZeroTime = 6 * 100; // 6us for GH in HT1 mode + } + else { + int lssel; + value = pci_read_config32(nb_dev, 0xac); + lssel = extractbits (value, 7, 8); + vgainfo.usUMADataReturnTime = 1300; + if (lssel == 0) vgainfo.usUMADataReturnTime = 150; + } + } + /* Transfer the Table to VBIOS. */ pointer = (u32 *)&vgainfo; for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) { #if (CONFIG_GFXUMA == 1) - *GpuF0MMReg = 0x80000000 + 0x10000000 - 512 + i; + *GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i; #else *GpuF0MMReg = 0x80000000 + 0x8000000 - 512 + i; #endif @@ -584,7 +630,6 @@ * Set registers in RS780 and CPU to enable the internal GFX. * Please refer to CIM source code and BKDG. */ -extern uint64_t uma_memory_base, uma_memory_size; static void rs780_internal_gfx_enable(device_t dev) { @@ -637,7 +682,9 @@ #if (CONFIG_GFXUMA == 1) /* GFX_InitUMA. */ /* Copy CPU DDR Controller to NB MC. */ + device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1)); device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2)); + device_t k8_f4 = dev_find_slot(0, PCI_DEVFN(0x18, 4)); for (i = 0; i < 12; i++) { l_dword = pci_read_config32(k8_f2, 0x40 + i * 4); @@ -646,24 +693,40 @@ l_dword = pci_read_config32(k8_f2, 0x80); nbmc_write_index(nb_dev, 0x3c, l_dword); - l_dword = pci_read_config32(k8_f2, 0x94); - if(l_dword & (1<<22)) - set_nbmc_enable_bits(nb_dev, 0x3c, 0, 1<<16); - else - set_nbmc_enable_bits(nb_dev, 0x3c, 1<<16, 0); + set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<22))<<16); + set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<< 8))<<17); + l_dword = pci_read_config32(k8_f2, 0x90); + set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<10))<<18); + if (is_family10h()) + { + for (i = 0; i < 12; i++) + { + l_dword = pci_read_config32(k8_f2, 0x140 + i * 4); + nbmc_write_index(nb_dev, 0x3d + i, l_dword); + } - if(l_dword & (1<<8)) - set_nbmc_enable_bits(nb_dev, 0x3c, 0, 1<<17); - else - set_nbmc_enable_bits(nb_dev, 0x3c, 1<<17, 0); + l_dword = pci_read_config32(k8_f2, 0x180); + nbmc_write_index(nb_dev, 0x49, l_dword); + l_dword = pci_read_config32(k8_f2, 0x194); + set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<<22))<<16); + set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<< 8))<<17); + l_dword = pci_read_config32(k8_f2, 0x190); + set_nbmc_enable_bits(nb_dev, 0x49, 0, !!(l_dword & (1<<10))<<18); - l_dword = pci_read_config32(k8_f2, 0x90); - if(l_dword & (1<<10)) - set_nbmc_enable_bits(nb_dev, 0x3c, 0, 1<<18); - else - set_nbmc_enable_bits(nb_dev, 0x3c, 1<<18, 0); + l_dword = pci_read_config32(k8_f2, 0x110); + nbmc_write_index(nb_dev, 0x4a, l_dword); + l_dword = pci_read_config32(k8_f2, 0x114); + nbmc_write_index(nb_dev, 0x4b, l_dword); + l_dword = pci_read_config32(k8_f4, 0x44); + set_nbmc_enable_bits(nb_dev, 0x4a, 0, !!(l_dword & (1<<22))<<24); + l_dword = pci_read_config32(k8_f1, 0x40); + nbmc_write_index(nb_dev, 0x4c, l_dword); + l_dword = pci_read_config32(k8_f1, 0xf0); + nbmc_write_index(nb_dev, 0x4d, l_dword); + } + /* Set UMA in the 780 side. */ /* UMA start address, size. */ /* The UMA starts at 0xC0000000 of internal RS780 address space @@ -672,7 +735,7 @@ nbmc_write_index(nb_dev, 0x10, ((uma_memory_size - 1 + 0xC0000000) & (~0xffff)) | 0xc000); nbmc_write_index(nb_dev, 0x11, uma_memory_base); nbmc_write_index(nb_dev, 0x12, 0); - nbmc_write_index(nb_dev, 0xf0, 256); + nbmc_write_index(nb_dev, 0xf0, uma_memory_size >> 20); /* GFX_InitUMA finished. */ #else /* GFX_InitSP. */ @@ -1016,7 +1079,7 @@ /* 5.9.1.1. Disables the GFX REFCLK transmitter so that the GFX * REFCLK PAD can be driven by an external source. */ /* 5.9.1.2. Enables GFX REFCLK receiver to receive the REFCLK from an external source. */ - set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28, 0 << 29 | 1 << 28); + set_nbmisc_enable_bits(nb_dev, 0x38, 1 << 29 | 1 << 28 | 1 << 26, 1 << 28); /* 5.9.1.3 Selects the GFX REFCLK to be the source for PLL A. */ /* 5.9.1.4 Selects the GFX REFCLK to be the source for PLL B. */ Index: src/southbridge/amd/rs780/rs780_pcie.c =================================================================== --- src/southbridge/amd/rs780/rs780_pcie.c (revision 6011) +++ src/southbridge/amd/rs780/rs780_pcie.c (working copy) @@ -221,6 +221,7 @@ printk(BIOS_DEBUG, "disable_pcie_bar3()\n"); pci_write_config32(nb_dev, 0x1C, 0); /* clear BAR3 address */ set_nbcfg_enable_bits(nb_dev, 0x7C, 1 << 30, 0 << 30); /* Disable writes to the BAR3. */ + set_htiu_enable_bits(nb_dev, 0x32, 1 << 28, 0); /* disable bar3 decode */ ProgK8TempMmioBase(0, EXT_CONF_BASE_ADDRESS, TEMP_MMIO_BASE_ADDRESS); }

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coreboot November 2010