coreboot November 2010

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[PATCH] ASL should report AMD SB600/SB700 RTC as not PIIX4 compatible
by Scott Duplichan 07 Nov '10

07 Nov '10

DSDT.asl should not report the AMD SB600/SB700 RTC as Intel PIIX4 compatible. The extended cmos is accessed differently for AMD and Intel RTCs. Not sure what if any OS cares about this distinction, but non-Intel compatible seems like a safer way to report the AMD RTC. Tested with Win7 on Mahogany_fam10 and kino-780am2-fam10. Signed-off-by: Scott Duplichan <scott(a)notabs.org> Index: src/mainboard/amd/dbm690t/dsdt.asl =================================================================== --- src/mainboard/amd/dbm690t/dsdt.asl (revision 6030) +++ src/mainboard/amd/dbm690t/dsdt.asl (working copy) @@ -1308,7 +1308,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Index: src/mainboard/amd/mahogany/dsdt.asl =================================================================== --- src/mainboard/amd/mahogany/dsdt.asl (revision 6030) +++ src/mainboard/amd/mahogany/dsdt.asl (working copy) @@ -1324,7 +1324,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Index: src/mainboard/amd/mahogany_fam10/dsdt.asl =================================================================== --- src/mainboard/amd/mahogany_fam10/dsdt.asl (revision 6030) +++ src/mainboard/amd/mahogany_fam10/dsdt.asl (working copy) @@ -1366,7 +1366,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Index: src/mainboard/amd/pistachio/dsdt.asl =================================================================== --- src/mainboard/amd/pistachio/dsdt.asl (revision 6030) +++ src/mainboard/amd/pistachio/dsdt.asl (working copy) @@ -1307,7 +1307,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Index: src/mainboard/amd/tilapia_fam10/dsdt.asl =================================================================== --- src/mainboard/amd/tilapia_fam10/dsdt.asl (revision 6030) +++ src/mainboard/amd/tilapia_fam10/dsdt.asl (working copy) @@ -1366,7 +1366,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Index: src/mainboard/asrock/939a785gmh/dsdt.asl =================================================================== --- src/mainboard/asrock/939a785gmh/dsdt.asl (revision 6030) +++ src/mainboard/asrock/939a785gmh/dsdt.asl (working copy) @@ -1282,7 +1282,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Index: src/mainboard/asus/m4a785-m/dsdt.asl =================================================================== --- src/mainboard/asus/m4a785-m/dsdt.asl (revision 6030) +++ src/mainboard/asus/m4a785-m/dsdt.asl (working copy) @@ -1366,7 +1366,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Index: src/mainboard/gigabyte/ma785gmt/dsdt.asl =================================================================== --- src/mainboard/gigabyte/ma785gmt/dsdt.asl (revision 6030) +++ src/mainboard/gigabyte/ma785gmt/dsdt.asl (working copy) @@ -1366,7 +1366,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Index: src/mainboard/gigabyte/ma78gm/dsdt.asl =================================================================== --- src/mainboard/gigabyte/ma78gm/dsdt.asl (revision 6030) +++ src/mainboard/gigabyte/ma78gm/dsdt.asl (working copy) @@ -1366,7 +1366,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Index: src/mainboard/iei/kino-780am2-fam10/dsdt.asl =================================================================== --- src/mainboard/iei/kino-780am2-fam10/dsdt.asl (revision 6030) +++ src/mainboard/iei/kino-780am2-fam10/dsdt.asl (working copy) @@ -1366,7 +1366,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Index: src/mainboard/jetway/pa78vm5/dsdt.asl =================================================================== --- src/mainboard/jetway/pa78vm5/dsdt.asl (revision 6030) +++ src/mainboard/jetway/pa78vm5/dsdt.asl (working copy) @@ -1366,7 +1366,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Index: src/mainboard/kontron/kt690/dsdt.asl =================================================================== --- src/mainboard/kontron/kt690/dsdt.asl (revision 6030) +++ src/mainboard/kontron/kt690/dsdt.asl (working copy) @@ -1308,7 +1308,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Index: src/mainboard/technexion/tim5690/dsdt.asl =================================================================== --- src/mainboard/technexion/tim5690/dsdt.asl (revision 6030) +++ src/mainboard/technexion/tim5690/dsdt.asl (working copy) @@ -1308,7 +1308,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2) Index: src/mainboard/technexion/tim8690/dsdt.asl =================================================================== --- src/mainboard/technexion/tim8690/dsdt.asl (revision 6030) +++ src/mainboard/technexion/tim8690/dsdt.asl (working copy) @@ -1308,7 +1308,7 @@ /* Real Time Clock Device */ Device(RTC0) { - Name(_HID, EISAID("PNP0B01")) /* AT Real Time Clock */ + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ Name(_CRS, ResourceTemplate() { IRQNoFlags(){8} IO(Decode16,0x0070, 0x0070, 0, 2)

2 1

[commit] r6044 - trunk/src/mainboard/asus
by repository service 07 Nov '10

07 Nov '10

Author: ruik Date: Sun Nov 7 20:27:45 2010 New Revision: 6044 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6044 Log: This adds the m2v directory and necessary files to src/mainboards/asus and adjusts the Kconfig. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Modified: trunk/src/mainboard/asus/Kconfig Modified: trunk/src/mainboard/asus/Kconfig ============================================================================== --- trunk/src/mainboard/asus/Kconfig Sun Nov 7 20:17:18 2010 (r6043) +++ trunk/src/mainboard/asus/Kconfig Sun Nov 7 20:27:45 2010 (r6044) @@ -25,6 +25,8 @@ bool "A8N-E" config BOARD_ASUS_A8V_E_SE bool "A8V-E SE" +config BOARD_ASUS_M2V + bool "M2V" config BOARD_ASUS_M2V_MX_SE bool "M2V-MX SE" config BOARD_ASUS_M4A785M @@ -50,6 +52,7 @@ source "src/mainboard/asus/a8n_e/Kconfig" source "src/mainboard/asus/a8v-e_se/Kconfig" +source "src/mainboard/asus/m2v/Kconfig" source "src/mainboard/asus/m2v-mx_se/Kconfig" source "src/mainboard/asus/m4a785-m/Kconfig" source "src/mainboard/asus/mew-am/Kconfig"

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[commit] r6043 - trunk/src/southbridge/via/vt8237r
by repository service 07 Nov '10

07 Nov '10

Author: ruik Date: Sun Nov 7 20:17:18 2010 New Revision: 6043 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6043 Log: Depends on the "Introduce get_vt8237_lpc() function" and "Use get_vt8237_lpc() in vt8237_sb_enable_fid_vid()" patches. This adds VT8237A specific VLINK/LPC init in vt8237r_early_smbus.c I ran some tests and apparently both the | /* So the chip knows we are on AMD. */ | pci_write_config8(devctl, 0x7c, 0x7f); and | /* | * Allow SLP# signal to assert LDTSTOP_L. | * Will work for C3 and for FID/VID change. | */ | outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); in vt8237r_early_smbus.c are needed on VT8237A, otherwise I get a (non-fatal) fid/vid change error on boot. While vt8237a_vlink_init() in vt8237_ctrl.c is a modified vt8237r_vlink_init(), vt8237a_init() in vt8237r_lpc.c is a modified vt8237s_init(). Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Sun Nov 7 19:57:10 2010 (r6042) +++ trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Sun Nov 7 20:17:18 2010 (r6043) @@ -257,19 +257,30 @@ return; devid = pci_read_config16(dev, PCI_DEVICE_ID); - if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC) { - devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237_VLINK), 0); - if (devctl == PCI_DEV_INVALID) - return; + /* generic setup */ + + /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ + pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); + + /* Enable ACPI accessm RTC signal gated with PSON. */ + pci_write_config8(dev, 0x81, 0x84); + + /* chipset-specific parts */ - /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ - pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); + /* VLINK: FIXME: can we drop the devid check and just look for the VLINK device? */ + if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC || + devid == PCI_DEVICE_ID_VIA_VT8237A_LPC) { + devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237_VLINK), 0); - /* Enable ACPI accessm RTC signal gated with PSON. */ - pci_write_config8(dev, 0x81, 0x84); + if (devctl != PCI_DEV_INVALID) { + /* So the chip knows we are on AMD. */ + pci_write_config8(devctl, 0x7c, 0x7f); + } + } + if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC) { /* * Allow SLP# signal to assert LDTSTOP_L. * Will work for C3 and for FID/VID change. @@ -280,17 +291,10 @@ /* Reduce further the STPCLK/LDTSTP signal to 5us. */ pci_write_config8(dev, 0xec, 0x4); - /* So the chip knows we are on AMD. */ - pci_write_config8(devctl, 0x7c, 0x7f); - return; } - /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ - pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1); - - /* Enable ACPI accessm RTC signal gated with PSON. */ - pci_write_config8(dev, 0x81, 0x84); + /* VT8237R and VT8237A */ /* * Allow SLP# signal to assert LDTSTOP_L.

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[commit] r6042 - trunk/src/southbridge/via/vt8237r
by repository service 07 Nov '10

07 Nov '10

Author: ruik Date: Sun Nov 7 19:57:10 2010 New Revision: 6042 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6042 Log: This adds the VT8237A LPC pci_locate_device call in vt8237r_early_smbus.c Depends on the "Introduce get_vt8237_lpc() function" patch. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Sun Nov 7 19:51:13 2010 (r6041) +++ trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Sun Nov 7 19:57:10 2010 (r6042) @@ -146,6 +146,11 @@ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); + if (dev != PCI_DEV_INVALID) + return dev; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237A_LPC), 0); return dev; }

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[commit] r6041 - trunk/src/southbridge/via/vt8237r
by repository service 07 Nov '10

07 Nov '10

Author: ruik Date: Sun Nov 7 19:51:13 2010 New Revision: 6041 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6041 Log: Use get_vt8237_lpc() in vt8237_sb_enable_fid_vid() too. I broke this out into a seperate part to keep the other half as straight-forward as possible. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Sun Nov 7 19:46:13 2010 (r6040) +++ trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Sun Nov 7 19:51:13 2010 (r6041) @@ -244,17 +244,15 @@ void vt8237_sb_enable_fid_vid(void) { device_t dev, devctl; + u16 devid; /* Power management controller */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); - if (dev == PCI_DEV_INVALID) { - /* Power management controller */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); - if (dev == PCI_DEV_INVALID) - return; + dev = get_vt8237_lpc(); + if (dev == PCI_DEV_INVALID) + return; + devid = pci_read_config16(dev, PCI_DEVICE_ID); + if (devid == PCI_DEVICE_ID_VIA_VT8237S_LPC) { devctl = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237_VLINK), 0);

1 0

[commit] r6040 - trunk/src/southbridge/via/vt8237r
by repository service 07 Nov '10

07 Nov '10

Author: ruik Date: Sun Nov 7 19:46:13 2010 New Revision: 6040 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6040 Log: Instead of duplicating the pci_locate_device calls multiple times, add a get_vt8237_lpc() function. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Modified: trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Sun Nov 7 19:37:39 2010 (r6039) +++ trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c Sun Nov 7 19:46:13 2010 (r6040) @@ -134,6 +134,21 @@ #define PSONREADY_TIMEOUT 0x7fffffff +static device_t get_vt8237_lpc(void) +{ + device_t dev; + + /* Power management controller */ + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); + if (dev != PCI_DEV_INVALID) + return dev; + + dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); + return dev; +} + /** * Enable the SMBus on VT8237R-based systems. */ @@ -143,15 +158,9 @@ int loops; /* Power management controller */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); - if (dev == PCI_DEV_INVALID) { - /* Power management controller */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); - if (dev == PCI_DEV_INVALID) - die("Power management controller not found\n"); - } + dev = get_vt8237_lpc(); + if (dev == PCI_DEV_INVALID) + die("Power management controller not found\n"); /* Make sure the RTC power well is up before touching smbus. */ loops = 0; @@ -292,15 +301,9 @@ device_t dev; /* Power management controller */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); - if (dev == PCI_DEV_INVALID) { - /* Power management controller */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); - if (dev == PCI_DEV_INVALID) - return; - } + dev = get_vt8237_lpc(); + if (dev == PCI_DEV_INVALID) + return; /* ROM decode last 1MB FFC00000 - FFFFFFFF. */ pci_write_config8(dev, 0x41, 0x7f); @@ -316,15 +319,9 @@ print_debug("IN TEST WAKEUP\n"); /* Power management controller */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237R_LPC), 0); - if (dev == PCI_DEV_INVALID) { - /* Power management controller */ - dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, - PCI_DEVICE_ID_VIA_VT8237S_LPC), 0); - if (dev == PCI_DEV_INVALID) - die("Power management controller not found\n"); - } + dev = get_vt8237_lpc(); + if (dev == PCI_DEV_INVALID) + die("Power management controller not found\n"); /* Set ACPI base address to I/O VT8237R_ACPI_IO_BASE. */ pci_write_config16(dev, 0x88, VT8237R_ACPI_IO_BASE | 0x1);

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[commit] r6039 - trunk/src/southbridge/via/k8t890
by repository service 07 Nov '10

07 Nov '10

Author: ruik Date: Sun Nov 7 19:37:39 2010 New Revision: 6039 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6039 Log: Add pointer to public PCIe bridge documentation on http://linux.via.com.tw/ as VX800 seems to be compatible. Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Modified: trunk/src/southbridge/via/k8t890/k8t890_pcie.c Modified: trunk/src/southbridge/via/k8t890/k8t890_pcie.c ============================================================================== --- trunk/src/southbridge/via/k8t890/k8t890_pcie.c Sun Nov 7 19:28:34 2010 (r6038) +++ trunk/src/southbridge/via/k8t890/k8t890_pcie.c Sun Nov 7 19:37:39 2010 (r6039) @@ -24,6 +24,12 @@ #include <device/pci_ids.h> #include "k8t890.h" +/* + * Note: + * The pcie bridges are similar to the VX800 ones documented at + * http://linux.via.com.tw/ + */ + static void peg_init(struct device *dev) { u8 reg;

1 0

[commit] r6038 - trunk/src/southbridge/via/vt8237r
by repository service 07 Nov '10

07 Nov '10

Author: ruik Date: Sun Nov 7 19:28:34 2010 New Revision: 6038 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6038 Log: This adds VT8237A specific VLINK/LPC init functions in vt8237_ctrl.c and vt8237r_lpc.c. While vt8237a_vlink_init() in vt8237_ctrl.c is a modified vt8237r_vlink_init(), vt8237a_init() in vt8237r_lpc.c is a modified vt8237s_init(). Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Modified: trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c Modified: trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c Sun Nov 7 19:25:11 2010 (r6037) +++ trunk/src/southbridge/via/vt8237r/vt8237_ctrl.c Sun Nov 7 19:28:34 2010 (r6038) @@ -168,6 +168,75 @@ } +static void vt8237a_vlink_init(struct device *dev) +{ + u8 reg; + device_t devfun7; + + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CE_7, 0); + if (!devfun7) + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8M890CE_7, 0); + if (!devfun7) + devfun7 = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_K8T890CF_7, 0); + /* No pairing NB was found. */ + if (!devfun7) + return; + + /* + * This init code is valid only for the VT8237A! For different + * sounthbridges (e.g. VT8237S, VT8237R and VT8251) a different + * init code is required. + * + * FIXME: This is based on vt8237r_vlink_init() in + * k8t890/k8t890_ctrl.c and modified to fit what the AMI + * BIOS on my M2V wrote to these registers (by looking + * at lspci -nxxx output). + * Works for me. + */ + + /* disable auto disconnect */ + reg = pci_read_config8(devfun7, 0x42); + reg &= ~0x4; + pci_write_config8(devfun7, 0x42, reg); + + /* NB part setup */ + pci_write_config8(devfun7, 0xb5, 0x88); + pci_write_config8(devfun7, 0xb6, 0x88); + pci_write_config8(devfun7, 0xb7, 0x61); + + reg = pci_read_config8(devfun7, 0xb4); + reg |= 0x11; + pci_write_config8(devfun7, 0xb4, reg); + + pci_write_config8(devfun7, 0xb0, 0x6); + pci_write_config8(devfun7, 0xb1, 0x1); + + /* SB part setup */ + pci_write_config8(dev, 0xb7, 0x50); + pci_write_config8(dev, 0xb9, 0x88); + pci_write_config8(dev, 0xba, 0x8a); + pci_write_config8(dev, 0xbb, 0x88); + + reg = pci_read_config8(dev, 0xbd); + reg |= 0x3; + reg &= ~0x4; + pci_write_config8(dev, 0xbd, reg); + + reg = pci_read_config8(dev, 0xbc); + reg &= ~0x7; + pci_write_config8(dev, 0xbc, reg); + + pci_write_config8(dev, 0x48, 0x23); + + /* enable auto disconnect, for STPGNT and HALT */ + reg = pci_read_config8(devfun7, 0x42); + reg |= 0x7; + pci_write_config8(devfun7, 0x42, reg); +} + static void ctrl_enable(struct device *dev) { /* Enable the 0:13 and 0:13.1. */ @@ -193,6 +262,12 @@ vt8237s_vlink_init(dev); } + devsb = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237A_LPC, 0); + if (devsb) { + vt8237a_vlink_init(dev); + } + /* Configure PCI1 and copy mirror registers from D0F3. */ vt8237_cfg(dev); dump_south(dev); Modified: trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c ============================================================================== --- trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c Sun Nov 7 19:25:11 2010 (r6037) +++ trunk/src/southbridge/via/vt8237r/vt8237r_lpc.c Sun Nov 7 19:28:34 2010 (r6038) @@ -319,6 +319,58 @@ printk(BIOS_SPEW, "Leaving %s.\n", __func__); } +static void vt8237a_init(struct device *dev) +{ + /* + * FIXME: This is based on vt8237s_init() and the values the AMI + * BIOS on my M2V wrote to these registers (by loking + * at lspci -nxxx output). + * Works for me. + */ + u32 tmp; + + /* Set bit 3 of 0x4f (use INIT# as CPU reset). */ + tmp = pci_read_config8(dev, 0x4f); + tmp |= 0x08; + pci_write_config8(dev, 0x4f, tmp); + + /* + * bit2: REQ5 as PCI request input - should be together with INTE-INTH. + * bit5: usb power control lines as gpio + */ + pci_write_config8(dev, 0xe4, 0x24); + /* + * Enable APIC wakeup from INTH + * Enable SATA LED, disable special CPU Frequency Change - + * GPIO28 GPIO22 GPIO29 GPIO23 are GPIOs. + */ + pci_write_config8(dev, 0xe5, 0x69); + + /* Reduce further the STPCLK/LDTSTP signal to 5us. */ + pci_write_config8(dev, 0xec, 0x4); + + /* Host Bus Power Management Control, maybe not needed */ + pci_write_config8(dev, 0x8c, 0x5); + + /* Enable HPET at VT8237R_HPET_ADDR. */ + pci_write_config32(dev, 0x68, (VT8237R_HPET_ADDR | 0x80)); + + southbridge_init_common(dev); + + /* Share INTE-INTH with INTA-INTD for simplicity */ + pci_write_config8(dev, 0x46, 0x00); + + /* FIXME: Intel needs more bit set for C2/C3. */ + + /* + * Allow SLP# signal to assert LDTSTOP_L. + * Will work for C3 and for FID/VID change. + */ + outb(0x1, VT8237R_ACPI_IO_BASE + 0x11); + + dump_south(dev); +} + static void vt8237s_init(struct device *dev) { u32 tmp; @@ -537,6 +589,14 @@ .scan_bus = scan_static_bus, }; +static const struct device_operations vt8237r_lpc_ops_a = { + .read_resources = vt8237r_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = vt8237a_init, + .scan_bus = scan_static_bus, +}; + static const struct pci_driver lpc_driver_r __pci_driver = { .ops = &vt8237r_lpc_ops_r, .vendor = PCI_VENDOR_ID_VIA, @@ -544,7 +604,7 @@ }; static const struct pci_driver lpc_driver_a __pci_driver = { - .ops = &vt8237r_lpc_ops_r, + .ops = &vt8237r_lpc_ops_a, .vendor = PCI_VENDOR_ID_VIA, .device = PCI_DEVICE_ID_VIA_VT8237A_LPC, };

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[commit] r6037 - trunk/src/mainboard/asus/p2b
by repository service 07 Nov '10

07 Nov '10

Author: ruik Date: Sun Nov 7 19:25:11 2010 New Revision: 6037 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6037 Log: Remove empty files added by accident. Sorry about that. Rudolf Signed-off-by: Rudolf Marek <r.marek(a)assembler.cz> Acked-by: Rudolf Marek <r.marek(a)assembler.cz> Deleted: trunk/src/mainboard/asus/p2b/acpi_tables.c trunk/src/mainboard/asus/p2b/dsdt.asl trunk/src/mainboard/asus/p2b/romstage.c.orig

1 0

[commit] r6036 - in trunk/src: mainboard/amd/serengeti_cheetah mainboard/gigabyte/ga_2761gxdk mainboard/gigabyte/m57sli mainboard/hp/dl145_g3 mainboard/iwill/dk8_htx mainboard/iwill/dk8s2 mainboard...
by repository service 07 Nov '10

07 Nov '10

Author: oxygene Date: Sun Nov 7 19:20:51 2010 New Revision: 6036 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6036 Log: Move K8_ALLOCATE_IO_RANGE to Kconfig. Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Acked-by: Patrick Georgi <patrick(a)georgi-clan.de> Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c trunk/src/mainboard/gigabyte/m57sli/Kconfig trunk/src/mainboard/gigabyte/m57sli/romstage.c trunk/src/mainboard/hp/dl145_g3/Kconfig trunk/src/mainboard/hp/dl145_g3/romstage.c trunk/src/mainboard/iwill/dk8_htx/romstage.c trunk/src/mainboard/iwill/dk8s2/romstage.c trunk/src/mainboard/iwill/dk8x/romstage.c trunk/src/mainboard/msi/ms7260/Kconfig trunk/src/mainboard/msi/ms7260/romstage.c trunk/src/mainboard/msi/ms9185/romstage.c trunk/src/mainboard/nvidia/l1_2pvv/Kconfig trunk/src/mainboard/nvidia/l1_2pvv/romstage.c trunk/src/mainboard/sunw/ultra40/Kconfig trunk/src/mainboard/sunw/ultra40/romstage.c trunk/src/mainboard/supermicro/h8dme/Kconfig trunk/src/mainboard/supermicro/h8dme/romstage.c trunk/src/mainboard/supermicro/h8dmr/Kconfig trunk/src/mainboard/supermicro/h8dmr/romstage.c trunk/src/mainboard/tyan/s2895/Kconfig trunk/src/mainboard/tyan/s2895/romstage.c trunk/src/mainboard/tyan/s2912/Kconfig trunk/src/mainboard/tyan/s2912/romstage.c trunk/src/northbridge/amd/amdk8/Kconfig trunk/src/northbridge/amd/amdk8/incoherent_ht.c Modified: trunk/src/mainboard/amd/serengeti_cheetah/romstage.c ============================================================================== --- trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/amd/serengeti_cheetah/romstage.c Sun Nov 7 19:20:51 2010 (r6036) @@ -1,8 +1,5 @@ #define SET_NB_CFG_54 1 -//used by incoherent_ht -//#define K8_ALLOCATE_IO_RANGE 1 - //used by init_cpus and fidvid #define SET_FIDVID 0 //if we want to wait for core1 done before DQS training, set it to 0 Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/Kconfig Sun Nov 7 19:20:51 2010 (r6036) @@ -20,6 +20,7 @@ select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select K8_ALLOCATE_IO_RANGE config MAINBOARD_DIR string Modified: trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c Sun Nov 7 19:20:51 2010 (r6036) @@ -21,9 +21,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define K8_ALLOCATE_IO_RANGE 1 - - #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif Modified: trunk/src/mainboard/gigabyte/m57sli/Kconfig ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/Kconfig Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/gigabyte/m57sli/Kconfig Sun Nov 7 19:20:51 2010 (r6036) @@ -24,6 +24,7 @@ select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select K8_ALLOCATE_IO_RANGE config MAINBOARD_DIR string Modified: trunk/src/mainboard/gigabyte/m57sli/romstage.c ============================================================================== --- trunk/src/mainboard/gigabyte/m57sli/romstage.c Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/gigabyte/m57sli/romstage.c Sun Nov 7 19:20:51 2010 (r6036) @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define K8_ALLOCATE_IO_RANGE 1 - - #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif Modified: trunk/src/mainboard/hp/dl145_g3/Kconfig ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/Kconfig Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/hp/dl145_g3/Kconfig Sun Nov 7 19:20:51 2010 (r6036) @@ -22,6 +22,7 @@ select RAMINIT_SYSINFO select SB_HT_CHAIN_UNITID_OFFSET_ONLY select QRANK_DIMM_SUPPORT + select K8_ALLOCATE_IO_RANGE config MAINBOARD_DIR string Modified: trunk/src/mainboard/hp/dl145_g3/romstage.c ============================================================================== --- trunk/src/mainboard/hp/dl145_g3/romstage.c Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/hp/dl145_g3/romstage.c Sun Nov 7 19:20:51 2010 (r6036) @@ -25,9 +25,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define K8_ALLOCATE_IO_RANGE 1 - - #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif Modified: trunk/src/mainboard/iwill/dk8_htx/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8_htx/romstage.c Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/iwill/dk8_htx/romstage.c Sun Nov 7 19:20:51 2010 (r6036) @@ -1,8 +1,5 @@ #define SET_NB_CFG_54 1 -//used by incoherent_ht -//#define K8_ALLOCATE_IO_RANGE 1 - //used by init_cpus and fidvid #define SET_FIDVID 0 //if we want to wait for core1 done before DQS training, set it to 0 Modified: trunk/src/mainboard/iwill/dk8s2/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8s2/romstage.c Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/iwill/dk8s2/romstage.c Sun Nov 7 19:20:51 2010 (r6036) @@ -1,8 +1,5 @@ #define SET_NB_CFG_54 1 -//used by incoherent_ht -//#define K8_ALLOCATE_IO_RANGE 1 - //used by init_cpus and fidvid #define SET_FIDVID 0 //if we want to wait for core1 done before DQS training, set it to 0 Modified: trunk/src/mainboard/iwill/dk8x/romstage.c ============================================================================== --- trunk/src/mainboard/iwill/dk8x/romstage.c Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/iwill/dk8x/romstage.c Sun Nov 7 19:20:51 2010 (r6036) @@ -1,8 +1,5 @@ #define SET_NB_CFG_54 1 -//used by incoherent_ht -//#define K8_ALLOCATE_IO_RANGE 1 - //used by init_cpus and fidvid #define SET_FIDVID 0 //if we want to wait for core1 done before DQS training, set it to 0 Modified: trunk/src/mainboard/msi/ms7260/Kconfig ============================================================================== --- trunk/src/mainboard/msi/ms7260/Kconfig Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/msi/ms7260/Kconfig Sun Nov 7 19:20:51 2010 (r6036) @@ -22,6 +22,7 @@ select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select K8_ALLOCATE_IO_RANGE config MAINBOARD_DIR string Modified: trunk/src/mainboard/msi/ms7260/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms7260/romstage.c Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/msi/ms7260/romstage.c Sun Nov 7 19:20:51 2010 (r6036) @@ -24,7 +24,6 @@ // #define DQS_TRAIN_DEBUG 1 // #define RES_DEBUG 1 -#define K8_ALLOCATE_IO_RANGE 1 #if CONFIG_LOGICAL_CPUS == 1 #define SET_NB_CFG_54 1 #endif Modified: trunk/src/mainboard/msi/ms9185/romstage.c ============================================================================== --- trunk/src/mainboard/msi/ms9185/romstage.c Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/msi/ms9185/romstage.c Sun Nov 7 19:20:51 2010 (r6036) @@ -25,9 +25,6 @@ #define SET_NB_CFG_54 1 -//used by incoherent_ht -//#define K8_ALLOCATE_IO_RANGE 1 - //used by init_cpus and fidvid #define SET_FIDVID 1 //if we want to wait for core1 done before DQS training, set it to 0 Modified: trunk/src/mainboard/nvidia/l1_2pvv/Kconfig ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/Kconfig Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/nvidia/l1_2pvv/Kconfig Sun Nov 7 19:20:51 2010 (r6036) @@ -23,6 +23,7 @@ select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select K8_ALLOCATE_IO_RANGE config MAINBOARD_DIR string Modified: trunk/src/mainboard/nvidia/l1_2pvv/romstage.c ============================================================================== --- trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/nvidia/l1_2pvv/romstage.c Sun Nov 7 19:20:51 2010 (r6036) @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define K8_ALLOCATE_IO_RANGE 1 - - #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif Modified: trunk/src/mainboard/sunw/ultra40/Kconfig ============================================================================== --- trunk/src/mainboard/sunw/ultra40/Kconfig Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/sunw/ultra40/Kconfig Sun Nov 7 19:20:51 2010 (r6036) @@ -17,6 +17,7 @@ select CK804_USE_NIC select CK804_USE_ACI select QRANK_DIMM_SUPPORT + select K8_ALLOCATE_IO_RANGE config MAINBOARD_DIR string Modified: trunk/src/mainboard/sunw/ultra40/romstage.c ============================================================================== --- trunk/src/mainboard/sunw/ultra40/romstage.c Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/sunw/ultra40/romstage.c Sun Nov 7 19:20:51 2010 (r6036) @@ -1,6 +1,3 @@ -#define K8_ALLOCATE_IO_RANGE 1 - - #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif Modified: trunk/src/mainboard/supermicro/h8dme/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/Kconfig Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/supermicro/h8dme/Kconfig Sun Nov 7 19:20:51 2010 (r6036) @@ -23,6 +23,7 @@ select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select K8_ALLOCATE_IO_RANGE config MAINBOARD_DIR string Modified: trunk/src/mainboard/supermicro/h8dme/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dme/romstage.c Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/supermicro/h8dme/romstage.c Sun Nov 7 19:20:51 2010 (r6036) @@ -16,9 +16,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define K8_ALLOCATE_IO_RANGE 1 - - #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif Modified: trunk/src/mainboard/supermicro/h8dmr/Kconfig ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/Kconfig Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/supermicro/h8dmr/Kconfig Sun Nov 7 19:20:51 2010 (r6036) @@ -22,6 +22,7 @@ select BOARD_ROMSIZE_KB_1024 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select K8_ALLOCATE_IO_RANGE config MAINBOARD_DIR string Modified: trunk/src/mainboard/supermicro/h8dmr/romstage.c ============================================================================== --- trunk/src/mainboard/supermicro/h8dmr/romstage.c Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/supermicro/h8dmr/romstage.c Sun Nov 7 19:20:51 2010 (r6036) @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define K8_ALLOCATE_IO_RANGE 1 - - #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif Modified: trunk/src/mainboard/tyan/s2895/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2895/Kconfig Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/tyan/s2895/Kconfig Sun Nov 7 19:20:51 2010 (r6036) @@ -18,6 +18,7 @@ select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_1024 select QRANK_DIMM_SUPPORT + select K8_ALLOCATE_IO_RANGE config MAINBOARD_DIR string Modified: trunk/src/mainboard/tyan/s2895/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2895/romstage.c Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/tyan/s2895/romstage.c Sun Nov 7 19:20:51 2010 (r6036) @@ -1,6 +1,3 @@ -#define K8_ALLOCATE_IO_RANGE 1 - - #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif Modified: trunk/src/mainboard/tyan/s2912/Kconfig ============================================================================== --- trunk/src/mainboard/tyan/s2912/Kconfig Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/tyan/s2912/Kconfig Sun Nov 7 19:20:51 2010 (r6036) @@ -22,6 +22,7 @@ select BOARD_ROMSIZE_KB_512 select RAMINIT_SYSINFO select QRANK_DIMM_SUPPORT + select K8_ALLOCATE_IO_RANGE config MAINBOARD_DIR string Modified: trunk/src/mainboard/tyan/s2912/romstage.c ============================================================================== --- trunk/src/mainboard/tyan/s2912/romstage.c Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/mainboard/tyan/s2912/romstage.c Sun Nov 7 19:20:51 2010 (r6036) @@ -19,9 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define K8_ALLOCATE_IO_RANGE 1 - - #if CONFIG_LOGICAL_CPUS==1 #define SET_NB_CFG_54 1 #endif Modified: trunk/src/northbridge/amd/amdk8/Kconfig ============================================================================== --- trunk/src/northbridge/amd/amdk8/Kconfig Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/northbridge/amd/amdk8/Kconfig Sun Nov 7 19:20:51 2010 (r6036) @@ -53,6 +53,10 @@ bool default n +config K8_ALLOCATE_IO_RANGE + bool + default n + if K8_REV_F_SUPPORT config DIMM_DDR2 Modified: trunk/src/northbridge/amd/amdk8/incoherent_ht.c ============================================================================== --- trunk/src/northbridge/amd/amdk8/incoherent_ht.c Sun Nov 7 19:20:32 2010 (r6035) +++ trunk/src/northbridge/amd/amdk8/incoherent_ht.c Sun Nov 7 19:20:51 2010 (r6036) @@ -11,10 +11,6 @@ #define CONFIG_K8_HT_FREQ_1G_SUPPORT 0 #endif -#ifndef K8_ALLOCATE_IO_RANGE - #define K8_ALLOCATE_IO_RANGE 0 -#endif - // Do we need allocate MMIO? Current We direct last 64M to sblink only, We can not lose access to last 4M range to ROM #ifndef K8_ALLOCATE_MMIO_RANGE #define K8_ALLOCATE_MMIO_RANGE 0 @@ -720,7 +716,7 @@ uint8_t next_busn; uint8_t ht_c_num; uint8_t nodes; -#if K8_ALLOCATE_IO_RANGE == 1 +#if CONFIG_K8_ALLOCATE_IO_RANGE unsigned next_io_base; #endif @@ -740,7 +736,7 @@ next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/ -#if K8_ALLOCATE_IO_RANGE == 1 +#if CONFIG_K8_ALLOCATE_IO_RANGE /* io range allocation */ tempreg = 0 | (((reg>>8) & 0x3) << 4 )| (0x3<<12); //limit pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4, tempreg); @@ -753,7 +749,7 @@ for(ht_c_num=1;ht_c_num<4; ht_c_num++) { pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0); -#if K8_ALLOCATE_IO_RANGE == 1 +#if CONFIG_K8_ALLOCATE_IO_RANGE /* io range allocation */ pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc4 + ht_c_num * 8, 0); pci_write_config32(PCI_DEV(0, 0x18, 1), 0xc0 + ht_c_num * 8, 0); @@ -786,7 +782,7 @@ pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, tempreg); next_busn+=0x3f+1; -#if K8_ALLOCATE_IO_RANGE == 1 +#if CONFIG_K8_ALLOCATE_IO_RANGE /* io range allocation */ tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg); @@ -810,7 +806,7 @@ pci_write_config32(dev, regpos, reg); } -#if K8_ALLOCATE_IO_RANGE == 1 +#if CONFIG_K8_ALLOCATE_IO_RANGE /* io range allocation */ for(i = 0; i< 4; i++) { unsigned regpos;

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2005

2004

2003

2002

coreboot November 2010