Remainder of my ASUS M2V patchqueue, with the already applied parts removed. Rediffed against updated svn.
Needed to change class from raid to ide so seabios can boot from it.
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
---
Index: src/include/device/pci_ids.h =================================================================== --- src/include/device/pci_ids.h.orig 2010-11-07 17:32:22.000000000 +0100 +++ src/include/device/pci_ids.h 2010-11-07 17:33:44.000000000 +0100 @@ -1229,6 +1229,7 @@ #define PCI_DEVICE_ID_VIA_VT8237A_LPC 0x3337 #define PCI_DEVICE_ID_VIA_VT8237S_LPC 0x3372 #define PCI_DEVICE_ID_VIA_VT8237_SATA 0x5372 +#define PCI_DEVICE_ID_VIA_VT8237A_SATA 0x0591 #define PCI_DEVICE_ID_VIA_VT8237_VLINK 0x287e #define PCI_DEVICE_ID_VIA_VT8237R_UHCI 0x3038 #define PCI_DEVICE_ID_VIA_VT8237R_EHCI 0x3104 Index: src/southbridge/via/vt8237r/vt8237r_sata.c =================================================================== --- src/southbridge/via/vt8237r/vt8237r_sata.c.orig 2010-11-07 17:32:22.000000000 +0100 +++ src/southbridge/via/vt8237r/vt8237r_sata.c 2010-11-07 17:33:44.000000000 +0100 @@ -119,6 +119,12 @@ .device = PCI_DEVICE_ID_VIA_VT8237_SATA, };
+static const struct pci_driver northbridge_driver_i_a __pci_driver = { + .ops = &sata_i_ops, + .vendor = PCI_VENDOR_ID_VIA, + .device = PCI_DEVICE_ID_VIA_VT8237A_SATA, +}; + static const struct pci_driver northbridge_driver_i __pci_driver = { .ops = &sata_i_ops, .vendor = PCI_VENDOR_ID_VIA,
Tobias Diedrich wrote:
Needed to change class from raid to ide so seabios can boot from it.
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
Acked-by: Peter Stuge peter@stuge.se
r6061
Add the VT8237A id to src/southbridge/via/vt8237r/bootblock.c I missed this one since it was working anyway, since "The LPC BIOS ROM is always accessed when ISA addresses FFF80000-FFFFFFFF and 000F0000-000FFFFF are decoded" (VT8237R datasheet) And the rom I use for testing is smaller than this 512KB default range.
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
---
Index: src/southbridge/via/vt8237r/bootblock.c =================================================================== --- src/southbridge/via/vt8237r/bootblock.c.orig 2010-11-07 17:59:47.000000000 +0100 +++ src/southbridge/via/vt8237r/bootblock.c 2010-11-07 18:00:04.000000000 +0100 @@ -38,8 +38,14 @@ dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237S_LPC), 0);
- if (dev == PCI_DEV_INVALID) - return; + if (dev == PCI_DEV_INVALID) { + /* Power management controller */ + dev = pci_locate_device_on_bus(PCI_ID(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237A_LPC), 0); + + if (dev == PCI_DEV_INVALID) + return; + } }
pci_write_config8(dev, 0x41, 0x7f);
Tobias Diedrich wrote:
Add the VT8237A id to src/southbridge/via/vt8237r/bootblock.c I missed this one since it was working anyway, since "The LPC BIOS ROM is always accessed when ISA addresses FFF80000-FFFFFFFF and 000F0000-000FFFFF are decoded" (VT8237R datasheet) And the rom I use for testing is smaller than this 512KB default range.
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
Acked-by: Peter Stuge peter@stuge.se
r6062
Add mptable for ASUS M2V.
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
---
Index: src/mainboard/asus/m2v/mptable.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ src/mainboard/asus/m2v/mptable.c 2010-11-10 00:06:42.000000000 +0100 @@ -0,0 +1,152 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Rudolf Marek r.marek@assembler.cz + * Copyright (C) 2010 Tobias Diedrich ranma+coreboot@tdiedrich.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <string.h> +#include <stdint.h> +#include <arch/smp/mpspec.h> +#include <arch/ioapic.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include "southbridge/via/vt8237r/vt8237r.h" +#include "southbridge/via/k8t890/k8t890.h" + +static void smp_write_intsrc_pci(struct mp_config_table *mc, + unsigned char srcbus, unsigned char srcbusirq, + unsigned char dstapic, unsigned char dstirq) +{ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, + srcbus, srcbusirq, dstapic, dstirq); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + + mc = (void*)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, "M2V ", LAPIC_ADDR); + + smp_write_processors(mc); + mptable_write_buses(mc, NULL, &bus_isa); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, VT8237R_APIC_ID, 0x3, IO_APIC_ADDR); + smp_write_ioapic(mc, K8T890_APIC_ID, 0x3, K8T890_APIC_BASE); + + mptable_add_isa_interrupts(mc, bus_isa, VT8237R_APIC_ID, 0); + + /* agp? bridge */ + smp_write_intsrc_pci(mc, 0, (0x1 << 2) | 0, VT8237R_APIC_ID, 0x10); + smp_write_intsrc_pci(mc, 0, (0x1 << 2) | 1, VT8237R_APIC_ID, 0x11); + smp_write_intsrc_pci(mc, 0, (0x1 << 2) | 2, VT8237R_APIC_ID, 0x12); + smp_write_intsrc_pci(mc, 0, (0x1 << 2) | 3, VT8237R_APIC_ID, 0x13); + + /* peg bridge */ + smp_write_intsrc_pci(mc, 0, (0x2 << 2) | 0, K8T890_APIC_ID, 0x3); + smp_write_intsrc_pci(mc, 0, (0x2 << 2) | 1, K8T890_APIC_ID, 0x3); + smp_write_intsrc_pci(mc, 0, (0x2 << 2) | 2, K8T890_APIC_ID, 0x3); + smp_write_intsrc_pci(mc, 0, (0x2 << 2) | 3, K8T890_APIC_ID, 0x3); + + /* pex bridge */ + smp_write_intsrc_pci(mc, 0, (0x3 << 2) | 0, K8T890_APIC_ID, 0x7); + smp_write_intsrc_pci(mc, 0, (0x3 << 2) | 1, K8T890_APIC_ID, 0xb); + smp_write_intsrc_pci(mc, 0, (0x3 << 2) | 2, K8T890_APIC_ID, 0xf); + smp_write_intsrc_pci(mc, 0, (0x3 << 2) | 3, K8T890_APIC_ID, 0x13); + + /* SATA / IDE */ + smp_write_intsrc_pci(mc, 0, (0xf << 2) | 0, VT8237R_APIC_ID, 0x15); + + /* USB */ + smp_write_intsrc_pci(mc, 0, (0x10 << 2) | 0, VT8237R_APIC_ID, 0x14); + smp_write_intsrc_pci(mc, 0, (0x10 << 2) | 1, VT8237R_APIC_ID, 0x16); + smp_write_intsrc_pci(mc, 0, (0x10 << 2) | 2, VT8237R_APIC_ID, 0x15); + smp_write_intsrc_pci(mc, 0, (0x10 << 2) | 3, VT8237R_APIC_ID, 0x17); + + /* PCIE graphics */ + smp_write_intsrc_pci(mc, 2, (0x00 << 2) | 0, K8T890_APIC_ID, 0x0); + smp_write_intsrc_pci(mc, 2, (0x00 << 2) | 1, K8T890_APIC_ID, 0x1); + smp_write_intsrc_pci(mc, 2, (0x00 << 2) | 2, K8T890_APIC_ID, 0x2); + smp_write_intsrc_pci(mc, 2, (0x00 << 2) | 3, K8T890_APIC_ID, 0x3); + + /* onboard PCIE atl1 ethernet */ + smp_write_intsrc_pci(mc, 3, (0x00 << 2) | 0, K8T890_APIC_ID, 0x4); + smp_write_intsrc_pci(mc, 3, (0x00 << 2) | 1, K8T890_APIC_ID, 0x5); + smp_write_intsrc_pci(mc, 3, (0x00 << 2) | 2, K8T890_APIC_ID, 0x6); + smp_write_intsrc_pci(mc, 3, (0x00 << 2) | 3, K8T890_APIC_ID, 0x7); + + /* PCIE slot */ + smp_write_intsrc_pci(mc, 4, (0x00 << 2) | 0, K8T890_APIC_ID, 0x8); + smp_write_intsrc_pci(mc, 4, (0x00 << 2) | 1, K8T890_APIC_ID, 0x9); + smp_write_intsrc_pci(mc, 4, (0x00 << 2) | 2, K8T890_APIC_ID, 0xa); + smp_write_intsrc_pci(mc, 4, (0x00 << 2) | 3, K8T890_APIC_ID, 0xb); + + /* onboard marvell mv6121 sata */ + smp_write_intsrc_pci(mc, 5, (0x00 << 2) | 0, K8T890_APIC_ID, 0xc); + smp_write_intsrc_pci(mc, 5, (0x00 << 2) | 1, K8T890_APIC_ID, 0xd); + smp_write_intsrc_pci(mc, 5, (0x00 << 2) | 2, K8T890_APIC_ID, 0xe); + smp_write_intsrc_pci(mc, 5, (0x00 << 2) | 3, K8T890_APIC_ID, 0xf); + + /* azalia HDCA */ + smp_write_intsrc_pci(mc, 6, (0x01 << 2) | 0, VT8237R_APIC_ID, 0x11); + + /* pci slot 1 */ + smp_write_intsrc_pci(mc, 7, (6 << 2) | 0, VT8237R_APIC_ID, 0x10); + smp_write_intsrc_pci(mc, 7, (6 << 2) | 1, VT8237R_APIC_ID, 0x11); + smp_write_intsrc_pci(mc, 7, (6 << 2) | 2, VT8237R_APIC_ID, 0x12); + smp_write_intsrc_pci(mc, 7, (6 << 2) | 3, VT8237R_APIC_ID, 0x13); + + /* pci slot 2 */ + smp_write_intsrc_pci(mc, 7, (7 << 2) | 0, VT8237R_APIC_ID, 0x11); + smp_write_intsrc_pci(mc, 7, (7 << 2) | 1, VT8237R_APIC_ID, 0x12); + smp_write_intsrc_pci(mc, 7, (7 << 2) | 2, VT8237R_APIC_ID, 0x13); + smp_write_intsrc_pci(mc, 7, (7 << 2) | 3, VT8237R_APIC_ID, 0x10); + + /* pci slot 3 */ + smp_write_intsrc_pci(mc, 7, (8 << 2) | 0, VT8237R_APIC_ID, 0x12); + smp_write_intsrc_pci(mc, 7, (8 << 2) | 1, VT8237R_APIC_ID, 0x13); + smp_write_intsrc_pci(mc, 7, (8 << 2) | 2, VT8237R_APIC_ID, 0x10); + smp_write_intsrc_pci(mc, 7, (8 << 2) | 3, VT8237R_APIC_ID, 0x11); + + /* pci slot 4 */ + smp_write_intsrc_pci(mc, 7, (9 << 2) | 0, VT8237R_APIC_ID, 0x13); + smp_write_intsrc_pci(mc, 7, (9 << 2) | 1, VT8237R_APIC_ID, 0x10); + smp_write_intsrc_pci(mc, 7, (9 << 2) | 2, VT8237R_APIC_ID, 0x11); + smp_write_intsrc_pci(mc, 7, (9 << 2) | 3, VT8237R_APIC_ID, 0x12); + + /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0, 0x0, MP_APIC_ALL, 0x0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, 0, 0x0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums. */ + mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), + mc->mpe_length); + mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length); + + return smp_next_mpe_entry(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr); + return (unsigned long)smp_write_config_table(v); +} Index: src/mainboard/asus/m2v/Kconfig =================================================================== --- src/mainboard/asus/m2v/Kconfig.orig 2010-11-09 23:38:41.000000000 +0100 +++ src/mainboard/asus/m2v/Kconfig 2010-11-10 00:06:45.000000000 +0100 @@ -19,6 +19,7 @@ select TINY_BOOTBLOCK select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES + select HAVE_MP_TABLE
config MAINBOARD_DIR string
Uwe Hermann wrote:
Thanks, r6059.
Just a minute before I had sent a slightly updated version. :) Here is the diff:
Use the new mptable_write_buses()
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
---
Index: src/mainboard/asus/m2v/mptable.c =================================================================== --- src/mainboard/asus/m2v/mptable.c (revision 6059) +++ src/mainboard/asus/m2v/mptable.c (working copy) @@ -38,25 +38,15 @@ static void *smp_write_config_table(void *v) { struct mp_config_table *mc; - int bus_isa = 42; + int bus_isa;
mc = (void*)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, "M2V ", LAPIC_ADDR);
smp_write_processors(mc); + mptable_write_buses(mc, NULL, &bus_isa);
- /* Bus: Bus ID Type */ - smp_write_bus(mc, 0, "PCI "); /* root bus */ - smp_write_bus(mc, 1, "PCI "); /* agp? */ - smp_write_bus(mc, 2, "PCI "); /* pcie x16 */ - smp_write_bus(mc, 3, "PCI "); /* pcie x1 */ - smp_write_bus(mc, 4, "PCI "); /* pcie x1 */ - smp_write_bus(mc, 5, "PCI "); /* pcie x1 */ - smp_write_bus(mc, 6, "PCI "); /* azalia audio */ - smp_write_bus(mc, 7, "PCI "); /* pci */ - smp_write_bus(mc, bus_isa, "ISA "); - /* I/O APICs: APIC ID Version State Address */ smp_write_ioapic(mc, VT8237R_APIC_ID, 0x3, IO_APIC_ADDR); smp_write_ioapic(mc, K8T890_APIC_ID, 0x3, K8T890_APIC_BASE);
On Wed, Nov 10, 2010 at 08:21:28PM +0100, Tobias Diedrich wrote:
Use the new mptable_write_buses()
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
Thanks, r6060.
Uwe.
The only southbridge having a pirq_assign_irqs function (needed for CONFIG_PIRQ_ROUTE) so far is the amd cs5530. Add one for vt8237 too. Setting up the pci routing is important in case you want to boot DOS, OSes that don't support ACPI or MP tables and ROMs for add-in storage controllers may depend on this too. TODO: Fix the 4 routing links limitation in src/arch/i386/boot/pirq_routing.c
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
---
Index: src/southbridge/via/vt8237r/vt8237r_pirq.c =================================================================== --- /dev/null 1970-01-01 00:00:00.000000000 +0000 +++ src/southbridge/via/vt8237r/vt8237r_pirq.c 2010-11-10 02:47:03.000000000 +0100 @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Nikolay Petukhov nikolay.petukhov@gmail.com + * Copyright (C) 2010 Tobias Diedrich ranma+coreboot@tdiedrich.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <pc80/i8259.h> + +#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1) +void pirq_assign_irqs(const unsigned char route[4]) +{ + device_t pdev; + + pdev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237R_LPC, 0); + if (!pdev) + pdev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237S_LPC, 0); + if (!pdev) + pdev = dev_find_device(PCI_VENDOR_ID_VIA, + PCI_DEVICE_ID_VIA_VT8237A_LPC, 0); + if (!pdev) + return; + + pci_write_config8(pdev, 0x55, route[0] << 4); + pci_write_config8(pdev, 0x56, (route[2] << 4) | route[1]); + pci_write_config8(pdev, 0x57, route[3] << 4); + + /* Enable INT[E-H] mapped to INT[A-D] for simplicity */ + pci_write_config8(pdev, 0x46, 0x00); +} +#endif Index: src/southbridge/via/vt8237r/Makefile.inc =================================================================== --- src/southbridge/via/vt8237r/Makefile.inc.orig 2010-11-10 02:41:11.000000000 +0100 +++ src/southbridge/via/vt8237r/Makefile.inc 2010-11-10 02:41:20.000000000 +0100 @@ -23,5 +23,5 @@ driver-y += vt8237r_lpc.c driver-y += vt8237r_sata.c driver-y += vt8237r_usb.c -driver-y += vt8237r_nic.c +driver-$(CONFIG_PIRQ_ROUTE) += vt8237r_pirq.c ramstage-$(CONFIG_GENERATE_ACPI_TABLES) += vt8237_fadt.c Index: src/mainboard/asus/m2v/Kconfig =================================================================== --- src/mainboard/asus/m2v/Kconfig.orig 2010-11-10 02:41:19.000000000 +0100 +++ src/mainboard/asus/m2v/Kconfig 2010-11-10 02:47:09.000000000 +0100 @@ -18,6 +18,7 @@ select RAMINIT_SYSINFO select TINY_BOOTBLOCK select HAVE_PIRQ_TABLE + select PIRQ_ROUTE select HAVE_ACPI_TABLES select HAVE_MP_TABLE
Acked-by: Rudolf Marek r.marek@assembler.cz Committed revision 6081. Thanks, Rudolf
This problem was introduced with http://tracker.coreboot.org/trac/coreboot/changeset/3953
Note that all corresponding DSDTs only ever check TOM2 against 0.
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
---
Index: src/northbridge/amd/amdk8/amdk8_acpi.c =================================================================== --- src/northbridge/amd/amdk8/amdk8_acpi.c.orig 2010-11-03 23:19:03.000000000 +0100 +++ src/northbridge/amd/amdk8/amdk8_acpi.c 2010-11-03 23:19:37.000000000 +0100 @@ -270,7 +270,15 @@ msr = rdmsr(TOP_MEM); lens += acpigen_write_name_dword("TOM1", msr.lo); msr = rdmsr(TOP_MEM2); - lens += acpigen_write_name_qword("TOM2", (((uint64_t) msr.hi) << 32) | msr.lo); + /* + * Since XP only implements parts of ACPI 2.0, we can't use a qword + * here. + * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt + * slide 22ff. + * Shift value right by 20 bit to make it fit into 32bit, + * giving us 1MB granularity and a limit of almost 4Exabyte of memory. + */ + lens += acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20);
lens += k8acpi_write_HT(); //minus opcode Index: src/mainboard/gigabyte/ma78gm/dsdt.asl =================================================================== --- src/mainboard/gigabyte/ma78gm/dsdt.asl.orig 2010-11-03 23:19:03.000000000 +0100 +++ src/mainboard/gigabyte/ma78gm/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */
Index: src/mainboard/asrock/939a785gmh/dsdt.asl =================================================================== --- src/mainboard/asrock/939a785gmh/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/asrock/939a785gmh/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1122,7 +1122,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1530,7 +1530,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */
Index: src/mainboard/kontron/kt690/dsdt.asl =================================================================== --- src/mainboard/kontron/kt690/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/kontron/kt690/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1129,7 +1129,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1557,7 +1557,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */
Index: src/mainboard/gigabyte/ma785gmt/dsdt.asl =================================================================== --- src/mainboard/gigabyte/ma785gmt/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/gigabyte/ma785gmt/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */
Index: src/mainboard/amd/mahogany/dsdt.asl =================================================================== --- src/mainboard/amd/mahogany/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/amd/mahogany/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1126,7 +1126,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1572,7 +1572,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */
Index: src/mainboard/amd/pistachio/dsdt.asl =================================================================== --- src/mainboard/amd/pistachio/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/amd/pistachio/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1128,7 +1128,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1480,7 +1480,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */
Index: src/mainboard/amd/dbm690t/dsdt.asl =================================================================== --- src/mainboard/amd/dbm690t/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/amd/dbm690t/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1129,7 +1129,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1557,7 +1557,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */
Index: src/mainboard/amd/mahogany_fam10/dsdt.asl =================================================================== --- src/mainboard/amd/mahogany_fam10/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/amd/mahogany_fam10/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */
Index: src/mainboard/amd/tilapia_fam10/dsdt.asl =================================================================== --- src/mainboard/amd/tilapia_fam10/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/amd/tilapia_fam10/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */
Index: src/mainboard/iei/kino-780am2-fam10/dsdt.asl =================================================================== --- src/mainboard/iei/kino-780am2-fam10/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/iei/kino-780am2-fam10/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */
Index: src/mainboard/jetway/pa78vm5/dsdt.asl =================================================================== --- src/mainboard/jetway/pa78vm5/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/jetway/pa78vm5/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */
Index: src/mainboard/technexion/tim8690/dsdt.asl =================================================================== --- src/mainboard/technexion/tim8690/dsdt.asl.orig 2010-11-03 23:19:28.000000000 +0100 +++ src/mainboard/technexion/tim8690/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1129,7 +1129,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1557,7 +1557,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */
Index: src/mainboard/technexion/tim5690/dsdt.asl =================================================================== --- src/mainboard/technexion/tim5690/dsdt.asl.orig 2010-11-03 23:19:29.000000000 +0100 +++ src/mainboard/technexion/tim5690/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1129,7 +1129,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1557,7 +1557,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */
Index: src/mainboard/asus/m4a785-m/dsdt.asl =================================================================== --- src/mainboard/asus/m4a785-m/dsdt.asl.orig 2010-11-03 23:19:29.000000000 +0100 +++ src/mainboard/asus/m4a785-m/dsdt.asl 2010-11-03 23:19:37.000000000 +0100 @@ -1168,7 +1168,7 @@ /* Note: Only need HID on Primary Bus */ Device(PCI0) { External (TOM1) - External (TOM2) + External (TOM2) /* (<real tom2> >> 20) to make it fit into 32 bit for XP */ Name(_HID, EISAID("PNP0A03")) Name(_ADR, 0x00180000) /* Dev# = BSP Dev#, Func# = 0 */ Method(_BBN, 0) { /* Bus number = 0 */ @@ -1614,7 +1614,8 @@ /* * If(LNotEqual(TOM2, 0x00000000)){ * Store(0x100000000,DMHB) DRAM from 4GB to TopMem2 - * Subtract(TOM2, 0x100000000, DMHL) + * ShiftLeft(TOM2, 20, Local0) + * Subtract(Local0, 0x100000000, DMHL) * } */
Acked-by: Rudolf Marek r.marek@assembler.cz Committed revision 6082. Thanks,
Rudolf
Linux also needs the MMCONF area to be reserved either in E820 or as an ACPI motherboard resource or it will not enable MMCONFIG and the extended pcie configuration area will be unaccessible:
This patch adds the IORESOURCE_RESERVE flag to the APIC and MMCONF resource flags to do this. I also added a new resource for the mapped bios rom area just below 4GB. I'm not sure if the choice for the index parameter of new_resource() is correct though. Note that the bios rom decode is enabled in src/southbridge/via/vt8237r/vt8237r_early_smbus.c for the whole 4MB area (even though the comment says 1MB).
dmesg excerpt without patch: |BIOS-provided physical RAM map: | BIOS-e820: 0000000000000000 - 000000000009f000 (usable) | BIOS-e820: 000000000009f000 - 00000000000a0000 (reserved) | BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved) | BIOS-e820: 0000000000100000 - 00000000dffed000 (usable) | BIOS-e820: 00000000dffed000 - 00000000e0000000 (reserved) | BIOS-e820: 0000000100000000 - 0000000140000000 (usable) [...] |ACPI: bus type pci registered |PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) |PCI: not using MMCONFIG |PCI: PCI BIOS revision 2.10 entry at 0xffe77, last bus=7 |PCI: Using configuration type 1 for base access |bio: create slab <bio-0> at 0 |ACPI: EC: Look up EC in DSDT |ACPI: Interpreter enabled |ACPI: (supports S0 S5) |ACPI: Using IOAPIC for interrupt routing |PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) |[Firmware Bug]: PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] not reserved in ACPI motherboard resources |PCI: not using MMCONFIG |PCI: DMI: pci_use_crs=1 pci_probe=0000000b |PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug |ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) |pci_root PNP0A03:00: host bridge window [io 0x0000-0x0cf7] |pci_root PNP0A03:00: host bridge window [io 0x0d00-0xffff] |pci_root PNP0A03:00: host bridge window [mem 0xe0000000-0xffffffff]
dmesg excerpt with patch: |BIOS-provided physical RAM map: | BIOS-e820: 0000000000000000 - 000000000009f000 (usable) | BIOS-e820: 000000000009f000 - 00000000000a0000 (reserved) | BIOS-e820: 00000000000f0000 - 0000000000100000 (reserved) | BIOS-e820: 0000000000100000 - 00000000dffed000 (usable) | BIOS-e820: 00000000dffed000 - 00000000f0000000 (reserved) | BIOS-e820: 00000000fec00000 - 00000000fec00100 (reserved) | BIOS-e820: 00000000fecc0000 - 00000000fecc0100 (reserved) | BIOS-e820: 00000000ffc00000 - 0000000100000000 (reserved) | BIOS-e820: 0000000100000000 - 0000000140000000 (usable) [...] |ACPI: bus type pci registered |PCI: MMCONFIG for domain 0000 [bus 00-ff] at [mem 0xe0000000-0xefffffff] (base 0xe0000000) |PCI: MMCONFIG at [mem 0xe0000000-0xefffffff] reserved in E820 |PCI: Using MMCONFIG for extended config space |PCI: Using configuration type 1 for base access |bio: create slab <bio-0> at 0 |ACPI: EC: Look up EC in DSDT |ACPI: Interpreter enabled |ACPI: (supports S0 S5) |ACPI: Using IOAPIC for interrupt routing |PCI: DMI: pci_use_crs=1 pci_probe=00000008 |PCI: Using host bridge windows from ACPI; if necessary, use "pci=nocrs" and report a bug |ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) |pci_root PNP0A03:00: host bridge window [io 0x0000-0x0cf7] |pci_root PNP0A03:00: host bridge window [io 0x0d00-0xffff] |pci_root PNP0A03:00: host bridge window [mem 0xe0000000-0xffffffff]
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
---
Index: src/southbridge/via/k8t890/k8t890_traf_ctrl.c =================================================================== --- src/southbridge/via/k8t890/k8t890_traf_ctrl.c.orig 2010-11-10 14:29:57.000000000 +0100 +++ src/southbridge/via/k8t890/k8t890_traf_ctrl.c 2010-11-10 14:30:44.000000000 +0100 @@ -58,7 +58,7 @@ res->limit = res->base + res->size - 1; res->align = 8; res->gran = 8; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
/* Add an MMCONFIG resource. */ @@ -67,7 +67,7 @@ res->align = log2(res->size); res->gran = log2(res->size); res->limit = 0xffffffff; /* 4G */ - res->flags = IORESOURCE_MEM; + res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE; }
static void traf_ctrl_enable_generic(struct device *dev) Index: src/southbridge/via/vt8237r/vt8237r_lpc.c =================================================================== --- src/southbridge/via/vt8237r/vt8237r_lpc.c.orig 2010-11-10 14:29:57.000000000 +0100 +++ src/southbridge/via/vt8237r/vt8237r_lpc.c 2010-11-10 14:53:16.000000000 +0100 @@ -521,7 +521,7 @@ res->base = VT8237R_ACPI_IO_BASE; res->size = 128; res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
/* Fixed EISA ECLR I/O Regs */ @@ -529,7 +529,7 @@ res->base = 0x4d0; res->size = 2; res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
/* Fixed System Management Bus I/O Resource */ @@ -537,7 +537,7 @@ res->base = VT8237R_SMBUS_IO_BASE; res->size = 16; res->limit = 0xffffUL; - res->flags = IORESOURCE_IO | IORESOURCE_FIXED | + res->flags = IORESOURCE_IO | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
/* Fixed APIC resource */ @@ -547,7 +547,15 @@ res->limit = 0xffffffffUL; res->align = 8; res->gran = 8; - res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | + IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Fixed flashrom resource */ + res = new_resource(dev, 4); + res->base = 0xff800000UL; + res->size = 0x00800000UL; /* 8MB */ + res->limit = 0xffffffffUL; + res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_RESERVE | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
res = new_resource(dev, 1);
Acked-by: Rudolf Marek r.marek@assembler.cz
I removed the MMConfig reserve region in m2v-mx se mainboard code and I extended the flash region to 16MB (this is what VT8237S can decode)
Committed revision 6083. Thanks,
Rudolf
While adding the area between TOM1 and 4GB to \SB.PCI0._CRS seems to be the easiest way to get both Linux and Windows happy, it is not quite correct because reserved areas like APIC, MMCONF etc. ranges need to be excluded.
This is a proof of concept patch for the M2V board that dynamically creates a ResourceTemplate() containing these in the SSDT and adds a corresponding PNP0C02 device to the DSDT.
All resources that have IORESOURCE_RESERVE and (IORESOURCE_MEM or IORESOURCE_IO) set are added.
Here applied on top of the "Ranges unavailable for PCI BARs should be marked as reserved in the E820 memory map, in case the OS wants to change the BARs" patch, which adds the IORESOURCE_RESERVE flag to via k8t890/vt8237 apic/mmconf/bios resources.
coreboot log excerpt: |ACPI: * SSDT |processor_brand=AMD Athlon(tm) 64 Processor 3200+ |Pstates Algorithm ... |Pstate_freq[0] = 2000MHz Pstate_vid[0] = 8 Pstate_volt[0] = 1350mv Pstate_power[0] = 62000mw |Pstate_freq[1] = 1800MHz Pstate_vid[1] = 10 Pstate_volt[1] = 1300mv Pstate_power[1] = 51743mw |Pstate_freq[2] = 1000MHz Pstate_vid[2] = 18 Pstate_volt[2] = 1100mv Pstate_power[2] = 20581mw |m2v_write_mainboard_resources() |Adding M2V reserved resources |acpigen_add_mainboard_rsvd_mem32: base=fec00000 size=00000100 |acpigen_add_mainboard_rsvd_mem32: base=ffc00000 size=00400000 |acpigen_add_mainboard_rsvd_mem32: base=fecc0000 size=00000100 |acpigen_add_mainboard_rsvd_mem32: base=c0000000 size=10000000 |acpigen_add_mainboard_rsvd_io: base=0a20 size=0008 |ACPI: added table 7/32 Length now 64
Linux dmesg excerpt: |ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) |pci_root PNP0A03:00: host bridge window [io 0x0000-0x0cf7] |pci_root PNP0A03:00: host bridge window [io 0x0d00-0xffff] |pci_root PNP0A03:00: host bridge window [mem 0xc0000000-0xffffffff] |[...] |system 00:04: [io 0x0a20-0x0a27] has been reserved |system 00:04: [mem 0xfec00000-0xfec000ff] could not be reserved |system 00:04: [mem 0xffc00000-0xffffffff] has been reserved |system 00:04: [mem 0xfecc0000-0xfecc00ff] could not be reserved |system 00:04: [mem 0xc0000000-0xcfffffff] has been reserved |pci 0000:00:03.0: BAR 9: assigned [mem 0xd0500000-0xd06fffff 64bit pref]
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
---
Index: src/mainboard/asus/m2v/acpi_tables.c =================================================================== --- src/mainboard/asus/m2v/acpi_tables.c.orig 2010-11-10 15:08:13.000000000 +0100 +++ src/mainboard/asus/m2v/acpi_tables.c 2010-11-10 19:25:06.000000000 +0100 @@ -25,6 +25,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/smp/mpspec.h> #include <arch/ioapic.h> #include <device/device.h> @@ -88,6 +89,7 @@ { k8acpi_write_vars(); amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\_SB.PCI0.MBRS", "_CRS"); return (unsigned long) (acpigen_get_current()); }
Index: src/mainboard/asus/m2v/dsdt.asl =================================================================== --- src/mainboard/asus/m2v/dsdt.asl.orig 2010-11-10 15:08:13.000000000 +0100 +++ src/mainboard/asus/m2v/dsdt.asl 2010-11-10 19:24:47.000000000 +0100 @@ -399,6 +399,13 @@ } }
+ Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + + External(_CRS) /* Resource Template in SSDT */ + } + External(TOM1) /* top of memory below 4GB */
Method(_CRS, 0) { Index: src/arch/i386/boot/acpigen.c =================================================================== --- src/arch/i386/boot/acpigen.c.orig 2010-11-10 15:08:13.000000000 +0100 +++ src/arch/i386/boot/acpigen.c 2010-11-10 19:27:18.000000000 +0100 @@ -28,6 +28,7 @@ #include <string.h> #include <arch/acpigen.h> #include <console/console.h> +#include <device/device.h>
static char *gencurrent;
@@ -372,3 +373,111 @@ acpigen_patch_len(len - 1); return len + lenh; } + +int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size) +{ + acpigen_emit_byte(0x86); + acpigen_emit_byte(0x09); + acpigen_emit_byte(0x00); + acpigen_emit_byte(readwrite ? 0x01 : 0x00); + acpigen_emit_byte(base & 0xff); + acpigen_emit_byte((base >> 8) & 0xff); + acpigen_emit_byte((base >> 16) & 0xff); + acpigen_emit_byte((base >> 24) & 0xff); + acpigen_emit_byte(size & 0xff); + acpigen_emit_byte((size >> 8) & 0xff); + acpigen_emit_byte((size >> 16) & 0xff); + acpigen_emit_byte((size >> 24) & 0xff); + return 12; +} + +int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len) +{ + acpigen_emit_byte(0x47); + acpigen_emit_byte(0x01); + acpigen_emit_byte(min & 0xff); + acpigen_emit_byte((min >> 8) & 0xff); + acpigen_emit_byte(max & 0xff); + acpigen_emit_byte((max >> 8) & 0xff); + acpigen_emit_byte(align & 0xff); + acpigen_emit_byte(len & 0xff); + return 8; +} + +int acpigen_write_resourcetemplate_header(void) +{ + int len; + len = acpigen_emit_byte(0x11); /* resourcetemplate */ + len += acpigen_write_len_f(); + len += acpigen_emit_byte(0x0b); /* word */ + len_stack[ltop++] = acpigen_get_current(); + len += acpigen_emit_byte(0x00); + len += acpigen_emit_byte(0x00); + return len; +} + +int acpigen_write_resourcetemplate_footer(int len) +{ + char *p = len_stack[--ltop]; + len += acpigen_emit_byte(0x79); + len += acpigen_emit_byte(0x00); + p[0] = (len-6) & 0xff; + p[1] = ((len-6) >> 8) & 0xff; + acpigen_patch_len(len-1); + return 2; +} + +static void acpigen_add_mainboard_rsvd_mem32(void *gp, struct device *dev, + struct resource *res) +{ + acpigen_write_mem32fixed(0, res->base, res->size); +} + +static void acpigen_add_mainboard_rsvd_io(void *gp, struct device *dev, + struct resource *res) +{ + resource_t base = res->base; + resource_t size = res->size; + while (size > 0) { + resource_t sz = size > 255 ? 255 : size; + acpigen_write_io16(base, base+sz-1, 0, sz); + size -= sz; + base += sz; + } +} + +int acpigen_write_mainboard_resource_template(void) +{ + int len; + char *start; + char *end; + len = acpigen_write_resourcetemplate_header(); + start = acpigen_get_current(); + + /* Add reserved memory ranges */ + search_global_resources( + IORESOURCE_MEM | IORESOURCE_RESERVE, + IORESOURCE_MEM | IORESOURCE_RESERVE, + acpigen_add_mainboard_rsvd_mem32, 0); + + /* Add reserved io ranges */ + search_global_resources( + IORESOURCE_IO | IORESOURCE_RESERVE, + IORESOURCE_IO | IORESOURCE_RESERVE, + acpigen_add_mainboard_rsvd_io, 0); + + end = acpigen_get_current(); + len += end-start; + len += acpigen_write_resourcetemplate_footer(len); + return len; +} + +int acpigen_write_mainboard_resources(const char *scope, const char *name) +{ + int len; + len = acpigen_write_scope(scope); + len += acpigen_write_name(name); + len += acpigen_write_mainboard_resource_template(); + acpigen_patch_len(len - 1); + return len; +} Index: src/arch/i386/include/arch/acpigen.h =================================================================== --- src/arch/i386/include/arch/acpigen.h.orig 2010-11-10 15:08:13.000000000 +0100 +++ src/arch/i386/include/arch/acpigen.h 2010-11-10 15:10:49.000000000 +0100 @@ -46,5 +46,11 @@ typedef enum { SW_ALL=0xfc, SW_ANY=0xfd, HW_ALL=0xfe } PSD_coord; int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len); +int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size); +int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len); +int acpigen_write_resourcetemplate_header(void); +int acpigen_write_resourcetemplate_footer(int len); +int acpigen_write_mainboard_resource_template(void); +int acpigen_write_mainboard_resources(const char *scope, const char *name);
#endif
Dynamically generate PNP0C02 mainboard resources in SSDT
Updated patch with improved comments and small bugfix (use same value for min and max on io resource).
While adding the area between TOM1 and 4GB to \SB.PCI0._CRS seems to be the easiest way to get both Linux and Windows happy, it is not quite correct because reserved areas like APIC, MMCONF etc. ranges need to be excluded.
This is a proof of concept patch for the M2V board that dynamically creates a ResourceTemplate() containing these in the SSDT and adds a corresponding PNP0C02 device to the DSDT.
All resources that have IORESOURCE_RESERVE and (IORESOURCE_MEM or IORESOURCE_IO) set are added.
Here applied on top of the "Ranges unavailable for PCI BARs should be marked as reserved in the E820 memory map, in case the OS wants to change the BARs" patch, which adds the IORESOURCE_RESERVE flag to via k8t890/vt8237 apic/mmconf/bios resources.
coreboot log excerpt: |ACPI: * SSDT |processor_brand=AMD Athlon(tm) 64 Processor 3200+ |Pstates Algorithm ... |Pstate_freq[0] = 2000MHz Pstate_vid[0] = 8 Pstate_volt[0] = 1350mv Pstate_power[0] = 62000mw |Pstate_freq[1] = 1800MHz Pstate_vid[1] = 10 Pstate_volt[1] = 1300mv Pstate_power[1] = 51743mw |Pstate_freq[2] = 1000MHz Pstate_vid[2] = 18 Pstate_volt[2] = 1100mv Pstate_power[2] = 20581mw |m2v_write_mainboard_resources() |Adding M2V reserved resources |acpigen_add_mainboard_rsvd_mem32: base=fec00000 size=00000100 |acpigen_add_mainboard_rsvd_mem32: base=ffc00000 size=00400000 |acpigen_add_mainboard_rsvd_mem32: base=fecc0000 size=00000100 |acpigen_add_mainboard_rsvd_mem32: base=c0000000 size=10000000 |acpigen_add_mainboard_rsvd_io: base=0a20 size=0008 |ACPI: added table 7/32 Length now 64
Linux dmesg excerpt: |ACPI: PCI Root Bridge [PCI0] (domain 0000 [bus 00-ff]) |pci_root PNP0A03:00: host bridge window [io 0x0000-0x0cf7] |pci_root PNP0A03:00: host bridge window [io 0x0d00-0xffff] |pci_root PNP0A03:00: host bridge window [mem 0xc0000000-0xffffffff] |[...] |system 00:04: [io 0x0a20-0x0a27] has been reserved |system 00:04: [mem 0xfec00000-0xfec000ff] could not be reserved |system 00:04: [mem 0xffc00000-0xffffffff] has been reserved |system 00:04: [mem 0xfecc0000-0xfecc00ff] could not be reserved |system 00:04: [mem 0xc0000000-0xcfffffff] has been reserved |pci 0000:00:03.0: BAR 9: assigned [mem 0xd0500000-0xd06fffff 64bit pref]
Signed-off-by: Tobias Diedrich ranma+coreboot@tdiedrich.de
---
Index: src/mainboard/asus/m2v/acpi_tables.c =================================================================== --- src/mainboard/asus/m2v/acpi_tables.c.orig 2010-11-16 18:37:50.000000000 +0100 +++ src/mainboard/asus/m2v/acpi_tables.c 2010-11-16 18:39:37.000000000 +0100 @@ -25,6 +25,7 @@ #include <console/console.h> #include <string.h> #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/smp/mpspec.h> #include <arch/ioapic.h> #include <device/device.h> @@ -88,6 +89,7 @@ { k8acpi_write_vars(); amd_model_fxx_generate_powernow(0, 0, 0); + acpigen_write_mainboard_resources("\_SB.PCI0.MBRS", "_CRS"); return (unsigned long) (acpigen_get_current()); }
Index: src/mainboard/asus/m2v/dsdt.asl =================================================================== --- src/mainboard/asus/m2v/dsdt.asl.orig 2010-11-16 18:37:50.000000000 +0100 +++ src/mainboard/asus/m2v/dsdt.asl 2010-11-16 18:37:52.000000000 +0100 @@ -399,6 +399,13 @@ } }
+ Device(MBRS) { + Name (_HID, EisaId ("PNP0C02")) + Name (_UID, 0x01) + + External(_CRS) /* Resource Template in SSDT */ + } + External(TOM1) /* top of memory below 4GB */
Method(_CRS, 0) { Index: src/arch/i386/boot/acpigen.c =================================================================== --- src/arch/i386/boot/acpigen.c.orig 2010-11-16 18:37:50.000000000 +0100 +++ src/arch/i386/boot/acpigen.c 2010-11-16 18:38:51.000000000 +0100 @@ -28,6 +28,7 @@ #include <string.h> #include <arch/acpigen.h> #include <console/console.h> +#include <device/device.h>
static char *gencurrent;
@@ -372,3 +373,145 @@ acpigen_patch_len(len - 1); return len + lenh; } + +int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size) +{ + /* + * acpi 4.0 section 6.4.3.4: 32-Bit Fixed Memory Range Descriptor + * Byte 0: + * Bit7 : 1 => big item + * Bit6-0: 0000110 (0x6) => 32-bit fixed memory + */ + acpigen_emit_byte(0x86); + /* Byte 1+2: length (0x0009) */ + acpigen_emit_byte(0x09); + acpigen_emit_byte(0x00); + /* bit1-7 are ignored */ + acpigen_emit_byte(readwrite ? 0x01 : 0x00); + acpigen_emit_byte(base & 0xff); + acpigen_emit_byte((base >> 8) & 0xff); + acpigen_emit_byte((base >> 16) & 0xff); + acpigen_emit_byte((base >> 24) & 0xff); + acpigen_emit_byte(size & 0xff); + acpigen_emit_byte((size >> 8) & 0xff); + acpigen_emit_byte((size >> 16) & 0xff); + acpigen_emit_byte((size >> 24) & 0xff); + return 12; +} + +int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16) +{ + /* + * acpi 4.0 section 6.4.2.6: I/O Port Descriptor + * Byte 0: + * Bit7 : 0 => small item + * Bit6-3: 1000 (0x8) => I/O port descriptor + * Bit2-0: 111 (0x7) => 7 Bytes long + */ + acpigen_emit_byte(0x47); + /* does the device decode all 16 or just 10 bits? */ + /* bit1-7 are ignored */ + acpigen_emit_byte(decode16 ? 0x01 : 0x00); + /* minimum base address the device may be configured for */ + acpigen_emit_byte(min & 0xff); + acpigen_emit_byte((min >> 8) & 0xff); + /* maximum base address the device may be configured for */ + acpigen_emit_byte(max & 0xff); + acpigen_emit_byte((max >> 8) & 0xff); + /* alignment for min base */ + acpigen_emit_byte(align & 0xff); + acpigen_emit_byte(len & 0xff); + return 8; +} + +int acpigen_write_resourcetemplate_header(void) +{ + int len; + /* + * A ResourceTemplate() is a Buffer() with a + * (Byte|Word|DWord) containing the length, followed by one or more + * resource items, terminated by the end tag + * (small item 0xf, len 1) + */ + len = acpigen_emit_byte(0x11); /* Buffer opcode */ + len += acpigen_write_len_f(); + len += acpigen_emit_byte(0x0b); /* Word opcode */ + len_stack[ltop++] = acpigen_get_current(); + len += acpigen_emit_byte(0x00); + len += acpigen_emit_byte(0x00); + return len; +} + +int acpigen_write_resourcetemplate_footer(int len) +{ + char *p = len_stack[--ltop]; + /* + * end tag (acpi 4.0 Section 6.4.2.8) + * 0x79 <checksum> + * 0x00 is treated as a good checksum according to the spec + * and is what iasl generates. + */ + len += acpigen_emit_byte(0x79); + len += acpigen_emit_byte(0x00); + /* patch len word */ + p[0] = (len-6) & 0xff; + p[1] = ((len-6) >> 8) & 0xff; + /* patch len field */ + acpigen_patch_len(len-1); + return 2; +} + +static void acpigen_add_mainboard_rsvd_mem32(void *gp, struct device *dev, + struct resource *res) +{ + acpigen_write_mem32fixed(0, res->base, res->size); +} + +static void acpigen_add_mainboard_rsvd_io(void *gp, struct device *dev, + struct resource *res) +{ + resource_t base = res->base; + resource_t size = res->size; + while (size > 0) { + resource_t sz = size > 255 ? 255 : size; + acpigen_write_io16(base, base, 0, sz, 1); + size -= sz; + base += sz; + } +} + +int acpigen_write_mainboard_resource_template(void) +{ + int len; + char *start; + char *end; + len = acpigen_write_resourcetemplate_header(); + start = acpigen_get_current(); + + /* Add reserved memory ranges */ + search_global_resources( + IORESOURCE_MEM | IORESOURCE_RESERVE, + IORESOURCE_MEM | IORESOURCE_RESERVE, + acpigen_add_mainboard_rsvd_mem32, 0); + + /* Add reserved io ranges */ + search_global_resources( + IORESOURCE_IO | IORESOURCE_RESERVE, + IORESOURCE_IO | IORESOURCE_RESERVE, + acpigen_add_mainboard_rsvd_io, 0); + + end = acpigen_get_current(); + len += end-start; + len += acpigen_write_resourcetemplate_footer(len); + return len; +} + +int acpigen_write_mainboard_resources(const char *scope, const char *name) +{ + int len; + len = acpigen_write_scope(scope); + len += acpigen_write_name(name); + len += acpigen_write_mainboard_resource_template(); + acpigen_patch_len(len - 1); + return len; +} Index: src/arch/i386/include/arch/acpigen.h =================================================================== --- src/arch/i386/include/arch/acpigen.h.orig 2010-11-16 18:37:50.000000000 +0100 +++ src/arch/i386/include/arch/acpigen.h 2010-11-16 18:39:13.000000000 +0100 @@ -46,5 +46,11 @@ typedef enum { SW_ALL=0xfc, SW_ANY=0xfd, HW_ALL=0xfe } PSD_coord; int acpigen_write_PSD_package(u32 domain, u32 numprocs, PSD_coord coordtype); int acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len); +int acpigen_write_mem32fixed(int readwrite, u32 base, u32 size); +int acpigen_write_io16(u16 min, u16 max, u8 align, u8 len, u8 decode16); +int acpigen_write_resourcetemplate_header(void); +int acpigen_write_resourcetemplate_footer(int len); +int acpigen_write_mainboard_resource_template(void); +int acpigen_write_mainboard_resources(const char *scope, const char *name);
#endif
Acked-by: Rudolf Marek r.marek@assembler.cz Signed-off-by: Rudolf Marek r.marek@assembler.cz Added support to m2v-mx se too (trivial)
Thanks,Committed revision 6084.
Rudolf